Display panel

Abstract

Disclosed is a display panel including: a base layer having a hole; a circuit layer disposed on the base layer and including a pixel circuit and a plurality of insulating layers; an element layer disposed on the circuit layer and including a light emitting element electrically connected to the pixel circuit and a pixel defining layer defining an emission region; and an encapsulation layer covering the device layer. The circuit layer further includes a groove surrounding the hole, and the pixel defining layer includes a valley surrounding at least a portion of the emission region. A bottom surface of the recess and a side surface of the recess connected to the bottom surface are defined by an insulating layer among the plurality of insulating layers.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0109166 filed in the Korean Intellectual Property Office on August 21, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments are directed to a display panel having a simplified manufacturing process and improved product reliability. Background Art

[0004] The display device may be a device composed of various electronic components such as a display panel that displays an image, an input sensor that senses an external input, an electronic module, etc. The electronic module may include a camera, an infrared sensor, a proximity sensor, etc. The electronic module may be disposed under the display panel and the input sensor. A hole for exposing the electronic module may be disposed in the display panel and the input sensor. Summary of the invention

[0005] Embodiments provide a display panel having a simplified manufacturing process and improved product reliability.

[0006] According to an embodiment, the display panel may include: a base layer having a hole; a circuit layer disposed on the base layer and including a pixel circuit and a plurality of insulating layers; an element layer disposed on the circuit layer and including a light-emitting element electrically connected to the pixel circuit and a pixel defining layer defining an emission area; and an encapsulation layer covering the element layer. The circuit layer may also include a groove surrounding the hole, and the pixel defining layer may include a valley surrounding at least a portion of the emission area. The bottom surface of the groove and the side surface of the groove connected to the bottom surface may be defined by an insulating layer among the plurality of insulating layers.

[0007] The circuit layer may further include a first tip portion surrounding the hole and a second tip portion surrounding the first tip portion, and the first tip portion and the second tip portion may protrude from respective side surfaces of the groove.

[0008] The depth of the valley may be substantially the same as the height of the first tip portion, the height of the first tip portion being measured from a bottom surface of the groove to a bottom surface of the first tip portion.

[0009] A difference between a height of the first tip portion and a width of the first tip portion may be less than about 0.15 microns.

[0010] Each of the side surfaces of the groove may include a curved surface extending from the bottom surface and a tapered surface extending from the curved surface.

[0011] The valley may be formed of a valley bottom surface, a valley curved surface extending from the valley bottom surface, and a valley tapered surface extending from the valley curved surface, and the valley curved surface may have substantially the same shape as the curved surface of the groove.

[0012] The angle between the valley bottom surface and the valley tapered surface may be substantially the same as the angle between the bottom surface of the groove and the tapered surface of the groove.

[0013] The groove may include a plurality of grooves, and the encapsulation layer may include: a first encapsulation layer covering the plurality of grooves; a second encapsulation layer disposed on the first encapsulation layer to overlap with some of the plurality of grooves and so as not to overlap with other grooves of the plurality of grooves; and a third encapsulation layer disposed on the second encapsulation layer to cover the plurality of grooves.

[0014] The display panel may further include a sensor layer disposed on the encapsulation layer, and the sensor layer includes a first sensor conductive layer, a sensor insulating layer disposed on the first sensor conductive layer, and a second sensor conductive layer disposed on the sensor insulating layer, and at least one of the first sensor conductive layer and the second sensor conductive layer may include a covering pattern overlapping with the other grooves.

[0015] The circuit layer may further include a crack dam disposed between the groove and the hole, and the crack dam may include a tip portion protruding toward the hole. The cover pattern may overlap the crack dam and the tip portion.

[0016] The display panel may further include a cover layer disposed on the third encapsulation layer and overlapping the plurality of grooves.

[0017] The circuit layer may further include a crack dam disposed between the groove and the hole, and the crack dam may include a tip portion protruding toward the hole.

[0018] The circuit layer may further include at least one inorganic pattern disposed between the groove and the hole, and the at least one inorganic pattern may include the same material as the inorganic insulating layer among the plurality of insulating layers of the circuit layer.

[0019] The insulating layer among the plurality of insulating layers may be an organic insulating layer.

[0020] The light emitting element may include a first electrode, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer, and a portion of the intermediate layer and a portion of the second electrode may be disposed in the valley.

[0021] The intermediate layer may include a first functional layer, an emission layer disposed on the first functional layer, and a second functional layer disposed on the emission layer, and a portion of the first functional layer, a portion of the second functional layer, and a portion of the second electrode may be disposed in the groove.

[0022] The bottom surface of the groove may have a lower roughness than the bottom surface of the valley.

[0023] The light emitting element may include a first electrode, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer, and an indium gallium zinc oxide (IGZO) residue may be disposed on an upper surface of the first electrode.

[0024] According to an embodiment, a display panel may include: a base layer having a hole; a circuit layer disposed on the base layer and including a plurality of grooves surrounding the hole and including a plurality of tip portions protruding from a side surface of each of the plurality of grooves; an element layer disposed on the circuit layer and including a pixel defining layer defining an emission region; and an encapsulation layer covering the element layer. The pixel defining layer may include a valley surrounding at least a portion of the emission region, and the valley is formed in an upper surface of the pixel defining layer, and the depth of the valley may be substantially the same as the height of the plurality of tip portions, and the height of the plurality of tip portions is measured from the bottom surface of the plurality of grooves to the bottom surface of the plurality of tip portions.

[0025] The circuit layer may further include a plurality of insulating layers. An insulating layer among the plurality of insulating layers may define a bottom surface of the plurality of grooves and a side surface of the plurality of grooves extending from the bottom surface. The insulating layer among the plurality of insulating layers may be an organic insulating layer.

[0026] The circuit layer may further include at least one inorganic pattern disposed between the plurality of grooves and holes, and the at least one inorganic pattern may include the same material as the inorganic insulating layer among the plurality of insulating layers of the circuit layer.

[0027] The circuit layer may further include a crack dam disposed between the plurality of grooves and the hole, and the crack dam may include a tip portion protruding toward the hole.

[0028] The display panel may further include a sensor layer disposed on the encapsulation layer, and the sensor layer includes a first sensor conductive layer, a sensor insulating layer disposed on the first sensor conductive layer, and a second sensor conductive layer disposed on the sensor insulating layer. The encapsulation layer may include: a first encapsulation layer covering the plurality of grooves; a second encapsulation layer disposed on the first encapsulation layer to overlap with some of the plurality of grooves and so as not to overlap with other grooves of the plurality of grooves; and a third encapsulation layer disposed on the second encapsulation layer to cover the plurality of grooves. At least one of the first sensor conductive layer and the second sensor conductive layer may include a covering pattern overlapping with the other grooves.

[0029] The display panel may further include a plurality of dams formed between adjacent ones of the plurality of grooves, and the number of the plurality of tip portions may be twice or more the number of the plurality of dams. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other objects and features of the present disclosure will become apparent by describing in detail embodiments of the present disclosure with reference to the attached drawings.

[0031] Figure 1A is a schematic perspective view of an electronic device according to an embodiment.

[0032] Figure 1B is a schematic plan view of an electronic device according to an embodiment.

[0033] Figure 2 is a block diagram of an electronic device according to an embodiment.

[0034] Figure 3 is a schematic cross-sectional view of an electronic device according to an embodiment.

[0035] Figure 4 is a block diagram showing some components of an electronic device according to an embodiment.

[0036] Figure 5 is a schematic diagram of an equivalent circuit of a pixel according to an embodiment.

[0037] Figure 6 is a schematic plan view showing a portion of a display panel according to an embodiment.

[0038] Figure 7 is a schematic cross-sectional view of a display panel according to an embodiment.

[0039] Fig. 8A is an enlarged schematic cross-sectional view showing a portion of a display panel according to an embodiment.

[0040] Figure 8B is an enlarged schematic cross-sectional view showing a portion of a display panel according to an embodiment.

[0041] Fig. 9 is an image of a portion of a display panel according to an embodiment.

[0042] Fig.10 is an enlarged schematic plan view showing a portion of a display panel according to an embodiment.

[0043] Fig.11A is a schematic cross-sectional view of a display panel according to an embodiment.

[0044] Fig. 11B is a schematic cross-sectional view of a display panel according to an embodiment.

[0045] Fig. 11C is a schematic cross-sectional view of a display panel according to an embodiment.

[0046] Fig. 12Ais a schematic cross-sectional view of a display panel according to an embodiment.

[0047] Fig. 12B is a schematic cross-sectional view of a display panel according to an embodiment.

[0048] Fig. 12C is a schematic cross-sectional view of a display panel according to an embodiment.

[0049] Fig.13 is an image of a portion of a display panel according to an embodiment.

[0050] Fig.14 is a schematic cross-sectional view of a display panel according to an embodiment.

[0051] Fig.15 is a schematic cross-sectional view of a display panel according to an embodiment.

[0052] Fig.16 is a schematic cross-sectional view of a display panel according to an embodiment.

[0053] Fig.17 is a schematic cross-sectional view of a display panel according to an embodiment.

[0054] Fig.18 is an enlarged schematic cross-sectional view showing a portion of a display panel according to an embodiment.

[0055] Fig.19 is an enlarged schematic cross-sectional view showing a portion of a display panel according to an embodiment.

[0056] Fig. 20A , Fig. 20B , Fig.21A , Fig.21B , Fig.22A , Fig. 22B , Fig.23A , Fig. 23B , Fig.24A and Fig. 24B are schematic cross-sectional views showing some steps of a display panel manufacturing process according to an embodiment.

[0057] Fig.25A , Fig.25B , Fig.26A , Fig.26B , Fig.27A , Fig.27B , Fig.28A and Fig.28B are schematic cross-sectional views showing some steps of a display panel manufacturing process according to an embodiment. DETAILED DESCRIPTION

[0058] In the following description, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the present invention. As used herein, "embodiment" and "implementation" are interchangeable words, which are non-limiting examples of the devices or methods disclosed herein. However, it is apparent that various embodiments may be practiced without these specific details or with one or more equivalent arrangements. Here, various embodiments do not have to be exclusive, nor are they intended to limit the present disclosure. For example, specific shapes, configurations, and properties of embodiments may be used or implemented in another embodiment.

[0059] Unless otherwise specified, the embodiments shown should be understood to provide features of the present invention. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects, etc. (hereinafter individually or collectively referred to as "elements") of the various embodiments may be further combined, separated, interchanged and / or rearranged without departing from the scope of the present invention.

[0060] The use of cross hatching and / or shading is generally provided in the drawings to clarify the boundaries between adjacent elements. Therefore, unless otherwise stated, the presence or absence of cross hatching and / or shading does not convey or indicate any preference or requirement for a particular material, material property, size, ratio, commonality between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the drawings, the size and relative size of the elements may be exaggerated for the purpose of clarity and / or description. When the embodiments may be implemented differently, a specific process sequence may be performed differently from the described sequence. For example, two processes described in succession may be performed substantially simultaneously, or in an order opposite to the described sequence. Likewise, the same reference numerals represent the same elements.

[0061] When an element or layer is referred to as being "on", "connected to" or "coupled to" another element or layer, it may be directly on, directly connected to or directly coupled to another element or layer, or there may be an intervening element or layer. However, when an element or layer is referred to as being directly "on", "directly connected to" or "directly coupled to" another element or layer, there is no intervening element or layer. For this reason, the term "connection" may refer to a physical connection, an electrical connection and / or a fluid connection with or without an intervening element. In addition, the axis of the first direction DR1, the axis of the second direction DR2 and the axis of the third direction DR3 are not limited to the three axes of a rectangular coordinate system, such as the X-axis, the Y-axis and the Z-axis, and may be interpreted in a broader sense. For example, the axis of the first direction DR1, the axis of the second direction DR2 and the axis of the third direction DR3 may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purpose of this disclosure, "at least one of A and B" may be understood as only A, only B, or any combination of A and B. Furthermore, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as any combination of only X, only Y, only Z, or two or more of X, Y, and Z. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0062] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0063] For descriptive purposes, spatially relative terms such as "below," "below," "lower," "beneath," "above," "upper," "above," "higher," "side" (e.g., as in "sidewall"), etc. may be used herein to describe the relationship of one element to another element(s) as shown in the accompanying drawings. In addition to the orientation depicted in the accompanying drawings, spatially relative terms are intended to also include different orientations of the device in use, operation, and / or manufacture. For example, if the device in the accompanying drawings is turned over, the elements described as being "below" or "below" other elements or features will then be oriented as being "above" the other elements or features. Therefore, the term "below" can include both above and below orientations. In addition, the device can be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and therefore, the spatially relative descriptors used herein should be interpreted accordingly.

[0064] The terms used herein are used to describe the purpose of specific embodiments, rather than to limit them. As used herein, the singular forms "one", "an" and "said" are intended to also include plural forms, unless the context clearly indicates otherwise. In addition, when the terms "include", "comprise", "include", "include" and / or "include" are used in this specification, the existence of the stated features, integral bodies, steps, operations, elements, components and / or their groups is specified, but the existence or addition of one or more other features, integral bodies, steps, operations, elements, components and / or their groups is not excluded. Please also note that, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms, rather than as terms of degree, and therefore, are used to explain the inherent deviations of the values ​​that will be recognized by those of ordinary skill in the art in measuring, calculating and / or providing.

[0065] Various embodiments are described herein with reference to cross-sections and / or exploded illustrations as schematic illustrations of embodiments and / or intermediate structures. Therefore, variations in the shapes of the illustrations resulting from, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the embodiments disclosed herein should not be interpreted as being limited to the specific illustrated shapes of the regions, but rather include variations in shapes resulting from, for example, manufacturing. In this manner, the regions shown in the accompanying drawings may be schematic in nature, and the shapes of these regions may not reflect the actual shapes of the regions of the device, and therefore, are not necessarily intended to be limiting.

[0066] As is customary in the art, some embodiments are described and shown in the accompanying drawings for functional blocks, units and / or modules. It will be understood by those skilled in the art that these blocks, units and / or modules are physically implemented by electrical (or optical) circuits such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements, wiring connectors, etc. that can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where blocks, units and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein, and they can be optionally driven by firmware and / or software. In addition, it is also conceivable that each block, unit and / or module can be implemented by dedicated hardware, or implemented as a combination of dedicated hardware for performing some functions and processors for performing other functions (e.g., one or more programmed microprocessors and associated circuits). In addition, without departing from the scope of the present invention, each block, unit and / or module of some embodiments can be physically divided into two or more interactive and discrete blocks, units and / or modules. Furthermore, the blocks, units and / or modules of some embodiments may be physically combined into more complex blocks, units and / or modules without departing from the scope of the invention.

[0067] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0068] Figure 1A is a schematic perspective view of an electronic device EDE according to an embodiment.

[0069] refer to Figure 1A , the electronic device EDE may be a device activated according to an electrical signal. The electronic device EDE may be used not only for large electronic devices such as televisions and billboards, but also for small and medium-sized electronic devices such as personal computers, notebook computers, personal digital assistants, car navigation units, game consoles, portable electronic devices, and cameras. However, these devices are examples, and the electronic device EDE may be used for other electronic devices without departing from the spirit and scope of the present disclosure. Figure 1A An example is shown in which the electronic device EDE is a notebook computer.

[0070] The electronic device EDE may include a display panel DP. The display panel DP may be a component that displays an image. The display panel DP may be a light-emitting display panel. For example, the display panel DP may be an organic light-emitting display panel, an inorganic light-emitting display panel, an organic-inorganic light-emitting display panel, a quantum dot display panel, a micro-LED display panel, or a nano-LED display panel.

[0071] In an embodiment, the display panel DP may further include a function of sensing an external input. For example, the display panel DP may sense at least one of an active input through an input device and a passive input through a touch. The touch may utilize all input means capable of causing a capacitance change, such as a part of the user's body and an input device (e.g., a pen).

[0072] The display panel DP may have an active area 1000A and a peripheral area 1000NA. The display panel DP may display an image through the active area 1000A. The active area 1000A may include a plane defined by a first direction DR1 and a second direction DR2. The peripheral area 1000NA may surround the periphery of the active area 1000A. In another example, the peripheral area 1000NA may be omitted.

[0073] One or more sensor areas SA1 and SA2 may be defined in the active area 1000A. Figure 1A 2 and 3. In the embodiment of the present invention, two sensor areas SA1 and SA2 are shown as examples, but the number of sensor areas SA1 and SA2 formed in the display panel DP is not limited thereto. Each of the sensor areas SA1 and SA2 may overlap with at least one sensor. For example, each of the sensor areas SA1 and SA2 may overlap with a front camera module, an illumination sensor, a proximity sensor, an infrared camera, or a dot projector.

[0074] In an embodiment, the sensor areas SA1 and SA2 may be inactive areas that do not display an image and do not sense a touch. For example, the sensor areas SA1 and SA2 may be surrounded by the active area 1000A.

[0075] The thickness direction of the display panel DP may be parallel to a third direction DR3 intersecting the first direction DR1 and the second direction DR2. Therefore, the front surface (or upper surface) and the rear surface (or lower surface) of the member of the display panel DP may be defined based on the third direction DR3.

[0076] Figure 1B is a schematic plan view of an electronic device EDE-1 according to an embodiment.

[0077] refer to Figure 1B , the electronic device EDE-1 is a bar-shaped mobile phone. Figure 1B The bar-shaped electronic device EDE-1 is shown as an example, but the embodiment is not limited thereto. For example, the following description may be applied to various electronic devices, such as a foldable electronic device EDE-1, a rollable electronic device EDE-1, or a slidable electronic device EDE-1.

[0078] Figure 2 is a block diagram of an electronic device EDE according to an embodiment.

[0079] refer to Figure 2 , the electronic device EDE may include a display panel DP, an electronic module EM and a power module PM.

[0080] The display panel DP may include a display layer 100 and a sensor layer 200. The display layer 100 may be a component that substantially generates an image. The display layer 100 may be a light-emitting display layer. For example, the display layer 100 may be an organic light-emitting display layer, an inorganic light-emitting display layer, an organic-inorganic light-emitting display layer, a quantum dot display layer, a micro-LED display layer, or a nano-LED display layer.

[0081] The sensor layer 200 may sense an external input applied from the outside. The external input may be a user input. The user input may include various types of external inputs, such as a part of the user's body, light, heat, a pen, or pressure. In another example, the sensor layer 200 may be omitted.

[0082] The power module PM may supply power required for the overall operation of the electronic device EDE. The power module PM may include a conventional battery module.

[0083] The electronic module EM may include various functional modules for operating the electronic device EDE. The electronic module EM may be mounted (eg, directly mounted) on a motherboard electrically connected to the display panel DP, or may be mounted on a separate circuit board and electrically connected to the motherboard through a connector.

[0084] The electronic module EM may include a control module CM, a wireless communication module TM, an image input module IIM, an audio input module AIM, a memory MM, an external interface IF, an audio output module AOM, a light transmitting module LTM, a light receiving module LRM and a camera module CMM.

[0085] The control module CM may control the overall operation of the electronic device EDE. The control module CM may be a microprocessor. For example, the control module CM may enable or disable the display panel DP. The control module CM may control other modules such as the image input module IIM or the audio input module AIM based on a touch signal received from the display panel DP.

[0086] The wireless communication module TM can communicate with an external electronic device through a first network (e.g., a short-range communication network such as Bluetooth, WiFi Direct, or Infrared Data Association (IrDA)) or a second network (e.g., a long-range communication network such as a cellular network, the Internet, or a computer network (e.g., LAN or WAN)). The communication module included in the wireless communication module TM can be integrated into one component (e.g., a single chip), or can be implemented with components (e.g., chips) separated from each other. The wireless communication module TM can send / receive audio signals using a general communication line. The wireless communication module TM may include a transmitter TM1 that modulates a signal to be sent and sends the modulated signal, and a receiver TM2 that demodulates a received signal.

[0087] The image input module IIM may process the image signal to convert the image signal into image data that can be displayed on the display panel DP. The audio input module AIM may receive an external audio signal through a microphone in a voice recording mode or a voice recognition mode and may convert the external audio signal into electrical voice data.

[0088] The external interface IF may include a connector capable of physically connecting the electronic device EDE to an external electronic device. For example, the external interface IF may include a wired / wireless data port, a card (e.g., a memory card or SIM / UIM card) socket, or a connector into which an external charger is inserted.

[0089] The audio output module AOM may convert audio data received from the wireless communication module TM or audio data stored in the memory MM, and may output the converted data to the outside.

[0090] The light transmitting module LTM can generate and output light. The light transmitting module LTM can output infrared light. The light transmitting module LTM may include an LED element. The light receiving module LRM can sense infrared light. The light receiving module LRM may be activated when infrared light above a certain level is sensed. The light receiving module LRM may include a CMOS sensor. After the infrared light generated by the light transmitting module LTM is output, the infrared light may be reflected by an external object (e.g., a finger or face of a user), and the reflected infrared light may be incident on the light receiving module LRM.

[0091] The camera module CMM can take still images and videos. The camera module CMM may include a plurality of camera modules. A portion of the plurality of camera modules CMM may be connected to the sensor areas SA1 and SA2 (refer to Figure 1A ) overlap at least one of the sensor areas SA1 and SA2. External input (e.g., light) may be provided to the camera module CMM through at least one of the sensor areas SA1 and SA2. For example, the camera module CMM may capture an external image by receiving natural light passing through at least one of the sensor areas SA1 and SA2.

[0092] Figure 3 is a schematic cross-sectional view of an electronic device EDE according to an embodiment.

[0093] refer to Figure 3 , the electronic device EDE may include a display panel DP, an anti-reflection layer 300 , and a window 400 . The display panel DP may include a display layer 100 and a sensor layer 200 .

[0094] The display layer 100 may include a base layer 110 , a circuit layer 120 , an element layer 130 , and an encapsulation layer 140 .

[0095] The base layer 110 may be a member that provides a base surface on which the circuit layer 120 is disposed. The base layer 110 may be a rigid substrate, or a flexible substrate that can be bent, folded, or curled. The base layer 110 may be a glass substrate, a metal substrate, a silicon substrate, or a polymer substrate. However, the embodiment is not limited thereto, and the base layer 110 may be an inorganic layer, an organic layer, or a composite layer.

[0096] The circuit layer 120 may be disposed on the base layer 110. The circuit layer 120 may include an insulating layer, a semiconductor pattern, a conductive pattern, and a signal line. The insulating layer, the semiconductor layer, and the conductive layer may be formed on the base layer 110 by a process such as coating or deposition, and may be selectively patterned by performing a photolithography process multiple times. Thereafter, the semiconductor pattern, the conductive pattern, and the signal line included in the circuit layer 120 may be formed.

[0097] The element layer 130 may be disposed on the circuit layer 120. The element layer 130 may include a light emitting element. For example, the element layer 130 may include an organic light emitting material, an inorganic light emitting material, an organic-inorganic light emitting material, a quantum dot, a quantum rod, a micro-LED, or a nano-LED.

[0098] The encapsulation layer 140 may be disposed on the element layer 130. The encapsulation layer 140 may protect the element layer 130 from impurities such as moisture, oxygen, and dust particles.

[0099] The sensor layer 200 may be disposed on the display layer 100. The sensor layer 200 may be formed on the display layer 100 by a continuous process. For example, the sensor layer 200 may be disposed (e.g., directly disposed) on the display layer 100. In the case where the sensor layer 200 is directly disposed on the display layer 100, this may mean that a third component is not disposed between the sensor layer 200 and the display layer 100. For example, a separate bonding member may not be disposed between the sensor layer 200 and the display layer 100. In another example, the sensor layer 200 may be coupled to the display layer 100 by a bonding member. The bonding member may include a conventional adhesive or a sticky substance.

[0100] The anti-reflection layer 300 may be disposed on the sensor layer 200. The anti-reflection layer 300 may reduce the EDE (reference Figure 1A ) reflectance of external light incident from outside. The anti-reflection layer 300 may be disposed (eg, directly disposed) on the sensor layer 200. However, the embodiment is not limited thereto. For example, an adhesive member may be disposed between the anti-reflection layer 300 and the sensor layer 200.

[0101] The anti-reflection layer 300 may include a color filter. The color filter may have a certain arrangement. For example, the color filter may be arranged in consideration of the light emission color of the pixel included in the display layer 100. For example, the anti-reflection layer 300 may further include a black matrix adjacent to the color filter.

[0102] In another example, the anti-reflection layer 300 may include a reflection control layer. The reflection control layer may selectively absorb light in a partial wavelength band of light reflected inside the display panel DP and / or the electronic device EDE, or light in a partial wavelength band of light incident from outside the display panel DP and / or the electronic device EDE. For example, the reflection control layer may absorb light outside the wavelength range of red light, green light, or blue light emitted from the display layer 100, and thus may prevent or minimize a reduction in the brightness of the display panel DP and / or the electronic device EDE. For example, deterioration of the luminous efficiency of the display panel DP and / or the electronic device EDE may be prevented or minimized, and visibility may be improved.

[0103] In another case, the anti-reflection layer 300 may include a phase retarder and / or a polarizer. For example, the anti-reflection layer 300 may be attached to the sensor layer 200 by an adhesive layer. The phase retarder may be a film type or a liquid crystal coating type, and may include a λ / 2 phase retarder and / or a λ / 4 phase retarder. The polarizer may be a film type, and may include a retractable synthetic resin film. The phase retarder and the polarizer may also include a protective film. The phase retarder and the polarizer themselves or the protective film may be defined as the base layer of the anti-reflection layer 300.

[0104] The window 400 may be disposed on the anti-reflection layer 300. An adhesive member may be disposed between the anti-reflection layer 300 and the window 400. However, the embodiment is not limited thereto. The window 400 may include an optically transparent insulating material. For example, the window 400 may include glass or plastic. The window 400 may have a multilayer structure or a single-layer structure. For example, the window 400 may include a plastic film coupled by an adhesive, or may include a glass substrate and a plastic film coupled by an adhesive.

[0105] Figure 4 is a block diagram illustrating some components of an electronic device EDE according to an embodiment.

[0106] refer to Figure 4 The electronic device EDE may include a display layer 100, a driving controller 100C1, a data driving circuit 100C2, a scan driving circuit 100C3, a light emission driving circuit 100C4, and a voltage generator 100C5.

[0107] The display layer 100 may include pixels PX, scan lines GIL1 to GILn, GRL1 to GRLn and GWL1 to GWLn, light emission control lines EML1 to EMLn, and data lines DL1 to DLm.

[0108] The pixel PX may be disposed in an active area 1000A (refer to Figure 1A ) in the active area of ​​the display layer 100 corresponding to the pixel PX. Each of the pixels PX can be electrically connected to three scan lines, one light emission control line and one data line. Figure 4 As shown in , the pixels PX in the first row may be connected to the scan lines GIL1, GRL1, and GWL1 and the light emission control line EML1. For example, the pixels PX in the jth row may be connected to the scan lines GILj, GRLj, and GWLj and the light emission control line EMLj.

[0109] Each of the pixels PX may include a light emitting element ED (refer to Figure 5 ) and a pixel circuit PXC (reference Figure 5). The pixel circuit PXC may include one or more transistors and one or more capacitors.

[0110] The scan driving circuit 100C3 and the light emission driving circuit 100C4 may be embedded in the display layer 100. Therefore, the display layer 100 may include the scan driving circuit 100C3 and the light emission driving circuit 100C4. The scan driving circuit 100C3 and the light emission driving circuit 100C4 may include a thin film transistor formed by the same process as the process of forming the pixel circuit PXC.

[0111] In an embodiment, the pixel PX may not overlap with the scan driving circuit 100C3 and the light emission driving circuit 100C4. However, the embodiment is not limited thereto. For example, at least some of the pixels PX may overlap with the scan driving circuit 100C3 and the light emission driving circuit 100C4. For example, at least a portion of the scan driving circuit 100C3 and at least a portion of the light emission driving circuit 100C4 may be disposed in the display area.

[0112] The driving controller 100C1 may receive an input image signal RGB and a control signal CTRL. The driving controller 100C1 may generate an output image signal DATA by converting a data format of the input image signal RGB according to the specification of the interface with the data driving circuit 100C2. The driving controller 100C1 may output a scan driving signal SCS, a data driving signal DCS, and a light emission driving signal ECS.

[0113] The data driving circuit 100C2 may receive a data driving signal DCS and an output image signal DATA from the driving controller 100C1. The data driving circuit 100C2 may convert the output image signal DATA into a data signal and may output the data signal to data lines DL1 to DLm to be described below. The data signal may be an analog voltage corresponding to a grayscale value of the output image signal DATA.

[0114] The scan driving circuit 100C3 may receive a scan driving signal SCS from the driving controller 100C1. The scan driving circuit 100C3 may output a scan signal to the scan lines GIL1 to GILn, GRL1 to GRLn, and GWL1 to GWLn in response to the scan driving signal SCS. The scan lines GIL1 to GILn, the scan lines GRL1 to GRLn, and the scan lines GWL1 to GWLn may be referred to as first initialization scan lines GIL1 to GILn, compensation scan lines GRL1 to GRLn, and write scan lines GWL1 to GWLn, respectively.

[0115] The light emission driving circuit 100C4 may receive the light emission driving signal ECS from the driving controller 100C1. The light emission driving circuit 100C4 may output the light emission control signal to the light emission control lines EML1 to EMLn in response to the light emission driving signal ECS.

[0116] The scan driving circuit 100C3 may be disposed on a first side of the display layer 100. The scan lines GIL1 to GILn, GRL1 to GRLn, and GWL1 to GWLn extend from the scan driving circuit 100C3 in a first direction DR1. The light emission driving circuit 100C4 may be disposed on a second side of the display layer 100. The light emission control lines EML1 to EMLn extend from the light emission driving circuit 100C4 in a direction opposite to the first direction DR1.

[0117] Each of the scan lines GIL1 to GILn, GRL1 to GRLn, and GWL1 to GWLn and each of the light emission control lines EML1 to EMLn may be spaced apart from each other in the second direction DR2. The data lines DL1 to DLm may extend from the data driving circuit 100C2 in a direction opposite to the second direction DR2 and may be spaced apart from each other in the first direction DR1.

[0118] exist Figure 4 In the embodiment shown in , the scan drive circuit 100C3 and the light emission drive circuit 100C4 may be arranged to face each other, and the pixel PX is between the scan drive circuit 100C3 and the light emission drive circuit 100C4. However, the embodiment is not limited thereto. For example, the scan drive circuit 100C3 and the light emission drive circuit 100C4 may be arranged on one side of the first side and the second side of the display layer 100 so as to be adjacent to each other. In an embodiment, the scan drive circuit 100C3 and the light emission drive circuit 100C4 may be implemented as one circuit (or a single circuit).

[0119] The voltage generator 100C5 may generate voltages required for the operation of the display layer 100. In an embodiment, the voltage generator 100C5 may generate a first driving voltage ELVDD, a second driving voltage ELVSS, a reference voltage VREF, and an initialization voltage VINT. Each of the pixels PX may receive the first driving voltage ELVDD, the second driving voltage ELVSS, the reference voltage VREF, and the initialization voltage VINT from the voltage generator 100C5.

[0120] Figure 5 is a schematic diagram of an equivalent circuit of a pixel PXij according to an embodiment.

[0121] refer to Figure 4 and Figure 5, an equivalent circuit of a pixel PXij connected to a data line DLi among data lines DL1 to DLm, scan lines GIL1 to GILn, scan lines GILj, GRLj and GWLj among GRL1 to GRLn and GWL1 to GWLn, and a light emission control line EMLj among light emission control lines EML1 to EMLn is shown as an example. Figure 4 Each of the pixels PX shown in FIG. 1 may have a Figure 5 The equivalent circuit diagram of the pixel PXij has the same configuration as shown in FIG.

[0122] The pixel circuit PXC may include first, second, third, fourth and fifth thin film transistors T1, T2, T3, T4 and T5, a holding capacitor Chold and a transfer capacitor Cst. Figure 5 The pixel PXij shown in FIG. 1 is an example, and various changes and modifications may be made to the circuit configuration of the pixel PXij.

[0123] Each of the first to fifth thin film transistors T1 to T5 may be an N-type thin film transistor having an oxide semiconductor layer. The first to fifth thin film transistors T1 to T5 may be respectively referred to as a driving thin film transistor, a switching thin film transistor, a compensation thin film transistor, an initialization thin film transistor, and a light emission control thin film transistor.

[0124] The scan lines GILj, GRLj, and GWLj may transmit scan signals GIj, GRj, and GWj, and the light emission control line EMLj may transmit a light emission control signal EMj. The data line DLi may transmit a data signal Di. The data signal Di may have a similarity to the input image signal RGB (reference Figure 4 ) corresponds to the voltage level.

[0125] The first to fourth driving voltage lines VL1 to VL4 may transmit the first driving voltage ELVDD, the second driving voltage ELVSS, the reference voltage VREF, and the initialization voltage VINT to the pixels PXij.

[0126] The first thin film transistor T1 may include a first gate electrode E13, a first back gate electrode E14, a first electrode E11 electrically connected to the first driving voltage line VL1 via a fifth thin film transistor T5, and a second electrode E12 electrically connected to the anode of the light emitting element ED. A portion where the second electrode E12 of the first thin film transistor T1 and the light emitting element ED are connected may be defined as a second node N2.

[0127] The holding capacitor Chold may be connected between the first driving voltage line VL1 and the first back gate electrode E14. The first holding relative electrode Ch1 of the holding capacitor Chold may be connected to the first driving voltage line VL1, and the second holding relative electrode Ch2 of the holding capacitor Chold may be connected to the first back gate electrode E14. In another example, the holding capacitor Chold may be omitted. In another example, the first thin film transistor T1 may not include the first back gate electrode E14.

[0128] The second thin film transistor T2 may include a first electrode E21 connected to the data line DLi, a second electrode E22 connected to the first node N1, and a second gate electrode E23 connected to the scan line GWLj. The second thin film transistor T2 may transmit a data signal Di received through the data line DLi to the first node N1 in response to a scan signal GWj received through the scan line GWLj.

[0129] The transfer capacitor Cst may be connected between the first node N1 and the second node N2. A first counter electrode Cs1 of the transfer capacitor Cst may be connected to the first node N1, and a second counter electrode Cs2 of the transfer capacitor Cst may be connected to the second node N2.

[0130] The third thin film transistor T3 may include a first electrode E31 connected to a third driving voltage line (or reference voltage line) VL3, a second electrode E32 connected to the first node N1, and a third gate electrode E33 connected to the scan line GRLj. The third thin film transistor T3 may be turned on by a scan signal GRj received through the scan line GRLj, and may transmit a reference voltage VREF to the first node N1.

[0131] The fourth thin film transistor T4 may include a first electrode E41 connected to a fourth driving voltage line (or initialization voltage line) VL4, a second electrode E42 connected to the second node N2, and a fourth gate electrode E43 connected to the scan line GILj. The fourth thin film transistor T4 may transmit the initialization voltage VINT received through the fourth driving voltage line VL4 to the second node N2 in response to a scan signal GIj received through the scan line GILj.

[0132] The fifth thin film transistor T5 may include a first electrode E51 connected to the first driving voltage line VL1, a second electrode E52 connected to the first electrode E11 of the first thin film transistor T1, and a fifth gate electrode E53 connected to the light emission control line EMLj. The fifth thin film transistor T5 may be turned on by a light emission control signal EMj received through the light emission control line EMLj, and may electrically connect the first driving voltage line VL1 to the first electrode E11 of the first thin film transistor T1.

[0133] The light emitting element ED may include an anode connected to the second electrode E12 or the second node N2 of the first thin film transistor T1 and a cathode connected to the second driving voltage line VL2 .

[0134] Figure 6 is a schematic plan view showing a portion of a display panel DP according to an embodiment.

[0135] refer to Figure 6 , the active area 1000A of the display panel DP (reference Figure 1A ) may include emission areas PXA-B, PXA-R and PXA-G and non-emission areas NPXA surrounding the emission areas PXA-B, PXA-R and PXA-G. The emission areas PXA-B, PXA-R and PXA-G may include a first emission area PXA-B, a second emission area PXA-R and a third emission area PXA-G. The first emission area PXA-B, the second emission area PXA-R and the third emission area PXA-G may display light having different wavelengths. The first emission area PXA-B may display a first light as light having a blue wavelength, the second emission area PXA-R may display a second light as light having a red wavelength, and the third emission area PXA-G may display a third light as light having a green wavelength.

[0136] The emission regions PXA-B, PXA-R, and PXA-G may be formed by a pixel defining layer PDL (refer to Figure 7 ) are separated from each other. The non-emission region NPXA may be a region between adjacent emission regions PXA-B, PXA-R, and PXA-G, and may be a region corresponding to the pixel defining layer PDL. The emission regions PXA-B, PXA-R, and PXA-G may be separated from each other to correspond to the opening OP defined in the pixel defining layer PDL (refer to Figure 7 ).

[0137] The first emission region PXA-B may form a first pixel group arranged in the second direction DR2, and the second emission region PXA-R and the third emission region PXA-G may form a second pixel group alternately arranged in the second direction DR2. The first pixel group formed by the first emission region PXA-B and the second pixel group formed by the second emission region PXA-R and the third emission region PXA-G may be spaced apart from each other in the first direction DR1. The first pixel group and the second pixel group may be alternately arranged in the first direction DR1.

[0138] The emission regions PXA-B, PXA-R, and PXA-G may have different areas according to the wavelength of light emitted by the emission regions PXA-B, PXA-R, and PXA-G. Figure 6As shown in FIG. 1 , the first emission region PXA-B emitting the first light may have the largest area, and the second emission region PXA-R generating the second light may have the smallest area. However, the embodiment is not limited thereto, and the emission regions PXA-B, PXA-R, and PXA-G may have the same area, or may be arranged in the same area. Figure 6 The emission regions PXA-B, PXA-R, and PXA-G may emit light of other colors different from the light having a blue wavelength, the light having a red wavelength, and the light having a green wavelength described above.

[0139] In a plan view, each of the emission regions PXA-B, PXA-R, and PXA-G may have a rounded rectangular shape. In an embodiment, each of the first emission region PXA-B and the third emission region PXA-G may have a rounded rectangular shape having a long side extending in the second direction DR2 and a short side extending in the first direction DR1. In an embodiment, the second emission region PXA-R may have a rounded rectangular shape having a long side extending in the first direction DR1 and a short side extending in the second direction DR2. However, the shapes of the emission regions PXA-B, PXA-R, and PXA-G in a plan view are not limited thereto.

[0140] In an embodiment, the valleys VP1, VP2, and VP3 overlapped with the non-emission area NPXA may be defined in the pixel defining layer PDL (refer to Figure 7 ) (e.g., in the upper surface of the pixel defining layer PDL). The valleys VP1, VP2, and VP3 may surround at least a portion of the emission regions PXA-B, PXA-R, and PXA-G, respectively. For example, the valleys VP1, VP2, and VP3 may surround portions of the emission regions PXA-B, PXA-R, and PXA-G, respectively, and may not surround the rest of the emission regions PXA-B, PXA-R, and PXA-G. The valleys VP1, VP2, and VP3 may be referred to as control patterns, valley patterns, concave portions, concave grooves, grooves, or groove patterns.

[0141] The valleys VP1, VP2, and VP3 may be defined in the pixel defining layer PDL. In cross section, the valleys VP1, VP2, and VP3 may have a shape that is recessed from the upper surface of the pixel defining layer PDL in the thickness direction of the pixel defining layer PDL. The shapes of the valleys VP1, VP2, and VP3 in cross section will be described in detail below.

[0142] The valleys VP1, VP2, and VP3 may include a first valley VP1 surrounding a portion of the first emission region PXA-B, a second valley VP2 surrounding a portion of the second emission region PXA-R, and a third valley VP3 surrounding a portion of the third emission region PXA-G. The first valley VP1 may surround a portion of the first emission region PXA-B and may not surround the rest of the first emission region PXA-B. The second valley VP2 may surround a portion of the second emission region PXA-R and may not surround the rest of the second emission region PXA-R. The third valley VP3 may surround a portion of the third emission region PXA-G and may not surround the rest of the third emission region PXA-G. However, this is an example, and the first valley VP1, the second valley VP2, and the third valley VP3 may surround the first emission region PXA-B, the second emission region PXA-R, and the third emission region PXA-G, respectively.

[0143] In an embodiment, the valleys VP1, VP2, and VP3 may prevent the adjacent pixels PX (refer to Figure 4 ) generates a lateral leakage current between the light emitting element ED and the light emitting element ED. In the specification, "lateral leakage current" refers to a current flowing in another direction intersecting with the third direction DR3, rather than a current flowing in the third direction DR3. The third direction DR3 is the direction of the light emitting element ED (reference Figure 7 ) in a stacking direction, for example, in a direction in which an image is displayed. The lateral leakage current may refer to a current flowing in a direction parallel to a plane defined by the first direction DR1 and the second direction DR2 or in a direction similar to the directions. In an embodiment, since the valleys VP1, VP2, and VP3 recessed in the thickness direction of the pixel defining layer PDL are defined, the lateral leakage current may be prevented from being generated, and thus, color mixing due to undesired light emission of adjacent pixel areas may be prevented. Therefore, the color expression accuracy of the display panel DP may be improved.

[0144] Figure 7 is a schematic cross-sectional view of a display panel DP according to an embodiment. For example, Figure 7 Can be along Figure 6 A schematic cross-sectional view taken along line II'.

[0145] refer to Figure 7 , the circuit layer 120 may be disposed on the base layer 110. The circuit layer 120 may include a pixel circuit PXC (refer to Figure 5 ) and a barrier layer BRL, a buffer layer BFL, and a first insulating layer 10, a second insulating layer 20, a third insulating layer 30, a fourth insulating layer 40, and a fifth insulating layer 50 sequentially stacked on the base layer 110. Figure 7 , two thin film transistors T1 and T2 and two capacitors Cst and Chold of the pixel circuit PXC are shown.

[0146] The barrier layer BRL may be disposed on the base layer 110. The barrier layer BRL may have a single layer structure or a multi-layer structure. The barrier layer BRL may include at least one of silicon oxide, silicon nitride, silicon oxynitride, and amorphous silicon.

[0147] The lower conductive layers BMLa and BMLb may be disposed on the barrier layer BRL. However, the embodiment is not limited thereto. For example, in the case where the barrier layer BRL has a multilayer structure, the lower conductive layers BMLa and BMLb may be disposed between layers constituting the barrier layer BRL. For example, although Figure 7 An example in which each of the lower conductive layers BMLa and BMLb is implemented with one layer (or a single layer) is shown, but each of the lower conductive layers BMLa and BMLb may include a plurality of layers.

[0148] Each of the lower conductive layers BMLa and BMLb may include a reflective metal. For example, each of the lower conductive layers BMLa and BMLb may include titanium (Ti), molybdenum (Mo), an alloy containing molybdenum, aluminum (Al), an alloy containing aluminum, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), and copper (Cu). The lower conductive layers BMLa and BMLb may hinder the influence of the electric potential caused by the polarization phenomenon of the base layer 110 on the thin film transistors T1 and T2. For example, the lower conductive layers BMLa and BMLb may block light incident from below to the thin film transistors T1 and T2.

[0149] In an embodiment, a first lower conductive layer BMLa disposed under the first thin film transistor T1 and a second lower conductive layer BMLb disposed under the second thin film transistor T2 may be electrically isolated from each other. For example, the first lower conductive layer BMLa disposed under the first thin film transistor T1 may be synchronized with the second electrode E12 of the first thin film transistor T1. The second lower conductive layer BMLb disposed under the second thin film transistor T2 may be synchronized with the second gate electrode E23 of the second thin film transistor T2. However, this is an example, and the embodiment is not limited thereto. For example, the lower conductive layers BMLa and BMLb may independently receive a constant voltage or a pulse signal. In another example, each of the lower conductive layers BMLa and BMLb may be formed in a form isolated from another conductive pattern. Each of the lower conductive layers BMLa and BMLb according to the embodiment may be formed in various forms and is not limited to any one embodiment.

[0150] The buffer layer BFL may be disposed on the barrier layer BRL. The buffer layer BFL may prevent metal atoms or impurities from diffusing from the base layer 110 to the semiconductor pattern. In addition, the buffer layer BFL may adjust the speed at which heat is provided during a crystallization process for forming the semiconductor pattern, thereby enabling the semiconductor pattern to be uniformly formed. The buffer layer BFL may include an inorganic layer. For example, the buffer layer BFL may include a first sub-buffer layer including silicon nitride and a second sub-buffer layer disposed on the first sub-buffer layer and including silicon oxide.

[0151] The semiconductor pattern layer may be disposed on the buffer layer BFL. The semiconductor pattern layer may include a metal oxide. The metal oxide semiconductor may include a crystalline or amorphous oxide semiconductor. For example, the oxide semiconductor may include a metal oxide of zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti). In another example, the oxide semiconductor may include a mixture of a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti) and an oxide thereof. The oxide semiconductor may include indium tin oxide (ITO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO x )、Indium zinc oxide (IZO), Indium oxide (InO x ), titanium oxide (TiO x ), indium zinc tin oxide (IZTO) or zinc tin oxide (ZTO).

[0152] The semiconductor pattern layer may include a plurality of regions distinguished from each other according to whether the metal oxide is reduced. The region where the metal oxide is reduced (hereinafter referred to as the reduction region) may have a higher conductivity than the region where the metal oxide is not reduced (hereinafter referred to as the non-reduction region). The reduction region may basically serve as a signal line or a source / drain of a thin film transistor. The non-reduction region may basically correspond to a semiconductor region (or channel) of a thin film transistor. For example, a portion of the semiconductor pattern may be a semiconductor region of a thin film transistor, another portion may be a source / drain of a thin film transistor, and another portion may be a signal transmission region.

[0153] The semiconductor pattern layer may include a first channel region EA1 of a first thin film transistor T1 and a second channel region EA2 of a second thin film transistor T2. The first channel region EA1 and the second channel region EA2 may be non-reduction regions. Each of the first electrode E11 and the second electrode E12 of the first thin film transistor T1 may be a source region or a drain region of the first thin film transistor T1. Each of the first electrode E21 and the second electrode E22 of the second thin film transistor T2 may be a source region or a drain region of the second thin film transistor T2. The first electrode E11 and the second electrode E12 of the first thin film transistor T1 and the first electrode E21 and the second electrode E22 of the second thin film transistor T2 may be reduction regions.

[0154] The first insulating layer 10 may be disposed on the first channel area EA1 and the second channel area EA2. In an embodiment, the first insulating layer 10 may overlap only a specific conductive pattern. For example, the first insulating layer 10 may be disposed only in a region overlapping with a conductive layer disposed (e.g., directly disposed) on the first insulating layer 10. Figure 7 An example is shown in which the first insulating layer 10 is disposed only in a region overlapping with the first gate electrode E13 of the first thin film transistor T1, the second gate electrode E23 of the second thin film transistor T2, the first counter electrode Cs1 of the transfer capacitor Cst, and the first holding opposite electrode Ch1 of the holding capacitor Chold. However, the embodiment is not limited thereto. For example, the first insulating layer 10 may overlap (for example, completely overlap) with the base layer 110.

[0155] The second insulating layer 20 may be disposed on the buffer layer BFL and may cover the first insulating layer 10 , the first gate electrode E13 of the first thin film transistor T1 , the second gate electrode E23 of the second thin film transistor T2 , the first counter electrode Cs1 of the transfer capacitor Cst, and the first holding opposite electrode Ch1 of the holding capacitor Chold.

[0156] Each of the first insulating layer 10 and the second insulating layer 20 may be an inorganic layer and may have a single layer structure or a multilayer structure. Each of the first insulating layer 10 and the second insulating layer 20 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide. In an embodiment, each of the first insulating layer 10 and the second insulating layer 20 may be a single silicon oxide layer.

[0157] The second counter electrode Cs2 of the transfer capacitor Cst and the second holding opposing electrode Ch2 of the holding capacitor Chold may be disposed on the second insulating layer 20. The second counter electrode Cs2 and the second holding opposing electrode Ch2 may be connected to each other and may form one body (or an integrated body).

[0158] The third insulating layer 30 may be disposed on the second insulating layer 20 and may cover the second counter electrode Cs2 and the second holding opposite electrode Ch2. The third insulating layer 30 may be an inorganic layer and may have a single layer structure or a multilayer structure. The third insulating layer 30 may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0159] The first connection electrode CNE10 may be disposed on the third insulating layer 30. The first connection electrode CNE10 may be connected to the second counter electrode Cs2 through a contact hole penetrating the third insulating layer 30.

[0160] The fourth insulating layer 40 may be disposed on the third insulating layer 30. The fourth insulating layer 40 may be an organic layer. The second connection electrode CNE20 may be disposed on the fourth insulating layer 40. The second connection electrode CNE20 may be connected to the first connection electrode CNE10 through a contact hole penetrating the fourth insulating layer 40. The fifth insulating layer 50 may be disposed on the fourth insulating layer 40 and may cover the second connection electrode CNE20. The fifth insulating layer 50 may be an organic layer.

[0161] Each of the fourth insulating layer 40 and the fifth insulating layer 50 may include a general polymer such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA), or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide-based polymer, an aryl ether-based polymer, an amide-based polymer, a fluorine-based polymer, a p-xylene-based polymer, a vinyl alcohol-based polymer, or a mixture thereof. However, the embodiment is not limited thereto.

[0162] The element layer 130 may be disposed on the circuit layer 120. The element layer 130 may include a light emitting element ED. Figure 7 , a single light emitting element ED is representatively shown. An emission area PXA may be defined to correspond to the light emitting element ED. The emission area PXA may be defined by a pixel defining layer PDL to be described below.

[0163] The light emitting element ED may include a first electrode AE, an intermediate layer CEL, and a second electrode CE. The first electrode AE ​​may be referred to as a pixel electrode or an anode, and the second electrode CE may be referred to as a common electrode or a cathode. The intermediate layer CEL may include a common ground for the pixel PX (reference Figure 4 ) provided therein and an emission layer patterned to correspond to each of the pixels PX.

[0164] The first electrode AE ​​may be disposed on the fifth insulating layer 50. The first electrode AE ​​may be connected to the second connection electrode CNE20 through a contact hole penetrating the fifth insulating layer 50. The first electrode AE ​​may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. In an embodiment, the first electrode AE ​​may include a reflective layer formed of silver, magnesium, aluminum, platinum, palladium, gold, nickel, neodymium, iridium, chromium, or a compound thereof, and a transparent or semi-transparent electrode layer formed on the reflective layer. The transparent or semi-transparent electrode layer may include at least one selected from the group consisting of indium tin oxide, indium zinc oxide, indium gallium zinc oxide, zinc oxide, indium oxide, and aluminum-doped zinc oxide. For example, the first electrode AE ​​may include a multilayer structure in which indium tin oxide, silver, and indium tin oxide are sequentially stacked on top of each other.

[0165] The pixel defining layer PDL may be disposed on the fifth insulating layer 50. The pixel defining layer PDL may have a property of absorbing light. For example, the pixel defining layer PDL may be black in color. The pixel defining layer PDL may include a black colorant. The black colorant may include a black dye or a black pigment. The black colorant may include carbon black, a metal such as chromium, or an oxide thereof. The material of the pixel defining layer PDL is not limited thereto.

[0166] An opening OP for exposing a portion of the first electrode AE ​​may be defined in the pixel defining layer PDL. For example, the pixel defining layer PDL may cover the periphery of the first electrode AE. The emission area PXA may be defined by the pixel defining layer PDL. For example, valleys VP1 and VP2 overlapping the non-emission area NPXA may be defined in the pixel defining layer PDL. Valleys VP1 and VP2 may have a shape that is recessed from the upper surface of the pixel defining layer PDL in a third direction DR3 as a thickness direction. The depth of valleys VP1 and VP2 may be less than the maximum thickness of the pixel defining layer PDL. Therefore, the side surfaces and bottom surfaces of valleys VP1 and VP2 may be defined by the pixel defining layer PDL.

[0167] In an embodiment, a mask layer may be used to form valleys VP1 and VP2 in the pixel defining layer PDL. For example, residues of the mask layer may remain on the first electrode AE. For example, the mask layer may include indium gallium zinc oxide (IGZO). Residues of IGZO may remain on the upper surface of the first electrode AE.

[0168] Fig. 8A is an enlarged schematic cross-sectional view showing a portion of a display panel DP according to an embodiment. For example, Fig. 8A It is shown Figure 7 An enlarged schematic cross-sectional view of the region AA' shown in FIG. Fig. 8A , a portion of the pixel defining layer PDL is shown.

[0169] Reference together Figure 7 and Fig. 8A , each of the valleys VP1 and VP2 may be defined by a valley bottom surface VBS, a valley curved surface VCS, and a valley tapered surface VTS. The valley bottom surface VBS, the valley curved surface VCS, and the valley tapered surface VTS may be defined by a pixel defining layer PDL. The valley curved surface VCS may extend from the valley bottom surface VBS and may have a selectable curvature. For example, the radius of curvature of the valley curved surface VCS may be about 100 nm to about 230 nm, but embodiments are not limited thereto. The valley tapered surface VTS may extend from the valley curved surface VCS.

[0170] Since the valley curved surface VCS is defined between the valley bottom surface VBS and the valley tapered surface VTS, the angle of the side surface of the pixel defining layer PDL defining each of the valleys VP1 and VP2 may be gently changed. Therefore, the first encapsulation layer 141 to be described below may be stably formed.

[0171] Each of the valleys VP1 and VP2 may have a depth VP-D of about 0.45 micrometers or less and a width of about 4 micrometers. However, this is an example, and embodiments are not limited thereto. For example, the depth VP-D and the width of each of the valleys VP1 and VP2 may be changed according to the resolution of the display panel DP or product design.

[0172] The taper angle AG1 at which the valley tapered surface VTS is inclined relative to the plane aligned with the valley bottom surface VBS may have a certain angle. The certain angle may be about 70 degrees to about 80 degrees. In the case where the taper angle AG1 is less than about 70 degrees, the reduction degree of the thickness of the intermediate layer CEL and the second electrode CE disposed on the pixel defining layer PDL may be small, and thus the effect of preventing lateral leakage current may be reduced. In the case where the taper angle AG1 exceeds about 80 degrees, the side surfaces of the valleys VP1 and VP2 may have an inverted cone structure, which causes damage such as cracks in the layers disposed above.

[0173] The intermediate layer CEL may be disposed on the first electrode AE ​​and the pixel defining layer PDL. The intermediate layer CEL may include a first functional layer HFL, an emission layer EML, and a second functional layer EFL.

[0174] The first functional layer HFL may include a hole transport layer (HTL), may include a hole injection layer (HIL), or may include both a hole transport layer and a hole injection layer. The first functional layer HFL may be disposed in the entire active region 1000A (refer to Figure 1A Therefore, the first functional layer HFL may be disposed in the opening OP of the pixel defining layer PDL and in the valleys VP1 and VP2 of the pixel defining layer PDL.

[0175] The emission layer EML may be disposed on the first functional layer HFL, and may be disposed in a region overlapping with the opening OP of the pixel defining layer PDL. The emission layer EML may include an organic material, an inorganic material, or an organic-inorganic material that emits light having a certain color. At least a portion of the emission layer EML may be disposed in at least one of the valleys VP1 and VP2. For example, the emission layer EML may be disposed in a second valley VP2 adjacent to the opening OP in which the emission layer EML is disposed. However, embodiments are not limited thereto. For example, the emission layer EML may be disposed not only in an adjacent second valley VP2, but also in a first valley VP1 spaced apart from the opening OP (which overlaps with the emission layer EML), and the second valley VP2 is between the first valley VP1 and the opening OP.

[0176] The second functional layer EFL may be disposed on the first functional layer HFL and may cover the emission layer EML. Therefore, a portion of the second functional layer EFL may be disposed on the emission layer EML. The second functional layer EFL may include an electron transport layer (ETL), may include an electron injection layer (EIL), or may include both an electron transport layer and an electron injection layer. The second functional layer EFL may be disposed in the entire active region 1000A (refer to Figure 1A Therefore, the second functional layer EFL may be disposed in the opening OP of the pixel defining layer PDL and in the valleys VP1 and VP2 of the pixel defining layer PDL.

[0177] The second electrode CE may be disposed on the second functional layer EFL. The second electrode CE may be disposed in the entire active area 1000A (refer to Figure 1A Therefore, the second electrode CE may be disposed in the opening OP of the pixel defining layer PDL and in the valleys VP1 and VP2 of the pixel defining layer PDL.

[0178] In an embodiment, the thickness of the intermediate layer CEL and the thickness of the second electrode CE may be reduced by the valleys VP1 and VP2. The thickness TK2 of the second electrode CE facing the valley tapered surface VTS may be less than the thickness TK1 of the second electrode CE disposed on the flat upper surface of the pixel defining layer PDL. For example, the thickness TKa2 of the intermediate layer CEL facing the valley tapered surface VTS may be less than the thickness TKa1 of the intermediate layer CEL disposed on the flat upper surface of the pixel defining layer PDL. In an embodiment, a portion of the intermediate layer CEL may be cut off at a portion overlapping the valleys VP1 and VP2.

[0179] As the thickness of the intermediate layer CEL and the second electrode CE decreases, the resistance of the intermediate layer CEL and the second electrode CE may increase in a portion overlapping the valleys VP1 and VP2. Therefore, it may be possible to prevent current from leaking into portions where the valleys VP1 and VP2 are formed.

[0180] Reference again Figure 7 , the encapsulation layer 140 may be disposed on the element layer 130. The encapsulation layer 140 may include an organic layer and a plurality of inorganic layers that seal the organic layer. For example, the encapsulation layer 140 may include a first encapsulation layer 141, a second encapsulation layer 142, and a third encapsulation layer 143 that are sequentially stacked on top of each other, but the embodiment is not limited thereto. The first encapsulation layer 141 and the third encapsulation layer 143 may protect the element layer 130 from moisture and oxygen, and the second encapsulation layer 142 may protect the element layer 130 from foreign matter such as dust particles. For example, the first encapsulation layer 141 and the third encapsulation layer 143 may be inorganic encapsulation layers, and the second encapsulation layer 142 may be an organic encapsulation layer.

[0181] The sensor layer 200 may be disposed on the display layer 100. The sensor layer 200 may be referred to as a sensor, an input sensing layer, or an input sensing panel. The sensor layer 200 may have a function of sensing an external input. For example, the sensor layer 200 may sense at least one of an active input through an input device and a passive input through a touch.

[0182] The sensor layer 200 may include a sensor base layer 210 , a first sensor conductive layer 220 , a sensor insulating layer 230 , a second sensor conductive layer 240 , and a sensor cover layer 250 .

[0183] The sensor base layer 210 may be disposed (e.g., directly disposed) on the display layer 100. The sensor base layer 210 may be an inorganic layer including at least one of silicon nitride, silicon oxynitride, and silicon oxide. In another example, the sensor base layer 210 may be an organic layer including epoxy resin, acrylic resin, or imide-based resin. The sensor base layer 210 may have a single-layer structure, or may have a multi-layer structure stacked in the third direction DR3.

[0184] Each of the first sensor conductive layer 220 and the second sensor conductive layer 240 may have a single layer structure, or may have a multi-layer structure stacked in the third direction DR3.

[0185] The conductive layer having a single-layer structure may include a metal layer or a transparent conductive layer. The metal layer may include molybdenum, silver, titanium, copper, aluminum or an alloy thereof. The transparent conductive layer may include a transparent conductive oxide such as indium tin oxide, indium zinc oxide, zinc oxide or indium zinc tin oxide. For example, the transparent conductive layer may include a conductive polymer such as poly (3,4-ethylenedioxythiophene) (PEDOT), a metal nanowire or graphene.

[0186] The conductive layer having a multi-layer structure may include a metal layer. The metal layer may have a three-layer structure of, for example, titanium / aluminum / titanium. The conductive layer having a multi-layer structure may include at least one metal layer and at least one transparent conductive layer.

[0187] The sensor insulating layer 230 may be disposed between the first sensor conductive layer 220 and the second sensor conductive layer 240. The sensor cover layer 250 may be disposed on the sensor insulating layer 230 and may cover the second sensor conductive layer 240. The second sensor conductive layer 240 may include a conductive pattern. The sensor cover layer 250 may cover the conductive pattern and may reduce or eliminate the possibility of damage to the conductive pattern in subsequent processes.

[0188] Each of the sensor insulating layer 230 and the sensor cover layer 250 may include an inorganic film. The inorganic film may include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon nitride, silicon oxynitride, zirconium oxide, and hafnium oxide.

[0189] In another example, each of the sensor insulating layer 230 and the sensor cover layer 250 may include an organic film. The organic film may include at least one of acrylic resin, methacrylic resin, polyisoprene resin, vinyl resin, epoxy resin, urethane-based resin, cellulose resin, siloxane-based resin, polyimide resin, polyamide resin, and perylene-based resin.

[0190] Figure 8B FIG. 2 is a diagram showing a display panel DP (refer to FIG. 2 ) according to an embodiment. Figure 1A ) is an enlarged schematic cross-sectional view of a portion of ). Figure 8B According to the implementation method Figure 7 Schematic cross-sectional view of the area AA′ shown in .

[0191] refer to Figure 7 and Figure 8B , valleys VP1a and VP2a overlapping the non-emission area NPXA may be defined in the pixel defining layer PDL. Each of the valleys VP1a and VP2a may be defined by a valley bottom surface VBSa and a valley tapered surface VTSa. The valley bottom surface VBSa and the valley tapered surface VTSa may be connected to each other.

[0192] The taper angle AG2 at which the valley tapered surface VTSa is inclined relative to a plane aligned with the valley bottom surface VBSa may have a certain angle, which may be about 70 degrees to about 80 degrees.

[0193] In an embodiment, the thickness of the intermediate layer CEL and the thickness of the second electrode CE may be reduced by the valleys VP1a and VP2a. A portion of the intermediate layer CEL may be cut off at a portion overlapping the valleys VP1a and VP2a. As the thickness of the intermediate layer CEL and the second electrode CE decreases, the resistance of the intermediate layer CEL and the second electrode CE may increase in a portion overlapping the valleys VP1a and VP2a. Therefore, current leakage into a portion where the valleys VP1a and VP2a are formed may be prevented.

[0194] Fig. 9 The display panel DP according to the embodiment (refer to Figure 1A ) is a portion of an image. Fig. 9 The image shown in is an image of a portion of the pixel defining layer PDL where a valley surface VBS is defined.

[0195] refer to Figure 7 and Fig. 9 , the pixel defining layer PDL may include a black colorant. The black colorant may include carbon black, a metal such as chromium, or an oxide thereof. For example, in the case where the pixel defining layer PDL is etched to form the valleys VP1 and VP2, an uneven surface may be formed by the black colorant.

[0196] Fig.10 FIG. 2 is a diagram showing a display panel DP (refer to FIG. 2 ) according to an embodiment. Figure 1A ) is an enlarged schematic plan view of a portion of ). Fig.10 It is shown Figure 1A An enlarged schematic cross-sectional view of the area BB′ shown in FIG.

[0197] refer to Figure 1A , Figure 7 and Fig.10 , the hole HA may be defined in the display panel DP. The hole HA may be defined by removing a portion of the display panel DP. The active area 1000A of the display panel DP may surround the hole HA. The hole HA may overlap or correspond to the sensor area SA1. Although the hole HA is shown as a circular shape in the embodiment, the hole HA may have various shapes, such as a polygonal shape, an elliptical shape, a shape having at least one curved side, or an irregular shape, and is not limited to any one embodiment.

[0198] The hole HA may be formed in the display layer 100 (refer to Figure 3 ) and sensor layer 200 (reference Figure 3 ) are formed after both. In another example, the hole HA may be formed after the display layer 100 is formed. For example, the process of forming the hole HA may include forming a hole HA to the base layer 110 (reference Figure 3) and a process of providing an etchant toward the rear surface of the base layer 110. The process of applying laser may be a process of drawing a region to be removed on the base layer 110. The etchant may be provided in a direction from the rear surface to the upper surface of the base layer 110 along a third direction DR3.

[0199] The display panel DP may further include dams DM1, DM2, DM3, DM4, and DM5 adjacent to the hole HA. The dams DM1, DM2, DM3, DM4, and DM5 may control the flow of the monomer during the process of forming the second encapsulation layer 142 or protect the element layer 130 during the process of forming the hole HA. Fig.10 2 , five dams DM1 , DM2 , DM3 , DM4 , and DM5 are shown as an example, but the embodiment is not limited thereto. Some of the five dams DM1 , DM2 , DM3 , DM4 , and DM5 may be omitted, or more dams may be provided.

[0200] Fig.11A is a schematic cross-sectional view of a display panel DP according to an embodiment. For example, Fig.11A Can be along Fig.10 A schematic cross-sectional view taken along line II-II'.

[0201] refer to Figure 7 and Fig.11A , the display panel DP may include a sidewall DP-HS defining the hole HA. The display panel DP may include dams DM1, DM2, DM3, DM4, and DM5 adjacent to the hole HA and an inorganic dam IOP. Fig.11A 5 dams DM1, DM2, DM3, DM4 and DM5 and three inorganic dams IOP are shown as examples, but the embodiment is not limited thereto. Some of the five dams DM1, DM2, DM3, DM4 and DM5 and the three inorganic dams IOP may be omitted, or more dams may be provided.

[0202] The dams DM1, DM2, DM3, DM4, and DM5 may include a first dam DM1, a second dam DM2, a third dam DM3, a fourth dam DM4, and a fifth dam DM5. The first dam DM1, the second dam DM2, the third dam DM3, and the fourth dam DM4 may control the flow of the monomer during the process of forming the second encapsulation layer 142. The fifth dam DM5 and the inorganic dam IOP may prevent the propagation of cracks developed from the sidewall DP-HS. Therefore, the fifth dam DM5 may be referred to as a crack dam. The inorganic dam IOP may be referred to as an inorganic pattern.

[0203] Among the first dam DM1, the second dam DM2, the third dam DM3, the fourth dam DM4, and the fifth dam DM5, the first dam DM1 and the fourth dam DM4 may have the largest height (or thickness). For example, each of the first dam DM1 and the fourth dam DM4 may include a first conductive layer MP1, a second insulating layer 20, a second conductive layer MP2, a third insulating layer 30, a third conductive layer MP3, a first dam layer DMLa, a fourth conductive layer MP4, a second dam layer DMLb, and a third dam layer DMLc.

[0204] The first conductive layer MP1, the first gate electrode E13 of the first thin film transistor T1, the second gate electrode E23 of the second thin film transistor T2, the first counter electrode Cs1 of the transfer capacitor Cst, and the first holding opposite electrode Ch1 of the holding capacitor Chold may be disposed on the same layer. The first conductive layer MP1, the first gate electrode E13 of the first thin film transistor T1, the second gate electrode E23 of the second thin film transistor T2, the first counter electrode Cs1 of the transfer capacitor Cst, and the first holding opposite electrode Ch1 of the holding capacitor Chold may include the same material.

[0205] The second conductive layer MP2, the second counter electrode Cs2 of the transfer capacitor Cst, and the second holding opposite electrode Ch2 of the holding capacitor Chold may be disposed on the same layer. The second conductive layer MP2, the second counter electrode Cs2 of the transfer capacitor Cst, and the second holding opposite electrode Ch2 of the holding capacitor Chold may include the same material.

[0206] The third conductive layer MP3 and the first connection electrode CNE10 may be disposed on the same layer and may include the same material. The fourth conductive layer MP4 and the second connection electrode CNE20 may include the same material as the second connection electrode CNE20 and may be disposed on the same layer.

[0207] The first dam layer DMLa and the fourth insulating layer 40 may include the same material. The first dam layer DMLa may be a part of the fourth insulating layer 40. The second dam layer DMLb and the fifth insulating layer 50 may include the same material. The second dam layer DMLb may be a part of the fifth insulating layer 50. The third dam layer DMLc and the pixel defining layer PDL may be disposed on the same layer and may include the same material.

[0208] The second dam DM2 and the third dam DM3 may have a height or thickness smaller than that of the first dam DM1 and the fourth dam DM4. For example, each of the second dam DM2 and the third dam DM3 may include a first conductive layer MP1, a second insulating layer 20, a second conductive layer MP2, a third insulating layer 30, a third conductive layer MP3, a first dam layer DMLa, a fourth conductive layer MP4, and a second dam layer DMLb.

[0209] In an embodiment, the fourth conductive layer MP4 of each of the first dam DM1, the second dam DM2, the third dam DM3, and the fourth dam DM4 may be in contact with the third conductive layer MP3. For example, the continuity of the fourth insulating layer 40 may be destroyed by the third conductive layer MP3 and the fourth conductive layer MP4 in contact with each other. Therefore, the path along which the etchant can penetrate when the hole HA is processed may be shielded by the first dam DM1, the second dam DM2, the third dam DM3, and the fourth dam DM4.

[0210] Among the first dam DM1, the second dam DM2, the third dam DM3, the fourth dam DM4 and the fifth dam DM5, the fifth dam DM5 may be disposed closest to the hole HA. The fifth dam DM5 may include a second insulating layer 20, a third insulating layer 30, a third conductive layer MP3-1, a first dam layer DMLa, a fourth conductive layer MP4-1 and a second dam layer DMLb.

[0211] In an embodiment, the fourth conductive layer MP4-1 of the fifth dam DM5 may be in contact with the third conductive layer MP3-1. For example, the continuity of the fourth insulating layer 40 may be destroyed (or disconnected) by the third conductive layer MP3-1 and the fourth conductive layer MP4-1 in contact with each other. Therefore, the path along which the etchant can penetrate when the hole HA is processed may be additionally shielded by the fifth dam DM5. Therefore, the reliability of the display panel DP may be further improved.

[0212] In an embodiment, each of the inorganic dams IOP may include a first dam layer IL1 and a second dam layer IL2. The first dam layer IL1 and the second insulating layer 20 may include the same material and may be formed by the same process. The second dam layer IL2 and the third insulating layer 30 may include the same material and may be formed by the same process. However, this is an example, and the configuration of the layers constituting each of the inorganic dams IOP may be changed in various ways. The width of the first dam layer IL1 may be greater than the width of the second dam layer IL2. Therefore, each of the inorganic dams IOP may have a step shape.

[0213] The first groove GV1, the second groove GV2, the third groove GV3, the fourth groove GV4 and the fifth groove V5 may be defined as being adjacent to the first dam DM1, the second dam DM2, the third dam DM3, the fourth dam DM4 and the fifth dam DM5. The first groove GV1 and the second groove GV2 may be spaced apart from each other, and the first dam DM1 is between the first groove GV1 and the second groove GV2. The second groove GV2 and the third groove GV3 may be spaced apart from each other, and the second dam DM2 is between the second groove GV2 and the third groove GV3. The third groove GV3 and the fourth groove GV4 may be spaced apart from each other, and the third dam DM3 is between the third groove GV3 and the fourth groove GV4. The fourth groove GV4 and the fifth groove GV5 may be spaced apart from each other, and the fourth dam DM4 is between the fourth groove GV4 and the fifth groove GV5.

[0214] In an embodiment, the first groove GV1, the second groove GV2, the third groove GV3, the fourth groove GV4 and the fifth groove V5 can be formed by forming valleys VP1, VP2 and VP3 (refer to Figure 6 ). Therefore, an additional process for forming the first groove GV1, the second groove GV2, the third groove GV3, the fourth groove GV4, and the fifth groove GV5 may be omitted. For example, the number of masks used during the process of forming the display panel DP may be reduced, and the manufacturing cost of the display panel DP may be reduced.

[0215] In an embodiment, the first groove GV1, the second groove GV2, the third groove GV3, the fourth groove GV4 and the fifth groove V5 may be formed by the same process as the valleys VP1, VP2 and VP3. Therefore, the depths of the first groove GV1, the second groove GV2, the third groove GV3, the fourth groove GV4 and the fifth groove V5 may be determined according to the depths of the valleys VP1, VP2 and VP3. For example, the bottom surfaces of the first groove GV1, the second groove GV2, the third groove GV3, the fourth groove GV4 and the fifth groove V5 may be defined in the fourth insulating layer 40.

[0216] Since the depths of the first groove GV1, the second groove GV2, the third groove GV3, the fourth groove GV4, and the fifth groove V5 are not controlled by a separate process but are determined according to the depths of the valleys VP1, VP2, and VP3, the depths of the first groove GV1, the second groove GV2, the third groove GV3, the fourth groove GV4, and the fifth groove V5 may be less than the maximum thickness of the fourth insulating layer 40. To compensate for this, each of the first dam DM1, the second dam DM2, the third dam DM3, and the fourth dam DM4 may have a double-wing structure including a tip portion protruding in opposite directions. As many tip portions as possible may be provided, and thus the common layer CCL may be stably disconnected. Therefore, the reliability of the display panel DP may be further improved.

[0217] For example, each of the first dam DM1, the second dam DM2, the third dam DM3, and the fourth dam DM4 may be disposed between the first groove GV1, the second groove GV2, the third groove GV3, the fourth groove GV4, and the fifth groove V5. The number of the tip portions may be twice or more the number of the first dam DM1, the second dam DM2, the third dam DM3, and the fourth dam DM4. Therefore, the number of the tip portions may be 8 or more.

[0218] In an embodiment, the display panel DP may include tip portions TP1, TP2, TP3, TP4, TP5, TP6, TP7, TP8, TP9, and TP10. A first groove GV1, a second groove GV2, a third groove GV3, a fourth groove GV4, and a fifth groove V5 may be provided to form at least some of the tip portions TP1, TP2, TP3, TP4, TP5, TP6, TP7, TP8, TP9, and TP10. Therefore, the shapes of the tip portions TP1, TP2, TP3, TP4, TP5, TP6, TP7, TP8, TP9, and TP10 in a plan view may be similar to the shapes of the first groove GV1, the second groove GV2, the third groove GV3, the fourth groove GV4, and the fifth groove V5 in a plan view. Each of the tip portions TP1, TP2, TP3, TP4, TP5, TP6, TP7, TP8, TP9, and TP10 may have a shape surrounding the hole HA (see Fig.10 For example, the third tip portion TP3 may have a shape surrounding the hole HA, and the second tip portion TP2 may have a shape surrounding the third tip portion TP3.

[0219] The tip portions TP1, TP2, TP3, TP4, TP5, TP6, TP7, TP8, TP9, and TP10 may disconnect the common layer CCL formed with the opening mask. For example, the common layer CCL may include a first functional layer HFL, a second functional layer EFL, and a second electrode CE. A portion of the common layer CCL disconnected by the tip portions TP1, TP2, TP3, TP4, TP5, TP6, TP7, TP8, TP9, and TP10 (e.g., a disconnected layer GCP) may overlap the first groove GV1, the second groove GV2, the third groove GV3, the fourth groove GV4, and the fifth groove V5.

[0220] The first tip portion TP1 and the second tip portion TP2 may overlap the first groove GV1. The third tip portion TP3 and the fourth tip portion TP4 may overlap the second groove GV2. The fifth tip portion TP5 and the sixth tip portion TP6 may overlap the third groove GV3. The seventh tip portion TP7 and the eighth tip portion TP8 may overlap the fourth groove GV4. The ninth tip portion TP9 may overlap the fifth groove GV5. The tenth tip portion TP10 may protrude from the fifth dam DM5 in a direction toward the hole HA.

[0221] The first encapsulation layer 141 may cover all of the first groove GV1, the second groove GV2, the third groove GV3, the fourth groove GV4, and the fifth groove V5. The second encapsulation layer 142 may be disposed on the first encapsulation layer 141 and may overlap at least some of the first groove GV1, the second groove GV2, the third groove GV3, the fourth groove GV4, and the fifth groove V5. For example, the second encapsulation layer 142 may overlap the first groove GV1, the second groove GV2, the third groove GV3, and the fourth groove GV4. The third encapsulation layer 143 may be disposed on the second encapsulation layer 142 and may cover all of the first groove GV1, the second groove GV2, the third groove GV3, the fourth groove GV4, and the fifth groove V5.

[0222] In an embodiment, the first sensor conductive layer 220 of the sensor layer 200 may include a first cover pattern 220cp, and the second sensor conductive layer 240 of the sensor layer 200 may include a second cover pattern 240cp. Each of the first cover pattern 220cp and the second cover pattern 240cp may overlap with the remaining groove (e.g., the fifth groove GV5) that does not overlap with the second encapsulation layer 142. For example, each of the first cover pattern 220cp and the second cover pattern 240cp may overlap with the fifth dam DM5 (referred to as a crack dam) and the tenth tip portion TP10 protruding from the fifth dam DM5 toward the hole HA.

[0223] The flexure of the third encapsulation layer 143 may increase due to the fifth groove GV5 in which the second encapsulation layer 142 is not disposed. For example, the film quality of the third encapsulation layer 143 may deteriorate due to the flexure, and thus the third encapsulation layer 143 may be broken. In another example, even if the third encapsulation layer 143 includes silicon nitride, the third encapsulation layer 143 may be oxidized.

[0224] According to an embodiment, the first cover pattern 220cp and the second cover pattern 240cp may be disposed in a region overlapping the fifth groove GV5. Therefore, even if the third encapsulation layer 143 is cracked or oxidized, moisture and oxygen may be blocked by the first cover pattern 220cp and the second cover pattern 240cp. Therefore, the product reliability of the display panel DP may be improved.

[0225] Fig. 11B is a schematic cross-sectional view of a display panel DPa according to an embodiment. Fig. 11B When, with reference Fig.11A The same components as those described will be given the same reference numerals, and description thereof will be omitted for the convenience of description.

[0226] refer to Figure 7 and Fig. 11B , the first sensor conductive layer 220 of the sensor layer 200 may include a first covering pattern 220cp. The first covering pattern 220cp may overlap with the remaining grooves (e.g., the fifth groove GV5) that do not overlap with the second encapsulation layer 142. For example, the first covering pattern 220cp may overlap with the fifth dam DM5 (referred to as a crack dam) and the tenth tip portion TP10 protruding from the fifth dam DM5 toward the hole HA. Therefore, even if the third encapsulation layer 143 is cracked or oxidized, moisture and oxygen may be blocked by the first covering pattern 220cp. Therefore, the product reliability of the display panel DPa may be improved.

[0227] Fig. 11C is a schematic cross-sectional view of a display panel DPb according to an embodiment. Fig. 11C When, with reference Fig.11A The same components as those described above will be given the same reference numerals, and description thereof will be omitted for the convenience of description.

[0228] refer to Figure 7 and Fig. 11C, the second sensor conductive layer 240 of the sensor layer 200 may include a second covering pattern 240cp. The second covering pattern 240cp may overlap with the remaining grooves (e.g., the fifth groove GV5) that do not overlap with the second encapsulation layer 142. For example, the second covering pattern 240cp may overlap with the fifth dam DM5 (referred to as a crack dam) and the tenth tip portion TP10 protruding from the fifth dam DM5 toward the hole HA. Therefore, even if the third encapsulation layer 143 is cracked or oxidized, moisture and oxygen may be blocked by the second covering pattern 240cp. Therefore, the product reliability of the display panel DPb may be improved.

[0229] Fig. 12A The display panel DP according to the embodiment (refer to Fig.11A ) is a schematic cross-sectional view of the . Fig. 12A It is shown Fig.11A For example, Fig. 12A 2 is an enlarged schematic cross-sectional view showing a region defined with the second groove GV2. The following description may be equally applied to the first groove GV1, the third groove GV3, and the fourth groove GV4.

[0230] refer to Fig. 8A , Fig.11A and Fig. 12A Each of the third conductive layer MP3 and the fourth conductive layer MP4 may have a multi-layer structure. For example, each of the third conductive layer MP3 and the fourth conductive layer MP4 may have a three-layer structure of titanium (Ti) / aluminum (Al) / titanium (Ti).

[0231] The third conductive layer MP3 may include a first sub-conductive layer MP3a, a second sub-conductive layer MP3b, and a third sub-conductive layer MP3c. The fourth conductive layer MP4 may include a first sub-conductive layer MP4a, a second sub-conductive layer MP4b, and a third sub-conductive layer MP4c. The first sub-conductive layer MP3a, the third sub-conductive layer MP3c, the first sub-conductive layer MP4a, and the third sub-conductive layer MP4c may include titanium, and the second sub-conductive layer MP3b and the second sub-conductive layer MP4b may include aluminum. However, the embodiment is not limited thereto.

[0232] In an embodiment, the first side surface S1 of the first subconductive layer MP4a, the second side surface S2 of the second subconductive layer MP4b, and the third side surface S3 of the third subconductive layer MP4c defining the side surface SS of each of the third and fourth tip portions TP3 and TP4 may be aligned with each other.

[0233] The shapes of the first side surface S1, the second side surface S2, and the third side surface S3 may vary according to the components of the etchant used in the process of forming the first electrode AE ​​(e.g., the process of subjecting the first electrode AE ​​to patterning) or the materials of the first sub-conductive layer MP4a, the second sub-conductive layer MP4b, and the third sub-conductive layer MP4c. For example, the etchant may include a non-phosphoric acid-based etching composition. For example, the first side surface S1, the second side surface S2, and the third side surface S3 may have aligned shapes.

[0234] In an embodiment, the bottom surface GV-B of the second groove GV2 and the side surface GV-S connected to the bottom surface GV-B may be defined by a single insulating layer (e.g., a fourth insulating layer 40). The fourth insulating layer 40 may be an organic insulating layer. The second groove GV2 and the valleys VP1 and VP2 may be formed by the same process. Therefore, the shape of the second groove GV2 may be similar to the shapes of the valleys VP1 and VP2. The side surface GV-S of the second groove GV2 may include a curved surface GV-C extending from the bottom surface GV-B and a tapered surface GV-T extending from the curved surface GV-C. For example, the radius of curvature of the curved surface GV-C may be about 100 nm to about 230 nm, but embodiments are not limited thereto.

[0235] The cone angle AG1 at which the valley cone surface VTS is inclined relative to the plane aligned with the valley bottom surface VBS may be substantially the same as the angle AG3 of the cone surface GV-T relative to the plane aligned with the bottom surface GV-B. For example, the angle AG3 of the cone surface GV-T may be about 70 degrees to about 80 degrees, but the embodiment is not limited thereto.

[0236] In an embodiment, the depths of the first groove GV1, the second groove GV2, the third groove GV3, the fourth groove GV4, and the fifth groove V5 may be determined according to the depth VP-D of the valleys VP1 and VP2. For example, the depth VP-D of the valleys VP1 and VP2 may be substantially the same as the height TP-H of the fourth tip portion TP4, which is measured from the bottom surface GV-B of the second groove GV2 to the bottom surface of the fourth tip portion TP4.

[0237] In an embodiment, the difference between the width TP-W and the height TP-H of the fourth tip portion TP4 may be less than about 0.15 microns, and may be, for example, about 0.05 microns. The width TP-W of the fourth tip portion TP4 may correspond to the width of the exposed lower surface of the fourth conductive layer MP4. For example, the width TP-W of the fourth tip portion TP4 may be about 0.4 microns or less, and the height TP-H of the fourth tip portion TP4 may be about 0.45 microns or less. For example, the width TP-W of the fourth tip portion TP4 may be about 0.4 microns, and the height TP-H of the fourth tip portion TP4 may be about 0.45 microns. However, this is an example, and embodiments are not limited thereto.

[0238] The common layer CCL may be formed on the third tip portion TP3, the fourth tip portion TP4, the fifth insulating layer 50, and the fourth insulating layer 40 in which the second groove GV2 is defined. The common layer CCL may be disconnected by the third tip portion TP3 and the fourth tip portion TP4. Therefore, the disconnected layer GCP may be disposed in the second groove GV2. The disconnected layer GCP may include a first disconnected layer HFLp, a second disconnected layer EFLp, and a third disconnected layer CEp. The first disconnected layer HFLp ​​and the first functional layer HFL may include the same material. The second disconnected layer EFLp and the second functional layer EFL may include the same material. The third disconnected layer CEp and the second electrode CE may include the same material.

[0239] The first encapsulation layer 141 may be disposed on the common layer CCL. The first encapsulation layer 141 may be formed by a deposition process (e.g., a chemical vapor deposition (CVD)) process. In an embodiment, the first encapsulation layer 141 may be formed to correspond to the shapes of the third tip portion TP3 and the fourth tip portion TP4. For example, a thickness 141-t2 of a portion of the first encapsulation layer 141 disposed under the third tip portion TP3 and the fourth tip portion TP4 may be less than a thickness 141-t1 of a portion of the first encapsulation layer 141 disposed on the third tip portion TP3 and the fourth tip portion TP4.

[0240] Fig. 12B The display panel DP according to the embodiment (refer to Fig.11A ) is a schematic cross-sectional view of the .

[0241] refer to Figure 8B and Fig. 12B The fourth conductive layer MP4 may have a multi-layer structure. For example, the fourth conductive layer MP4 may include a first sub-conductive layer MP4a, a second sub-conductive layer MP4b, and a third sub-conductive layer MP4c.

[0242] In an embodiment, the first side surface S1a of the first subconductive layer MP4a, the second side surface S2a of the second subconductive layer MP4b, and the third side surface S3a of the third subconductive layer MP4c defining the side surface SSa of each of the third tip portion TP3a ​​and the fourth tip portion TP4a may not be aligned with each other. For example, the second side surface S2a may have a shape that is recessed relative to (or from) the first side surface S1a and the third side surface S3a.

[0243] The shapes of the first side surface S1a, the second side surface S2a, and the third side surface S3a may vary according to the composition of the etchant used in the process of forming the first electrode AE ​​or the materials of the first sub-conductive layer MP4a, the second sub-conductive layer MP4b, and the third sub-conductive layer MP4c. For example, the etchant may include a phosphoric acid-based etching composition, the first sub-conductive layer MP4a and the third sub-conductive layer MP4c may include titanium, and the second sub-conductive layer MP4b may include aluminum.

[0244] In an implementation, a bottom surface GV-B of the second groove GV2 and a side surface GV-Sa connected to the bottom surface GV-B may be defined (or formed) by an insulating layer (or a single layer, for example, the fourth insulating layer 40). The fourth insulating layer 40 may be an organic insulating layer.

[0245] The second groove GV2 and the valleys VP1a and VP2a may be formed by the same process. Therefore, the shape of the second groove GV2 may be similar to the shape of the valleys VP1a and VP2a. For example, the taper angle AG2 at which the valley tapered surface VTSa is inclined relative to the plane aligned with the valley bottom surface VBS may be substantially the same as the angle AG4 of the side surface GV-Sa relative to the plane aligned with the bottom surface GV-B.

[0246] Fig. 12C The display panel DP according to the embodiment (refer to Fig.11A ) is a schematic cross-sectional view of the .

[0247] refer to Figure 8B and Fig. 12C The fourth conductive layer MP4 may have a multi-layer structure. For example, the fourth conductive layer MP4 may include a first sub-conductive layer MP4a, a second sub-conductive layer MP4b, and a third sub-conductive layer MP4c.

[0248] In an embodiment, the first side surface S1b of the first subconductive layer MP4a, the second side surface S2b of the second subconductive layer MP4b, and the third side surface S3b of the third subconductive layer MP4c defining the side surface SSb of each of the third tip portion TP3b and the fourth tip portion TP4b may not be aligned with each other. For example, the second side surface S2b may have a shape protruding relative to (or from) the first side surface S1b and the third side surface S3b.

[0249] Fig.13 The display panel DP according to the embodiment (refer to Figure 1A ) is a portion of an image.

[0250] refer to Fig. 12A and Fig.13 , a thickness 141-t2 of a portion of the first encapsulation layer 141 disposed under the third tip portion TP3 and the fourth tip portion TP4 may be smaller than a thickness 141-t1 of a portion of the first encapsulation layer 141 disposed on the third tip portion TP3 and the fourth tip portion TP4. Therefore, a certain space 141sp may be defined in a region under each of the third tip portion TP3 and the fourth tip portion TP4 by the first encapsulation layer 141. The space 141sp may be filled with a material of the second encapsulation layer 142.

[0251] Fig.14 is a schematic cross-sectional view of a display panel DPc according to an embodiment. Fig.14 When, with reference Fig.11A The same components as those described will be given the same reference numerals, and description thereof will be omitted for the convenience of description.

[0252] refer to Fig.14 , the display panel DPc may further include a cover layer YOC. The cover layer YOC may be disposed on the third encapsulation layer 143. The cover layer YOC may be a layer provided to improve a step of an area adjacent to the hole HA. The cover layer YOC may include an organic material, but the embodiment is not limited thereto. The cover layer YOC may be referred to as a compensation layer, a step compensation layer, a planarization layer, or a partial planarization layer.

[0253] The sensor layer 200 may be disposed on the cover layer YOC. The cover layer YOC may be disposed in a region adjacent to the hole HA to provide a flat base surface. Therefore, the sensor layer 200 may be easily formed on a flat surface.

[0254] Fig.15 is a schematic cross-sectional view of a display panel DPd according to an embodiment. Fig.15 When, with reference Fig.11AThe same components as those described will be given the same reference numerals, and description thereof will be omitted for the convenience of description.

[0255] refer to Fig.15 The display panel DPd may include dams DM1, DM2, DM3, DM4, and DM5a adjacent to the hole HA and the inorganic dam IOP. The dams DM1, DM2, DM3, DM4, and DM5a may include a first dam DM1, a second dam DM2, a third dam DM3, a fourth dam DM4, and a fifth dam DM5a.

[0256] Among the first dam DM1, the second dam DM2, the third dam DM3, the fourth dam DM4 and the fifth dam DM5a, the fifth dam DM5a may be disposed closest to the hole HA. The fifth dam DM5a may include a second insulating layer 20, a third insulating layer 30, a third conductive layer MP3-2, a first dam layer DMLa, a fourth conductive layer MP4-2 and a second dam layer DMLb.

[0257] In an embodiment, the fourth conductive layer MP4-2 of the fifth dam DM5a may not contact the third conductive layer MP3-2. Therefore, in the area where the fifth dam DM5a is provided, the continuity of the fourth insulating layer 40 may not be destroyed. The tenth tip portion TP10 protruding toward the hole HA may be provided in the fifth dam DM5a. The tenth tip portion TP10 may prevent the crack developed from the side wall DP-HS from propagating into the display panel DPd. Therefore, the fifth dam DM5 may be referred to as a crack dam.

[0258] Fig.16 is a schematic cross-sectional view of a display panel DPe according to an embodiment. Fig.16 When, with reference Fig.11A The same components as those described will be given the same reference numerals, and description thereof will be omitted for the convenience of description.

[0259] refer to Fig.16 , the display panel DPe may include dams DM1, DM2, DM3, DM4, and DM5 adjacent to the hole HA. Fig.11A Compared with the display panel DP of FIG. 1 , the display panel DPe may not include the inorganic dam IOP. Since the inorganic dam IOP is omitted, the area of ​​the non-display region around the hole HA may be reduced. For example, since the inorganic dam IOP is omitted, the process may be simplified.

[0260] Fig.17 is a schematic cross-sectional view of a display panel DPf according to an embodiment. Fig.17 When, with reference Fig.11A The same components as those described will be given the same reference numerals, and description thereof will be omitted for the convenience of description.

[0261] refer to Fig.17 The display panel DPf may include dams DM1, DM2a, DM3a, DM4 and DM5 adjacent to the hole HA and the inorganic dam IOP. The dams DM1, DM2a, DM3a, DM4 and DM5 may include a first dam DM1, a second dam DM2a, a third dam DM3a, a fourth dam DM4 and a fifth dam DM5.

[0262] Each of the first dam DM1, the second dam DM2a, the third dam DM3a, and the fourth dam DM4 may be disposed between the grooves. In an embodiment, among the first dam DM1, the second dam DM2a, the third dam DM3a, and the fourth dam DM4, the first dam DM1 and the fourth dam DM4 may have the largest height (or thickness). The second dam DM2a and the third dam DM3a may have a smaller height or thickness than the first dam DM1 and the fourth dam DM4.

[0263] In an embodiment, each of the first dam DM1 and the fourth dam DM4 may have a double-wing structure including a tip portion protruding in opposite directions. The second dam DM2a and the third dam DM3a may have a single-wing structure including a tip portion protruding in one direction. Fig.11A The display panel DPf may not include the fifth tip portion TP5 and the seventh tip portion TP7 when compared with the display panel DP. However, this is an example, and one of the second dam DM2a and the third dam DM3a may have a double-wing structure including tip portions protruding in opposite directions, and the other of the second dam DM2a and the third dam DM3a may have a single-wing structure.

[0264] Fig.18 FIG. 2 is a diagram showing a display panel DPf (refer to FIG. 2 ) according to an embodiment. Fig.17 ) is an enlarged schematic cross-sectional view of a portion of the . For example, Fig.18 It is shown Fig.17 An enlarged schematic cross-sectional view of the region DD′ shown in FIG.

[0265] refer to Fig.17 and Fig.18 , the disconnected layer GCPa may be disposed in the fifth groove GV5. The disconnected layer GCPa may be disconnected by the ninth tip portion TP9 and may extend over the fifth dam DM5.

[0266] The first encapsulation layer 141 may cover the fifth groove GV5. A certain space 141spa may be defined below the ninth tip portion TP9. The space 141spa may have an open structure that is not completely closed by the first encapsulation layer 141.

[0267] During the process of forming the second encapsulation layer 142 , a monomer may or may not be disposed in the region defining the fifth groove GV5 . Therefore, the space 141 spa may or may not be filled with the material of the second encapsulation layer 142 .

[0268] although Fig.18 An example is shown in which the space 141spa is filled with the material of the third encapsulation layer 143, but the embodiment is not limited thereto. For example, the space 141spa may have a structure completely enclosed by the first encapsulation layer 141 and the third encapsulation layer 143. In the case where the space 141spa has a structure enclosed by the first encapsulation layer 141 and the third encapsulation layer 143, the space 141spa may contain a gas used during the process of forming the first encapsulation layer 141, or may be in a vacuum state.

[0269] According to an embodiment, the first cover pattern 220cp and the second cover pattern 240cp may be disposed in an area overlapping the fifth groove GV5. Therefore, even if the third encapsulation layer 143 is cracked or oxidized, moisture and oxygen may be blocked by the first cover pattern 220cp and the second cover pattern 240cp. Therefore, the product reliability of the display panel DPf may be improved.

[0270] Fig.19 FIG. 2 is a diagram showing a display panel DPf (refer to FIG. 2 ) according to an embodiment. Fig.17 ) is an enlarged schematic cross-sectional view of a portion of the . For example, Fig.19 It is shown Fig.17 An enlarged schematic cross-sectional view of the region DD' shown in FIG. Fig.19 When, with reference Fig.18 The same components as those described will be given the same reference numerals, and description thereof will be omitted for the convenience of description.

[0271] refer to Fig.17 and Fig.19 , the first encapsulation layer 141 may cover the fifth groove GV5. A certain space 141spb may be defined below the ninth tip portion TP9. The space 141spb may have a structure that is completely enclosed by the first encapsulation layer 141. For example, another material (e.g., a material of the second encapsulation layer 142 or a material of the third encapsulation layer 143) may not be disposed in the space 141spb. For example, the space 141spb may contain a gas used during the process of forming the first encapsulation layer 141, or may be in a vacuum state.

[0272] Fig. 20A , Fig. 20B , Fig.21A , Fig.21B , Fig.22A , Fig. 22B , Fig.23A , Fig. 23B , Fig.24A and Fig. 24B are schematic cross-sectional views showing some steps of a display panel manufacturing process according to an embodiment.

[0273] Fig. 20A , Fig.21A , Fig.22A , Fig.23A and Fig.24A is a cross-sectional view illustrating a process of forming a valley VP in the preliminary pixel defining layer PDL-bf (eg, in an upper surface of the preliminary pixel defining layer PDL-bf). Fig. 20B , Fig.21B , Fig. 22B , Fig. 23B and Fig. 24B is a schematic cross-sectional view showing a process of forming a second groove GV2 in the preliminary insulating layer 40 - bf (eg, in the upper surface of the preliminary insulating layer 40 - bf). The following description may also apply to the first groove GV1, the third groove GV3, and the fourth groove GV4 described above.

[0274] exist Fig. 20A and Fig. 20B , the region corresponding to the region AA' and the region corresponding to the region CC' placed in the same process are shown. Fig. 20A , a first electrode AE ​​may be formed on the fifth insulating layer 50, and a preliminary pixel defining layer PDL-bf may be formed on the first electrode AE. Fig. 20B , defining a third tip portion TP3 and a fourth tip portion TP4 that are not covered by the fifth insulating layer 50. A portion of the preliminary insulating layer 40-bf is exposed between the third tip portion TP3 and the fourth tip portion TP4. The preliminary insulating layer 40-bf is formed with the fourth insulating layer 40 (refer to Fig.11A ) corresponding layer.

[0275] refer to Fig.21A and Fig.21B , the mask layer MP may cover the first electrode AE, the preliminary pixel defining layer PDL-bf, the fifth insulating layer 50, the third tip portion TP3, and the fourth tip portion TP4. The mask layer MP may have a first opening MP-OP1 and a second opening MP-OP2 defined therein. The first opening MP-OP1 may overlap the preliminary pixel defining layer PDL-bf, and the second opening MP-OP2 may overlap a portion of the preliminary insulating layer 40-bf, a portion of the third tip portion TP3, and a portion of the fourth tip portion TP4. The mask layer MP may include indium gallium zinc oxide (IGZO), but the embodiment is not limited thereto.

[0276] In an embodiment, the sidewall of the mask layer MP defining the second opening MP-OP2 may be spaced apart from the end portions of the third and fourth tip portions TP3 and TP4. For example, the upper surfaces of the third and fourth tip portions TP3 and TP4 may be exposed by at least 0.5 micrometers or more.

[0277] refer to Fig.22A and Fig. 22B , the first etching EC1 may be performed on the preliminary pixel defining layer PDL-bf and the preliminary insulating layer 40-bf at the same time. The first etching EC1 may be dry etching, and may be anisotropic etching with a specific orientation. Grooves having substantially the same depth may be formed in the preliminary pixel defining layer PDL-bf and the preliminary insulating layer 40-bf (e.g., in the upper surfaces of the preliminary pixel defining layer PDL-bf and the preliminary insulating layer 40-bf) by the first etching EC1.

[0278] refer to Fig.23A and Fig. 23B , the second etching EC2 may be performed on the preliminary pixel defining layer PDL-bf and the preliminary insulating layer 40-bf at the same time. The second etching EC2 may be dry etching and may be isotropic etching. The space formed by the first etching EC1 and the second etching EC2 may have an undercut shape relative to the mask layer MP or the third tip portion TP3 and the fourth tip portion TP4.

[0279] refer to Fig.24A and Fig. 24B , when the mask layer MP is removed, a pixel defining layer PDL in which a valley VP is defined and a fourth insulating layer 40 in which a second groove GV2 is defined may be formed. The valley VP and the second groove GV2 formed by the same process may have similar shapes. For example, the depth VP-D of the valley VP may be substantially the same as the depth GV-D of the second groove GV2 defined by the fourth insulating layer 40 (or formed in the fourth insulating layer 40).

[0280] In an embodiment, the pixel defining layer PDL may include a black colorant. The black colorant may include carbon black, a metal such as chromium, or an oxide thereof. For example, in the case of etching the pixel defining layer PDL to form the valley VP, an uneven surface may be formed by the black colorant. For example, the fourth insulating layer 40 may not include a black colorant. Therefore, the roughness of the bottom surface of the second groove GV2 may be lower than the roughness of the bottom surface of each of the valleys VP. For example, the bottom surface of the second groove GV2 may be smoother than the bottom surface of the valley VP.

[0281] In an embodiment, the first groove GV1, the second groove GV2, the third groove GV3, the fourth groove GV4 and the fifth groove V5 (refer to Fig.11A) can be formed by the same process as the process of forming the valley VP. Therefore, an additional process for forming the first groove GV1, the second groove GV2, the third groove GV3, the fourth groove GV4, and the fifth groove V5 can be omitted. For example, the number of masks used during the process of forming the display panel DP can be reduced, and the manufacturing cost of the display panel DP can be reduced.

[0282] Fig.25A , Fig.25B , Fig.26A , Fig.26B , Fig.27A , Fig.27B , Fig.28A and Fig.28B are schematic cross-sectional views showing some steps of a display panel manufacturing process according to an embodiment.

[0283] Fig.25A , Fig.26A , Fig.27A and Fig.28A 2 is a schematic cross-sectional view illustrating a process of forming a valley VP in the preliminary pixel defining layer PDL-bfa (eg, in the upper surface of the preliminary pixel defining layer PDL-bfa). Fig.25B , Fig.26B , Fig.27B and Fig.28B 4 is a schematic cross-sectional view showing a process of forming a second groove GV2a in the preliminary insulating layer 40-bf (eg, in the upper surface of the preliminary insulating layer 40-bf). The following description may also apply to the first groove GV1, the third groove GV3, and the fourth groove GV4 described above.

[0284] exist Fig.25A and Fig.25B , the region corresponding to the region AA' and the region corresponding to the region CC' placed in the same process are shown. Fig.25A and Fig.25B , a first electrode AE ​​may be formed on the fifth insulating layer 50, and a preliminary pixel defining layer PDL-bfa having an opening OP formed therein may be formed on the first electrode AE. In an embodiment, the preliminary pixel defining layer PDL-bfa may include a protruding portion PDLpt. The protruding portion PDLpt may overlap with a position where a valley VP (to be described below) will be formed. A third tip portion TP3 and a fourth tip portion TP4 not covered by the fifth insulating layer 50 are defined. A portion of the preliminary insulating layer 40-bf is exposed between the third tip portion TP3 and the fourth tip portion TP4. The preliminary insulating layer 40-bf is in contact with the fourth insulating layer 40 (reference Fig.11A ) corresponding layer.

[0285] The mask layer MP may cover the first electrode AE, the preliminary pixel defining layer PDL-bfa, the fifth insulating layer 50, the third tip portion TP3, and the fourth tip portion TP4. The mask layer MP may have a first opening MP-OP1 and a second opening MP-OP2 defined therein. The first opening MP-OP1 may overlap the preliminary pixel defining layer PDL-bfa, and the second opening MP-OP2 may overlap a portion of the preliminary insulating layer 40-bf, a portion of the third tip portion TP3, and a portion of the fourth tip portion TP4. The mask layer MP may include indium gallium zinc oxide (IGZO), but the embodiment is not limited thereto.

[0286] refer to Fig.26A and Fig.26B , the first etching EC1a may be performed on the preliminary pixel defining layer PDL-bfa and the preliminary insulating layer 40-bf at the same time. The first etching EC1a may be dry etching, and may be anisotropic etching with a specific orientation. In an embodiment, the preliminary pixel defining layer PDL-bfa may include a protruding portion PDLpt. Therefore, even if the preliminary pixel defining layer PDL-bfa and the preliminary insulating layer 40-bf are etched identically in the same process, the depth of the groove (i.e., valley) formed in the preliminary pixel defining layer PDL-bfa may be shallower than the depth of the groove formed in the preliminary insulating layer 40-bf.

[0287] refer to Fig.27A and Fig.27B , the second etching EC2 may be performed on the preliminary pixel defining layer PDL-bfa and the preliminary insulating layer 40-bf at the same time. The second etching EC2 may be dry etching and may be isotropic etching. The space formed by the first etching EC1a and the second etching EC2 may have an undercut shape relative to the mask layer MP or the third tip portion TP3 and the fourth tip portion TP4.

[0288] refer to Fig.28A and Fig.28B , when the mask layer MP is removed, a pixel defining layer PDL in which a valley VP is defined and a fourth insulating layer 40a in which a second groove GV2a is defined may be formed. The valley VP and the second groove GV2a formed by the same process may have similar shapes. Since the preliminary pixel defining layer PDL-bfa includes the protruding portion PDLpt before the process, the depth VP-D of the valley VP may be shallower than the depth GV-Da of the second groove GV2a defined by the fourth insulating layer 40a (or formed in the fourth insulating layer 40a).

[0289] As described above, the grooves and valleys formed by the same process can be defined in the display panel. Therefore, an additional process for forming the grooves can be omitted. For example, the number of masks used in the process of forming the display panel can be reduced, and the manufacturing cost of the display panel can be reduced.

[0290] The path along which the etchant can penetrate in the case of processing a hole of the display panel can be shielded by the dam. In addition, the path can be additionally shielded by a crack dam arranged closest to the hole. For example, each of the dams defined between the grooves may include a tip portion protruding in opposite directions. Therefore, even if the depth of the groove is reduced, as many tip portions as possible can be provided, and thus the common layer can be smoothly disconnected. Therefore, the reliability of the display panel can be further improved.

[0291] The area overlapping the groove not covered by the organic encapsulation layer in the groove can be covered by at least one covering pattern. Therefore, even if the inorganic encapsulation layer is oxidized or cracked due to the deflection of the groove, moisture and oxygen can be blocked by the covering pattern. Therefore, the product reliability of the display panel can be improved.

[0292] While the present disclosure has been described with reference to the embodiments thereof, it will be apparent to those skilled in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the disclosure as set forth in the appended claims.

Claims

1. Display panel, including: a base layer having holes; A circuit layer, disposed on the base layer, the circuit layer comprising a pixel circuit and a plurality of insulating layers; An element layer, disposed on the circuit layer, the element layer comprising a light-emitting element electrically connected to the pixel circuit and a pixel defining layer defining an emission area; as well as a packaging layer, covering the component layer, Wherein, the circuit layer further comprises a groove surrounding the hole, The pixel defining layer includes a valley surrounding at least a portion of the emission region, and A bottom surface of the groove and a side surface of the groove connected to the bottom surface are defined by an insulating layer among the plurality of insulating layers.

2. The display panel according to claim 1, wherein: The circuit layer also includes: a first tip portion surrounding the aperture, and a second tip portion surrounding said first tip portion, and The first tip portion and the second tip portion protrude from the respective side surfaces of the groove.

3. The display panel according to claim 2, wherein: The depth of the valley is the same as the height of the first tip portion, the height of the first tip portion being measured from the bottom surface of the groove to the bottom surface of the first tip portion.

4. The display panel according to claim 3, wherein: A difference between the height of the first tip portion and the width of the first tip portion is less than 0.15 microns.

5. The display panel according to claim 1, wherein: Each of the side surfaces of the groove includes a curved surface extending from the bottom surface and a tapered surface extending from the curved surface.

6. The display panel according to claim 5, wherein: The valley is formed by a valley bottom surface, a valley curved surface extending from the valley bottom surface, and a valley conical surface extending from the valley curved surface, and The valley curved surface has the same shape as the curved surface of the groove.

7. The display panel according to claim 6, wherein: An angle between the valley bottom surface and the valley tapered surface is the same as an angle between the bottom surface of the groove and the tapered surface of the groove.

8. The display panel according to claim 1, wherein: The groove includes a plurality of grooves, and The encapsulation layer comprises: a first encapsulation layer, covering the plurality of grooves, a second encapsulation layer disposed on the first encapsulation layer to overlap with some of the plurality of grooves and so as not to overlap with other grooves of the plurality of grooves, and The third packaging layer is disposed on the second packaging layer to cover the plurality of grooves.

9. The display panel according to claim 8, further comprising: A sensor layer is arranged on the packaging layer, and the sensor layer comprises: The first sensor conductive layer, a sensor insulating layer, disposed on the first sensor conductive layer, and A second sensor conductive layer is disposed on the sensor insulating layer, Wherein, at least one of the first sensor conductive layer and the second sensor conductive layer includes a covering pattern overlapping with the other grooves.

10. The display panel according to claim 9, wherein: The circuit layer further includes a crack dam disposed between the groove and the hole, The crack dam includes a tip portion protruding toward the hole, and The covering pattern overlaps the crack dam and the tip portion.

11. The display panel according to claim 8, further comprising: A cover layer is disposed on the third encapsulation layer and overlaps the plurality of grooves.

12. The display panel according to claim 1, wherein: The circuit layer further includes a crack dam disposed between the groove and the hole, and The crack dam includes a tip portion protruding toward the hole.

13. The display panel according to claim 1, wherein: The circuit layer further includes at least one inorganic pattern disposed between the groove and the hole, and The at least one inorganic pattern includes the same material as an inorganic insulating layer among the plurality of insulating layers of the circuit layer.

14. The display panel according to claim 1, wherein: The insulating layer among the plurality of insulating layers is an organic insulating layer.

15. The display panel according to claim 1, wherein: The light emitting element comprises: The first electrode, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer, and A portion of the intermediate layer and a portion of the second electrode are disposed in the valley.

16. The display panel according to claim 15, wherein: The intermediate layer comprises: The first functional layer, an emission layer, disposed on the first functional layer, and a second functional layer disposed on the emitting layer, and A portion of the first functional layer, a portion of the second functional layer, and a portion of the second electrode are disposed in the groove.

17. The display panel according to claim 1, wherein: The bottom surface of the groove has a lower roughness than a valley bottom surface of the valley.

18. The display panel according to claim 1, wherein: The light emitting element comprises: The first electrode, an intermediate layer disposed on the first electrode, and a second electrode disposed on the intermediate layer, and Indium gallium zinc oxide residue is disposed on an upper surface of the first electrode.

19. Display panel, comprising: a base layer having holes; A circuit layer is arranged on the base layer, and the circuit layer comprises: a plurality of grooves surrounding the hole, and a plurality of tip portions protruding from a side surface of each of the plurality of grooves; a component layer, disposed on the circuit layer, the component layer comprising a pixel defining layer defining an emission area; and a packaging layer, covering the component layer, wherein the pixel defining layer includes a valley surrounding at least a portion of the emission region, the valley being formed in an upper surface of the pixel defining layer, and The depth of the valley is the same as the height of the plurality of tip portions, the height of the plurality of tip portions being measured from bottom surfaces of the plurality of grooves to bottom surfaces of the plurality of tip portions.

20. The display panel according to claim 19, wherein: The circuit layer also includes a plurality of insulating layers, An insulating layer among the plurality of insulating layers defines the bottom surfaces of the plurality of grooves and side surfaces of the plurality of grooves extending from the bottom surfaces, and The insulating layer among the plurality of insulating layers is an organic insulating layer.

21. The display panel according to claim 20, wherein: The circuit layer further includes at least one inorganic pattern disposed between the plurality of grooves and the holes, and The at least one inorganic pattern includes the same material as an inorganic insulating layer among the plurality of insulating layers of the circuit layer.

22. The display panel according to claim 19, wherein: The circuit layer further includes a crack dam disposed between the plurality of grooves and the hole, and The crack dam includes a tip portion protruding toward the hole.

23. The display panel according to claim 19, further comprising: A sensor layer is arranged on the packaging layer, and the sensor layer comprises: The first sensor conductive layer, a sensor insulating layer, disposed on the first sensor conductive layer, and A second sensor conductive layer is disposed on the sensor insulating layer, Wherein, the encapsulation layer comprises: a first encapsulation layer, covering the plurality of grooves, a second encapsulation layer disposed on the first encapsulation layer to overlap with some of the plurality of grooves and so as not to overlap with other grooves of the plurality of grooves, and a third packaging layer, disposed on the second packaging layer to cover the plurality of grooves, and At least one of the first sensor conductive layer and the second sensor conductive layer includes a covering pattern overlapping the other groove.

24. The display panel according to claim 19, wherein: The display panel further includes a plurality of dams formed between adjacent grooves among the plurality of grooves, and The number of the plurality of tip portions is twice or more the number of the plurality of dams.

Images