Power control for decoder

Abstract

Systems and methods for power control for a decoder are disclosed. In one aspect, a decoder for a communication bus is placed in a sleep or low power mode when the bus is idle, such as when blanking information is communicated on a camera serial interface (CSI) bus. By warning the decoder that there is an opportunity to operate at low power, power consumption may be reduced, and a recharge time metric may be improved, especially for battery powered mobile devices, which improves user experience.

Description

[0001] Priority application

[0002] This application claims priority to U.S. patent application serial number 17 / 815,254, filed on July 27, 2022, entitled “POWER CONTROL FOR A DECODER,” which is incorporated herein by reference in its entirety. background

[0003] I. Technical field

[0004] The technology of the present disclosure generally relates to power consumption control in a communication bus, and in particular to power consumption control on a bus configured to use the Camera Serial Interface (CSI) standard promulgated by MIPI.

[0005] II. Background Technology

[0006] Computing devices, and more specifically mobile communication devices, are ubiquitous in modern society and have become increasingly common. The popularity of these mobile communication devices is due in part to the many features now enabled on such devices. The increased processing power in such devices has meant that mobile communication devices have evolved from pure communication tools to sophisticated mobile entertainment centers, enabling an enhanced user experience. With the myriad of features available for such devices, the pressure to find ways to reduce power consumption has become greater. Finding new ways to reduce power consumption provides opportunities for innovation. Summary of the invention

[0007] Aspects disclosed in the detailed description include systems and methods for power control for a decoder. In particular, a decoder for a communication bus is placed in a sleep mode or low power mode when the bus is idle, such as when blanking information is transmitted on a camera serial interface (CSI) bus. By alerting the decoder that an opportunity for low power operation exists, power consumption can be reduced, and recharge time metrics can be improved, especially for battery-powered mobile devices, which improves the user experience.

[0008] In this regard, in one aspect, an integrated circuit (IC) circuit is disclosed. The IC includes a bus interface configured to be coupled to a communication bus. The IC also includes a decoder coupled to the bus interface and configured to decode data transmitted on the communication bus through the bus interface in a frame. The IC also includes a control circuit coupled to the bus interface and the decoder. The control circuit is configured to instruct the decoder to enter a low power mode for at least a portion of a blanking interval within the frame.

[0009] In another aspect, a method of controlling power consumption is disclosed. The method includes receiving data in a frame including a blanking interval. The method also includes instructing a decoder to enter a low power mode during at least a portion of the blanking interval. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a block diagram of a mobile terminal having a plurality of communication buses therein;

[0011] Figure 2 This is done by, for example, Figure 1 A more detailed block diagram of sensors and processors connected by a communication bus found in a mobile terminal;

[0012] Figure 3 is Figure 2 A signal diagram of an exemplary frame transmitted on a communication bus of;

[0013] Figure 4 yes Figure 3 a more detailed view of a frame of , showing a low power state for a communication bus; and

[0014] Figure 5 is a flow chart illustrating an exemplary process for detecting a low power state on a communication bus and placing a decoder in a low power state according to an exemplary aspect of the present disclosure. DETAILED DESCRIPTION

[0015] Referring now to the accompanying drawings, several exemplary aspects of the present disclosure are described. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as preferred or advantageous over other aspects.

[0016] Aspects disclosed in the detailed description include systems and methods for power control for a decoder. In particular, a decoder for a communication bus is placed in a sleep mode or low power mode when the bus is idle, such as when blanking information is transmitted on a camera serial interface (CSI) bus. By alerting the decoder that an opportunity for low power operation exists, power consumption can be reduced, and recharge time metrics can be improved, especially for battery-powered mobile devices, which improves the user experience.

[0017] While exemplary aspects of the present disclosure are well suited for CSI buses under current MIPI standards (e.g., CSI-2 version 4 released to MIPI members in December 2021), the present disclosure is not limited thereto, and other buses with continuously active decoders may also benefit from the present disclosure. In this regard, Figure 1A system-level block diagram of an exemplary mobile terminal 100 (such as a smartphone, a mobile computing device tablet, etc.) is illustrated, which includes multiple communication buses. The mobile terminal 100 includes an application processor 104 (sometimes referred to as a host) that communicates with a mass storage element 106 via a universal flash memory (UFS) bus 108. The application processor 104 may be further connected to a display 110 via a display serial interface (DSI) bus 112 and to a camera 114 via a CSI bus 116. The application processor 104 may be an integrated circuit (IC) and include an image serial processor (ISP, hereinafter referred to as Figure 2 116) to help process signals associated with the CSI bus 116. Various audio elements, such as a microphone 118, a speaker 120, and an audio codec 122, may be coupled to the application processor 104 via a serial low-power inter-chip multimedia bus (SLIMbus) 124. Additionally, the audio elements may communicate with each other via a SOUNDWIRE bus 126. A modem 128 may also be coupled to the SLIMbus 124 and / or the SOUNDWIRE bus 126. The modem 128 may be further connected to the application processor 104 via a peripheral component interconnect (PCI) or PCI Express (PCIe) bus 130 and / or a system power management interface (SPMI) bus 132.

[0018] Continue to refer Figure 1 , the SPMI bus 132 may also be coupled to a local area network (LAN or WLAN) IC (LAN IC or WLAN IC) 134, a power management integrated circuit (PMIC) 136, a companion IC (sometimes referred to as a bridge chip) 138, and a radio frequency IC (RFIC) 140. It should be understood that separate PCI buses 142 and 144 may also couple the application processor 104 to the companion IC 138 and the WLAN IC 134. The application processor 104 may further be connected to a sensor 146 via a sensor bus 148. The modem 128 and the RFIC 140 may communicate using a bus 150.

[0019] Continue to refer Figure 1 , RFIC 140 may be coupled to one or more RFFE elements, such as antenna tuner 152, switch 154, and power amplifier 156, via a radio frequency front end (RFFE) bus 158. Additionally, RFIC 140 may be coupled to envelope tracking power supply (ETPS) 160 via bus 162, and ETPS 160 may communicate with power amplifier 156. Together, these RFFE elements, including RFIC 140, may be considered an RFFE system 164.

[0020] As noted, the application processor 104 may include an ISP 200 that Figure 2 104. Alternatively, the ISP 200 may be separate and distinct from the application processor 104 (or may be integrated into some other IC, such as the modem 128). The ISP 200 may include a physical layer (PHY or CSIPHY) 202 configured to couple to the CSI bus 116, and may therefore be referred to as a bus interface. The camera 114 is coupled to the other end of the CSI bus 116. The PHY 202 may transmit a receive signal to a decoder 204 (also referred to as a CSI decoder or CSID). The control circuit 206 may be coupled to both the PHY 202 and the decoder 204, and more specifically to a power control logic circuit 208 within or associated with the decoder 204. The power control logic circuit 208 may include a register 210 into which operating parameters may be written by the control circuit 206. Alternatively, the register 210 may be within the decoder 204. Note that the camera 114 may also have registers (not shown) to which the CSI driver writes operating parameters. Furthermore, while the above discussion refers to register 210 , it may be a single register 210 or at least one register 210 .

[0021] In use, a sensor such as camera 114 may collect data (e.g., take a picture or video) using operating parameters stored in local registers and encode the data using MIPI CSI hardware, which encodes the data according to the MIPI CSI standard and transmits the data over a data lane in CSI bus 116. Camera 114 may stream data and use blanking (no data) to control exposure and frame rate, as in Figure 3 300 ′, there is an active portion 302 and an inactive or frame blanking portion 304. Whenever there is blanking, the CSI standard allows the camera 114 to intelligently switch the data channel to a low power consumption mode (LPM). In addition, the CSI standard allows the PHY 202 to follow the LPM transition and also enter a low power mode.

[0022] Figure 4, where a frame 400 begins with a start of frame (FS) packet 402, followed by an end of transmission (EoT) symbol 404. After the EoT symbol 404, there is a low power state (LPS) portion 406 between image lines. At some point in time, a start of transmission (SoT) symbol 408 is transmitted, followed by a packet 410. The packet 410 includes a packet header (PH) 412, data 414, and a packet trailer (PF) 416. After the packet 410, another EoT symbol 418 is transmitted, followed by another LPS portion 420. Subsequent packets such as the last packet 422 are preceded by a SoT symbol 424 and followed by an EoT symbol 426. The end of the frame may include a final LPS portion 428, a SoT symbol 430, and an end of frame (FE) symbol 432. Note that Figure 4 From the MIPI specification for CSI-2 version 4, which is due for release in December 2021.

[0023] However, conventional systems do not communicate blanking information to the decoder, and in conventional systems the decoder must be clocked continuously. Such always-on operation and the use of a clock consume power without purpose. Such power consumption may cause the user to charge the battery more frequently (i.e., a generally undesirable situation) and / or may cause the battery charge to drop to a level that degrades the user experience (i.e., also undesirable). Therefore, such operation is open to innovation.

[0024] An exemplary aspect of the present disclosure uses the control circuit 206 to use the power control logic circuit 208 to move the decoder 204 into a low power mode during a blanking interval. Specifically, the control circuit 206 or software used by the control circuit 206 can determine the blanking interval for the sensor of the camera 114 and share this information with the decoder 204, such as by storing operating parameters in registers 210. Based on these operating parameters, the decoder 204 can enter a low power mode for at least a portion of the blanking interval. In an exemplary aspect, less than the entire blanking interval is spent in the low power mode to allow time to wake up and stabilize in an active mode before the next data sequence to be decoded.

[0025] Figure 5A process 500 for providing power savings on a bus according to an exemplary aspect of the present disclosure is illustrated. In this regard, the process 500 begins when a remote sensor or camera 114 is activated (block 502), such as by turning on the camera 114. The sensor is remote in the sense that it is not part of the application processor 104, although it may be in the same device (e.g., a camera in a phone). A user may activate the camera 114 in an attempt to protect a photo or video, such as by pressing an activation icon, etc. In response to such activation, the camera 114 captures an initial image under default settings related to exposure time versus frame length (block 504). For example, the default frame length may be thirty-three milliseconds (33 ms) and the exposure length may be 30 ms. The camera 114 transmits the captured data to the application processor 104 (and specifically, to the ISP 200) via the CSI bus 116 (block 506). The control circuit 206 executes an automatic configuration algorithm (e.g., using an application specific IC (ASIC) or software) (block 508) to determine an appropriate exposure time relative to the frame rate to achieve a desired amount of captured light (e.g., dim interior lighting may require a longer exposure relative to a brightly illuminated exterior scene). In an exemplary aspect, the frame rate is configured using a framelengthline (FLT) parameter (corresponding to the frame length) and a linecount (LC) parameter (corresponding to the exposure length).

[0026] The control circuit 206 transmits the operating parameters to the registers 210 in the camera 114 and the decoder 204 (block 510). The camera 114 captures an image and transmits image data using the operating parameters provided by the application processor 104 (block 512). In most cases, at least some portion of the frame will be a blanking gap, and the CSI bus 116 will enter a low power mode during the blanking gap (block 514), as specified by the CSI specification. The decoder 204 is also aware of the blanking gap and enters a low power mode for at least a portion of the blanking gap (block 516). The decoder 204 then powers up at or before the end of the blanking gap (block 518) so that there is time for the clock to stabilize and be ready for the next image data from the camera 114. The time for the clock to stabilize can form a threshold that is subtracted from the blanking gap to determine how long the decoder 204 is in low power mode.

[0027] By way of example, a typical frame length may be 33 ms. A typical exposure length for bright light may be 10 ms to 15 ms. A typical exposure for dim indoor lighting conditions may be 25 ms to 30 ms. Wake-up and stabilization may take approximately 1 ms. Thus, almost any normal lighting situation may benefit from aspects of the present disclosure.

[0028] As a first variation of process 500, control circuit 206 may check the duration of the blanking interval against the amount of time required to wake up and stabilize. Control circuit 206 may prevent decoder 204 from entering a low power mode when the blanking interval is less than the amount of time required to wake up and stabilize.

[0029] As a second variation of process 500, the battery charge may be checked during the auto-configuration algorithm, and a low battery state (e.g., below twenty percent) may cause the auto-configuration to limit the exposure length to save power. Such a battery charge override will not only limit the time that the CSI bus 116 is active, but also allow the decoder 204 to be placed in a low power mode as well, thereby reducing power consumption, albeit with a possible loss of information in the image.

[0030] As a variation of the second variation, the user may be provided with the ability to override the battery level override. That is, the user may be notified that the battery is low and that the camera settings have been adjusted with the option to accept or reject such adjustments.

[0031] As a third variation, there is a move to compress the time within a frame used to send data to less than the length of the exposure length. For example, if the auto-configuration algorithm indicates that the exposure length is 15 ms, the camera may compress the data transmission to 8 ms to maximize the blanking interval and the time that the CSI bus 116 spends in low power mode. If the control circuit 206 knows that the camera 114 uses this compression, the control circuit 206 may store the modified value in the register 210 so that the decoder 204 may also be in a low power mode that matches the mode of the CSI bus 116.

[0032] Systems and methods for power control for a decoder according to various aspects disclosed herein may be provided in or integrated into any processor-based device. Examples, not limiting, include: a set-top box, an entertainment unit, a navigation device, a communication device, a fixed location data unit, a mobile location data unit, a global positioning system (GPS) device, a mobile phone, a cellular phone, a smart phone, a session initiation protocol (SIP) phone, a tablet, a tablet phone, a server, a computer, a portable computer, a mobile computing device, a wearable computing device (e.g., a smart watch, a health or fitness tracker, glasses, etc.), a desktop computer, a personal digital assistant (PDA), a monitor, a computer monitor, a television, a tuner, a radio, a satellite radio, a music player, a digital music player, a portable music player, a digital video player, a video player, a digital video disc (DVD) player, and a portable digital video player.

[0033] It will be further understood by those skilled in the art that various exemplary logic blocks, modules, circuits and algorithms described in conjunction with the various aspects disclosed herein may be implemented as electronic hardware, instructions stored in a memory or in another computer-readable medium, wherein any such instructions are executed by a processor or other processing device or a combination of the two. As an example, the master device and slave device described herein may be adopted in any circuit, hardware component, IC, or IC chip. The memory disclosed herein may be a memory of any type and size, and may be configured to store any type of information desired. In order to clearly illustrate this interchangeability, the functionality of various exemplary components, blocks, modules, circuits and steps has been generally described above. How such functionality is implemented depends on specific applications, design choices, and / or design constraints imposed on the overall system. The technician may implement the described functionality in different ways for each specific application, but such specific implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

[0034] The various illustrative logical blocks, modules, and circuits described in conjunction with the various aspects disclosed herein may be implemented or performed with a processor, a digital signal processor (DSP), an ASIC, a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but in an alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in cooperation with a DSP core, or any other such configuration).

[0035] The various aspects disclosed herein may be embodied in hardware and instructions stored in hardware, and may reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable medium known in the art. An exemplary storage medium is coupled to a processor so that the processor can read information from and write information to the storage medium. In an alternative, the storage medium may be integral to the processor. The processor and storage medium may reside in an ASIC. The ASIC may reside in a remote station. In an alternative, the processor and storage medium may reside in a remote station, a base station, or a server as discrete components.

[0036] It is also noted that the operation steps described in any exemplary aspect of this article are described in order to provide examples and discussions. The described operation can be performed in many different orders except for the illustrated order. In addition, the operation described in a single operation step can actually be performed in multiple different steps. In addition, one or more operation steps discussed in the exemplary aspects can be combined. It will be understood that, as will be apparent to those skilled in the art, many different modifications can be made to the operation steps illustrated in the flow chart. It will be equally understood by those skilled in the art that any of a variety of different technologies and techniques can be used to represent information and signals. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be mentioned throughout the above description can be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof.

[0037] The previous description of the disclosure is provided to enable any person skilled in the art to make or use the disclosure. Various modifications to the disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations. Therefore, the disclosure is not intended to be limited to the examples and designs described herein, but to conform to the widest scope consistent with the principles and novel features disclosed herein.

[0038] Specific implementation examples are described in the following numbered aspects / clauses:

[0039] 1. An integrated circuit (IC) circuit, the integrated circuit (IC) circuit comprising:

[0040] a bus interface configured to couple to a communication bus;

[0041] a decoder coupled to the bus interface and configured to decode data transmitted in frames on the communication bus through the bus interface;

[0042] and

[0043] a control circuit coupled to the bus interface and the decoder, the control circuit being configured to:

[0044] The decoder is instructed to enter a low power mode for at least a portion of a blanking interval within the frame.

[0045] 2. The IC of clause 1, wherein the bus interface is configured to couple to a camera serial interface (CSI) bus.

[0046] 3. An IC according to clause 1 or 2, wherein the control circuit is further configured to receive an initial image from a remote sensor via the bus interface.

[0047] 4. The IC of clause 3, wherein the control circuit is further configured to implement an automatic configuration algorithm using the initial image to determine operating parameters for the remote sensor, the operating parameters including a frame length and the blanking interval.

[0048] 5. The IC of clause 4, wherein the control circuit is further configured to transmit the operating parameter to the remote sensor.

[0049] 6. An IC as described in clause 4 or 5, further comprising a register associated with the decoder, and wherein the control circuit is further configured to store the operating parameter in the register.

[0050] 7. An IC as described in any of clauses 1 to 6, wherein the portion of the blanking gap comprises the entire blanking gap minus a threshold.

[0051] 8. The IC of clause 7, wherein the threshold is based on a wake-up time associated with the decoder.

[0052] 9. An IC as described in any of clauses 1 to 8, wherein the control circuit is configured to determine the blanking interval based on a battery charge.

[0053] 10. The IC of clause 9, wherein the control circuit is configured to determine the blanking interval based on a user override related to the battery charge.

[0054] 11. A method for controlling power consumption, the method comprising:

[0055] receiving data in a frame including a blanking interval; and

[0056] A decoder is instructed to enter a low power mode during at least a portion of the blanking interval.

[0057] 12. The method of clause 11, further comprising determining the blanking interval.

[0058] 13. The method of clause 12, wherein determining the blanking gap comprises using battery power to determine the blanking gap.

[0059] 14. The method of clause 12, wherein determining the blanking gap comprises determining the blanking gap using information associated with an initial image.

[0060] 15. The method of any of clauses 12 to 14, further comprising transmitting the blanking gap to a remote sensor.

[0061] 16. A method according to any of clauses 12 to 14, further comprising storing the blanking interval in a register associated with the decoder.

[0062] 17. The method of any of clauses 11 to 16, wherein receiving the data in the frame comprises receiving over a camera serial interface (CSI) bus.

Claims

1. An integrated circuit (IC) circuit, the integrated circuit (IC) circuit comprising: a bus interface configured to couple to a communication bus; a decoder coupled to the bus interface and configured to decode data transmitted in frames on the communication bus through the bus interface; and a control circuit coupled to the bus interface and the decoder, the control circuit being configured to: The decoder is instructed to enter a low power mode for at least a portion of a blanking interval within the frame.

2. The IC of claim 1, wherein the bus interface is configured to couple to a camera serial interface (CSI) bus. 3 . The IC of claim 1 , wherein the control circuit is further configured to receive an initial image from a remote sensor via the bus interface.

4. The IC of claim 3, wherein the control circuit is further configured to implement an automatic configuration algorithm using the initial image to determine operating parameters for the remote sensor, the operating parameters including frame length and the blanking interval. 5 . The IC of claim 4 , wherein the control circuit is further configured to transmit the operating parameter to the remote sensor.

6. The IC of claim 4, further comprising a register associated with the decoder, and wherein the control circuit is further configured to store the operating parameter in the register.

7. The IC of claim 1, wherein the portion of the blanking interval comprises the entire blanking interval minus a threshold.

8. The IC of claim 7, wherein the threshold is based on a wake-up time associated with the decoder.

9. The IC of claim 1, wherein the control circuit is configured to determine the blanking interval based on a battery charge.

10. The IC of claim 9, wherein the control circuit is configured to determine the blanking interval based on a user override related to the battery charge.

11. A method for controlling power consumption, the method comprising: Receiving data in a frame including a blanking interval; as well as A decoder is instructed to enter a low power mode during at least a portion of the blanking interval.

12. The method of claim 11, further comprising determining the blanking interval.

13. The method of claim 12, wherein determining the blanking interval comprises using a battery charge to determine the blanking interval.

14. The method of claim 12, wherein determining the blanking interval comprises determining the blanking interval using information associated with an initial image.

15. The method of claim 12, further comprising transmitting the blanking gap to a remote sensor.

16. The method of claim 12, further comprising storing the blanking interval in a register associated with the decoder.

17. The method of claim 11, wherein receiving the data in the frame comprises receiving over a camera serial interface (CSI) bus.

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