Semi-constant operand multiplier

Abstract

Aspects of the present disclosure relate to multiplier circuits for semi-constant operand multiplication. The multiplier circuit may receive an operand for multiplication. The multiplier circuit may convert one of the operands into a set of configuration bits, such as a normative signed digital representation (CSD). The multiplier circuit may process another operand using the set of configuration bits to generate a multiplied output.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is a continuation of U.S. patent application No. 18 / 215,332 filed on June 28, 2023, the disclosure of which is incorporated herein by reference. Background Art

[0003] A multiplier circuit may receive two input operands and output a multiplied output. A multiplier circuit may perform multiple operations where one of the operands remains constant to reduce the power consumed by the multiplier circuit and memory accesses. However, the multiplier circuit may still consume more energy than necessary in each multiplication operation. In addition, the multiplier circuit may be designed to support rapid changes in both operands, even if only one operand changes frequently, resulting in a larger multiplier circuit than necessary. Summary of the invention

[0004] Aspects of the present disclosure relate to a multiplier circuit for semi-constant operand multiplication. The multiplier circuit may receive an operand for multiplication. The multiplier circuit may convert one of the operands into a set of configuration bits, such as a canonical signed digital representation (CSD). The multiplier circuit may use the set of configuration bits to process another operand to generate a multiplication output.

[0005] One aspect of the present disclosure provides a multiplier circuit for semi-constant operand multiplication, which includes a first subcircuit, a second subcircuit and one or more processors, wherein the one or more processors are configured to: receive a first operand and a second operand for multiplication; convert the first operand into a signed digital representation, the signed digital representation including a positive number and a negative number; process the second operand in the first subcircuit based on the positive number to generate a positive field of the signed digital representation; process the second operand in the second subcircuit based on the negative number to generate a negative field of the signed digital representation; and subtract the negative field from the positive field to generate a multiplication output.

[0006] In one example, the second subcircuit is a subset of the first subcircuit. In another example, the first subcircuit and the second subcircuit are equivalent.

[0007] In yet another example, the first subcircuit includes one or more multiplexers and adder circuits. In yet another example, processing the second operand in the first subcircuit further includes outputting the output of the one or more multiplexers as input to one or more adder circuits. In yet another example, the second subcircuit includes one or more multiplexers and adder circuits. In yet another example, processing the second operand in the second subcircuit further includes outputting the output of the one or more multiplexers as input to one or more adder circuits.

[0008] In yet another example, the one or more processors are further configured to swap the positive term of the positive field with the negative term of the negative field.

[0009] In yet another example, the multiplier circuit is implemented in at least one of a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC).

[0010] Another aspect of the present disclosure provides a multiplier circuit for semi-constant operand multiplication, which includes a processing circuit and one or more processors, wherein the one or more processors are configured to: receive a first operand and a second operand for multiplication; convert the first operand to a set of configuration bits; and use the set of configuration bits to process the second operand to generate a multiplication output.

[0011] In one example, converting the first operand to a set of configuration bits includes converting the first operand to a signed digital representation. In another example, processing the second operand includes: processing the second operand in a first subcircuit of the processing circuit using a first portion of the set of configuration bits to generate a first output; and processing the second operand in a second subcircuit of the processing circuit using a second portion of the set of configuration bits to generate a second output. In yet another example, processing the second operand includes subtracting the second output from the first output to generate the multiplication output. In yet another example, the second subcircuit is a subset of the first subcircuit, or the first subcircuit and the second subcircuit are equivalent.

[0012] In yet another example, the first subcircuit includes one or more multiplexers and adder circuits. In yet another example, processing the second operand in the first subcircuit further includes outputting the output of the one or more multiplexers as input to one or more adder circuits. In yet another example, the second subcircuit includes one or more multiplexers and adder circuits. In yet another example, processing the second operand in the second subcircuit further includes outputting the output of the one or more multiplexers as input to one or more adder circuits.

[0013] In yet another example, processing the second operand further includes swapping one or more outputs.

[0014] Another aspect of the present disclosure provides a method for semi-constant operand multiplication, which includes: receiving a first operand and a second operand for multiplication by one or more processors; converting the first operand to a signed digital representation by the one or more processors, the signed digital representation including a positive number and a negative number; processing the second operand in a first subcircuit of a multiplier circuit based on the positive number to generate a positive field of the signed digital representation by the one or more processors; processing the second operand in a second subcircuit of the multiplier circuit based on the negative number to generate a negative field of the signed digital representation by the one or more processors; and subtracting the negative field from the positive field by the one or more processors to generate a multiplication output. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 Depicted is a block diagram of an example multiplier circuit for semi-constant operand multiplication in accordance with aspects of the present disclosure.

[0016] Figure 2 Depicted is a block diagram of an example multiplier circuit for semi-constant operand multiplication, where a first input operand has been converted to a signed digital representation, in accordance with aspects of the present disclosure.

[0017] Figure 3 Depicted is a block diagram of an example positron circuit for a 3-bit unsigned multiplier in accordance with aspects of the present disclosure.

[0018] Figure 4 Depicted is a block diagram of an example negative subcircuit for a 3-bit unsigned multiplier in accordance with aspects of the present disclosure.

[0019] Figure 5 Depicted is a block diagram of an example positron circuit for an 8-bit signed multiplier in accordance with aspects of the present disclosure.

[0020] Figure 6Depicted is a block diagram of an example positron circuit for an 8-bit signed multiplier taking into account symmetry in accordance with aspects of the present disclosure.

[0021] Figure 7 Depicted is a block diagram of an example negative subcircuit for an 8-bit signed multiplier in accordance with aspects of the present disclosure.

[0022] Figure 8 Depicted is a block diagram of an example multiplier circuit implementing a switch in accordance with aspects of the present disclosure.

[0023] Fig. 9 Depicted is a block diagram of an example large-term subcircuit for an 8-bit signed multiplier in accordance with aspects of the present disclosure.

[0024] Fig.10 Depicted is a block diagram of an example small-term subcircuit for an 8-bit signed multiplier in accordance with aspects of the present disclosure.

[0025] Fig.11 Depicted is a block diagram of a data processing system implementing an example computing unit in accordance with aspects of the present disclosure.

[0026] Fig.12 A block diagram of an example environment for implementing a data processing system including a computing unit in accordance with aspects of the present disclosure is depicted. DETAILED DESCRIPTION

[0027] The present technology generally relates to a multiplier circuit with at least one semi-constant operand. Semi-constant can refer to at least two consecutive multiplications. Semi-constant operand multiplier can refer to an operand multiplier that is substantially constantly used in this article so that continuous operations (e.g., multiplication) are continuously performed with a limited downtime. Alternatively, semi-constant operand multiplier can also refer to an operand multiplier that is periodically used for at least two consecutive multiplications in this article. Multiplier circuit can receive two operands as input. Multiplier circuit can process an operand in two circuits to generate positive and negative fields based on the positive and negative numbers of another operand encoded in the past with a signed digital representation, respectively. Multiplier circuit can subtract negative fields from positive fields to generate an output that multiplies two operands.

[0028] The multiplier circuit disclosed herein allows for semi-constant operands to be implemented to allow for the following technical advantages: reducing the number of gates, so that more operators can be packed into the same space; reducing the logic depth, so that the cycle time can be improved; and / or reducing switching, so that the energy to produce the result can be reduced. Thus, since the operation can be implemented in a smaller space, the technical effect of reducing the size of the circuit package can be achieved. This advantage is particularly advantageous when the multiplier circuit is implemented in an FPGA or ASIC (such as a GPU or TPU) to perform machine learning reasoning or training, because a large number of operations are required in such scenarios, and it is desirable to reduce the size of the circuit package in these scenarios.

[0029] Figure 1 A block diagram of an example multiplier circuit 100 for semi-constant operand multiplication is depicted. The multiplier circuit 100 includes a plurality of input registers 102 and a processing circuit 104. The multiplier circuit 100 may also include a conversion engine 106. The multiplier circuit 100 may receive two input operands, such as a first input operand 108 and a second input operand 110. The multiplier circuit may receive the first input operand 108 at the conversion engine 106 and the second input operand 110 at the input register 102. The conversion engine 106 may be configured to convert the first input operand 108 into a set of configuration bits 112 to provide to the processing circuit 104. The conversion engine 106 may convert the first input operand 108 into a set of configuration bits 112 based on a mapping. For example, the conversion engine 106 may convert a binary operand into a set of configuration bits associated with a signed digital representation, such as a canonical signed digital (CSD) representation or Booth encoding. The conversion engine 106 may convert to a binary operand using a table listing some or all possible multiplicands.

[0030] The input register 102 may be configured to hold a second input operand 110 to provide to the processing circuit 104. The processing circuit 104 may be configured to process the second input operand 110 using the set of configuration bits 112 to generate a multiplication output 114. The processing circuit 104 may include a plurality of multiplexers and adder circuits to allow for the addition of non-zero terms in the signed digital representation. The multiplexer may select the bits received from the input register 102 based on the configuration bits 112. The output of the multiplexer may be provided to an adder circuit that adds the outputs to generate the multiplication output 114.

[0031] Figure 2A block diagram of an example multiplier circuit 200 for semi-constant operand multiplication is depicted, wherein a first input operand has been converted to a set of configuration bits associated with a signed digital representation. The multiplier circuit 200 may include a plurality of input registers 202, a positive subcircuit 204 (i.e., a first subcircuit), a negative subcircuit 206 (i.e., a second subcircuit), and a subtractor 208. The positive subcircuit 204, the negative subcircuit 206, and the subtractor 208 may correspond to Figure 1 Processing circuit 104 is depicted. A plurality of input registers 202 may receive a second input operand. The plurality of input registers 202 may be configured to retain the input operand to provide as bits to positive subcircuit 204 and negative subcircuit 206.

[0032] The positive subcircuit 204 and the negative subcircuit 206 may also receive configuration bits, which are the first input operands converted to signed digital representations. The positive subcircuit 204 may receive configuration bits corresponding to positive numbers, referred to as positive digital bits, and the negative subcircuit 206 may receive configuration bits corresponding to negative numbers, referred to as negative digital bits. The negative subcircuit 206 may be a subset of the positive subcircuit 204 or equivalent to the positive subcircuit 204. The positive subcircuit 204 and the negative subcircuit 206 may each include a plurality of multiplexer and adder circuits or their logical equivalents. For the positive subcircuit 204, the multiplexer may select the bits received from the input register 202 based on the positive digital bits. For the negative subcircuit 206, the multiplexer may select the bits received from the input register 202 based on the negative digital bits. The output of the multiplexer can be provided to an adder circuit that adds the outputs to generate a positive field of a signed digital representation and a negative field of a signed digital representation for the positive subcircuit 204 and the negative subcircuit 206, respectively. The subtractor 208 can be configured to subtract the negative field from the positive field to generate a multiplication output. Such circuitry provides for implementing semi-constant operands to allow the following technical advantages to be achieved: reducing the number of gates, so that more operators can be packed into the same space; reducing the logic depth, so that the cycle time can be improved; and / or reducing switching, so that the energy to produce the result can be reduced. Therefore, a circuit package with reduced size can be achieved.

[0033] Figure 3 A block diagram of an example positron circuit 300 for a 3-bit unsigned multiplier, for example supporting multiplicands 0 to 7, is depicted. The positron circuit 300 may correspond to Figure 2 Positron circuit 204 is depicted.

[0034] The positive subcircuit 300 may include a plurality of multiplexers, such as a first multiplexer 302, a second multiplexer 304, and a third multiplexer 306. The positive subcircuit 300 may also include an adder circuit 308. The multiplexers 302, 304, 306 may receive configuration bits that are positive digital bits. The positive digital bits may be the positive terms of the first input operand converted to a CSD representation. The first input operand may be converted to a CSD representation using a table such as the table depicted below for a 3-bit unsigned multiplier.

[0035] Binary CSD+ 0 000 0000 1 001 0001 2 010 0010 3 011 0010 4 100 0100 5 101 0101 6 110 1000 7 111 1000

[0036] The first multiplexer 302 may be a 4:1 multiplexer configured to receive four inputs from a plurality of registers, such as a first register 310, a second register 312, a third register 314, and a fourth register 316. The plurality of registers may correspond to, for example, Figure 2 The depicted register 202. Since the CSD representation of a 3-bit unsigned multiplexer includes four digits, in this example, the plurality of registers may correspond to four registers. Based on the positive digit, the first multiplexer 302 may output one of the four inputs to the third multiplexer 306.

[0037] In other examples, the first multiplexer 302 can be a 3:1 multiplexer, or the first multiplexer 302 can be a 4:1 multiplexer that receives an empty bit input. The second multiplexer 304 can be a 2:1 multiplexer that is configured to receive inputs from multiple registers, such as from the first register 310. The second multiplexer 304 also receives an empty bit input. Based on the positive digital bit, the second multiplexer 304 can output the input from the multiple registers or the empty bit to the adder circuit 308. In other examples, the second multiplexer 304 can be replaced with an AND gate or any logical equivalent circuit.

[0038] In still other examples, the second multiplexer 304 can be removed. The third multiplexer 306 can also be a 2:1 multiplexer configured to receive input from the first multiplexer 302 and receive an empty bit input. Based on the positive digital bit, the third multiplexer 306 can output the input from the first multiplexer 302 or the empty bit to the adder circuit 308. In other examples, the third multiplexer 306 can be replaced with an AND gate or any logical equivalent circuit. The adder circuit 308 can be configured to add the outputs received from the second multiplexer 304 and the third multiplexer 306 to generate an output representing a positive term.

[0039] Figure 4 A block diagram of an example negative subcircuit 400 for a 3-bit unsigned multiplier is depicted. The negative subcircuit 400 may correspond to Figure 2 Negative subcircuit 206 is depicted. Negative subcircuit 400 may be as Figure 3 A subset of the positive subcircuit 300 is depicted because the multipliers in this example involve unsigned bits.

[0040] The negative subcircuit 400 may include a plurality of multiplexers, such as a first multiplexer 402 and a second multiplexer 404. The multiplexers 402, 404 may receive configuration bits as negative digital bits. The negative digital bits may be the negative terms of the first input operand converted to CSD representation. The first input operand may be converted to CSD representation using a table such as the table depicted below for a 3-bit unsigned multiplier.

[0041] Binary CSD- 0 000 0000 1 001 0000 2 010 0000 3 011 0001 4 100 0000 5 101 0000 6 110 0010 7 111 0001

[0042] The first multiplexer 402 may be a 2:1 multiplexer configured to receive two inputs from a plurality of registers, such as a first register 406 and a second register 408. The plurality of registers may correspond to, for example, Figure 2 The register 202 is depicted. The multiple registers for the negative subcircuit 400 may be as follows Figure 3 A subset of the plurality of registers depicted for the positive subcircuit 300. Based on a positive digital bit, the first multiplexer 402 may output one of the two inputs to the second multiplexer 404. The second multiplexer 404 may be a 2:1 multiplexer configured to receive an input from the first multiplexer 402 and an empty bit input. Based on a positive digital bit, the second multiplexer 404 may output either the input from the first multiplexer 402 or the empty bit to generate an output representing a negative term. In other examples, the second multiplexer 404 may be replaced with an AND gate or any logical equivalent circuit.

[0043] Figure 5 A block diagram of an example positron circuit 500 for an 8-bit signed multiplier, for example, supporting multiplicands from -128 to 128, is depicted. The positron circuit 500 may correspond to Figure 2 Positron circuit 204 is depicted.

[0044] The positive subcircuit 500 may include a plurality of multiplexers, such as a first multiplexer 502, a second multiplexer 504, a third multiplexer 506, a fourth multiplexer 508, a fifth multiplexer 510, a sixth multiplexer 512, a seventh multiplexer 514, and an eighth multiplexer 516. The positive subcircuit 500 may also include a plurality of adder circuits, such as a first adder circuit 518, a second adder circuit 520, and a third adder circuit 522. The multiplexers 502-516 may receive configuration bits as positive digits. The positive digits may be positive terms of the first input operand converted to CSD representation. The first input operand may be converted to CSD representation using a table such as the table depicted below for an 8-bit signed multiplier. For simplicity, only an excerpt of the table is depicted below, but the entire table should be understood by those skilled in the art to include all numbers from -128 to 128.

[0045] Binary CSD+ -128 -10000000 00000000 -91 -01011011 00100101 -85 -01010101 00000000 -3 -00000011 00000001 3 00000011 00000100 85 01010101 01010101 91 01011011 10000000 128 10000000 10000000

[0046] The first multiplexer 502 may be a 2:1 multiplexer configured to receive two inputs from a plurality of registers, such as a first register 524 and a second register 526. The plurality of registers may correspond to, for example, Figure 2 The depicted register 202. Since the CSD representation of an 8-bit signed multiplexer includes eight digits, in this example, the plurality of registers may correspond to eight registers. Based on the positive digit, the first multiplexer 502 may output one of the two inputs to the fifth multiplexer 510. The second multiplexer 504 may be a 4:1 multiplexer configured to receive four inputs from a plurality of registers, such as from a third register 528, a fourth register 530, a fifth register 532, and a sixth register 534. Based on the positive digit, the second multiplexer 504 may output one of the four inputs to the sixth multiplexer 512. The third multiplexer 506 may also be a 4:1 multiplexer configured to receive four inputs from a plurality of registers, such as from a fifth register 532, a sixth register 534, a seventh register 536, and an eighth register 538. Based on the positive digit, the third multiplexer 506 may output one of the four inputs to the seventh multiplexer 514. The fourth multiplexer 508 may be a 2:1 multiplexer configured to receive two inputs from a plurality of registers, such as from the seventh register 536 and the eighth register 538. The fourth multiplexer 508 may output one of the two inputs to the eighth multiplexer 516 based on the positive digital bit.

[0047] The fifth multiplexer 510 may be a 2:1 multiplexer configured to receive an input from the first multiplexer 502 and an empty bit input. Based on the positive digital bit, the fifth multiplexer 510 may output the input from the first multiplexer 502 or an empty bit to the first adder circuit 518. The sixth multiplexer 512 may also be a 2:1 multiplexer configured to receive an input from the second multiplexer 504 and an empty bit input. Based on the positive digital bit, the sixth multiplexer 512 may output the input from the second multiplexer 504 or an empty bit to the first adder circuit 518. The seventh multiplexer 514 may still also be a 2:1 multiplexer configured to receive an input from the third multiplexer 506 and an empty bit input. Based on the positive digital bit, the seventh multiplexer 514 can output the input from the third multiplexer 506 or an empty bit to the second adder circuit 520. The eighth multiplexer 516 can also be a 2:1 multiplexer configured to receive the input from the fourth multiplexer 508 and an empty bit input. Based on the positive digital bit, the eighth multiplexer 516 can output the input from the fourth multiplexer 508 or an empty bit to the second adder circuit 520. In other examples, one or more of the fifth multiplexer, the sixth multiplexer, the seventh multiplexer, and the eighth multiplexer 510-516 can be replaced with an AND gate or any logical equivalent circuit.

[0048] The first adder circuit 518 may be configured to add the outputs received from the fifth multiplexer 510 and the sixth multiplexer 512 to generate an output provided to the third adder circuit 522. The second adder circuit 520 may be configured to add the outputs received from the seventh multiplexer 514 and the eighth multiplexer 516 to generate an output also provided to the third adder circuit 522. The third adder circuit 522 may be configured to add the outputs received from the first adder circuit 518 and the second adder circuit 520 to generate an output representing a positive term.

[0049] Figure 6 A block diagram of an example positron circuit 600 for an 8-bit signed multiplier taking into account one or more symmetries in a CSD representation is depicted. Exploiting the symmetry allows the positron circuit 600 to generate positive terms using fewer and / or smaller multiplexers, which can save space in a circuit package. Thus, a technical effect of reducing the size of the circuit package can be achieved. The positron circuit 600 can exploit the symmetry by calculating a term, delaying the term by one or more cycles, and then adding the term to itself. For example, a CSD representation of +85 has four positive terms, such as Figure 5As depicted, this requires three adders, but since +85 in binary is 01010101, which replicates the pattern 0101, the multiplexer can calculate 0101 once, and then after a delay of two cycles, that term can be added to itself to obtain 01010101. This therefore reduces the number of multiplexer components required to complete the calculation represented by +85, since the term 0101 can be added to itself to obtain 01010101 by utilizing the replicated pattern and calculation of the previous output. This avoids the need for further calculations, thereby meaning that the operation is more computationally efficient and requires fewer / smaller multiplexers. Similar principles can be applied to other numbers where a repeating pattern is identified, resulting in a substantial reduction in computational power and the number / size of multiplexers required in the overall circuit.

[0050] The positive subcircuit 600 may include a plurality of multiplexers, such as a first multiplexer 602, a second multiplexer 604, a third multiplexer 606, a fourth multiplexer 608, a fifth multiplexer 610, a sixth multiplexer 612, and a seventh multiplexer 614. The positive subcircuit 600 may also include a plurality of adder circuits, such as a first adder circuit 616 and a second adder circuit 618. The positive subcircuit 600 may also include a plurality of flip-flops, such as a first flip-flop 620 and a second flip-flop 622. The multiplexers 602-616 may receive configuration bits as positive digital bits. The positive digital bits may be the positive terms of the first input operand converted to the CSD representation.

[0051] The first multiplexer 602 may be a 2:1 multiplexer configured to receive two inputs from a plurality of registers, such as a first register 624 and a second register 626. The plurality of registers may correspond to Figure 2 The depicted register 202. Based on the positive digital bit, the first multiplexer 602 can output one of the two inputs to the fourth multiplexer 608. The second multiplexer 604 can be a 4:1 multiplexer configured to receive four inputs from a plurality of registers, such as from a third register 628, a fourth register 630, a fifth register 632, and a sixth register 634. Based on the positive digital bit, the second multiplexer 604 can output one of the four inputs to the fifth multiplexer 610. The third multiplexer 606 can also be a 4:1 multiplexer configured to receive four inputs from a plurality of registers, such as from a fifth register 632, a sixth register 634, a seventh register 636, and an eighth register 638. Based on the positive digital bit, the third multiplexer 606 can output one of the four inputs to the sixth multiplexer 612.

[0052] The fourth multiplexer 608 may be a 2:1 multiplexer configured to receive an input from the first multiplexer 602 and an empty bit input. Based on the positive digital bit, the fourth multiplexer 608 may output the input from the first multiplexer 602 or an empty bit to the first adder circuit 616. The fifth multiplexer 610 may also be a 2:1 multiplexer configured to receive an input from the second multiplexer 604 and an empty bit input. Based on the positive digital bit, the sixth multiplexer 610 may output the input from the second multiplexer 604 or an empty bit to the first adder circuit 616. The sixth multiplexer 612 may still also be a 2:1 multiplexer configured to receive an input from the third multiplexer 606 and an empty bit input. Based on the positive digital bit, the sixth multiplexer 612 can output the input from the third multiplexer 606 or a null bit to the seventh multiplexer 614. In other examples, one or more of the fourth multiplexer 608, the fifth multiplexer 610, and the sixth multiplexer 612 can be replaced with an AND gate or any logical equivalent circuit.

[0053] The first adder circuit 616 may be configured to add the outputs received from the fourth multiplexer 608 and the fifth multiplexer 610 to generate an output provided to the second adder circuit 618. The output of the first adder circuit 616 may also be input to the first flip-flop 620 to store the output of the first adder circuit 616 for one cycle. The output of the first flip-flop 620 may be input to the second flip-flop 622 to store the output of the first flip-flop 620 for one cycle. The output of the second flip-flop 622 may be input to the seventh multiplexer 614.

[0054] The seventh multiplexer 614 may be a 2:1 multiplexer configured to receive an input from the second flip-flop 622 and an input from the sixth multiplexer 612. Based on the positive digital bit, the seventh multiplexer 614 may output one of the two inputs to the second adder circuit 618. The second adder circuit 618 may be configured to add the outputs received from the first adder circuit 616 and the seventh multiplexer 614 to generate an output representing a positive term.

[0055] Figure 7 A block diagram of an example negative subcircuit 700 for an 8-bit signed multiplier is depicted. The negative subcircuit 700 may correspond to Figure 2 The negative subcircuit 206 is depicted. The negative subcircuit 700 may be equivalent to its corresponding positive subcircuit, such as Figure 5 The positron circuit 500 depicted or Figure 6 The depicted positive subcircuit 600 is shown because the multiplier in this example involves a signed bit. Figure 7 The depicted negative subcircuit 700 corresponds to Figure 6 Positron circuit 600 is depicted.

[0056] The negative subcircuit 700 may include a plurality of multiplexers, such as a first multiplexer 702, a second multiplexer 704, a third multiplexer 706, a fourth multiplexer 708, a fifth multiplexer 710, a sixth multiplexer 712, and a seventh multiplexer 714. The negative subcircuit 700 may also include a plurality of adder circuits, such as a first adder circuit 716 and a second adder circuit 718. The negative subcircuit 700 may also include a plurality of flip-flops, such as a first flip-flop 720 and a second flip-flop 722. The multiplexers 702-716 may receive configuration bits as negative digital bits. The negative digital bits may be the negative terms of the first input operand converted to CSD representation. The first input operand may be converted to CSD representation using a table, such as the table depicted below for an 8-bit signed multiplier. For simplicity, only an excerpt of the table is depicted below, but the entire table should be understood by those skilled in the art to include all numbers from -128 to 128.

[0057] Binary CSD- -128 -10000000 10000000 -91 -01011011 10000000 -85 -01010101 01010101 -3 -00000011 00000100 3 00000011 00000001 85 01010101 00000000 91 01011011 00100101 128 10000000 00000000

[0058] The first multiplexer 702 may be a 2:1 multiplexer configured to receive two inputs from a plurality of registers, such as a first register 724 and a second register 726. The plurality of registers may correspond to Figure 2 The depicted register 202. Based on the negative digital bit, the first multiplexer 702 can output one of the two inputs to the fourth multiplexer 708. The second multiplexer 704 can be a 4:1 multiplexer configured to receive four inputs from a plurality of registers, such as from a third register 728, a fourth register 730, a fifth register 732, and a sixth register 734. Based on the negative digital bit, the second multiplexer 704 can output one of the four inputs to the fifth multiplexer 710. The third multiplexer 706 can also be a 4:1 multiplexer configured to receive four inputs from a plurality of registers, such as from a fifth register 732, a sixth register 734, a seventh register 736, and an eighth register 738. Based on the negative digital bit, the third multiplexer 706 can output one of the four inputs to the sixth multiplexer 712.

[0059] The fourth multiplexer 708 may be a 2:1 multiplexer configured to receive an input from the first multiplexer 702 and an empty bit input. Based on the negative digital bit, the fourth multiplexer 708 may output the input from the first multiplexer 702 or an empty bit to the first adder circuit 716. The fifth multiplexer 710 may also be a 2:1 multiplexer configured to receive an input from the second multiplexer 704 and an empty bit input. Based on the negative digital bit, the sixth multiplexer 710 may output the input from the second multiplexer 704 or an empty bit to the first adder circuit 716. The sixth multiplexer 712 may still also be a 2:1 multiplexer configured to receive an input from the third multiplexer 706 and an empty bit input. Based on the negative digital bit, the sixth multiplexer 712 can output the input from the third multiplexer 706 or a null bit to the seventh multiplexer 714. In other examples, one or more of the fourth multiplexer 708, the fifth multiplexer 710, and the sixth multiplexer 712 can be replaced with an AND gate or any logical equivalent circuit.

[0060] The first adder circuit 716 may be configured to add the outputs received from the fourth multiplexer 708 and the fifth multiplexer 710 to generate an output provided to the second adder circuit 718. The output of the first adder circuit 716 may also be input to the first flip-flop 720 to store the output of the first adder circuit 716 for one cycle. The output of the first flip-flop 720 may be input to the second flip-flop 722 to store the output of the first flip-flop 720 for one cycle. The output of the second flip-flop 722 may be input to the seventh multiplexer 714.

[0061] The seventh multiplexer 714 may be a 2:1 multiplexer configured to receive an input from the second flip-flop 722 and an input from the sixth multiplexer 712. Based on the negative digital bit, the seventh multiplexer 714 may output one of the two inputs to the second adder circuit 718. The second adder circuit 718 may be configured to add the outputs received from the first adder circuit 716 and the seventh multiplexer 714 to generate an output representing a negative term.

[0062] Although Figures 3 to 7 The positive and negative subcircuits are depicted for the 3-bit unsigned multiplier example and the 8-bit signed multiplier example, but as Figure 2 The depicted positive and negative subcircuits can be used for signed or unsigned multipliers of arbitrary bits. In addition, although Figures 3 to 7 The positive and negative subcircuits for single-bit serial multiplication are depicted, but as Figure 2 The depicted positive and negative subcircuits may be used for multi-bit serial multiplication by including additional adder circuits and / or shift registers.

[0063] Figure 8 A block diagram of an example multiplier circuit 800 is depicted, which implements a switch to allow fewer and / or smaller circuit systems, thereby saving space in the circuit package. As a result, the technical effect of reducing the size of the circuit package can be achieved. In the example multiplier circuit 800, the first input operand has been converted to a set of configuration bits associated with the signed digital representation. The multiplier circuit 800 may include multiple input registers 802, a large term subcircuit 804, a small term subcircuit 806, a switch 808, and a subtractor 810. The large term subcircuit 804, the small term subcircuit 806, the switch 808, and the subtractor 810 may correspond to Figure 1 The processing circuit 104 depicted. As an example, the large term subcircuit 804 can correspond to a circuit for 1 to 4 terms of the operand, and the small term subcircuit 806 can correspond to a circuit for 1 to 2 terms of the operand. For example, in a CSD representation of an n-bit number, the sum of the "1"s in the positive and negative terms will be less than or equal to half of n. Therefore, if the positive term contains p "1's", the negative term will have n / 2-p "1's" or less, and vice versa. Instead of splitting the processing circuit into positive and negative terms, the processing circuit can be split into a large term subcircuit 804 and a small term subcircuit 806, wherein the switch 808 is configured to place each term in the correct position of the subtractor 810. In this way, separate components for positive and negative terms are not required, and therefore less circuitry is required to complete the calculation.

[0064] The plurality of input registers 802 may receive the second input operand. The plurality of input registers 802 may be configured to store the input operand to be provided as bits to the big-term subcircuit 804 and the small-term subcircuit 806.

[0065] The big term subcircuit 804 and the small term subcircuit 806 may also receive a configuration bit, which is a first input operand converted to a signed digital representation. The big term subcircuit 804 may receive the big term bit, and the small term subcircuit 806 may receive the small term bit. The small term subcircuit 806 may be a subset of the big term subcircuit 804. The big term subcircuit 804 and the small term subcircuit 806 may each include a plurality of multiplexers and adder circuits. For the big term subcircuit 804, the multiplexer may select the bit received from the input register 802 based on the big term bit. For the small term subcircuit 806, the multiplexer may select the bit received from the input register 802 based on the small term bit. The output of the multiplexer may be provided to the adder circuit, which adds the output to generate a first field of the big term of the signed digital representation and a second field of the small term of the signed digital representation for the big term subcircuit 804 and the small term subcircuit 806, respectively. The exchanger 808 can be configured to exchange the major terms and minor terms from the first field and the second field, respectively, based on the received configuration bits to generate an exchanged first field and an exchanged second field. Based on the received configuration bits, the exchanger 808 can also retain the major terms and minor terms as they are. The subtractor 810 can be configured to subtract the exchanged second field from the exchanged first field, or if there is no exchange, subtract the second field from the first field to generate a multiplication output.

[0066] Fig. 9 A block diagram of an example large term subcircuit 900 for an 8-bit signed multiplier is depicted. The large term subcircuit 900 may correspond to Figure 8 The depicted large term subcircuit 804. The large term subcircuit 900 may correspond to a positive subcircuit, such as Figure 5 The positron circuit 500 depicted or Figure 6 The depicted positron circuit 600. Fig. 9 The depicted large term subcircuit 900 corresponds to Figure 6 Positron circuit 600 is depicted.

[0067] The large term subcircuit 900 may include a plurality of multiplexers, such as a first multiplexer 902, a second multiplexer 904, a third multiplexer 906, a fourth multiplexer 908, a fifth multiplexer 910, a sixth multiplexer 912, and a seventh multiplexer 914. The large term subcircuit 900 may also include a plurality of adder circuits, such as a first adder circuit 916 and a second adder circuit 918. The large term subcircuit 900 may also include a plurality of flip-flops, such as a first flip-flop 920 and a second flip-flop 922. The multiplexers 902-916 may receive configuration bits as large term bits. The large term bits may be 1 to 4 of the first input operand converted to CSD representation. The first input operand may be converted to CSD representation using a table.

[0068] The first multiplexer 902 may be a 2:1 multiplexer configured to receive two inputs from a plurality of registers, such as a first register 924 and a second register 926. The plurality of registers may correspond to Figure 8 802 is depicted. Based on the major entry bit, the first multiplexer 902 can output one of the two inputs to the fourth multiplexer 908. The second multiplexer 904 can be a 4:1 multiplexer configured to receive four inputs from a plurality of registers, such as from a third register 928, a fourth register 930, a fifth register 932, and a sixth register 934. Based on the major entry bit, the second multiplexer 904 can output one of the four inputs to the fifth multiplexer 910. The third multiplexer 906 can also be a 4:1 multiplexer configured to receive four inputs from a plurality of registers, such as from a fifth register 932, a sixth register 934, a seventh register 936, and an eighth register 938. Based on the major entry bit, the third multiplexer 906 can output one of the four inputs to the sixth multiplexer 912.

[0069] The fourth multiplexer 908 may be a 2:1 multiplexer configured to receive an input from the first multiplexer 902 and an empty bit input. Based on the major term bit, the fourth multiplexer 908 may output an input from the first multiplexer 902 or an empty bit to the first adder circuit 916. The fifth multiplexer 910 may also be a 2:1 multiplexer configured to receive an input from the second multiplexer 904 and an empty bit input. Based on the major term bit, the sixth multiplexer 910 may output an input from the second multiplexer 904 or an empty bit to the first adder circuit 916. The sixth multiplexer 912 may still also be a 2:1 multiplexer configured to receive an input from the third multiplexer 906 and an empty bit input. Based on the major term bit, the sixth multiplexer 912 can output the input from the third multiplexer 906 or the empty bit to the seventh multiplexer 914. In other examples, one or more of the fourth multiplexer 908, the fifth multiplexer 910, and the sixth multiplexer 912 can be replaced with an AND gate or any logical equivalent circuit.

[0070] The first adder circuit 916 may be configured to add the outputs received from the fourth multiplexer 908 and the fifth multiplexer 910 to generate an output provided to the second adder circuit 918. The output of the first adder circuit 916 may also be input to the first flip-flop 920 to store the output of the first adder circuit 916 for one cycle. The output of the first flip-flop 920 may be input to the second flip-flop 922 to store the output of the first flip-flop 920 for one cycle. The output of the second flip-flop 922 may be input to the seventh multiplexer 914.

[0071] The seventh multiplexer 914 may be a 2:1 multiplexer configured to receive an input from the second flip-flop 922 and an input from the sixth multiplexer 912. Based on the major term bit, the seventh multiplexer 914 may output one of the two inputs to a second adder circuit 918. The second adder circuit 918 may be configured to add the outputs received from the first adder circuit 916 and the seventh multiplexer 914 to generate an output representing the major term.

[0072] Fig.10 A block diagram of an example small term subcircuit 1000 for an 8-bit signed multiplier is depicted. The small term subcircuit 1000 may correspond to Figure 8 The depicted small term subcircuit 806. The small term subcircuit 1000 may be as follows Fig. 9 A subset of the larger subcircuit 900 is depicted.

[0073] The small term subcircuit 1000 may include a plurality of multiplexers, such as a first multiplexer 1002, a second multiplexer 1004, a third multiplexer 1006, and a fourth multiplexer 1008. The small term subcircuit 1000 may also include one or more adder circuits, such as an adder circuit 1010. Multiplexers 1002-1008 may receive configuration bits as small term bits. The small term bits may be 1 to 2 terms of a first input operand converted to a CSD representation. The first input operand may be converted to a CSD representation using a table.

[0074] The first multiplexer 1002 may be a 4:1 multiplexer configured to receive four inputs from a plurality of registers, such as a first register 1012, a second register 1014, a third register 1016, and a fourth register 1018. The plurality of registers may correspond to, for example, Figure 8 The depicted register 802. Based on the small term bit, the first multiplexer 1002 can output one of the four inputs to the third multiplexer 1006. The second multiplexer 1004 can be a 2:1 multiplexer configured to receive two inputs from a plurality of registers, such as from a fifth register 1020 and a sixth register 1022. Based on the small term bit, the second multiplexer 1004 can output one of the two inputs to the fourth multiplexer 1008.

[0075] The third multiplexer 1006 may be a 2:1 multiplexer configured to receive an input and an empty bit input from the first multiplexer 1002. Based on the small term bit, the third multiplexer 1006 may output the input from the first multiplexer 1002 or an empty bit to the adder circuit 1010. The fourth multiplexer 1008 may also be a 2:1 multiplexer configured to receive an input and an empty bit input from the second multiplexer 1004. Based on the small term bit, the fourth multiplexer 1008 may output the input from the second multiplexer 1004 or an empty bit to the adder circuit 1010. In other examples, one or more of the third multiplexer 1006 and the fourth multiplexer 1008 may be replaced with an AND gate or any logical equivalent circuit.

[0076] The adder circuit 1010 may be configured to add the outputs received from the third multiplexer 1006 and the fourth multiplexer 1008 to generate an output representing a small term.

[0077] Although Figures 9 and 10 The big-term and small-term subcircuits for the 8-bit signed multiplier example are depicted, but Figure 8 The depicted large-term and small-term subcircuits can be used for signed or unsigned multipliers of arbitrary bits. Figures 9 and 10 The large-term and small-term subcircuits for single-bit serial multiplication are depicted, but Figure 8 The depicted large-term subcircuit and small-term subcircuit may be used for multi-bit serial multiplication by including additional adder circuits and / or shift registers.

[0078] Fig.11 1 depicts a block diagram of a data processing system 1100 that implements an example computing unit 1102. Computing unit 1102 may be or include any of a variety of different computing units, such as Figure 1 to Figure 2 or Figure 8 The multiplier circuit depicted.

[0079] Data processing system 1100 may include a host interface 1104, a sequencer circuit 1106, one or more processors 1108, a memory 1110, and a timing circuit 1112. Data processing system 1100 may be implemented in one or more devices at one or more physical locations, such as those described above. Fig.12 Further described. In some examples, the components of data processing system 1100 can be implemented on one or more chips, which can be interfaced with a host device according to any of a variety of data buses or other physical interconnect interfaces. In some examples, data processing system 1100 can be implemented on one or more devices on a network, for example, on one or more servers of a cloud platform.

[0080] The processor 1108 and the memory 1110 may be as described herein with reference to Fig.12 Any of the various different types of processors and memories described. In some examples, processor 1108 receives instructions that can be executed by computing unit 1102 to process data. For example, the instructions can be part of a computer program written to perform operations using computing unit 1102. Computer program instructions are provided herein that, when executed by computing unit 1102, cause one or more computers to perform the methods described herein.

[0081] The sequencer circuit 1106 may convert the received instructions into one or more signals understood by the computing unit 1102, which cause the computing unit 1102 to perform any of a variety of preconfigured operations. These operations may include loading data (e.g., from the memory 1110) into the multiplier circuit of the computing unit 1102, moving the data into one or more processing elements of the multiplier circuit, processing the data by one or more processing elements, and pushing the data out of the multiplier circuit. The sequencer circuit 1106 may also be configured to generate one or more control signals to control when instructions are pushed to the computing unit 1102.

[0082] Host interface 1104 may be configured to receive data from outside of data processing system 1100 (e.g., from a processor or another device) and to send data generated by computing unit 1102 (e.g., the product of a matrix multiplication) to outside of data processing system 1100 (e.g., one or more devices or processors).

[0083] Timing circuit 1112 may be configured to control the timing of computing unit 1102 , such as its clock frequency or clock rate. For example, operations performed by computing unit 1102 may be performed once per clock cycle, where such clock cycles are managed by timing circuit 1112 .

[0084] Data processing system 1100 may also be connected to power source 1114. Power source 1114 may be a battery or other form of power available on a host device implementing data processing system 1100, or may be a source that is external to the host device and connected to the host device and data processing system 1100 by some wireless or physical connection (e.g., by wires). Power source 1114 may supply a voltage to computing unit 1102 that may be managed by processor 1108, such as adjusted to be higher or adjusted to be lower.

[0085] Fig.12 A block diagram of an example environment 1200 for implementing a data processing system 1202 including a computing unit is depicted. The data processing system 1202 may correspond to Fig.11 The data processing system 1100 is depicted. The data processing system 1202 may be implemented on one or more devices having one or more processors in one or more locations, such as in a server computing device 1204. The user computing device 1206 and the server computing device 1204 may be communicatively coupled to one or more storage devices 1208 via a network 1210. The storage device 1208 may be a combination of volatile memory and non-volatile memory and may be located in the same or a different physical location as the computing devices 1204, 1206. For example, the storage device 1208 may include any type of non-transitory computer-readable medium capable of storing information, such as a hard drive, a solid-state drive, a tape drive, optical storage, a memory card, ROM, RAM, DVD, CD-ROM, writable memory, and read-only memory.

[0086] The server computing device 1204 may include one or more processors 1212 and memory 1214. The memory 1214 may store information accessible by the processor 1212, including instructions 1216 that may be executed by the processor 1212. The memory 1214 may also include data 1218 that may be retrieved, manipulated, or stored by the processor 1212. The memory 1214 may be a type of non-transitory computer-readable medium capable of storing information accessible by the processor 1212, such as volatile memory and non-volatile memory. The processor 1212 may include one or more central processing units (CPUs), graphics processing units (GPUs), field programmable gate arrays (FPGAs), and / or application-specific integrated circuits (ASICs), such as tensor processing units (TPUs). The non-transitory computer-readable storage medium may have instructions stored thereon that, in response to execution by one or more processors 1212 of the server computing device 1204, cause the server computing device 1204 to perform the methods described herein.

[0087] Instructions 1216 may include one or more instructions that, when executed by processor 1212, cause one or more processors 1212 to perform actions defined by instructions 1216. Instructions 1216 may be stored in an object code format for direct processing by processor 1212, or in other formats, including interpretable scripts or independent source code module sets that are interpreted on demand or compiled in advance. Instructions 1216 may include instructions for implementing data processing system 1202 as described herein. Data processing system 1202 may be executed using processor 1212, and / or using other processors located remotely from server computing device 1204.

[0088] Data 1218 may be retrieved, stored, or modified by processor 1212 in accordance with instructions 1216. Data 1218 may be stored in a computer register, in a relational or non-relational database as a table with a plurality of different fields and records, or as a JSON, YAML, proto, or XML document. Data 1218 may also be formatted in a computer-readable format, such as, but not limited to, binary values, ASCII, or Unicode. In addition, data 1218 may include information sufficient to identify the relevant information, such as numbers, descriptive text, proprietary codes, pointers, references to data stored in other storage (including other network locations), or information used by a function to calculate the relevant data.

[0089] The user computing device 1206 may also be configured similarly to the server computing device 1204, with one or more processors 1220, memory 1222, instructions 1224, and data 1226. The user computing device 1206 may also include user output 1228 and user input 1230. The user input 1230 may include any suitable mechanism or technology for receiving input from a user, such as a keyboard, mouse, mechanical actuator, soft actuator, touch screen, microphone, and sensor.

[0090] The server computing device 1204 may be configured to transmit data to the user computing device 1206, and the user computing device 1206 may be configured to display at least a portion of the received data on a display implemented as part of the user output 1228. The user output 1228 may also be used to display an interface between the user computing device 1206 and the server computing device 1204. The user output 1228 may alternatively or additionally include one or more speakers, transducers or other audio outputs, tactile interfaces, or other tactile feedback that provides non-visual and non-auditory information to a platform user of the user computing device 1206.

[0091] although Fig.12 Processors 1212, 1220 and memories 1214, 1222 are shown as being within computing devices 1204, 1206, but the components described herein may include multiple processors and memories that may operate at different physical locations rather than within the same computing device. For example, processor 1212 may include a set of processors that may perform concurrent and / or sequential operations.

[0092] The server computing device 1204 may be configured to receive requests for processing data from the user computing device 1206. For example, the environment 1200 may be part of a computing platform configured to provide various services to users through various user interfaces and / or APIs that expose the platform services. One or more services may be a machine learning framework, or a collection of tools for generating neural networks or other machine learning models based on specified tasks and training data. The user computing device 1206 may receive and transmit data that specifies operations to be performed by the computing units of the data processing system 1202.

[0093] The computing devices 1204, 1206 may be able to communicate directly and indirectly over the network 1210. The computing devices 1204, 1206 may set up listening sockets that may accept initiated connections for sending and receiving information. The network 1210 itself may include a variety of configurations and protocols, including the Internet, the World Wide Web, an intranet, a virtual private network, a wide area network, a local area network, and a private network using one or more company-proprietary communication protocols. The network 1210 may support a variety of short-range and long-range connections. The short-range and long-range connections may be made over different bandwidths, such as 2.402 GHz to 2.480 GHz (commonly used with wireless networks). standards), 2.4 GHz and 11 GHz (usually associated with or using various communication standards, such as for wireless broadband communication Additionally or alternatively, the network 1210 may also support wired connections between the computing devices 1204, 1206, including through various types of Ethernet connections.

[0094] although Fig.12 A single server computing device 1204, a user computing device 1206, and a data processing system 1202 are shown, but it should be understood that various aspects of the present disclosure can be implemented according to various different configurations and numbers of computing devices (including in examples of sequential or parallel processing), or through a distributed network of multiple devices. In some implementations, various aspects of the present disclosure can be performed on a single device and any combination thereof. In some examples, one or more devices implement one or more data processing systems, each of which includes one or more computing units according to various aspects of the present disclosure. In some examples, a single device can implement multiple computing units, each of which is configured to communicate with at least one other computing unit to perform distributed data processing tasks, such as in sequential or parallel processing.

[0095] Aspects of the present disclosure may be implemented in digital electronic circuit systems, or in tangibly embodied computer software or firmware and / or in computer hardware (such as the structures disclosed herein, their structural equivalents, or combinations thereof). Aspects of the present disclosure may be further implemented as one or more computer programs, such as one or more modules of computer program instructions encoded on a tangible, non-transitory computer storage medium, for one or more data processing devices to execute or control the operation of the one or more data processing devices. The computer storage medium may be a machine-readable storage device, a machine-readable storage substrate, a random or serial access memory device, or a combination thereof. The computer program instructions may be encoded on an artificially generated propagation signal (such as a machine-generated electrical, optical, or electromagnetic signal), which is generated to encode information for transmission to a suitable receiver device for execution by a data processing device.

[0096] The term "configuration" is used herein in conjunction with system and computer program components. For a system of one or more computers configured to perform specific operations or actions, it is meant that the system has installed thereon software, firmware, hardware, or a combination thereof that causes the system to perform those operations or actions. For one or more computer programs configured to perform specific operations or actions, it is meant that the one or more programs include instructions that, when executed by one or more data processing devices, cause the devices to perform those operations or actions.

[0097] The term "data processing apparatus" or "data processing system" refers to data processing hardware and encompasses a variety of devices, apparatuses, and machines for processing data, including programmable processors, computers, or combinations thereof. Data processing apparatus may include dedicated logic circuitry, such as a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC). Data processing apparatus may include code that creates an execution environment for a computer program, such as code that constitutes processor firmware, a protocol stack, a database management system, an operating system, or a combination thereof.

[0098] The term "computer program" refers to a program, software, software application, application, module, software module, script or code. A computer program can be written in any form of programming language, including compiled, interpreted, declarative or procedural languages ​​or combinations thereof. A computer program can be deployed in any form, including as a stand-alone program or as a module, component, subroutine or other unit suitable for a computing environment. A computer program may correspond to a file in a file system and may be stored in a portion of a file that holds other programs or data (such as one or more scripts stored in a markup language document), in a single file dedicated to the program in question, or in multiple coordinated files (such as files storing one or more modules, subroutines or code portions). A computer program may be executed on one computer or on multiple computers located at one site, or distributed on multiple sites and interconnected by a data communications network.

[0099] The term "database" refers to any data set. The data may be unstructured, or structured in any manner. The data may be stored on one or more storage devices in one or more locations. For example, an index database may include multiple data sets, each of which may be organized and accessed differently.

[0100] The term "engine" refers to a software-based system, subsystem, or process that is programmed to perform one or more specific functions. An engine can be implemented as one or more software modules or components or can be installed on one or more computers in one or more locations. A specific engine can have its own dedicated computer or computers, or multiple engines can be installed and run on the same computer or computers.

[0101] The processes and logic flows described herein may be performed by one or more computers executing one or more computer programs to perform functions by operating on input data and generating output data. The processes and logic flows may also be performed by a dedicated logic circuit system or by a combination of a dedicated logic circuit system and one or more computers.

[0102] A computer or dedicated logic circuit system that executes one or more computer programs may include a central processing unit (including a general or special microprocessor) for running or executing instructions, and one or more memory devices for storing instructions and data. The central processing unit can receive instructions and data from one or more memory devices (such as read-only memory, random access memory, or a combination thereof), and can run or execute these instructions. The computer or dedicated logic circuit system may also include or be operatively coupled to one or more storage devices (such as magnetic disks, magneto-optical disks, or optical disks) for storing data to receive data from the storage device or transfer data to the storage device. The computer or dedicated logic circuit system may be embedded in another device, such as, for example, a mobile phone, a personal digital assistant (PDA), a mobile audio or video player, a game console, a global positioning system (GPS), or a portable storage device, such as a universal serial bus (USB) flash drive.

[0103] Computer-readable media suitable for storing one or more computer programs may include any form of volatile or non-volatile memory, medium, or storage device. Examples include semiconductor memory devices (e.g., EPROM, EEPROM, or flash memory devices), magnetic disks (e.g., internal hard disks or removable disks), magneto-optical disks, CD-ROM disks, DVD-ROM disks, or combinations thereof.

[0104] Aspects of the invention may be implemented in a computing system that includes a back-end component (e.g., as a data server), a middleware component (e.g., an application server), or a front-end component (e.g., a client computer with a graphical user interface, a web browser, or an application, or any combination thereof). The components of the system may be interconnected by any form or medium of digital data communication, such as a communication network. Examples of communication networks include local area networks (LANs) and wide area networks (WANs), such as the Internet.

[0105] A computing system may include a client and a server. The client and server may be remote from each other and interact through a communication network. The relationship of client and server arises from computer programs running on respective computers and having a client-server relationship to each other. For example, a server may transmit data (e.g., an HTML page) to a client device (e.g., for the purpose of displaying data to a user interacting with the client device and receiving user input from the user). Data generated at the client device (e.g., the result of a user interaction) may be received from the client device at the server.

[0106] Unless otherwise stated, the foregoing alternative examples are not mutually exclusive, but may be implemented in various combinations to achieve unique advantages. Since these and other variations and combinations of the features discussed above may be utilized without departing from the subject matter defined by the claims, the description of the foregoing embodiments should be made in an illustrative manner rather than in a manner that limits the subject matter defined by the claims. In addition, the examples described herein and the provision of clauses expressed as "such as," "including," etc. should not be interpreted as limiting the subject matter of the claims to specific examples; rather, these examples are intended to illustrate only one of many possible embodiments. In addition, the same reference numerals in different figures may identify the same or similar elements.

Claims

1. A multiplier circuit for semi-constant operand multiplication, the multiplier circuit comprising a first subcircuit, a second subcircuit and one or more processors, the one or more processors being configured to: receiving a first operand and a second operand for multiplication; converting the first operand to a signed digital representation, the signed digital representation including positive and negative numbers; processing the second operand in the first subcircuit based on the positive number to generate a positive field of the signed digital representation; processing the second operand in the second subcircuit based on the negative number to generate a negative field of the signed digital representation; and The negative field is subtracted from the positive field to generate a multiplication output.

2. The multiplier circuit of claim 1, wherein the second subcircuit is a subset of the first subcircuit.

3. The multiplier circuit of claim 1, wherein the first subcircuit and the second subcircuit are equivalent.

4. The multiplier circuit of claim 1, wherein the first subcircuit comprises one or more multiplexer and adder circuits.

5. The multiplier circuit of claim 4, wherein processing the second operand in the first subcircuit further comprises outputting the output of the one or more multiplexers as input to one or more adder circuits.

6. The multiplier circuit of claim 1, wherein the second subcircuit comprises one or more multiplexer and adder circuits.

7. The multiplier circuit of claim 6, wherein processing the second operand in the second subcircuit further comprises outputting the output of the one or more multiplexers as input to one or more adder circuits.

8. The multiplier circuit of claim 1, wherein the one or more processors are further configured to swap positive terms of the positive field with negative terms of the negative field.

9. The multiplier circuit of claim 1, wherein the multiplier circuit is implemented in at least one of a field programmable gate array (FPGA) or an application specific integrated circuit (ASIC).

10. A multiplier circuit for semi-constant operand multiplication, the multiplier circuit comprising a processing circuit and one or more processors, the one or more processors being configured to: receiving a first operand and a second operand for multiplication; converting the first operand to a set of configuration bits; and The second operand is processed using the set of configuration bits to generate a multiplication output.

11. The multiplier circuit of claim 10, wherein converting the first operand to a set of configuration bits comprises converting the first operand to a signed digital representation.

12. The multiplier circuit of claim 10 , wherein processing the second operand comprises: processing the second operand in a first subcircuit of the processing circuit using a first portion of the set of configuration bits to generate a first output; as well as The second operand is processed in a second subcircuit of the processing circuit using a second portion of the set of configuration bits to generate a second output.

13. The multiplier circuit of claim 12, wherein processing the second operand comprises subtracting the second output from the first output to generate the multiplied output.

14. The multiplier circuit of claim 12, wherein the second subcircuit is a subset of the first subcircuit, or the first subcircuit and the second subcircuit are equivalent.

15. The multiplier circuit of claim 12, wherein the first subcircuit comprises one or more multiplexer and adder circuits.

16. The multiplier circuit of claim 15, wherein processing the second operand in the first subcircuit further comprises outputting the output of the one or more multiplexers as input to one or more adder circuits.

17. The multiplier circuit of claim 12, wherein the second subcircuit comprises one or more multiplexer and adder circuits.

18. The multiplier circuit of claim 17, wherein processing the second operand in the second subcircuit further comprises outputting the output of the one or more multiplexers as input to one or more adder circuits.

19. The multiplier circuit of claim 10, wherein processing the second operand further comprises swapping one or more outputs.

20. A method for semi-constant operand multiplication, comprising: receiving, by one or more processors, a first operand and a second operand for multiplication; converting, by the one or more processors, the first operand to a signed digital representation, the signed digital representation including positive and negative numbers; processing, by the one or more processors, the second operand in a first subcircuit of a multiplier circuit based on the positive number to generate a positive field of the signed digital representation; processing, by the one or more processors, the second operand in a second subcircuit of the multiplier circuit based on the negative number to generate a negative field of the signed digital representation; as well as The negative field is subtracted from the positive field by the one or more processors to generate a multiplication output.

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