Semiconductor arrangement with direct liquid cooling

Abstract

A semiconductor arrangement (100a, 100b) comprising: a power module (110) for power conversion, the power module (110) comprising a first module side (111a) and a second module side (111b) opposite the first module side (111a) wherein a first mold body (113) is disposed between the first module side (111a) and the second module side (111b); the first module side (111a) comprises an upper metal layer (114a); a second mold body (120) at least partially encapsulating the power module (110), in which a portion of the upper metal layer (114a) forming an upper heat dissipation region (115a) of the power module (110) is not covered by the second mold body (120); in a transition region (131a) between the upper heat dissipation region (115a) and the second mold body (120), the upper heat dissipation region (115a) and the second mold body (120) are covered by an upper metal sealing element (130a) to seal the power module (110), preventing coolant from flowing through the upper heat dissipation region (115a).

Description

Technical Field

[0001] The present application relates to the field of sealing technology for direct liquid cooling of electronic modules, for example, cooling molded power modules that can be used in automobiles and industrial equipment, etc. The present application particularly relates to a semiconductor arrangement cooled by a coolant. The present application also relates to a sealing element to seal a power module to prevent the flow of coolant. Background Art

[0002] In automotive and industrial applications, especially in automotive inverter systems, efficient cooling is critical for improved performance and longer service life. Such cooling systems involve heat paths from the chip surface to the cooling medium (coolant, for example, water or a water glycol mixture). The more efficient these heat paths are, the higher the power that the system can handle within a given active chip area. Basic simulations of cooling power modules have shown that the performance of "direct liquid cooling" technology is higher than other technologies. This concept assumes that the cooling medium is in direct contact with the heat dissipation area of ​​the package, so efficient sealing of the cooling medium is required.

[0003] Recent results have shown that the sealing of the package to the cooling medium produced by the molding process is insufficient, since the temperature of the mold during the molding process is not high enough when it reaches the area of ​​the power module. A "cold" mold leads to insufficient adhesion and thus to insufficient sealing.

[0004] Therefore, a sealing concept is needed to achieve optimal sealing reliability for direct liquid cooling modules. Summary of the invention

[0005] The apparatus and method according to the present application may provide a solution for semiconductor arrangements using coolants for cooling without the above-mentioned disadvantages.

[0006] Therefore, a solution for an efficient sealed direct liquid cooling module is provided.

[0007] The above and other objects are achieved by the features of the independent claims. Other implementations are apparent from the dependent claims, the description and the drawings.

[0008] This application provides two different embodiments for sealing:

[0009] 1) The first embodiment relates to a sealing ring, also called a sealing ring, such as Figure 1 and Figure 3 As described in.

[0010] 2) The second embodiment is based on, for example Figure 2 and Figure 4 The sealing cover described in.

[0011] The solution proposed in this application may involve one or more of the following:

[0012] - Repositioning the sealing area to the top of the second mould body by means of a suitable sealing element, which can be used in two different embodiments, in embodiment 1 as a sealing ring, also called a sealing ring, and in embodiment 2 as a sealing cover, which can be made of aluminium, for example.

[0013] - The sealing element (ie the sealing ring or the sealing cover) is mounted and sealed to the module cooler surface (made of aluminum in Example 1 and made of copper in Example 2) by laser welding or ultrasonic welding.

[0014] - Since the second mold body will initially have stickiness issues (resulting in a cold mold as described above), an additional laser processing step is required

[0015] The lower overlapping mold body is remelted so that the rough surface of the sealing element and the thermoplastic of the second mold body are reliably interconnected with each other.

[0016] - The turbulence structure is fixed directly to the module cooler surface by means of a laser welding step or an ultrasonic welding process. The first version uses a zigzag

[0017] shaped components, the second version uses aluminum tape adhesive.

[0018] - The sealing cover of embodiment 2 may have a pre-attached turbulent structure.

[0019] - The turbulent structure can be formed asymmetrically for junction temperature matching.

[0020] - Cooling fins for turbulent liquid flow can be positioned according to the orientation of the chip in the power module to achieve ideal short thermal

[0021] path and ensure the lowest temperature deviation between each chip.

[0022] - Compared with indirect cooling methods, the critical heat path from the chip (heat source) to the cooling medium (such as water or ethylene glycol) can be shortened.

[0023] - Due to the overlapping concept proposed in this application, the solution described below improves the connection between the module cooler area and the second mold body.

[0024] The sealing and interconnection quality between them.

[0025] - The sealing ring (Example 1) does not require additional interlayers which could affect the thermal path or integrity of the module.

[0026] - Thanks to the sealing solution described in this application, it is no longer necessary to roughen the cooler for better adhesion.

[0027] - The turbulence structure can be easily attached to the module cooler area by direct bonding or welding.

[0028] - For the sealing cover according to embodiment 2, an asymmetric turbulent structure can be used. The asymmetric turbulent structure makes all the turbulent flows in the system

[0029] All chips can operate at almost the same junction temperature level, which is extremely beneficial to improving system performance.

[0030] - The turbulence structure can be easily clamped on the module surface.

[0031] The present application also relates to a turbulent structure, in particular an uneven turbulent structure. This turbulent structure can be sandwiched between the cooler area of ​​the module and the cover plate (top and bottom) so that the chip temperature can be balanced, for example, within a certain range of about 5°C, 10°C or 15°C throughout the semiconductor arrangement. This temperature balance is conducive to the uniform flow of the cooling medium through the power module, thereby improving performance and reliability. In this concept, an uneven turbulent plug can be attached to the cooler area, for example, sandwiched between the cooler area and the cover plate (top and bottom). The uneven turbulent plug ensures such contact and such diffusion properties that the chip temperature can be maintained within a certain temperature range, for example, within 5°C, 10°C or 15°C even under full load.

[0032] According to a first aspect, the present application relates to a semiconductor arrangement with coolant cooling, the semiconductor arrangement comprising: a power module for power conversion, the power module comprising a first module side and a second module side opposite to the first module side, wherein a first mold body is arranged between the first module side and the second module side; the first module side comprises an upper metal layer; a second mold body at least partially encapsulating the power module, wherein a portion of the upper metal layer forming an upper heat dissipation area of ​​the power module is not covered by the second mold body; in a transition area between the upper heat dissipation area and the second mold body, the upper heat dissipation area and the second mold body are covered by an upper metal sealing element to seal the power module and prevent coolant from flowing through the upper heat dissipation area.

[0033] This semiconductor arrangement provides a seal that enables optimal sealing reliability for direct liquid-cooled modules, whether single-sided or double-sided cooled modules.

[0034] Although a semiconductor arrangement with a power module is described above, this is not limited to a semiconductor arrangement consisting of a single power module. It should be understood that the semiconductor arrangement may include one or more such power modules.

[0035] In an exemplary implementation of the semiconductor arrangement, the upper metal sealing element forms a solder joint with the upper heat sink region.

[0036] This has the advantage that heat can be optimally transferred from the power module to the upper heat dissipation area via the solder joint.

[0037] In an exemplary implementation of the semiconductor arrangement, the upper metal sealing element forms a rough surface connection with the second mold body in the transition area between the upper heat sink region and the second mold body.

[0038] The rough surface structure provides the technical effect that the upper metal sealing element comprises a drilled structure that can snap into the soft material of the second mold body, for example, a drilled structure made of thermoplastic. Thus, the rough surface structure of the upper metal sealing element has sharp edges that snap into the second mold body and thus provide a tight or sealed connection by mechanical adhesion (for example, in the manner of Velcro fasteners).

[0039] In an exemplary implementation of the semiconductor arrangement, the second mold body includes a remelted mold material in the transition region between the upper heat sink region and the second mold body, the remelted mold material having a rough surface.

[0040] This has the advantage that the rough surface structure of the remelted second mold body can be efficiently clamped into the rough surface structure of the upper metal sealing element to provide an optimal seal.

[0041] In an exemplary implementation of the semiconductor arrangement, the second module side includes a lower metal layer; wherein a portion of the lower metal layer forming a lower heat dissipation region of the power module is not covered by the second mold body; the semiconductor arrangement also includes: in a transition area between the lower heat dissipation region and the second mold body, the lower heat dissipation region and the second mold body are covered by a lower metal sealing element to seal the power module and prevent coolant from flowing through the lower heat dissipation region.

[0042] This semiconductor arrangement provides a seal that enables optimal sealing reliability not only for single-sided cooling modules but also for double-sided cooling modules.

[0043] In an exemplary implementation of the semiconductor arrangement, the semiconductor arrangement includes: a turbulence element installed above the upper metal layer and / or below the lower metal layer, for generating turbulence in the coolant flowing through the upper heat dissipation area and / or below the lower heat dissipation area.

[0044] By using such a turbulence element, the power module can be cooled efficiently. The turbulence generated by the turbulence element on the cooling medium enables all semiconductor chips of the power module to have similar junction temperatures and similar cooling conditions.

[0045] In an exemplary implementation of the semiconductor arrangement, the upper metal sealing element forms a sealing ring, and the sealing ring forms an annular structure or a frame structure along the transition area between the upper heat dissipation area and the second mold body.

[0046] The advantage of this is that the sealing ring provides an optimal seal in the transition area between the upper heat dissipation area and the second mold body.

[0047] In an exemplary implementation of the semiconductor arrangement, the turbulence element is mounted on the upper metal layer without contacting the upper metal sealing element.

[0048] This has the advantage that heat can be transferred directly from the upper metal layer to the outside of the semiconductor arrangement. Independent heat transfer can be achieved through the seal.

[0049] In an exemplary implementation of the semiconductor arrangement, the upper metal sealing element forms a sealing cover, which covers the upper heat dissipation area of ​​the power module.

[0050] The advantage of this is that the sealing cover can simultaneously realize the two functions of sealing and heat transfer.

[0051] In an exemplary implementation of the semiconductor arrangement, the turbulence element is mounted on the upper metallic sealing element.

[0052] The advantage of this is that efficient cooling and sealing can be achieved at the same time.

[0053] In an exemplary implementation of the semiconductor arrangement, the turbulence element comprises a plurality of turbulence flakes, and the plurality of turbulence flakes are symmetrically or asymmetrically arranged on the upper metal layer and / or the lower metal layer.

[0054] The advantage of the turbulence lamellae is that they form a maximum heat dissipation and turbulence surface.

[0055] In an exemplary implementation of the semiconductor arrangement, the semiconductor arrangement includes: a plurality of chips embedded in the power module, wherein each chip is placed at a pre-specified position relative to the upper metal layer and / or the lower metal layer, and the pre-specified position is pre-specified by the package layout; and at least one turbulence sheet of the turbulence element is placed at the pre-specified position of the upper metal layer and / or the lower metal layer.

[0056] This has the advantage that the design of the semiconductor arrangement can optimize heat transfer for each of the plurality of chips.

[0057] Each power module of the semiconductor arrangement may have the same number of chips or a different number of chips. In one example, each power module may have 6 chips or 12 chips. In other examples, the power module may have 2 chips, 3 chips, 4 chips, 5 chips or even only 1 chip. It should be understood that other numbers of chips are also possible, for example, 7, 8, 9, 10, 11, 13, 14, 15, 16, 17, 18, 19, 20 and more.

[0058] In an exemplary implementation of the semiconductor arrangement, the turbulence element is welded on the upper metal layer, and the turbulence element and the upper metal layer form a first welding pattern; or the turbulence element is welded on the upper metal sealing element, and the turbulence element and the upper metal sealing element form a first welding pattern, and the upper metal sealing element and the upper metal layer form a second welding pattern.

[0059] This has the advantage that the first soldering pattern and / or the second soldering pattern can be designed to achieve optimal heat transfer based on the known position of the chip embedded in the power module.

[0060] In an exemplary implementation of the semiconductor arrangement, the first weld pattern and / or the second weld pattern are aligned with an arrangement of the turbulence sheets of the turbulence element.

[0061] This has the advantage that the turbulence sheets can be placed on the power module for optimal heat transfer.

[0062] In an exemplary implementation of the semiconductor arrangement, the first welding pattern and / or the second welding pattern are aligned with the pre-designated positions of the plurality of chips embedded in the power module.

[0063] The benefit of this is that the solder pattern can be designed to achieve optimal heat transfer. It should be noted that heat is generated by the chip; when the solder pattern is aligned with the location of the chip, optimal heat dissipation can be achieved.

[0064] In an exemplary implementation of the semiconductor arrangement, the first soldering pattern and / or the second soldering pattern includes a plurality of soldering points, and a density of the soldering points is based on a temperature of the plurality of chips embedded in the power module.

[0065] The benefit of this is that more heat can be transferred to higher temperature locations on the chip.

[0066] In an exemplary implementation of the semiconductor arrangement, the plurality of solder joints are disposed in a plurality of bonding lines, and a distance between any two of the bonding lines is based on temperatures of corresponding chips of the plurality of chips placed below the two bonding lines.

[0067] The advantage of this is that heat dissipation can be controlled through design by utilizing the distance between the welding lines.

[0068] The temperature of multiple chips embedded in a power module is usually not evenly distributed. Chips with higher temperatures have more solder joints, while chips with lower temperatures have fewer solder joints.

[0069] The soldering pattern may be adjusted based on the individual thermal characteristics of the individual chips.

[0070] Different from the chip with low temperature, the turbulent structure and the welding structure can be arranged more densely or at a higher density in the chip with high temperature.

[0071] In one example, the turbulent structure is uniform and the soldering structure is non-uniform, depending on the temperature of the chip. In another example, the soldering structure is uniform and the turbulent structure is non-uniform, depending on the temperature of the chip.

[0072] In an exemplary implementation of the semiconductor arrangement, the temperature of the plurality of chips embedded in the power module is within a temperature range of 5° C., 10° C., or 15° C. relative to a reference temperature.

[0073] It will be appreciated that other temperature ranges may also be applied, for example, at 1°C, 2°C, 3°C, 4°C, 6°C, 7°C, 8°C, 9°C, 11°C, 12°C, 13°C, 14°C, 16°C, 17°C, 18°C, 19°C, 20°C or values ​​therebetween or above 20°C.

[0074] The advantage of this is that, based on the design of the welding structure, uniform heat transfer can be achieved in the heat distribution area.

[0075] In an exemplary implementation of the semiconductor arrangement, the upper metal layer or the upper metal sealing element forms a metal-to-metal contact with the turbulence sheets of the turbulence element, and the metal-to-metal contact forms the first welding pattern and / or the second welding pattern.

[0076] The metal-to-metal contact may be a cold connection, such as aluminum-to-aluminum, or a metal-to-metal connection.

[0077] The benefit of this is that such metal-to-metal contact allows for efficient heat transfer.

[0078] In an exemplary implementation of the semiconductor arrangement, the turbulence element is clamped or clipped or welded or connected to the upper metal layer and / or the lower metal layer.

[0079] The benefits of this are more flexible design and more efficient heat transfer.

[0080] According to a second aspect, the present application relates to a method for producing a semiconductor arrangement with coolant cooling, the method comprising: providing a power module for power conversion, the power module comprising a first module side and a second module side opposite to the first module side, wherein a first mold body is arranged between the first module side and the second module side; the first module side comprises an upper metal layer; a second mold body at least partially encapsulates the power module, wherein a portion of the upper metal layer forming an upper heat dissipation area of ​​the power module is not covered by the second mold body; in a transition area between the upper heat dissipation area and the second mold body, the upper heat dissipation area and the second mold body are covered by an upper metal sealing element to seal the power module and prevent coolant from flowing through the upper heat dissipation area.

[0081] The method can also be used to provide a semiconductor arrangement with double-sided cooling. Then, as described above, a process step is included, including a lower metal sealing element covering the lower heat dissipation region and the second mold body in a transition area between the lower heat dissipation region and the second mold body to seal the power module and prevent coolant from flowing through the lower heat dissipation region.

[0082] This approach provides a seal that enables optimal sealing reliability for direct liquid-cooled modules, whether single-sided or double-sided.

[0083] In an exemplary implementation of the method, the method includes: welding the upper metal sealing element to the upper heat dissipation area by laser welding or ultrasonic welding process steps.

[0084] This has the advantage that the seal can be easily produced by using known production tools.

[0085] In an exemplary implementation of the method, the method includes attaching the upper metal sealing element to the second mold body by a remelting process step of the second mold body.

[0086] This has the advantage that remelting the second mold body can provide a rough surface structure in the second mold body, which can be effectively clamped into the rough surface structure of the upper metal sealing element to provide a reliable seal.

[0087] In an exemplary implementation of the method, the method includes: mounting the turbulence element on the upper metal layer or the upper metal sealing element by laser welding or ultrasonic welding process steps to generate turbulence in the coolant flowing through the upper heat dissipation area.

[0088] By using such a turbulence element, the power module can be cooled efficiently. The turbulence generated by the turbulence element on the cooling medium enables all semiconductor chips of the power module to have similar junction temperatures and similar cooling conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0089] Other embodiments of the present application will be described in conjunction with the following drawings, in which:

[0090] Figure 1 shows a schematic 3D view of an exemplary semiconductor arrangement 100a with a sealing ring according to a first embodiment;

[0091] Figure 2 shows a schematic 3D view of an exemplary semiconductor arrangement 100b with a sealing cover according to a second embodiment;

[0092] Figure 3 A schematic diagram showing a cross section of an exemplary semiconductor arrangement 100a with a sealing ring according to a first embodiment;

[0093] Figure 4 A schematic diagram showing a cross section of an exemplary semiconductor arrangement 100b with a sealing cover according to a second embodiment;

[0094] Figure 5 exemplarily shows a top view of a semiconductor arrangement 100 a , 100 b with three power modules 110 and mounted turbulence elements;

[0095] Figure 6 Two top views 610 , 620 of a power module 110 are shown, on which irregularly spaced turbulence elements are mounted;

[0096] Figure 7 Two top views of a power module 110 are shown on which a turbulence element having irregularly spaced lamellae is mounted;

[0097] Figure 8 A schematic diagram of a method 800 of producing a semiconductor arrangement according to the present application is shown. DETAILED DESCRIPTION

[0098] In the following detailed description, reference is made to the accompanying drawings which form a part of this specification, wherein specific aspects of the application can be practiced are illustrated by way of illustration. It should be understood that other aspects may be utilized, and structural or logical changes may be made without departing from the scope of the application. Therefore, the following specific embodiments should not be understood in a restrictive sense, and the scope of the application is defined by the appended claims.

[0099] It should be understood that comments related to the described method are also applicable to the corresponding device or system for performing the method, and vice versa. For example, if a specific method step is described, the corresponding device may include a unit for performing the described method step, even if such a unit is not explicitly described or shown in the drawings. In addition, it should be understood that the features of the various exemplary aspects described in this application can be combined with each other unless otherwise explicitly stated.

[0100] The semiconductor arrangements, devices, and systems described in this application can be implemented in automotive, industrial, or consumer electronics applications, for example, for driving loads, converting power, etc. However, the semiconductor arrangements, devices, and systems described in this application can also be implemented in wireless communication schemes (for example, communication schemes based on 5G or Wi-Fi), for example, for the Internet of Things, etc. The described semiconductor arrangements, devices, and systems may include integrated circuits and / or power semiconductors and may be manufactured according to various technologies. For example, semiconductor arrangements, devices, and systems may be used for power and / or logic integrated circuits, analog integrated circuits, mixed signal integrated circuits, etc.

[0101] In this application, single side cooling (SSC) packages and double side cooling (DSC) packages are described. The single side cooling (SSC) package is covered by an insulating mold. Therefore, the heat dissipation path of the package is mainly its bottom (e.g., drain or collector) side cooling plate. The double side cooling (DSC) package has a top (e.g., source or emitter) side cooling plate in addition to the bottom side cooling plate. These cooling plates help to reduce thermal resistance. Since heat is dissipated from both the top and bottom surfaces, the double side cooling package can efficiently utilize the heat sink. The double side cooling package is designed for efficient cooling to achieve the highest energy levels that such a system can switch.

[0102] In the present application, power modules with semiconductor chips are described. For example, these power modules may include MOSFET transistors or IGBTs. For example, the power modules may be produced based on silicon nitride or gallium nitride semiconductor technology or silicon semiconductor technology.

[0103] In the present application, sealing rings and sealing covers are described. A sealing ring is a sealing element that covers two separate areas or materials that are in contact with each other. The sealing ring produces a sealing effect, sealing the two areas or materials from each other. The sealing ring only covers the transition area where the two areas or materials are in contact with each other, while the rest of the two areas or materials are not covered. For example, the sealing ring can be formed as a sealing ring or a sealing frame. Examples of sealing rings are Figure 1 and Figure 3 shown.

[0104] The sealing cover is similar to the sealing ring in that it is also a sealing element covering two separate areas or materials that are in contact with each other. The sealing cover also produces a sealing effect, sealing the two areas or materials from each other. However, unlike the sealing ring, the sealing cover not only covers the transition area where the two areas are in contact with each other, but also covers the entire first area or the entire area of ​​the first material in addition to the transition area, which means that the entire first area or material is covered by the sealing cover. For example, the sealing cover can be formed as a closed rectangle, a closed square, or any other closed geometric shape. Examples of sealing covers are Figure 2 and Figure 4 shown.

[0105] Figure 1 A schematic 3D view of an exemplary semiconductor arrangement 100a with a sealing ring according to a first embodiment is shown. The semiconductor arrangement 100a is configured to be cooled by a coolant (eg water). The cooling may be performed from one side or from both sides.

[0106] like Figure 1 As shown, the semiconductor arrangement 100a includes one or more power modules 110, a second mold body 120, and an upper metal sealing element 130a. Figure 1 In FIG. 1 , three such power modules are exemplarily shown. It should be understood that any other number of power modules may be applied to the semiconductor arrangement 100 a.

[0107] The power module 110 may be used for power conversion. The power module 110 includes a first module side 111a and a second module side 111b opposite to the first module side 111a. Figure 1 Shown in the zoomed image at lower right.

[0108] The first mold body 113 of the power module 110 is disposed between the first module side 111 a and the second module side 111 b .

[0109] The first module side 111a includes an upper metal layer 114a, such as Figure 1 Shown in the zoomed image at lower right.

[0110] Unlike the first mold body 113 which is a mold body of the corresponding power module 110 , the second mold body 120 is a mold body of the entire semiconductor arrangement 100 a .

[0111] The second mold body 120 at least partially encapsulates the power module 110, wherein a portion of the upper metal layer 114a forming the upper heat dissipation region 115a of the power module 110 is not covered by the second mold body 120. Figure 1 shown.

[0112] The upper metal sealing member 130a covers the upper heat dissipation region 115a and the second mold body 120 in a transition region 131a therebetween to seal the power module 110 and prevent the coolant from flowing through the upper heat dissipation region 115a. Figure 1 The zoomed view at the bottom right shows the transition region 131a in more detail.

[0113] The upper metal sealing element 130a may form a welded joint with the upper heat dissipation region 115a.

[0114] The upper metal sealing member 130 a may form a rough surface connection with the second mold body 120 in a transition region 131 a between the upper heat dissipation region 115 a and the second mold body 120 .

[0115] The second mold body 120 may include a remelted mold material in a transition region 131a between the upper heat sink region 115a and the second mold body 120. Such a remelted mold material may have a rough surface or surface structure.

[0116] The semiconductor arrangement 100a can be used for single-sided cooling and / or double-sided cooling. Although the above sections have described the features of the semiconductor arrangement 100a required for single-sided cooling, i.e., features related to upper heat dissipation, the following description relates to additional features required for double-sided cooling, especially additional features related to lower heat dissipation.

[0117] The second module side 111b may include a lower metal layer 114b, such as Figure 1 This is shown in more detail in the zoomed view at the lower right.

[0118] A portion of the lower metal layer 114 b forming the lower heat dissipation region 115 b of the power module 110 is not covered by the second mold body 120 .

[0119] The semiconductor arrangement 100a may further include a lower metal sealing element 130b covering the lower heat dissipation region 115b and the second mold body 120 in a transition region 131b therebetween to seal the power module 110 and prevent coolant from flowing through the lower heat dissipation region 115b. Figure 1The zoomed view at the lower right shows the transition region 131b in more detail.

[0120] like Figure 1 As shown, the semiconductor arrangement 100a may include a turbulence element 140 mounted above the upper metal layer 114a and / or below the lower metal layer 114b for generating turbulence in the coolant flowing through the upper heat dissipation region 115a and / or below the lower heat dissipation region 115b.

[0121] exist Figure 1 In the first embodiment shown, the upper metal sealing element 130a forms a sealing ring. For example, the sealing ring can form an annular structure or a frame structure along the transition area 131a between the upper heat dissipation area 115a and the second mold body 120, such as Figure 1 shown.

[0122] The turbulence element 140 may be mounted on the upper metal layer 114a without contacting the upper metal sealing element 130a, such as Figure 1 shown.

[0123] The turbulence element 140 may include a plurality of turbulence sheets 340a, such as Figure 3 These turbulent flakes 340a may be disposed symmetrically or asymmetrically on the upper metal layer 114a and / or the lower metal layer 114b.

[0124] The advantage of turbulent sheets is that they form a maximum heat dissipation and turbulence surface.

[0125] In this schematic diagram, three power modules 110 are exemplarily shown. However, the semiconductor arrangement 100 may include any number of power modules, for example 1, 2, 4, 5, 6, 7, 8, 9, 10, 11, 12, etc.

[0126] Figure 2 A schematic 3D view of an exemplary semiconductor arrangement 100 b with a sealing cover according to a second embodiment is shown.

[0127] The construction of the semiconductor arrangement 100b is similar to Figure 1 The only difference is that they use different sealing elements, namely Figure 2 The sealing cover in.

[0128] The upper metal sealing element 130 a forms a sealing cover that covers the upper heat dissipation region 115 a of the power module 110 .

[0129] The sealing cover 130a corresponding to the upper metal sealing element 130a covers the upper heat dissipation region 115a and the second mold body 120 in the transition region 131a therebetween to seal the power module 110 and prevent the coolant from flowing through the upper heat dissipation region 115a. Figure 2 The zoomed view at the bottom right shows the transition region 131a in more detail.

[0130] However, the sealing cover 130a covers not only the transition area 131a but also the entire upper heat dissipation area 115a, like a lid covering the area 115a.

[0131] It should be noted that Figure 2 The turbulence element 140 is shown not covered by the sealing cover 130a. The turbulence element 140 may be mounted on the upper metal sealing element 130a.

[0132] The sealing cover 130a may be formed into a closed rectangle with rounded corners, such as Figure 2 shown.

[0133] The same structure can be implemented on the lower heat dissipation area 115b, that is, the sealing cover 130b covering not only the transition area 131b but also the entire lower heat dissipation area 115b. Another turbulence element 140 can be installed on the lower metal sealing element 130b, that is, the lower sealing cover 130b.

[0134] Figure 3 FIG. 1 is a schematic diagram showing a cross section of an exemplary semiconductor arrangement 100 a having a sealing ring according to a first embodiment. The structure of the semiconductor arrangement 100 a is similar to that of the semiconductor arrangement 100 a described above with reference to FIG. Figure 1 Same as described. However, Figure 3 A cross section is shown, in which further details can be seen, in particular regarding the placement of the power module 110 and the embedded chip 310 and the turbulence element 140 .

[0135] The turbulence element 140 may include a plurality of turbulence sheets 340a, such as Figure 3 The turbulent flakes 340a may be disposed symmetrically or asymmetrically on the upper metal layer 114a and / or the lower metal layer 114b.

[0136] Each power module 110 of the semiconductor arrangement 100 a may include a plurality of chips 310 embedded in the power module 110 .

[0137] The spacers 313 may be used to equalize the gap between the top substrates 114a, 114c, 114e forming the upper metal layer 114a and the bottom substrates 114b, 114d, 114f forming the lower metal layer 114b.

[0138] The top substrate 114a, 114c, 114e may include an isolation layer 114c (eg, ceramic) between an inner conductive layer 114e (eg, copper) and an outer layer 114a (eg, copper or alumina or alumina-coated copper).

[0139] In the same manner, the bottom substrate 114b, 114d, 114f may include an isolation layer 114d (eg, ceramic) between an inner conductive layer 114f (eg, copper) and an outer layer 114b (eg, copper or alumina or alumina-coated copper).

[0140] The chip 310 and the spacer 313 may be placed between the bottom substrate 114b, 114d, 114f and the top substrate 114a, 114c, 114e. Specifically, the chip 310 may be placed between the first interconnect layer 311 placed on the inner conductive layer 114f of the bottom substrate and the second interconnect layer 312 placed on the bottom side of the spacer 313. The spacer 313 may be placed between the second interconnect layer 312 and the third interconnect layer 314 placed under the top substrate, especially the inner conductive layer 114e of the top substrate.

[0141] from Figure 3 It can be seen that the lead frame 301 can be attached to the bottom substrate 114b, 114d, 114f or to the top substrate 114a, 114c, 114e ( Figure 3 not shown).

[0142] Each chip 310 may be placed at a pre-specified position relative to the upper metal layer 114 a and / or the lower metal layer 114 b. For example, the pre-specified position may be pre-specified by the package layout.

[0143] One or more turbulence flakes 340a of the turbulence element 140 may be placed at pre-designated locations on the upper metal layer 114a and / or the lower metal layer 114b.

[0144] Each power module 110 of the semiconductor arrangement may have the same number of chips or a different number of chips. In one example, each power module 110 may have 6 chips or 12 chips. In other examples, the power module 110 may have 2 chips, 3 chips, 4 chips, 5 chips or even only 1 chip. It should be understood that other numbers of chips are also possible, for example, 7, 8, 9, 10, 11, 13, 14, 15, 16, 17, 18, 19, 20 and more.

[0145] The turbulence elements 140 may be welded to the upper metal layer 114a and / or the lower metal layer 114b.

[0146] from Figure 3It can be seen that the turbulence element 140 can form a first welding pattern 350a with the upper metal layer 114a and / or another first welding pattern 350b with the lower metal layer 114b. The two welding patterns 350a, 350b can be the same or different.

[0147] The first weld pattern 350a and / or another first weld pattern 350b may be aligned with the arrangement of the turbulence flakes 340a, 340b of the turbulence element 140. For example, the first weld patterns 350a, 350b are located at locations of the upper metal layer 114a and / or the lower metal layer 114b where the flakes contact the respective metal layer 114a, 114b, and the weld points are attached to form a welded connection of the turbulence element 140 to the respective metal layer 114a, 114b.

[0148] The first welding pattern 350a and the other first welding pattern 350b may be aligned with pre-specified positions of the plurality of chips 310 embedded in the power module 110. This means that the positions where the chips are embedded in the semiconductor arrangement require better cooling than the positions between the embedded chips. At these positions where the chips are embedded, the thin sheets may be more densely distributed, thereby generating more welding points.

[0149] The first welding pattern 350 a and the other first welding pattern 350 b may include a plurality of welding points, and the density of the welding points may be based on the temperature of the plurality of chips 310 embedded in the power module 110 .

[0150] For example, multiple solder joints can be arranged in Figure 6 The distance between any two bonding lines 601 may be based on the temperature of the corresponding chips in the plurality of chips 310 .

[0151] For example, the temperature of the plurality of chips 310 embedded in the power module 110 may be within a temperature range of 5° C., 10° C., or 15° C. with respect to a reference temperature.

[0152] It will be appreciated that other temperature ranges may also be applied, for example, at 1°C, 2°C, 3°C, 4°C, 6°C, 7°C, 8°C, 9°C, 11°C, 12°C, 13°C, 14°C, 16°C, 17°C, 18°C, 19°C, 20°C or values ​​therebetween or above 20°C.

[0153] The upper metal layer 114a may form a metal-to-metal contact with the turbulence sheets 340a of the turbulence element 140. The metal-to-metal contact forms a first weld pattern 350a.

[0154] In the same manner, the lower metal layer 114b may form a metal-to-metal contact with the turbulence sheets 340b of the turbulence element 140. The metal-to-metal contact forms another first weld pattern 350b.

[0155] Metal-to-metal contact can be a cold connection, such as aluminum-to-aluminum, or a metal-to-metal connection.

[0156] The turbulence elements 140 may be clamped or clipped or welded or connected to the upper metal layer 114a and / or the lower metal layer 114b.

[0157] Figure 4 A schematic diagram showing a cross section of an exemplary semiconductor arrangement 100 b with a sealing cover according to a second embodiment is shown.

[0158] The structure of the semiconductor arrangement 100b is similar to that of the semiconductor arrangement 100b described above. Figure 3 However, in the second embodiment with a sealing cover, the entire upper metal layer 114a is covered by the upper metal sealing element 130a. Similarly, the entire lower metal layer 114b is covered by the lower metal sealing element 130b.

[0159] In the second embodiment, the turbulence element 140 is welded to the upper metal sealing element 130a. The turbulence element 140 and the upper metal sealing element 130a form a first welding pattern 350a. The upper metal sealing element 130a and the upper metal layer 114a form a second welding pattern 351a.

[0160] For the bottom side, similar features can be seen, namely, the turbulence element 140 is welded to the lower metal sealing element 130b, the turbulence element 140 and the lower metal sealing element 130b form another first welding pattern 350b, and the lower metal sealing element 130b and the lower metal layer 114b form another second welding pattern 351b.

[0161] The first weld pattern 350a and / or the second weld pattern 351a may be aligned with the arrangement of turbulence flakes 340a of the turbulence element 140 .

[0162] For the bottom side, another first weld pattern 350 b and / or another second weld pattern 351 b may be aligned with the arrangement of turbulence flakes 340 b of the turbulence element 140 .

[0163] The first welding pattern 350 a and / or the second welding pattern 351 a may be aligned with pre-designated positions of the plurality of chips 310 embedded in the power module 110 .

[0164] For the bottom side, another first welding pattern 350 b and / or another second welding pattern 351 b may be aligned with pre-designated positions of the plurality of chips 310 embedded in the power module 110 .

[0165] The first welding pattern 350a and / or the second welding pattern 351a may include a plurality of welding points. The density of these welding points may be based on the temperature of the plurality of chips 310 embedded in the power module 110, for example, as described above in conjunction with Figure 3 The same relationship also exists for another first welding pattern 350b and another second welding pattern 351b.

[0166] The upper metal sealing element 130a may form a metal-to-metal contact with the turbulence sheets 340a of the turbulence element 140. The metal-to-metal contact may form a first weld pattern and / or a second weld pattern.

[0167] For the bottom side, the lower metal sealing element 130b may form a metal-to-metal contact with the turbulence sheets 340b of the turbulence element 140. The metal-to-metal contact may form another first weld pattern and / or another second weld pattern (on the bottom side).

[0168] Metal-to-metal contact can be a cold connection, such as aluminum-to-aluminum, or a metal-to-metal connection.

[0169] The turbulence element 140 may be clamped or clipped or welded or connected to the upper metal sealing element 130a and / or the lower metal sealing element 130b.

[0170] Figure 5 A top view of a semiconductor arrangement 100a, 100b with three power modules 110 and mounted turbulence elements is shown by way of example. The turbulence elements may correspond to the above-described combination of Figures 1 to 4 The turbulence element 140 described above. The semiconductor arrangement 100a, 100b may correspond to the above combination Figures 1 to 4 The semiconductor arrangement.

[0171] exist Figure 5 , the positions of the chips 310 in the power module 110 are shown. These positions may have a design-specific distribution. The cooling fins for turbulent liquid flow may be distributed at optimized positions depending on the chip orientation.

[0172] Figure 6 Two top views 610 , 620 of a power module 110 are shown, with irregularly spaced turbulence elements mounted thereon.

[0173] As above combined Figure 3 and Figure 4 As described above, the plurality of solder joints may be disposed in the plurality of bonding lines 601. The distance between any two bonding lines may be based on the temperature of a corresponding chip among the plurality of chips 310 disposed below the two bonding lines 601 (or above the bottom side).

[0174] In the left top view 610, regions 611 and 612 with different welding line densities are shown. For example, unlike the second region 612, the welding lines 601 in the first region 611 may be less, that is, the distribution distance between each other is larger.

[0175] In this configuration, the chip temperature of the chip under the first region 611 may be lower than the chip temperature of the chip under the second region 612 .

[0176] In the top view 620 on the right, a region 621 with a higher density of bonding wires is shown. The chips below this region 621 can have a higher temperature by design.

[0177] The temperature of multiple chips embedded in a power module is usually not evenly distributed. Chips with higher temperatures have more solder joints, while chips with lower temperatures have fewer solder joints.

[0178] The solder pattern can be adjusted based on the individual thermal characteristics of the individual chips.

[0179] Unlike a chip with a low temperature, the turbulent structure and the welding structure can be arranged more densely or at a higher density in a chip with a high temperature.

[0180] In one example, the turbulent structure is uniform while the solder structure is non-uniform, depending on the temperature of the chip. In another example, the solder structure is uniform while the turbulent structure is non-uniform, depending on the temperature of the chip.

[0181] For example, the temperature of the plurality of chips 310 embedded in the power module 110 may be within a temperature range of 5° C., 10° C., or 15° C. with respect to a reference temperature.

[0182] It will be appreciated that other temperature ranges may also be applied, for example, at 1°C, 2°C, 3°C, 4°C, 6°C, 7°C, 8°C, 9°C, 11°C, 12°C, 13°C, 14°C, 16°C, 17°C, 18°C, 19°C, 20°C or values ​​therebetween or above 20°C.

[0183] Figure 7 Two top views of a power module 110 are shown, on which a turbulence element having irregularly spaced fins is mounted.

[0184] For example, in the left top view, a power module 110 is shown, wherein the turbulence element 140 comprises two parts 710 having different regions with flakes 340a, 340b distributed at different densities. In the first region 711, the flake density is lower than in the second region 712 and the third region 713, while in the third region 713, the flake density is the highest.

[0185] Similarly, the top view on the right shows a power module 110 with a turbulence element 140, which includes two parts 710, 720 with different areas of thin sheets 340a, 340b distributed with different densities. In the first area 711, the thin sheet density is lower than the second area 712 and the third area 713, while the thin sheet density is the highest in the third area 713. The two parts 710, 720 can have different numbers of thin sheet rows. For example, part 710 has five rows of thin sheets, while part 720 has four rows of thin sheets.

[0186] Figure 8 A schematic diagram of a method 800 for producing a semiconductor arrangement with coolant cooling according to the present application is shown.

[0187] The method 800 includes: providing 801 a power module 110 for power conversion, the power module 110 including a first module side 111a and a second module side 111b opposite to the first module side 111a, for example, as described above in combination with Figures 1 to 4 As described above, the first mold body 113 is disposed between the first module side 111 a and the second module side 111 b ; the first module side 111 a includes an upper metal layer 114 a .

[0188] The method 800 includes encapsulating 802 the power module 110 at least partially by the second mold body 120 , wherein a portion of the upper metal layer 114 a forming an upper heat dissipation region 115 a of the power module 110 is not covered by the second mold body 120 .

[0189] The method 800 includes: in a transition area 131a between the upper heat dissipation area 115a and the second mold body 120, covering 803 the upper heat dissipation area 115a and the second mold body 120 with an upper metal sealing element 130a to seal the power module 110 and prevent the coolant from flowing through the upper heat dissipation area 115a, for example, as described above in combination with Figures 1 to 4 described.

[0190] The method can also be used to provide a semiconductor arrangement with double-sided cooling. Then, as described above, a process step is performed including a lower metal sealing element 130b covering the lower heat dissipation region 115b and the second mold body 120 in a transition region 131b between the lower heat dissipation region 115b and the second mold body 120 to seal the power module 110 and prevent the coolant from flowing through the lower heat dissipation region 115b.

[0191] The method 800 may include welding the upper metal sealing element 130 a to the upper heat dissipation region 115 a by laser welding or ultrasonic welding process steps.

[0192] The method 800 may include attaching the upper metal sealing element 130 a to the second mold body 120 through a remelting process step of the second mold body 120 .

[0193] The method 800 may include mounting the turbulence element 140 on the upper metal layer 114a or the upper metal sealing element 130a by laser welding or ultrasonic welding process steps to generate turbulence in the coolant flowing through the upper heat dissipation region 115a.

[0194] Although specific features or aspects of the present application may have been disclosed with respect to only one implementation in several implementations, such features or aspects may be advantageously combined with one or more other features or aspects of other implementations as desired and for any given or specific application. In addition, to a certain extent, the terms "comprise", "have", "have" or other variations of these words are used in the detailed description or claims, and such terms and the term "comprise" are similar, all of which represent the meaning of inclusion. Similarly, the terms "exemplary" and "for example" are only represented as examples, rather than the best or optimal. The terms "coupled" and "connected" and derivatives may be used. It should be understood that these terms may be used to indicate that two elements cooperate or interact with each other, regardless of whether they are in direct physical contact or electrical contact, or they are not in direct contact with each other.

[0195] Although specific aspects have been illustrated and described herein, it will be understood by those skilled in the art that various alternative and / or equivalent implementations may be used to replace the specific aspects shown and described without departing from the scope of the present application. This application is intended to cover any modifications or changes to the specific aspects discussed in this application.

[0196] Although elements in the following claims are listed in a specific order with corresponding labels, these elements are not necessarily limited to being implemented in that specific order unless the claim recitation otherwise implies a specific order for implementing some or all of these elements.

[0197] According to the above guidance, many substitutions, modifications and changes are obvious to those skilled in the art. Of course, it is easy for those skilled in the art to recognize that, in addition to the applications described in the present application, there are many other applications of the present application. Although the present application has been described with reference to one or more specific embodiments, it is recognized by those skilled in the art that many changes can be made to the present application without departing from the scope of the present application. Therefore, it should be understood that, as long as it is within the scope of the attached claims and their equivalents, the present application can be practiced in a manner different from the specific description of the present application.

Claims

1. A semiconductor arrangement (100a, 100b), characterized in that include: A power module (110) for power conversion, the power module (110) comprising a first module side (111a) and a second module side (111b) opposite to the first module side (111a), wherein a first mold body (113) is disposed between the first module side (111a) and the second module side (111b); The first module side (111a) includes an upper metal layer (114a); a second mold body (120) at least partially encapsulating the power module (110), wherein a portion of the upper metal layer (114a) forming an upper heat dissipation region (115a) of the power module (110) is not covered by the second mold body (120); An upper metal sealing element (130a) covers the upper heat dissipation region (115a) and the second mold body (120) in a transition region (131a) between the upper heat dissipation region (115a) and the second mold body (120) to seal the power module (110) and prevent coolant from flowing through the upper heat dissipation region (115a).

2. The semiconductor arrangement (100a, 100b) according to claim 1, characterized in that The upper metal sealing element (130a) forms a welding joint with the upper heat dissipation area (115a).

3. The semiconductor arrangement (100a, 100b) according to claim 1 or 2, characterized in that The upper metal sealing element (130a) forms a rough surface connection with the second mold body (120) in the transition area (131a) between the upper heat dissipation area (115a) and the second mold body (120).

4. The semiconductor arrangement (100a, 100b) according to claim 3, characterized in that The second mold body (120) includes a remelted mold material in the transition area (131a) between the upper heat sink area (115a) and the second mold body (120), the remelted mold material having a rough surface.

5. The semiconductor arrangement (100a, 100b) according to any one of the preceding claims, characterized in that The second module side (111b) includes a lower metal layer (114b); A portion of the lower metal layer (114b) forming the lower heat dissipation region (115b) of the power module (110) is not covered by the second mold body (120); The semiconductor arrangement (100a, 100b) further comprises: A lower metal sealing element (130b) covers the lower heat dissipation region (115b) and the second mold body (120) in a transition region (131b) between the lower heat dissipation region (115b) and the second mold body (120) to seal the power module (110) and prevent coolant from flowing through the lower heat dissipation region (115b).

6. The semiconductor arrangement (100a, 100b) according to claim 5, characterized in that include: The turbulence element (140) installed above the upper metal layer (114a) and / or below the lower metal layer (114b) is used to generate turbulence in the coolant flowing through the upper heat dissipation area (115a) and / or below the lower heat dissipation area (115b).

7. The semiconductor arrangement (100a) according to claim 6, characterized in that The upper metal sealing element (130a) forms a sealing ring, and the sealing ring forms an annular structure or a frame structure along the transition area (131a) between the upper heat dissipation area (115a) and the second mold body (120).

8. The semiconductor arrangement (100a) according to claim 7, characterized in that The turbulence element (140) is mounted on the upper metal layer (114a) without contacting the upper metal sealing element (130a).

9. The semiconductor arrangement (100b) according to claim 6, characterized in that The upper metal sealing element (130a) forms a sealing cover, and the sealing cover covers the upper heat dissipation area (115a) of the power module (110).

10. The semiconductor arrangement (100b) according to claim 9, characterized in that The turbulence element (140) is mounted on the upper metal sealing element (130a).

11. The semiconductor arrangement (100a, 100b) according to any one of claims 6 to 10, characterized in that The turbulence element (140) includes a plurality of turbulence sheets (340a) symmetrically or asymmetrically arranged on the upper metal layer (114a) and / or the lower metal layer (114b).

12. The semiconductor arrangement (100a, 100b) according to claim 11, characterized in that include: A plurality of chips embedded in the power module (110), wherein each chip is placed at a pre-specified position relative to the upper metal layer (114a) and / or the lower metal layer (114b), the pre-specified position being pre-specified by a package layout; At least one turbulence sheet (340a) of the turbulence element (140) is placed on the pre-designated position of the upper metal layer (114a) and / or the lower metal layer (114b).

13. The semiconductor arrangement (100a, 100b) according to claim 12, characterized in that The turbulence element (140) is welded to the upper metal layer (114a), and the turbulence element (140) and the upper metal layer (114a) form a first welding pattern (350a); or The turbulence element (140) is welded to the upper metal sealing element (130a), the turbulence element (140) and the upper metal sealing element (130a) form a first welding pattern (350a), and the upper metal sealing element (130a) and the upper metal layer (114a) form a second welding pattern (351a).

14. The semiconductor arrangement (100a, 100b) according to claim 13, characterized in that The first weld pattern (350a) and / or the second weld pattern (351a) are aligned with an arrangement of the turbulence sheets (340a) of the turbulence element (140).

15. The semiconductor arrangement (100a, 100b) according to claim 13 or 14, characterized in that The first welding pattern (350a) and / or the second welding pattern (351a) are aligned with pre-designated positions of the plurality of chips (310) embedded in the power module (110).

16. The semiconductor arrangement (100a, 100b) according to any one of claims 13 to 15, characterized in that The first welding pattern (350a) and / or the second welding pattern (351a) includes a plurality of welding points, and the density of the welding points is based on the temperature of the plurality of chips (310) embedded in the power module (110).

17. The semiconductor arrangement (100a, 100b) according to claim 16, characterized in that The plurality of solder joints are arranged in a plurality of soldering lines (601), and a distance between any two of the soldering lines (601) is based on the temperature of corresponding chips of the plurality of chips (310) placed below the two soldering lines (601).

18. The semiconductor arrangement (100a, 100b) according to any one of claims 12 to 17, characterized in that The temperature of the plurality of chips (310) embedded in the power module (110) is within a temperature range of 5°C, 10°C or 15°C relative to a reference temperature.

19. The semiconductor arrangement (100a, 100b) according to any one of claims 13 to 18, characterized in that The upper metal layer (114a) or the upper metal sealing element (130a) forms metal-to-metal contact with the turbulence sheet (340a) of the turbulence element (140), and the metal-to-metal contact forms the first welding pattern and / or the second welding pattern.

20. The semiconductor arrangement (100a, 100b) according to any one of claims 6 to 19, characterized in that The turbulence element (140) is clamped or stuck or welded or connected to the upper metal layer (114a) and / or the lower metal layer (114b).

21. A method (800) of producing a semiconductor arrangement (100a, 100b), characterized in that The method comprises: A power module (110) for power conversion is provided (801), the power module (110) comprising a first module side (111a) and a second module side (111b) opposite to the first module side (111a), wherein a first mold body (113) is disposed between the first module side (111a) and the second module side (111b); The first module side (111a) includes an upper metal layer (114a); encapsulating (802) the power module (110) at least partially by a second mold body (120), wherein a portion of the upper metal layer (114a) forming an upper heat dissipation region (115a) of the power module (110) is not covered by the second mold body (120); In a transition region (131a) between the upper heat dissipation region (115a) and the second mold body (120), the upper heat dissipation region (115a) and the second mold body (120) are covered (803) by an upper metal sealing element (130a) to seal the power module (110) and prevent coolant from flowing through the upper heat dissipation region (115a).

22. The method (800) according to claim 21, characterized in that include: The upper metal sealing element (130a) is welded to the upper heat dissipation area (115a) by laser welding or ultrasonic welding process steps.

23. The method (800) according to claim 21 or 22, characterized in that: include: The upper metal sealing element (130a) is attached to the second mold body (120) through a remelting process step of the second mold body (120).

24. The method (800) according to any one of claims 21 to 23, characterized in that include: A turbulence element (140) is mounted on the upper metal layer (114a) or the upper metal sealing element (130a) by laser welding or ultrasonic welding process steps to generate turbulence in the coolant flowing through the upper heat dissipation area (115a).

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