Circuit assembly having two circuit carriers and semiconductor components

Abstract

The invention relates to a circuit assembly (1) having two circuit carriers (3, 5) and a semiconductor component (7) arranged between the circuit carriers (3, 5), said semiconductor component having two load terminals (12, 13). The first load termination (12) has a first load termination surface (15) facing the first circuit carrier (3), around which an electrically insulating edge structure (17) is arranged. The second load termination (13) has a second load termination surface (16) facing the second circuit carrier (5), the second load termination surface being larger than the first load termination surface (15). The first circuit carrier (3) has at least one first contact via (34), which electrically connects the first load termination surface (15) to at least one first conductor path (37, 38), which extends within the first circuit carrier (3) or on an upper side of the first circuit carrier (3) facing away from the semiconductor component (7). The second circuit carrier (5) has an upper side facing the semiconductor component (7), which is formed by a first electrically conductive layer (8), which is electrically connected to the second load termination surface (16).

Description

Technical Field

[0001] The invention relates to a circuit arrangement having two circuit carriers and at least one semiconductor component, in particular a power semiconductor. Background Art

[0002] In the field of power electronics, semiconductor components, such as switching elements, are usually present in the form of power modules (also called power modules) or discrete packages. The semiconductor components are usually connected by specific wire bonding techniques and the power module is fixed to the circuit carrier by welding connections, spring connections or press connections. The use of wire bonding limits the maximum permissible current density through the semiconductor components. In addition, parasitic inductances occur, which limit the achievable switching speed of the switching elements.

[0003] WO2020 / 249479A1 discloses an electronic switching circuit, which further includes a first circuit carrier, a second circuit carrier and a power electronic semiconductor component. The semiconductor component has an upper side, which is adjacent to the lower side of the first circuit carrier, and a lower side, which is adjacent to the upper side of the second circuit carrier. The first circuit carrier has a contact through hole (via in English, through hole), which electrically connects the upper side of the first semiconductor component to the conductor path of the first circuit carrier. The second circuit carrier, for example, has a conductive layer forming the upper side of the circuit carrier and an electrically insulating layer arranged on the side of the conductive layer away from the first circuit carrier.

[0004] WO 2014 / 197917 Al discloses a power module having a printed circuit board core, which contains at least one electronic power component embedded in an insulating layer. The core is arranged between two heat sinks, wherein each heat sink has a metal outer layer and a metal inner layer electrically isolated from the heat sink by a heat-conducting electrically insulating intermediate layer.

[0005] DE10 2021 125 094Al discloses a semiconductor package having a carrier and a semiconductor chip. The carrier has an electrical insulator and a contact structure on the side of the electrical insulator. The semiconductor chip has a pad, which is mounted on the contact structure of the carrier, wherein the pad is at a source potential or an emitter potential. The pad is spaced inwardly from the edge of the semiconductor chip by a first distance. The semiconductor chip has an edge region between the edge and the pad. The contact structure of the carrier is spaced inwardly from the edge of the semiconductor chip by a second distance, which is greater than the first distance.

[0006] US2012 / 243192A1 discloses a three-dimensional power electronic package with a metallized substrate arrangement, a first power electronic device and a second power electronic device. The metallized substrate arrangement includes an insulating dielectric substrate with a current lead extending completely through the insulating dielectric substrate, a first conductive layer on a first surface of the insulating dielectric substrate and a second conductive layer on a second surface of the insulating dielectric substrate. The first conductive layer is electrically coupled to the second conductive layer through the current lead. Summary of the invention

[0007] The object of the present invention is to disclose an improved circuit arrangement having two circuit carriers and at least one semiconductor component.

[0008] This object is achieved according to the invention by a circuit arrangement having the features of claim 1 .

[0009] Advantageous embodiments of the invention are the subject matter of the dependent claims.

[0010] The circuit assembly according to the present invention comprises

[0011] - a first circuit carrier of at least two layers,

[0012] - a second circuit carrier, and

[0013] a semiconductor component arranged between the first circuit carrier and the second circuit carrier, the semiconductor component having a first load terminal and a second load terminal, wherein

[0014] the first load terminal has a first load terminal surface facing the first circuit carrier, an electrically insulating edge structure being arranged around the first load terminal surface,

[0015] the second load terminal has a second load terminal surface facing the second circuit carrier, the second load terminal surface being larger than the first load terminal surface,

[0016] the first circuit carrier has a first load terminal contact pad on the underside facing the semiconductor component,

[0017] The first load terminal contact pad is electrically connected to the first load terminal surface,

[0018] the first circuit carrier has at least one first contact via which connects the first load terminal contact pad to at least one conductor path which extends within the first circuit carrier or on an upper side of the first circuit carrier remote from the semiconductor component, and

[0019] The second circuit carrier has an upper side facing the semiconductor component, which upper side is formed by the first electrically conductive layer and is electrically connected to the second load connection surface.

[0020] The terms "upper side" and "lower side" are not to be understood as limiting, but rather are to be positioned according to the representation in the figures. Furthermore, the statement that a circuit component has one semiconductor component does not prevent the circuit component from having a plurality of semiconductor components. Thus, the circuit component has at least one semiconductor component having the disclosed features.

[0021] The semiconductor component has two load terminals, which are arranged on different sides of the semiconductor component. The load terminals are not contacted via wire bonding, but the first load terminal is contacted by a first load terminal contact pad of a first circuit carrier and the second load terminal is contacted by a first conductive layer of a second circuit carrier (so-called flip chip technology). The first load terminal contact pad is also connected by at least one first contact via to at least one first conductor path in an inner layer of the first circuit carrier or in an outer layer of the first circuit carrier remote from the semiconductor component. Thus, limitations on the maximum permissible current density of the current through the semiconductor component and limitations on the switching speed of the semiconductor component due to wire bonding are advantageously eliminated. The semiconductor component can be, for example, a transistor, a thyristor or a diode.

[0022] An important feature of the circuit assembly according to the invention is that, among other things, the first load terminal faces the first circuit carrier and the second load terminal faces the second circuit carrier, wherein the first load terminal is the load terminal whose load terminal surface is surrounded by the edge structure. The edge structure serves to reduce the potential difference between the two load terminals.

[0023] In contrast, in the arrangement known from the prior art WO 2020 / 249479 Al, the first load terminal surface faces the second circuit carrier and is electrically connected to its first conductive layer. Since the potential of the second load terminal is applied at the outer edge of the edge structure, in the arrangement known from the prior art, a sufficient distance is required between the first load terminal and the second circuit carrier, since its extensive first conductive layer is at the potential of the first load terminal. The required distance depends on the insulating material used and the reverse voltage of the semiconductor component. In order to comply with this distance, for example, a sintering paste deposition with a spacer function, a sintering preform or a welding preform is used, and / or the edge structure is electrically isolated from the first conductive layer of the second circuit carrier by a passivation structure and / or a suitable casting material, the casting material must be cast in a laborious casting process adapted to the casting material and coordinated with the casting material. This problem is corrected by the arrangement of the invention, on the one hand by arranging the second load terminal instead of the first load terminal on the second circuit carrier, and on the other hand by connecting the first load terminal to at least one conductor path extending inside the first circuit carrier or on the upper side of the first circuit carrier via at least one first contact via, so that the substrate (base material) of the first circuit carrier provides an additional insulating layer between each of these conductor paths and the edge structure of the semiconductor component. Compared with the known WO2020 / 249479Al arrangement, this simplifies the manufacture of the circuit assembly and allows a more compact form of the circuit assembly, since the distance between the semiconductor component and the circuit carrier can be reduced.

[0024] In one embodiment of the present invention, the first load terminal contact pad is completely arranged in the area of ​​the lower side of the first circuit carrier, which area corresponds to the area of ​​the semiconductor component surrounded by the edge structure. The area of ​​the lower side of the first circuit carrier corresponding to the area of ​​the semiconductor component surrounded by the edge structure is named as the area of ​​the lower side of the first circuit carrier, on which the area of ​​the semiconductor component surrounded by the edge structure is mapped by parallel displacement along a straight line parallel to the normal vector of the lower side of the first circuit carrier. Therefore, the area of ​​the lower side of the first circuit carrier corresponding to the area of ​​the semiconductor component surrounded by the edge structure directly faces the area of ​​the semiconductor component surrounded by the edge structure and has the same area and shape as the area of ​​the semiconductor component surrounded by the edge structure.

[0025] The above-described embodiments of the present invention prevent the region of the edge structure and the region of the first load terminal contact pad from directly facing each other, thereby advantageously separating the region of the edge structure located at the second load terminal potential from the first load terminal contact pad located at the first load terminal potential.

[0026] In a further embodiment of the invention, the at least one first contact via extends parallel to a first straight line which forms a non-zero angle with a normal vector to the first circuit carrier underside.

[0027] In a further embodiment of the invention, the first load terminal contact pad is connected by at least one first contact via to at least one first conductor path extending inside the first circuit carrier, and this conductor path is connected by at least one further contact via, a so-called blind via, to at least one conductor path extending on the upper side of the first circuit carrier.

[0028] The above two embodiments of the present invention achieve a balance of the connection portion and the conductor path on the upper side of the first circuit carrier by means of the first contact vias and / or blind vias extending obliquely. Therefore, the required voltage interval, air gap and creepage distance on the upper side of the first circuit carrier can be advantageously maintained, and the circuit assembly can be further compacted, thereby saving material in particular.

[0029] In a further embodiment of the invention, the semiconductor component has a control terminal having a control terminal surface facing the first circuit carrier, the control terminal surface being arranged in the region of the semiconductor component surrounded by the edge structure. In addition, the first circuit carrier has a control terminal contact pad on the underside of the first circuit carrier, the control terminal contact pad being electrically connected to the control terminal surface. In addition, the first circuit carrier has at least one second contact via, the second contact via connecting the control terminal contact pad to at least one second conductor path, the conductor path extending inside the first circuit carrier or on the upper side of the first circuit carrier.

[0030] In a further embodiment of the invention, the control terminal contact pad is also arranged completely in a region of the first circuit carrier underside which corresponds to the semiconductor component region surrounded by the edge structure.

[0031] The above two embodiments according to the invention relate to a circuit assembly having at least one semiconductor component that can be controlled by a control terminal (Gate in English). Such semiconductor components are, for example, transistors and thyristors. These embodiments according to the invention provide a contact of the control terminal that is similar to the contact of the first load terminal with the above advantages.

[0032] In a further embodiment of the present invention, the control terminal contact pad extends into an area of ​​the lower side of the first circuit carrier, which area corresponds to the first load terminal surface. Similar to the above description, the area of ​​the lower side of the first circuit carrier corresponding to the first load terminal surface is named the area of ​​the lower side of the first circuit carrier, on which the first load terminal surface is mapped by parallel displacement along a straight line parallel to the normal vector of the lower side of the first circuit carrier.

[0033] The above-described embodiment of the invention takes into account the fact that the control terminals of semiconductor components are usually very small. In this case, it is advantageous to design the control terminal contact pad to be large enough so that it is inserted into the area of ​​the lower side of the first circuit carrier, which area corresponds to the first load terminal surface. This also ensures that, in the event of misalignment, there is always sufficient overlap or coverage between the control terminal contact pad and the control terminal surface and the control terminal can therefore be contacted securely. The first load terminal contact pad is designed to be correspondingly smaller in this embodiment of the control terminal contact pad.

[0034] In a further embodiment of the invention, a section of the control terminal contact pad has at least one inaccessible region, which extends into a region of the first circuit carrier underside corresponding to the first load terminal surface.

[0035] In a further embodiment of the invention, the region of the underside of the first circuit carrier between the control terminal contact pad and the first load terminal contact pad has an incontactable region.

[0036] The above two embodiments of the invention advantageously prevent undefined adhesive loss between the control terminal contact pad and the first load terminal contact pad and the risk of short circuits between the control terminal contact pad and the first load terminal contact pad or the first load terminal surface by means of an uncontactable area, which is produced, for example, by coating with an additional material such as a protective lacquer, by locally influencing wettability, for example by laser oxidation, or by removing existing material, for example by step etching.

[0037] In another embodiment of the present invention, each second contact via extends parallel to the first contact via. In particular, all first contact vias and second contact vias can extend parallel to each other. This simplifies the manufacture and arrangement of the first contact vias and the second contact vias, and prevents these contact vias from crossing.

[0038] In a further embodiment of the invention, the second circuit carrier has a bottom side facing the semiconductor component, which bottom side is formed by the second conductive layer, and an electrically insulating insulating layer is arranged between the first conductive layer and the second conductive layer. The insulating layer advantageously achieves electrical insulation of the bottom side of the second circuit carrier from the top side of the second circuit carrier. In particular, this achieves isolation with respect to a heat sink arranged on the bottom side. Such heat sinks are usually used for heat dissipation of circuit components. The second conductive layer can in particular achieve an increased robustness of the second circuit carrier with respect to thermal deformations.

[0039] In a further embodiment of the invention, the first circuit carrier has a second load terminal contact pad on the underside of the first circuit carrier, which contact pad is electrically connected to the first electrically conductive layer of the second circuit carrier.

[0040] In a further embodiment of the invention, the first circuit carrier has at least one third contact via which connects the second load terminal contact pad to at least one third conductor path which extends within the first circuit carrier or on the upper side of the first circuit carrier.

[0041] The two above-described embodiments of the invention make it possible to supply the potential of the second load terminal to the first circuit carrier and to connect the second load terminal to at least one conductor path of the first circuit carrier.

[0042] In a further embodiment of the invention, at least one third contact via extends parallel to a second straight line, which forms a non-zero angle with a normal vector to the first circuit carrier underside, so that in a plane parallel to the first circuit carrier underside, the distance of each third contact via from each first contact via increases as the distance of the plane from the first circuit carrier underside increases. Embodiments of the invention achieve equalization of conductor paths and connections on the first circuit carrier top side by obliquely extending third contact vias, so as to comply with the required voltage spacing, air gaps and creepage distances on the first circuit carrier top side, and to make the circuit assembly more compact. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] The above characteristics, features and advantages of the present invention, as well as methods for achieving the same, will become clearer and easier to understand in conjunction with the following description of the embodiments, which will be described in more detail with the help of the accompanying drawings. The drawings are as follows:

[0044] Figure 1 shows a first schematic cross-sectional view of a first schematic embodiment of a circuit assembly,

[0045] Figure 2 Shows Figure 1 a second schematic cross-sectional view of the circuit assembly shown,

[0046] Figure 3 shows a schematic cross-sectional view of a second exemplary embodiment of a circuit assembly,

[0047] Figure 4 shows a schematic cross-sectional view of a third exemplary embodiment of a circuit assembly,

[0048] Figure 5 shows a schematic cross-sectional view of a fourth exemplary embodiment of a circuit assembly,

[0049] Figure 6 shows a schematic cross-sectional view of a fifth exemplary embodiment of a circuit assembly,

[0050] Figure 7 A schematic cross-sectional view showing a sixth exemplary embodiment of a circuit assembly

[0051] Figure 8 shows a schematic cross-sectional view of a seventh exemplary embodiment of a circuit assembly,

[0052] Fig. 9 shows a schematic cross-sectional view of an eighth exemplary embodiment of a circuit assembly,

[0053] Fig.10 A schematic cross-sectional view of a ninth exemplary embodiment of a circuit assembly is shown.

[0054] Parts that correspond to each other are provided with the same reference symbols in the figures. DETAILED DESCRIPTION

[0055] Figure 1 FIG1 shows a first schematic sectional view of a first exemplary embodiment of a circuit arrangement 1. The circuit arrangement 1 comprises a first circuit carrier 3, a second circuit carrier 5 and a semiconductor component 7 arranged between the first circuit carrier 3 and the second circuit carrier 5.

[0056] In this embodiment, the first circuit carrier 3 is a multilayer printed circuit board. The second circuit carrier 5 has a first conductive layer 8, a second conductive layer 9 and an electrically insulating insulating layer 10 arranged between the two conductive layers 8, 9. The first conductive layer 8 forms the upper side of the second circuit carrier 5 facing the semiconductor component 7. The second conductive layer 9 forms the lower side of the second circuit carrier 5 facing away from the semiconductor component 7. The insulating layer 10 is, for example, a ceramic layer, for example made of aluminum oxide, aluminum nitride or silicon nitride. For example, the second circuit carrier 5 is a DCB substrate (abbreviation DCB: direct copper bonding) or an AMB substrate (abbreviation AMB: active metal brazing).

[0057] In this exemplary embodiment, the semiconductor component 7 is a transistor having a control terminal 11, a first load terminal 12 and a second load terminal 13. For example, the transistor is a bipolar transistor or a bipolar transistor with an insulated gate electrode (English: Insulated-Gate Bipolar Transistor, abbreviated as IGBT), whose first load terminal 12 is the emitter terminal and whose second load terminal 13 is the collector terminal. Alternatively, the transistor is, for example, a field effect transistor, in particular a metal oxide semiconductor field effect transistor (English: Metal-Oxide-Semiconductor Field-Effect Transistor, abbreviated as MOSFET), whose first load terminal 12 is the source terminal and whose second load terminal 13 is the drain terminal. In other exemplary embodiments, the semiconductor component 7 can be, for example, a thyristor or a diode instead of a transistor. In the case where the semiconductor component 7 is a diode, however, the control terminal 11 and the components of the circuit component 1 connected thereto are omitted.

[0058] The control terminal 11 has a control terminal surface 14 facing the first circuit carrier 3. The first load terminal 12 has a first load terminal surface 15 facing the first circuit carrier. The second load terminal 13 has a second load terminal surface 16 facing the second circuit carrier 5 and the second load terminal surface is larger than the first load terminal surface 15. An electrically insulating edge structure 17 is arranged on the control terminal surface 14 and the first load terminal surface 15, which reduces the potential difference between the two load terminals 12, 13.

[0059] The first circuit carrier 3 has a control terminal contact pad 18, a first load terminal contact pad 19 and a second load terminal contact pad 20 on the lower side facing the semiconductor component 7. The control terminal contact pad 18 is electrically connected to the control terminal surface 14. The first load terminal contact pad 19 is electrically connected to the first load terminal surface 15. The second load terminal contact pad 20 and the second load terminal surface 16 are each electrically connected to the first conductive layer 8 of the second circuit carrier 5. The electrical connections between these components are each made by a connecting material 30, such as a solder material or a sintering material, which electrically connects the two components. The connecting material can depend on the connected components, but for simplicity, all these electrical connections are named with the same reference numeral 30 in the figure.

[0060] The first circuit carrier 3 has a plurality of contact through-holes 34, 35, 36, each of which connects the first load terminal contact pad 19, the control terminal contact pad 18 or the second load terminal contact pad 20 to at least one conductor path 37 to 40, which extend inside the first circuit carrier 3, that is, in an inner layer of the first circuit carrier, or on the upper side away from the semiconductor component 7, that is, in an outer layer of the upper side of the first circuit carrier 3. Figure 1 A plurality of first contact vias 34 are shown, which connect the first load terminal contact pad 19 with a conductor path 37 extending in the interior of the first circuit carrier 3 and with a first conductor path 38 extending on the upper side of the first circuit carrier 3. In addition, Figure 1 A second contact via 35 is shown, which connects the control terminal contact pad 18 with a second conductor path 39 extending on the upper side of the first circuit carrier 3, and a plurality of third contact vias 36 are shown, which each connects the second load terminal contact pad 20 with a third conductor path 40 extending on the upper side of the first circuit carrier 3.

[0061] The control terminal contact pad 18 and the first load terminal contact pad 19 are arranged completely within a region 41 of the underside of the first circuit carrier 3 which corresponds to the region of the semiconductor component 7 surrounded by the edge structure 17 .

[0062] The remaining spatial region between the underside of the first circuit carrier 3 and the second circuit carrier 5 is filled with a casting material 42 , for example by a casting resin.

[0063] Figure 2 FIG2 shows the bottom area 41 of the first circuit carrier 3. Figure 1 , which corresponds to the region of the semiconductor component 7 which is surrounded by the edge structure 17 . Figure 2 As shown, the control terminal contact pad 18 is surrounded by the first load terminal contact pad 19 on three sides, the ends of the contact pad side of the first contact through-holes 34 form a two-dimensional array on the first load terminal contact pad 19, and the control terminal contact pad 18 can be connected to more than one second contact through-hole 35. In other exemplary embodiments, the control terminal contact pad 18 can also be surrounded by the load terminal contact pad 19 on four sides, that is, surrounded by the load terminal contact pad 19. In addition, Figure 2 It is shown that the first load terminal contact pad 19 and the control terminal contact pad 18 are arranged completely in the region 41 , and therefore the contact pad-side ends of the first contact via 34 and the second contact via 35 are also located completely in the region 41 .

[0064] Figure 3 FIG3 shows a schematic cross-sectional view of a second exemplary embodiment of the circuit assembly 1. Figure 1 The exemplary embodiment shown differs only in that the region of the underside of the first circuit carrier 3 between the control terminal contact pad 18 and the first load terminal contact pad 19 has an inaccessible region 43 which is formed, for example, by a solder resist. Figure 3 Only one region of the circuit assembly 1 is shown, which surrounds the region of the lower side of the first circuit carrier 3. This exemplary embodiment takes into account the fact that the control terminal contact pad 18 extends into a region of the lower side of the first circuit carrier 3, which region corresponds to the first load terminal surface 15. The control terminal contact pad 18 extends into a region of the lower side of the first circuit carrier 3, which region corresponds to the first load terminal surface 15, advantageously increasing the size of the control terminal contact pad 18 and thereby achieving a safe electrical contact of the control terminal contact pad 18 with the control terminal 11 and the second contact via 35. The non-contactable region 43 prevents undefined loss of adhesive between the control terminal contact pad 18 and the first load terminal contact pad 19 and the risk of a short circuit between the control terminal contact pad 18 and the first load terminal contact pad 19. Instead of applying a solder resist layer (the same applies to the solder resist layer), the wettability of the connecting material 30 between the control terminal contact pad 18 and the first load terminal contact pad 19 in the region of the lower side of the first circuit carrier 3 can be reduced by local additional treatment, for example by laser oxidation or step etching. Figure 3 and Figure 4illustrative embodiment shown).

[0065] Figure 4 (FIG4) shows the Figure 3 A schematic cross-sectional view of a third exemplary embodiment of a similar circuit assembly 1. Figure 3 The illustrated exemplary embodiment differs only in that the non-contactable area 43 also includes an area facing the first load terminal contact pad 19 and the control terminal contact pad 18 of the first load terminal surface, so as to prevent the risk of a short circuit between the control terminal contact pad 18 and the first load terminal surface 15 .

[0066] Figure 5 (FIG5) shows the Figure 3 and Figure 4 A schematic cross-sectional view of a fourth exemplary embodiment of a similar circuit assembly 1. Figure 3 and Figure 4 The illustrated exemplary embodiment differs only in that the non-contactable area 43 is only the area of ​​the control terminal contact pad 18 facing the first load terminal surface 15 in order to prevent the risk of a short circuit between the control terminal contact pad 18 and the first load terminal surface 15 .

[0067] Figure 6 FIG6 shows a schematic cross-sectional view of a fifth exemplary embodiment of the circuit assembly 1. Figure 1 The schematic embodiment shown differs only in that the conductor path 37 extending inside the first circuit carrier 3 and the conductor path 38 extending on the top side of the first circuit carrier 3 are connected via an additional contact via 47 (blind via), which advantageously reduces the current density of the current between the conductor path 37 and the conductor path 38.

[0068] Figure 7 FIG7 shows a schematic cross-sectional view of a sixth exemplary embodiment of the circuit assembly 1. Figure 6 The only difference to the schematic embodiment shown is that the first contact holes 34 each extend only as far as a conductor path 37 extending inside the first circuit carrier 3, and the second contact holes 35 each extend only as far as a further conductor path 45 extending inside the first circuit carrier 3, which is connected to a second conductor path 39 extending on the upper side of the first circuit carrier 3 via a further contact hole 46 (further blind hole).

[0069] Figure 8 FIG8 shows a schematic cross-sectional view of a seventh exemplary embodiment of the circuit assembly 1. Figure 1The illustrated exemplary embodiment differs only in that the third contact via 36 extends parallel to a straight line which forms a non-zero angle with the normal vector to the underside of the first circuit carrier 3 .

[0070] Fig. 9 FIG9 shows a schematic cross-sectional view of an eighth exemplary embodiment of the circuit assembly 1. Figure 1 The illustrated exemplary embodiment differs only in that the first contact via 34 and the second contact via 35 extend parallel to a straight line which forms a non-zero angle with the normal vector to the underside of the first circuit carrier 3 .

[0071] Fig.10 FIG10 shows a schematic cross-sectional view of a ninth exemplary embodiment of the circuit assembly 1. Figure 1 The illustrated exemplary embodiment differs only in that the first contact via 34 and the second contact via 35 extend parallel to a first straight line which forms a non-zero first angle with the normal vector to the underside of the first circuit carrier 3 , and the third contact via 36 extends parallel to a second straight line which forms a non-zero second angle with the normal vector to the underside of the first circuit carrier 3 .

[0072] exist Figures 8 to 10 In the exemplary embodiment shown, the angles formed by the contact vias 34, 35, 36 and the normal vector of the lower side of the first circuit carrier 3 are selected such that the distances of each third contact via 36 from each first contact via 34 and each second contact via 35 in a plane parallel to the lower side of the first circuit carrier 3 increase as the distance of the plane from the lower side of the first circuit carrier 3 increases. As a result, the required voltage spacing, air gaps and creepage distances (e.g., the distances of the conductor paths 38, 39 and 40) on the upper side of the first circuit carrier 3 can be advantageously maintained, and the circuit assembly 1 can be made compact.

[0073] Although the present invention has been illustrated and described in detail by means of preferred exemplary embodiments, the present invention is not limited to the disclosed examples and a person skilled in the art can derive other variants therefrom without departing from the scope of protection of the present invention.

Claims

1. A circuit assembly (1), comprising: - a first circuit carrier (3) of at least two layers, - a second circuit carrier (5), and a semiconductor component (7) arranged between the first circuit carrier (3) and the second circuit carrier (5), the semiconductor component having a first load terminal (12) and a second load terminal (13), wherein the first load terminal (12) has a first load terminal surface (15) facing the first circuit carrier (3), around which an electrically insulating edge structure (17) is arranged, the second load terminal (13) has a second load terminal surface (16) facing the second circuit carrier (5), the second load terminal surface being larger than the first load terminal surface (15), the first circuit carrier (3) has a first load terminal contact pad (19) on the lower side facing the semiconductor component (7), the first load terminal contact pad being electrically connected to the first load terminal surface (15), the first circuit carrier (3) has at least one first contact hole (34) which connects the first load terminal contact pad (19) to at least one first conductor path (37, 38), which first conductor path extends within the first circuit carrier (3) or on an upper side of the first circuit carrier (3) facing away from the semiconductor component (7), the second circuit carrier (5) has an upper side facing the semiconductor component (7) and formed by a first electrically conductive layer (8), the first electrically conductive layer being electrically connected to the second load terminal surface (16), the second circuit carrier (5) has an underside remote from the semiconductor component (7) which is formed by a second electrically conductive layer (9), and an electrically insulating insulation layer (10) is arranged between the first electrically conductive layer (8) and the second electrically conductive layer (9), and The first circuit carrier (3) has a second load terminal contact pad (20) on the underside of the first circuit carrier, the second load terminal contact pad being electrically connected to the first electrically conductive layer (8) of the second circuit carrier (5).

2. The circuit assembly (1) according to claim 1, wherein: The first load terminal contact pad (19) is arranged completely within a region (41) of the underside of the first circuit carrier (3), which region corresponds to the region of the semiconductor component (7) surrounded by the edge structure (17).

3. The circuit assembly (1) according to claim 1 or 2, wherein: At least one first contact via (34) extends parallel to a first straight line which forms a non-zero angle with a normal vector of the underside of the first circuit carrier (3).

4. The circuit arrangement (1) according to any one of the preceding claims, wherein: The first load terminal contact pad (19) is connected to at least one first conductor path (37) extending inside the first circuit carrier (3) via at least one first contact via (34), and the conductor path (37) is connected to at least one conductor path (38) extending on the upper side of the first circuit carrier (3) via at least one further contact via (47).

5. The circuit arrangement (1) according to any one of the preceding claims, wherein: The semiconductor component (7) has a control terminal (11), the control terminal having a control terminal surface (14) facing the first circuit carrier (3), the control terminal surface being arranged within a region of the semiconductor component (7) surrounded by the edge structure (17), and the first circuit carrier (3) having a control terminal contact pad (18) on the lower side of the first circuit carrier, the control terminal contact pad being electrically connected to the control terminal surface (14), and the first circuit carrier (3) having at least one second contact through-hole (35), the second contact through-hole connecting the control terminal contact pad (18) to at least one second conductor path (39, 45), the second conductor path extending inside the first circuit carrier (3) or on the upper side of the first circuit carrier (3).

6. The circuit assembly (1) according to claim 5, wherein: The control terminal contact pad (18) is arranged completely within a region (41) of the bottom side of the first circuit carrier (3) which corresponds to a region of the semiconductor component (7) surrounded by the edge structure (17).

7. The circuit assembly (1) according to claim 5 or 6, wherein: The control terminal contact pad (18) extends into a region of the underside of the first circuit carrier (3) corresponding to the first load terminal surface (15).

8. The circuit assembly (1) according to claim 7, wherein: The section of the control terminal contact pad (18) extending into the area of ​​the underside of the first circuit carrier (3) corresponding to the first load terminal surface (15) has at least one non-contactable area (43).

9. The circuit assembly (1) according to any one of claims 5 to 8, wherein: The area of ​​the lower side of the first circuit carrier (3) between the control terminal contact pad (18) and the first load terminal contact pad (19) has an incontactable area (43).

10. The circuit assembly (1) according to any one of claims 5 to 9, wherein: Each second contact via (35) extends parallel to the first contact via (34).

11. The circuit arrangement (1) according to any one of the preceding claims, wherein: The first circuit carrier (3) has at least one third contact hole (36) which connects the second load terminal contact pad (20) to at least one third conductor path (40) which extends inside the first circuit carrier (3) or on the upper side of the first circuit carrier (3).

12. The circuit assembly (1) according to claim 11, wherein: At least one third contact hole (36) extends parallel to a second straight line, which forms a non-zero angle with a normal vector of the bottom side of the first circuit carrier (3), so that in a plane parallel to the bottom side of the first circuit carrier (3), the distance between the third contact hole (36) and each first contact hole (34) increases as the distance of the plane from the bottom side of the first circuit carrier (3) increases.

Images