Robust half-bridge

Abstract

A semiconductor transistor includes: a drain region; a plurality of source regions; and a plurality of gate regions interleaved with the source regions.

Description

[0001] Related Applications

[0002] This application claims the benefit of U.S. Provisional Application No. 63,343,348, filed on May 18, 2022, under 35 U.S.C. 119(e), the disclosure of which is incorporated herein by reference.

[0003] field

[0004] Embodiments of the present invention are directed to providing a half-bridge circuit with improved punch-through resistance.

[0005] background

[0006] A common element of many circuits, particularly high power conversion circuits, is a half H-bridge or half bridge. A half bridge comprises a first switch and a second switch, typically a MOSFET transistor, connected in series at a junction serving as the output node of the half bridge.

[0007] In operation, a first MOSFET transistor (commonly referred to as a high-side (HS) transistor or switch) is connected to a high-voltage terminal of a power supply, and a second MOSFET transistor (commonly referred to as a low-side (LS) transistor or switch) is connected to a low-voltage terminal of the power supply. A dedicated HS gate driver and LS gate driver are connected to the gate of the HS transistor and the gate of the LS transistor, respectively, and control the transistors to be turned on (closed) and conducting, or to be turned off (disconnected) and non-conducting. The load is connected between the output node of the half-bridge and the low-voltage terminal of the power supply. When the HS gate driver controls the HS transistor to turn on and the LS driver controls the LS transistor to turn off, the voltage "V HS ", it can be said that the half-bridge is turned on, the load is connected to the HS terminal of the power supply, and the power supply provides current and power to the load. When the gate driver controls the HS transistor to turn off and controls the LS transistor to turn on, the voltage "V LS ", it can be said that the half-bridge is off, and the power supply stops providing current and power to the load. In order to prevent a shoot-through rush of current through the half-bridge - the shoot-through rush shorts out and possibly damages the power supply and / or components of the circuit including the power supply, the HS gate driver and the LS gate driver are synchronously controlled so that when one of the transistors is turned on, the other transistor is turned off.

[0008] Since the switching times of the HS transistors and the LS transistors always experience jitter, to help protect the power supply from short circuits, the gate drivers are synchronized to control both transistors to be off for a short period of time, referred to as a dead period or simply dead time, before switching between the on and off states of the half-bridge. However, even when protected by the dead time intermittent, when switching between the dead time and the on state of the half-bridge, a voltage surge at the LS transistor of the half-bridge may generate a voltage at the gate of the LS transistor, which turns on the LS transistor when the HS transistor is turned on, and produces a breakdown of the half-bridge.

[0009] Overview

[0010] Aspects of embodiments of the present disclosure relate to providing a half-bridge with improved immunity to shoot-through. In order to provide enhanced immunity to shoot-through, according to embodiments of the present disclosure, the LS transistor is formed to have multiple source regions interlaced with gate regions, and the gate regions are operable to control the current flowing to the same drain region. When the source regions are electrically connected in parallel to form a composite source, and the gate regions are electrically connected in parallel to form a composite gate, the interlaced source regions and gate regions give the LS transistor a relatively large built-in gate-source capacitance, which is connected by a relatively low impedance current channel between the composite gate and the composite source. When the half-bridge switches from dead time to on, the large built-in capacitance operates to mitigate the voltage swing between the gate and the source and reduce the probability of breakdown.

[0011] This Summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to be used to limit the scope of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Non-limiting examples of embodiments of the present invention are described below with reference to the attached drawings listed after this paragraph. The same structures, elements, or components that appear in more than one drawing are generally labeled with the same numbers in all drawings in which they appear. Labels in the drawings of embodiments of the present disclosure that are labeled with icons representing a given feature may be used to reference the given feature. The sizes of the components and features shown in the drawings are selected for convenience and clarity of presentation and are not necessarily shown to scale.

[0014] Figure 1 Schematically shows a half bridge according to the prior art;

[0015] Figure 2 A to Figure 2 D schematically shows a method according to the prior art Figure 1The operation of the half-bridge shown in when cycling between on and off states interleaved with dead time;

[0016] Figure 3A Schematically shows the prior art Figure 2 A zoomed-in image of the half-bridge after switching from the dead-time state to the on-state;

[0017] Figure 3B The following schematically shows the prior art Figure 3A The half bridge shown in , the half bridge includes a shunt capacitor to reduce the probability of breakdown;

[0018] Figure 4 Schematically shows an embodiment according to the present disclosure Figure 3A The half-bridge shown in , which includes a low-side transistor with a relatively large built-in capacitance to reduce the probability of breakdown;

[0019] FIG. 5A to FIG. 5B Schematically illustrates changes made to the construction of an LS transistor according to an embodiment of the present disclosure, which LS transistor is optionally used in a half-bridge to reduce the probability of breakdown;

[0020] FIG. 6A to FIG. 6B schematically illustrates a transistor having a source region and a gate region completely surrounding a drain region of the transistor according to an embodiment of the present disclosure; and

[0021] 7A to 7D A transistor switching die including a plurality of transistors according to an embodiment of the present disclosure is schematically shown.

[0022] Detailed Description

[0023] When discussing, unless otherwise specified, adjectives such as "substantially" and "approximately" that modify the condition or relationship characteristics of one or more features of the embodiments of the present disclosure should be understood to mean that the condition or feature is defined within an acceptable tolerance for the operation of the embodiment in its intended application. Wherever the general terms in the present disclosure are described by reference to an example or a list of example examples, the one or more examples mentioned are non-limiting example examples of the general terms, and the general terms are not intended to be limited to the one or more specific example examples mentioned. The phrase "in an embodiment", whether or not associated with a loose form such as "may", "optionally" or "by way of example", is used to introduce configurations of possible embodiments of the present disclosure that are considered as examples but not necessarily required. Each of the verbs "comprise", "include" and "have" and their variations is used to indicate that one or more objects of the verb are not necessarily a complete list of parts, elements or parts of one or more subjects of the verb. Unless otherwise specified, the word "or" in the specification and claims is considered to be an inclusive "or", not an exclusive "or", and represents any combination of at least one or more of the items it combines.

[0024] Figure 1 Schematically shows a half-bridge 10 common to many conversion circuits according to the prior art. The half-bridge 10 includes a high-side switch QHS-12 and a low-side switch QLS-13 connected in series at a junction 15 used as an output node of the half-bridge 10, which is usually a MOSFET transistor. Each transistor has a source S, a drain D and a gate G. The high-side gate driver HS_DRIVER 16 is connected between the gate G and the source S of the transistor QHS-12, and controls the voltage difference between the source and the gate to control QHS-12 to turn on (close) and conduct or turn off (disconnect) and not conduct. Similarly, the low-side gate driver LS_DRIVER 17 is connected between the source S and the gate G of the low-side transistor QLS-13, and controls the low-side transistor to turn on or off. In the accompanying drawings, the half-bridge 10 is shown as being connected to a load L and to a high-voltage terminal 20 connected to a high-voltage power supply VS, and the high-voltage power supply VS provides a voltage HV+ at the high-voltage terminal 20, and provides a voltage HV- at the low-voltage terminal 25. As an example, it is assumed that transistors QHS-12 and QLS-13 are n-channel transistors, and the drain D of transistor QHS-12 is connected to a high voltage terminal 20 providing a voltage HV+, and the source S of transistor QLS-13 is connected to a low voltage terminal 25 providing a voltage HV-. A load L is connected between the output node 15 of the half bridge 10 and the low voltage terminal 25 of the power supply VS.

[0025] Figure 1The half bridge 10 is shown turned on, with the high side gate driver HS-16 controlling the transistor QHS-12 to turn on (switch closed), and the low side driver LS-17 controlling the transistor QLS-13 to turn off (switch open). With the half bridge 10 turned on, the output node 15 is set to the voltage HV+ provided by the terminal 20, and the power supply VS drives a current represented by the dashed line 45 with an arrow through the load L.

[0026] Figure 2 A to Figure 2 D schematically shows HS-Driver 16 and LS-Driver 17, which control transistors QHS-12 and QLS-13 to switch half-bridge 10 on and off by a regular sequence of on-states and off-states of the half-bridge interspersed with dead-time periods, thereby alternately connecting and disconnecting load L to voltage HV+ and providing power to load L with current pulses. Figure 2 The timeline 47 at the bottom of A shows that the half bridge 10 is turned on and drives the current 45 through the load L, as Figure 1 As depicted in . Figure 2 B shows the Figure 2 The half bridge 10 shown in A is then in a dead time period, where both QHS-12 and QLS-12 are off. When switching to the dead time, a transient decay current represented by a dashed line 50 supported by parasitic inductance and capacitance flows through the load L for a limited period of time. Figure 2 C schematically shows a half-bridge being turned off, where gate drivers 16 and 17 respectively control transistor QHS-12 to turn off and control transistor QLS-13 to turn on, followed by Figure 2 The dead time is shown as D. In the off state, the half-bridge node 15 drops to the low voltage HV- at the terminal 25 of the power supply VS, there is no voltage drop across the load L, and the power supply VS stops providing current and power to the load.

[0027] Figure 3A The details of the half bridge 10 related to the operation of the half bridge are schematically shown, and the half bridge is illustrated when the dead time ( Figure 2 D) Switch to On ( Figure 2 A) may result in a half-bridge behavior with destructive current breakdown and ringing of the voltage applied to the load L.

[0028] The transistor QHS-12 is characterized by parasitic capacitances CdgHS, CgsHS, and CdsHS, and is included in a QHS-package-51 having internal impedances ZgIN / H and ZkIN / H, through which the gate G and source S of the transistor can be electrically connected from outside the die, respectively. The HS-driver 16 is connected to the gate G and source S of the transistor QHS-12 via impedances ZgEx / H and ZkEx / H, respectively, outside the QHS-package-51. ZgEx / H and ZkEx / H are typically features of conductive traces connecting the HS-driver and the transistor QHS-12 on a printed circuit board (PCB) on which the HS-driver and the transistor QHS-12 are mounted. Similarly, transistor QLS-13 is characterized by parasitic capacitances CdgLS, CgsLS, and CdsLS, and is included in a QLS-package-52 having internal impedances ZgIN / L and ZkIN / L, through which the gate G and source S of transistor QLS-13 can be electrically connected, respectively. LS-driver 17 is connected to transistor QLS-13 via ZgEx / L and ZkEx / L outside QLS-package-51.

[0029] When transistor QHS-12 is turned on to provide a dead time ( Figure 2 D) and the on-state of the half-bridge ( Figure 2 When switching between the power supply VS and the power supply A), a transient current represented by a thick arrow 70 flows from the power supply VS through the transistor QHS-12 to QLS-13. The transient current 70 is split into transient currents represented by dashed lines 71 and 72, which charge the parasitic capacitances CdgLS, CgsLS and CdsLS of the transistor QLS-13 and continue to flow to the low voltage terminal 25 of the power supply VS. A portion 73 of the current 71 flows through the impedances ZgIN / L, ZgEx / L, ZkEx / L and ZkIN / L to reach the power supply VS. The transient current 70 and its transient tributary currents 71, 72 and 73 raise the parasitic capacitor CgsLS to a voltage that produces a voltage at the gate G of QLS-13, which provides a voltage difference between the gate G and the source S of the transistor QLS-12, which operates to turn on the transistor and cause a potentially destructive breakdown current.

[0030] Prior art attempts to prevent breakdown and / or moderate ringing at output node 15 typically include providing transistor QLS-13 with capacitor 75 in parallel with parasitic capacitance CgsLS, such as Figure 3BAs schematically shown in FIG. Due to structural constraints, capacitor 75 is mounted outside QLS-package-52 and operates as a low impedance, thereby shunting the external impedances ZgEX / L and ZkEx / L. When switching between dead time and on, transient currents 70', 71', 72' and 73' are generated, but as shown Figure 3B As schematically shown in FIG. 7 , substantially no current flows through ZgEX / L and ZkEx / L. Capacitor 75 reduces the total impedance between the gate G and source S of QLS-13 to approximately the impedance generated by the impedance inside the QLS-package 52 in parallel with capacitor 75. The reduced impedance advantageously limits the voltage generated between the gate G and source S of transistor QLS-13 when half-bridge 10 switches from the dead time to the on state.

[0031] Figure 4 A half-bridge 80 configured to exhibit relatively robust punch-through capability according to an embodiment of the present disclosure is schematically shown. The half-bridge 80 includes a transistor QLS-85 having a "built-in" capacitor 90 that shunts not only the external impedances ZgEX / L and ZkEx / L of the QLS package 52, but also the internal impedances ZgIN / L and ZkIN / L. When switching between dead time and on, transient currents 70*, 71*, 72* and 73* are generated, but as shown in FIG. Figure 4 As schematically shown in FIG. 1 , substantially no transient current flows through the impedance series ZgIN / L, ZgEx / L, ZkEx / L, and ZkIN / L. The internal capacitor 90 increases the ratio CgsLS / CgdLS and reduces the impedance between the gate G and source S of the transistor QLS-85 to substantially the impedance of the capacitor 90 in parallel with the parasitic impedance CgsLS. The increased ratio CgsLS / CgdLS and reduced impedance advantageously limits the voltage generated between the gate G and source S of the transistor QLS-85 when the half-bridge 10 switches from the dead time to the on state to a voltage greater than that generated by Figure 3B The prior art configuration shown in provides a significantly smaller voltage. The integrated internal capacitor CgsLS also enables faster switching, resulting in higher overall efficiency.

[0032] Figure 5A and Figure 5B Schematically illustrates the difference between a prior art transistor (such as QLS-13) included in the half-bridge 10 and a transistor QLS-85 according to an embodiment of the present disclosure, which may be included in Figure 4 in the half bridge 80 to mitigate or prevent the breakdown current in the half bridge.

[0033] Figure 5AThe conventional transistor QLS-13 shown in FIG. 1 has a source region and a drain region, and a gate region, the source region and the drain region are covered by a source electrode and a gate electrode marked as S and D, respectively, and the gate region is covered by a gate electrode G for controlling the resistance between the source region and the drain region and the current I indicated by the thick arrow. For ease of presentation, Figure 5A and Figure 5B , the source region, drain region, and gate region are not explicitly shown or distinguished from their corresponding electrodes, but are referenced by the same labels S, D, and G that mark the electrodes. Parasitic capacitances Cgs and Cdg couple the source region S to the gate region G and the gate region G to the drain region D, respectively. Parasitic capacitance Cds couples the drain region D to the source region S.

[0034] On the other hand, Figure 5B As shown, according to an embodiment of the present disclosure, the transistor QLS-85 is configured to have a plurality of (optionally three) source regions S interlaced with three gate regions G, the three gate regions G being operable to control resistance, thereby controlling the current between the source regions S and the same drain region D. Each source region S is coupled to an adjacent gate region G through an internal parasitic capacitance Cgs*. The three source regions are electrically connected in parallel to form a composite source S. C , and the three gate regions are electrically connected in parallel to form a composite gate G C .for Figure 5B In the configuration shown in Figure 1, the composite source S C and composite gate G C There are five internal parasitic capacitors Cgs* connected in parallel. Assuming that all parasitic capacitors have substantially the same size, the dashed capacitor C GS Schematic representation of the total internal built-in parasitic capacitance bridging the composite source S C and composite gate G C , and provides a relatively large built-in parasitic capacitance for transistor QLS-85 that is approximately equal to 5×Cgs*. This large internal parasitic capacitance shunts the internal impedance of the transistor and operates to provide enhanced anti-breakdown protection for half-bridge 80.

[0035] Note that usually for Figure 5B The N gate-source pairs in the QLS-85 are schematically shown in FIG. 1 , and the built-in parasitic capacitance C GS It can be approximated to be approximately equal to (2N-1)Cgs*. C can be adjusted by selecting an appropriate number N of gate-source pairs, as required by a given circuit and the environmental stray capacitance and / or inductance to which the circuit may be exposed. GS Size. GSThe size of the built-in capacitance can also be adjusted by forming gate-source pairs with different sizes and / or different distances between the gate and source regions of different gate-source pairs, or the distances between different gate-source pairs. For example, assuming that the first gate-source pair has Figure 5B The y-axis of the coordinate system shown in FIG is substantially parallel to the lateral extent Lgs, and the other N′ gate-source pairs optionally have the same y-axis lateral extent αLgs, where 0≤α≤1, then C GS The expression C GS ~Cgs*+2N'αCgs* is approximated. In the last expression, it is also assumed that the distances along the x-axis between all gate regions and their corresponding adjacent source regions are the same for all gate regions.

[0036] Fig. 6A and Figure 6B Schematically shown are top views of transistors 100 and 120, respectively, according to embodiments of the present disclosure, which have relatively large built-in parasitic capacitances and can be advantageously used as low-side switching transistors in a half-bridge. Transistors 100 and 120 are characterized by having a source-gate pair having a substantially rounded rectangular shape, which optionally completely surrounds the drain of the transistor. Fig. 6A The transistor 100 shown in FIG. 1 includes a single drain 106 surrounded by a source-gate pair including a surround source 102 and a surround gate 104 nested inside the surround source 102. Ignoring the rounded ends of the surround 102 and the surround gate 104, and assuming that one side of the surround source-gate pair has a "one-side" stray capacitance approximately equal to Cgs*, the total built-in parasitic capacitance C of the transistor 100 is GS can be estimated to be approximately equal to 2Cgs*.

[0037] Similarly, Figure 6B The transistor 120 shown in FIG. 1 includes 2 surrounding source-gate pairs and can be estimated to have a total parasitic capacitance C approximately equal to (2×3)Cgs*. GS In general, a transistor having N surrounding source-gate pairs surrounding a single drain according to an embodiment of the present disclosure may be estimated to have a built-in stray capacitance C GS = 2(2N-1)Cgs*. The wraparound feature around the source-gate pair generally operates to approximately double the built-in stray capacitance of a source-gate pair that is similar in structure and geometry to a single side of the wraparound source-gate pair.

[0038] 7A to 7D 1 shows a circuit including a plurality of transistors 100 ( Fig. 6A ) or 120( Figure 6B ) is a schematic diagram of a composite switching device (also called a switch die).

[0039] Fig. 7A A schematic diagram of a switch die 200 is shown that includes an array 202 having a plurality of transistors 100. In addition to the array 202, the switch die 200 also includes an array 204 of built-in capacitors 206 along the underside of the array 202, each capacitor 206 having a center electrode 208 surrounded by a surrounding electrode 207. A conductive trace 221 connects the surrounding electrodes 207 of all capacitors 206 and the sources 102 of all transistors 100 in parallel. A conductive trace 222 connects the center electrodes 208 of all capacitors 206 and the gates 104 of all transistors 100 in parallel. A conductive trace 223 connects the drains 106 of all transistors 100 in parallel.

[0040] Figure 7B A schematic diagram of a switch die 250 including a plurality of transistors 100 interleaved with an array 252 of built-in capacitors 206 is shown. Conductive trace 271 connects the surrounding electrodes 207 of all capacitors 206 and the sources 102 of all transistors 100 in parallel. Conductive trace 272 connects the center electrodes 208 of all capacitors 206 and the gates 104 of all transistors 100 in parallel. Conductive trace 273 connects the drains 106 of all transistors 100 in parallel.

[0041] Figure 7C A schematic diagram of a switch die 300 including an array 302 having a plurality of transistors 100 is shown. In addition to the array 302, the switch die 200 also includes an array 304 of built-in capacitors 306 along the underside of the array 302, each capacitor 306 having a center electrode 308 surrounded by a surrounding electrode 307 and extending the entire length along the underside. A conductive trace 321 connects the surrounding electrodes 307 of all capacitors 306 and the sources 102 of all transistors 100 in parallel. A conductive trace 322 connects the center electrodes 308 of all capacitors 306 and the gates 104 of all transistors 100 in parallel. A conductive trace 323 connects the drains 306 of all transistors 100 in parallel.

[0042] Fig.7D 1 shows a circuit including a plurality of transistors 120 ( Figure 6B ) is a schematic diagram of a switch die 350 of FIG. 1 . Conductive trace 371 connects the sources 102 of all transistors 120 in parallel. Conductive trace 374 connects the gates 104 of all transistors 120 in parallel. Conductive trace 375 connects the drains 106 of all transistors 120 in parallel.

[0043] The description of the embodiments of the present invention in this application is provided by way of example and is not intended to limit the scope of the present invention. The described embodiments include different features, not all of which are required in all embodiments of the present invention. Some embodiments utilize only some features or possible combinations of features. Those skilled in the art will appreciate variations of the described embodiments of the present invention and embodiments of the present invention that include different combinations of the features mentioned in the described embodiments. The scope of the present invention is limited only by the claims.

Claims

1. A semiconductor transistor, comprising: drain region; multiple source regions; and A plurality of gate regions are interlaced with the source regions.

2. The semiconductor transistor according to claim 1, wherein All source regions are electrically connected together.

3. The semiconductor transistor according to claim 2, wherein: All gate regions are electrically connected together.

4. A semiconductor transistor according to any one of the preceding claims, wherein: The number of the plurality of gate regions is equal to the number of the plurality of source regions to form a plurality of gate-source pairs, each gate-source pair including a gate region and an adjacent source region on a far side of the gate region relative to the drain region.

5. The semiconductor transistor according to claim 4, wherein: The total built-in internal gate-source capacitance C of the transistor GS is an increasing function of the number of gate-source pairs.

6. The semiconductor transistor according to claim 5, wherein: At least two gate-source pairs have different lateral extents.

7. The semiconductor transistor according to claim 5 or claim 6, wherein: For at least two gate-source pairs of the plurality of gate-source pairs, a distance between the source region and the gate region is different.

8. The semiconductor transistor according to claim 5 or claim 6, wherein: A distance between the gate region and the source region is the same for all gate-source pairs in the plurality of gate-source pairs.

9. The semiconductor transistor according to claim 8, wherein: The gate-source pairs are equally spaced apart.

10. The semiconductor transistor according to claim 9, wherein: If N is equal to the number of gate-source pairs, and the capacitance between the gate and source regions is represented by Cgs*, then C GS Approximately equal to (2N-1)Cgs*.

11. The semiconductor transistor according to any one of claims 1 to 9, wherein: A source region among the plurality of source regions is a surrounding source region that completely surrounds the drain region.

12. The semiconductor transistor according to claim 11, wherein A gate region among the plurality of gate regions is a surrounding gate region that completely surrounds the drain region.

13. A semiconductor transistor comprising: drain region; A surrounding source region, wherein the surrounding source region completely surrounds the drain region; and A wraparound source gate region completely surrounds the drain region and is nested within the source region.

14. A semiconductor switch die comprising a plurality of transistors according to any one of the preceding claims.

15. The semiconductor switch die of claim 14, wherein: The sources of the plurality of transistors are electrically connected in parallel.

16. The semiconductor switch die according to claim 14 or claim 15, wherein: The gates of the plurality of transistors are electrically connected in parallel.

17. The semiconductor switch die according to any one of claims 14 to 16, wherein: The drains of the plurality of transistors are electrically connected in parallel.

18. A half-bridge with a low-side switch comprising a semiconductor transistor according to any one of the preceding claims.

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