Power semiconductor device and method for producing power semiconductor device

Abstract

A power semiconductor device and a method for manufacturing a power semiconductor device are provided. A power semiconductor device (100) comprises: a semiconductor body (1) having a top side (10); a main electrode (2) on the top side; and a gate electrode (3) on the top side and arranged alongside the main electrode in a first lateral direction (L1). The semiconductor body comprises a drift layer (11) of the first conductivity type, a base region (12) of the second conductivity type vertically arranged between the drift layer and the top side, a contact region (13) of the first conductivity type vertically arranged between the drift layer and the top side. The contact region adjoins the base region and the top side. Furthermore, the semiconductor body comprises a drift region (14) of the first conductivity type, which drift region is arranged alongside and adjoining the base region in the first lateral direction. The main electrode is in electrical contact with the contact region. In a plan view of the top side, the gate electrode at least partially covers a channel portion (12a) of the base region, the channel portion being located between the contact region and the drift region in the first lateral direction. At the top side, at least one of the contact region and the drift region protrudes beyond the base region in the vertical direction.

Description

Technical Field

[0001] The present disclosure relates to a power semiconductor device and a method for manufacturing a power semiconductor device. Summary of the invention

[0002] There is a need for an improved power semiconductor device, for example with good contact resistance and / or reduced parasitic capacitance. Furthermore, there is a need for an improved method for manufacturing such a power semiconductor device.

[0003] Embodiments of the present disclosure relate to an improved power semiconductor device. Other embodiments relate to an improved method for manufacturing a power semiconductor device.

[0004] First, a power semiconductor device is described in detail. The power semiconductor device is, for example, configured to handle a current of at least 1 A and / or a voltage of at least 100 V. The power semiconductor device is, for example, a so-called vertical power semiconductor device.

[0005] According to an embodiment, a power semiconductor device includes: a semiconductor body having a top side; a main electrode located on the top side; and a gate electrode located on the top side and arranged next to the main electrode in a first lateral direction. The semiconductor body includes a drift layer of a first conductivity type, a base region of a second conductivity type vertically arranged between the drift layer and the top side, and a contact region of a first conductivity type vertically arranged between the drift layer and the top side. The contact region adjoins the base region and the top side. In addition, the semiconductor body includes a drift region of a first conductivity type, which is arranged next to the base region and adjoins the base region in a first lateral direction. The main electrode is in electrical contact with the contact region. In a plan view of the top side, the gate electrode at least partially covers a channel portion of the base region, which is located between the contact region and the drift region in a first lateral direction. At the top side, at least one of the contact region and the drift region protrudes beyond the base region in a vertical direction.

[0006] Most of the current commercially available power semiconductor devices are based on cell designs with a planar channel aligned to the top side of the semiconductor body. However, the increase in current density in such devices is hampered by the parasitic junction FET (parasitic JFET) below the gate electrode and by the increasing contact resistance as the scale is reduced. Additionally, the parasitic gate / drain capacitance Cgd, which is strongly associated with the parasitic JFET, increases significantly with decreasing pitch dimensions. Although the trench design originally promised to reduce or even eliminate the parasitic JFET, current trench power semiconductor devices do still rely on it.

[0007] The device concept proposed herein is based inter alia on the idea of ​​using raised source and / or drift regions. This allows a significant reduction in contact resistance and the elimination of parasitic gate / drain capacitance Cgd. This in turn leads to unparalleled switching performance and enables a significant reduction in chip size.

[0008] The semiconductor body is, for example, based on Si, SiC or GaN. The main electrode on the top side is, for example, a metal electrode. The gate electrode can be made of metal or highly doped polysilicon. The gate electrode is electrically isolated from the semiconductor body, for example, by an electrically isolating material (e.g., SiO2). Therefore, the power semiconductor device can be an insulated gate device. In particular, the gate electrode and the main electrode are electrically isolated from each other so that they can be set to different potentials for operation.

[0009] The gate electrode is arranged beside or adjacent to the main electrode along a first lateral direction. The lateral direction in this context is, for example, a direction parallel to the main extension plane of the semiconductor body. Thus, the vertical direction is defined as a direction perpendicular to the main extension plane of the semiconductor body.

[0010] The drift layer has a first conductivity type. The first conductivity type may be electron conductivity or hole conductivity. The second conductivity type is different from the first conductivity type, that is, hole conductivity or electron conductivity. The region or layer with electron conductivity is n-doped, and the region or layer with hole conductivity is p-doped. For example, the doping concentration in the first drift layer is at least 10 8 cm -3 And at most 10 15 cm -3 .

[0011] The base region is arranged vertically between the drift layer and the top side, i.e., arranged between the top side and the drift layer in a vertical direction. For example, the base region adjoins the drift layer and / or the top side. For example, the doping concentration in the base region is greater than the doping concentration in the drift layer, for example, at least 10 times or at least 100 times greater. For example, the doping concentration in the base region is at least 10 15 cm -3 and / or up to 10 18 cm -3 .

[0012] Herein, when comparing the doping concentrations of the layers or regions, what is compared is the average doping concentration or the maximum doping concentration of these layers or regions. When defining the upper and lower limits of the doping concentration in a layer or region, it means that the maximum doping concentration in the corresponding layer / region does not exceed the upper limit and the minimum doping concentration in the corresponding layer / region is not lower than the lower limit. The regions mentioned herein are, for example, each continuous region, in particular without holes or interruptions.

[0013] The contact region has the same conductivity type as the drift region. For example, the doping concentration of the contact region is greater than the doping concentration of the drift layer and / or the base region, for example, at least 10 times or at least 100 times greater. For example, the doping concentration in the contact region is at least 10 17 cm -3 or at least 10 18 cm -3 or at least 10 19 cm -3 .

[0014] The contact region adjoins the base region and the top side, i.e. forms part of the top side. The contact region may adjoin the base region in a vertical direction and / or in a lateral direction, in particular in a first lateral direction. For example, the contact region is partially or completely laterally surrounded by the base region. The contact region may be embedded in the base region.

[0015] The drift region has the same conductivity type as the contact region and the drift layer. For example, the doping concentration in the drift region is less than the doping concentration in the contact region, for example, at least 10 times or at least 100 times less. However, the doping concentration in the drift region may be greater than the doping concentration in the drift layer, for example, at least 10 times or at least 100 times greater. For example, the doping concentration in the drift region is at least 10 15 cm -3 and / or up to 10 18 cm -3 The drift region is also called the JFET region.

[0016] The drift region is arranged beside the base region along a first lateral direction and adjoins the base region along the first lateral direction. The drift region is spaced apart from the contact region along the first lateral direction by a portion of the base region, which portion is referred to herein as a “channel portion”. The drift region and / or the channel portion may adjoin a top side of the semiconductor body, i.e. form a portion of the top side.

[0017] The main electrode is in electrical contact with the contact region, ie in direct electrical contact. The main electrode may adjoin the contact region at the top side. Electrical contact herein means, for example, ohmic electrical contact.

[0018] The gate electrode is arranged laterally beside the main electrode and aligned with the channel portion of the base region along a first lateral direction. Thus, in a plan view of the top side, the gate electrode partially or completely covers or overlaps the channel portion, respectively. In this plan view, the gate electrode may also overlap a portion of the contact region and / or a portion of the drift region. However, the gate electrode may be electrically isolated from the channel portion, the contact region and the base region by an electrically isolating material.

[0019] The semiconductor body may comprise several drift regions, base regions and corresponding contact regions. All features disclosed in connection with one drift region, one base region and one contact region are also disclosed for all other drift regions, base regions and contact regions. For example, the drift region is arranged between each pair of base regions along a first lateral direction. Furthermore, each channel portion of the base region may be assigned a gate electrode, which in a plan view of the top side overlaps the channel portion.

[0020] The channel portion is the portion through which charge carriers flow from the contact region into the drift region during operation. For example, a power semiconductor device is configured to deplete the channel portion at the side facing the gate electrode by means of a gate electrode and thereby enable current to flow from the main electrode through the contact region, via the depleted channel portion and into the drift region.

[0021] At the top side, at least one of the contact region and the drift region protrudes beyond the base region in a vertical direction. For example, the contact region and / or the drift region protrudes beyond the base region by at least 50 nm or at least 100 nm and / or at most 1 μm or at most 5 μm. In other words, the contact region and / or the drift region terminates at a greater height relative to the drift layer than the base region. For example, both the contact region and the drift region protrude beyond the base region in a vertical direction at the top side. The protruding contact region and / or the drift region may taper in a vertical direction away from the drift layer.

[0022] By means of a raised contact region, the contact resistance can be reduced. A raised drift region allows, for example, a reduction in Cgd.

[0023] According to a further embodiment, at least one of the contact region and the drift region is epitaxially grown. For example, both the contact region and the drift region are epitaxially grown. The contact region and / or the drift region may be grown on a base semiconductor body including a drift layer. The drift layer and / or the base region may be formed by implanting dopants.

[0024] According to at least one embodiment, at least one of the epitaxially grown zones (i.e., the contact zone and / or the drift zone) has an inverse doping profile, for example over its entire volume, wherein the doping concentration decreases in a direction (along this direction) from the interior of the semiconductor body toward the top side. Additionally or alternatively, at least one of the epitaxially grown zones has a uniform doping profile, for example over its entire volume. It is possible that both zones have an inverse doping profile or a uniform doping profile. It is also possible that the epitaxially grown contact zone has a uniform doping profile and the epitaxially grown drift zone has an inverse doping profile, or vice versa.

[0025] An epitaxially grown region with an inverse doping profile has, for example, a minimum doping concentration that is at least one order of magnitude or at least two orders of magnitude lower than the maximum doping concentration in the region. An epitaxially grown region with a uniform doping profile has, for example, a maximum deviation from the average doping concentration of at most 20% or at most 10%.

[0026] It is also possible that at least one of the epitaxially grown regions has a doping profile whose doping concentration decreases in a direction (along this direction) from the top side towards the interior of the semiconductor body. For the reverse doping profile, the difference between the maximum doping concentration and the minimum doping concentration may be the same.

[0027] Growing the contact and / or drift regions epitaxially not only allows these regions to be formed to protrude beyond the base region, but also enables the doping concentrations of these regions to be set individually and independently. Furthermore, the doping concentrations of these regions can be set higher than when these regions are formed using implantation. Furthermore, the doping concentrations of these regions can be made very uniform over the entire volume of the region or have a special doping profile, such as an inverted doping profile.

[0028] According to a further embodiment, at the top side, the drift region protrudes beyond the base region in a vertical direction. In a plan view of the top side, the gate electrode covers at most a portion of the drift region. For example, in a plan view of the top side, the gate electrode covers at most 50% or at most 25% of the drift region. For example, the gate electrode does not cover the drift region at all, for example, it is spaced apart from the drift region in a first lateral direction or ends flush with the drift region in a first lateral direction.

[0029] The raised / protruding drift region enables the gate electrode to be formed such that it does not completely overlap the drift region. In this way, Cgc can be significantly reduced.

[0030] According to a further embodiment, the contact region and the channel portion are at least partially aligned in a vertical direction. For example, when viewed along a first lateral direction, the contact region and the channel portion at least partially overlap each other. For example, in this view, the contact region and the channel portion completely overlap each other. The alignment in the vertical direction enables efficient injection of charge carriers from the contact region into the channel portion.

[0031] Starting from the top side, the contact region may protrude deeper into the semiconductor body than the base region, or the base region may protrude deeper into the semiconductor body than the contact region. In the second case, a portion of the base region may be arranged vertically between the contact region and the drift layer. In other words, the distance between the contact portion and the back side of the semiconductor body may be greater or smaller than the distance between the base region and the back side. The back side is the side of the semiconductor body opposite to the top side.

[0032] According to a further embodiment, the doping concentration in the drift region is greater than the doping concentration in the drift layer, eg at least 10 times or at least 100 times greater.

[0033] According to a further embodiment, in a plan view of the top side, the gate electrode partially covers the contact region and / or the drift region. The gate electrode may have a first section that tapers towards the top side, i.e. the lateral extension along the first lateral direction decreases in the direction towards the top side. In a plan view, the first section may overlap the contact region and / or the drift region. For example, the taper is a result of the manufacturing process.

[0034] The gate electrode may further have a second section that tapers in a direction away from the top side.The first section may be arranged vertically between the top side and the second section.

[0035] According to a further embodiment, the power semiconductor device is a MOSFET or an IGBT or a JFET or a MISFET or a thyristor.

[0036] According to a further embodiment, the semiconductor body is based on a wide bandgap semiconductor, such as SiC or GaN.

[0037] According to a further embodiment, the gate electrode, and at least one of the contact region and the drift region protruding beyond the base region are at least partially aligned in a vertical direction. For example, when viewed along a first lateral direction, the gate electrode and the protruding contact region and / or the protruding drift region at least partially overlap each other.

[0038] Next, a method for manufacturing a power semiconductor device is described in detail. The method can be particularly used to manufacture a power semiconductor device according to any of the embodiments described herein. Therefore, all features disclosed for the power semiconductor device are also disclosed for the method, and vice versa.

[0039] According to an embodiment, the method comprises the following steps: manufacturing a semiconductor body with a top side, so that the semiconductor body has a drift layer of a first conductivity type, a base region of a second conductivity type arranged vertically between the drift layer and the top side, a contact region of the first conductivity type arranged vertically between the drift layer and the top side and adjacent to the base region and the top side, and a drift region of the first conductivity type arranged next to the base region and adjacent to the base region in a first lateral direction. In a further step, a main electrode is applied to the top side, and an electrical contact between the main electrode and the contact region is established. In a further step, a gate electrode is manufactured, so that, ultimately, the gate electrode is arranged on the top side and next to the main electrode in the first lateral direction, and so that in a plan view of the top side, the gate electrode at least partially overlaps with a channel portion of the base region, which channel portion is located between the contact region and the drift region in the first lateral direction. The semiconductor body is manufactured so that at the top side, at least one of the contact region and the drift region protrudes beyond the base region in the vertical direction.

[0040] The gate electrode may be manufactured before or after applying the main electrode. Furthermore, the gate electrode may be manufactured before or after forming the raised (ie protruding) contact region and / or the drift region.

[0041] According to a further embodiment, the manufacture of the semiconductor body comprises the following steps: providing a base semiconductor body having a drift layer and a base region. Prior to that, the base region and / or the drift layer may be formed in the base semiconductor body by means of implanting dopants. The base semiconductor body may be based on a wide bandgap semiconductor, such as SiC or GaN.

[0042] According to a further embodiment, the manufacturing of the semiconductor body comprises the step of epitaxially growing at least one of the contact region and the drift region on the base semiconductor body.

[0043] In accordance with at least one embodiment, the epitaxial growth is accomplished by chemical vapor deposition (CVD).

[0044] According to at least one embodiment, at least one of the following precursors is used for epitaxial growth: monosilane, disilane, trisilane, a chlorinated precursor such as DCS (dichlorosilane), a carbon precursor such as methane.

[0045] According to at least one embodiment, at least one of the following doping precursors is used for doping during epitaxial growth: diborane and phosphine.

[0046] According to at least one embodiment, the doping profile of the epitaxially grown region is set by adjusting the mass flow of the doping precursors. For example, a reverse doping profile is generated by reducing the mass flow of the doping precursors during epitaxial growth.

[0047] According to a further embodiment, before growing the contact region, a portion of the base semiconductor is removed in the region where the contact region is to be formed. The contact region is then grown in that region.

[0048] For example, a hole is etched into the base semiconductor body in order to define an area for growing the contact region. The depth of the hole measured in the vertical direction is, for example, at least 1 μm or at least 2 μm. For example, the hole is etched so that it extends completely through the base region in the vertical direction. Alternatively, the hole can be etched to have such a depth that it leads to the base region.

[0049] According to a further embodiment, before growing the drift region, a portion of the base semiconductor is removed in the region where the drift region is to be formed. The drift region is then grown in that region.

[0050] For example, a hole is etched into the base semiconductor body in order to define an area for growing the drift zone.The depth of the hole measured in the vertical direction is, for example, at least 1 μm or at least 2 μm.

[0051] According to a further embodiment, a gate electrode is formed on the base semiconductor body. For example, this is done after forming the base region and / or the drift layer. The gate electrode may be formed before producing at least one of the drift region and the contact region, for example by means of epitaxial growth.

[0052] To form the gate electrode, a gate electrode layer may first be applied to the top side of the base semiconductor body. The gate electrode layer may thereby be electrically isolated from the top side by a layer of electrically isolating material arranged between the gate electrode layer and the top side.

[0053] In a further step, the gate electrode layer and the underlying electrically insulating layer may be structured in order to form the gate electrode. Thereby, parts of the gate electrode layer and the underlying insulating layer may be removed, for example by means of etching. For structuring the gate electrode layer and the electrically insulating layer, a mask may be used.

[0054] According to a further embodiment, the electrically isolating material is applied at least on lateral surfaces of the gate electrode. These lateral surfaces are surfaces which delimit the gate electrode in a lateral direction, in particular in a first lateral direction. The lateral surfaces extend obliquely or perpendicularly to a main extension plane of the (base) semiconductor body.

[0055] The electrical isolation material may be deposited onto the gate electrode by means of a non-directional or conformal deposition method, respectively.

[0056] According to a further embodiment, at least one of the contact region and the drift region is selectively grown adjacent to a gate electrode having an isolation material applied thereon. That is, the gate electrode with the applied isolation material is used as a mask for a selective growth process. For example, the contact region is grown on one side of the gate electrode and the drift region is grown on another side of the gate electrode, wherein "side" and "another side" are intended to be relative to a first lateral direction.

[0057] For example, when growing the contact region and / or the drift region, the respective region is grown such that it adjoins the electrically isolating material in a first lateral direction.

[0058] Hereinafter, power semiconductor devices and methods for manufacturing power semiconductors will be explained in more detail with reference to the accompanying drawings based on exemplary embodiments. The accompanying drawings are included to provide further understanding. In the drawings, elements having the same structure and / or function may be referenced with the same reference numerals. It will be understood that the embodiments shown in the drawings are only illustrative representations and are not necessarily drawn to scale. As long as the elements or components in different figures correspond to each other in terms of their functions, their description will not be repeated for each of the following figures. For the sake of clarity, the elements may not appear in all figures with the corresponding reference numerals. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] Figures 1 to 4 shows an exemplary embodiment of a power semiconductor device,

[0060] Figure 5 A flow chart showing an exemplary embodiment of a method for manufacturing a power semiconductor device, and

[0061] Figures 6 to 12 Different locations in an exemplary embodiment of a method for producing a power semiconductor device are shown. DETAILED DESCRIPTION

[0062] according to Figure 1 The first exemplary embodiment of a power semiconductor device 100 comprises a semiconductor body 1 , which is based on a wide bandgap material, such as 6H-SiC or 3C-SiC, for example. A main electrode 2 and two gate electrodes 3 are arranged on a top side 10 of the semiconductor body 1 .

[0063] The semiconductor body 1 comprises a drift layer 11, which has a first conductivity type. In the following, it is assumed that the first conductivity type is electron conductivity or n-conductivity, respectively. Therefore, the drift layer 11 is n-doped. The second conductivity type is hole conductivity or p-conductivity, respectively, and the corresponding doping is therefore p-type doping. However, the whole concept also works when different regions or layers have opposite types of doping. For example, the doping concentration in the drift layer 11 is 10 8 cm -3 Up to 1015 cm -3 within the range.

[0064] On the bottom side of the drift layer 11, a substrate 15 adjoining the drift layer 11 is arranged, i.e. a SiC substrate 15. The substrate 15 also has a first conductivity type, i.e. in the present case n-doped. For example, the doping concentration is in the same range as the drift layer 11. In a vertical direction V perpendicular to the main extension plane of the semiconductor body 1, the substrate 15 is arranged between the further main electrode 6 and the drift layer 11. The further main electrode 6 adjoins the substrate 15 and is in electrical contact with the substrate 15. For example, the further main electrode is made of metal.

[0065] The semiconductor body 1 comprises two base regions 12 spaced apart from each other along a first lateral direction L1, the first lateral direction L1 being parallel to a main extension plane of the semiconductor body 1. The semiconductor body 1 further comprises a drift region 14 arranged between the two base regions 12 along the first lateral direction L1. The base region 12 has a second conductivity type (i.e., p-doped), and the drift region 14 has a first conductivity type (i.e., n-doped). The base region 12 adjoins the drift region 14 along the first lateral direction L1. The base region 12 and the drift region 14 are arranged between the drift layer 11 and the top side 10 of the semiconductor body 1 along the vertical direction V. Thus, the drift region 14 and the base region 12 adjoin the top side 10 and the drift layer 11 along the vertical direction V.

[0066] For example, the base regions 12 each have a 15 cm -3 with 10 18 cm -3 The doping concentration of the drift region 14 may be greater than the doping concentration of the drift layer 11, for example, in the range of 10 15 cm -3 with 10 18 cm -3 in the range between.

[0067] The semiconductor body 1 further comprises two contact regions 13, wherein each contact region 13 is assigned to a base region 12. The contact regions 13 have a first conductivity type and each adjoin the assigned base region 12 and the top side 10 of the semiconductor body 1. Figure 1 In an exemplary embodiment of the present invention, the contact region 13 adjoins the assigned base region 12 in the vertical direction V and in the first lateral direction L1. The doping concentration of the first contact region 13 is, for example, in each case at least 10 19 cm -3 .

[0068] exist Figure 1In an exemplary embodiment of the present invention, the contact region 13 and the drift region 14 protrude beyond the base region 12 in the vertical direction V, for example in each case by at least 1 μm. Therefore, the top side 10 is not flat, but includes a raised section due to the protruding region. The contact region 13 is in electrical contact with the main electrode 2, which is made of metal, for example. The gate electrode 3 (which is arranged in each case between the contact region 13 and the drift region 14 along the first lateral direction L1) is made of highly doped polysilicon, for example. Each gate electrode 3 is assigned to the base region 12 and covers the channel portion 12a of the corresponding base region 12 in a plan view of the top side 10. However, in this plan view, the gate electrode 3 does not overlap with the protruding drift region 14, that is, it is not aligned with the drift region along the first lateral direction L1.

[0069] The gate electrode 3 is electrically isolated from the semiconductor body 1 by means of an electrically isolating material 5, which is, for example, SiO2. The electrically isolating material 5 covers the gate electrode 3 on the side facing the semiconductor body 1, on the side facing away from the semiconductor body 1 and on the lateral surfaces extending obliquely to the main extension plane of the semiconductor body 1. In a first lateral direction L1, the contact region 13 as well as the drift region 14 adjoin the isolation material 5 covering the lateral surface of the gate electrode 3. This is possible because the raised contact region 13 and the raised drift region 14 are partially aligned with the gate electrode 3 in the vertical direction V.

[0070] like Figure 1 It can further be seen in FIG. 1 that the contact region 13 protrudes into the assigned base region 12 such that a channel portion 12a of the base region 12 is partially aligned with the contact region 13 in the vertical direction V. The drift region 14 protrudes deeper into the semiconductor body 1 than the base region 12 , ie in the vertical direction V closer to the further main electrode 6 .

[0071] Figure 1 The power semiconductor device 100 is a vertical MOSFET. The path of the electrons during operation is indicated by arrows. During operation and in the on-state of the MOSFET, the channel portion 12a of the base region 12 is partially depleted with the help of the gate electrode 3. This enables current (i.e., electrons) to flow from the main electrode 2 via the contact region 13 and the depletion portion of the channel portion 12a into the drift region 14 and from there through the drift layer 11 to reach the other main electrode 6. Since the contact region 13 protrudes beyond the base region 12, the contact resistance can be reduced. Since the protruding drift region 14 and the gate electrode 3 are not aligned in the lateral direction, the capacitance between the gate electrode 3 and the other main electrode 6 is kept small. Since the contact region 13 protrudes into the base region 12, electrons can be efficiently injected from the contact region 13 into the depletion portion of the channel portion 12a.

[0072] Figure 2A second exemplary embodiment of a power semiconductor device 100 is shown, which is again a vertical power MOSFET. In this case, only one base region 12, one contact region 13 and one gate electrode 3 are shown. However, in this case, several base regions 12 and assigned contact regions 13 as well as several gate electrodes 3 may also be present.

[0073] As from Figure 2 It can be guessed that, in a plan view of the top side 10, the gate electrode 3 covers or overlaps the contact region 13 and the drift region 14, respectively. In addition, the first section of the gate electrode 3 tapers in a direction toward the top side 10, and the second section tapers in a direction away from the top side 10. Figure 2 In the cross-sectional view of , the gate electrode 3 is a rhombus. When the gate electrode 3 is formed after the contact region 13 and / or after the drift region 14, such a structure can be produced.

[0074] Figure 3 A third exemplary embodiment of a power semiconductor device 100 is shown, in which only the contact region 13 protrudes beyond the base region 12 at the top side 10. In a plan view of the top side 10, the gate electrode 3 completely overlaps the drift region 14.

[0075] Figure 4 A fourth exemplary embodiment of a power semiconductor component 100 is shown, in which, in contrast to the previous exemplary embodiments, the contact region 13 projects completely through the base region 12 and deeper into the semiconductor body 1 than the base region 12 .

[0076] In all exemplary embodiments of the power semiconductor device 100 shown so far, the contact region 13 and / or the drift region 14 protruding beyond the base region 12 may be epitaxially grown.

[0077] Figure 5A flow chart of an exemplary embodiment of a method for manufacturing a power semiconductor device is shown. In step S1, a semiconductor body having a top side is manufactured so that the semiconductor body has a drift layer of a first conductivity type, a base region of a second conductivity type arranged vertically between the drift layer and the top side, a contact region of a first conductivity type arranged vertically between the drift layer and the top side and adjacent to the base region and the top side, and a drift region of the first conductivity type next to the base region and adjacent to the base region in a first lateral direction. In a further step S2, a main electrode is applied to the top side, and an electrical contact between the main electrode and the contact region is established. In a further step S3, a gate electrode is manufactured so that, ultimately, the gate electrode is located on the top side and next to the main electrode in a first lateral direction, and so that in a plan view of the top side, the gate electrode at least partially overlaps with a channel portion of the base region, which channel portion is located between the contact region and the drift region in a first lateral direction. In step S1 , a semiconductor body is manufactured such that, at a top side, at least one of the contact region and the drift region protrudes beyond the base region in a vertical direction.

[0078] Figure 6 A method for manufacturing a power semiconductor device (eg, Figure 1 In this position, a base semiconductor body 1' is provided, which is for example based on Figure 1 The base semiconductor body 1' comprises a substrate 15, an n-doped drift layer 11, and a p-doped base region 12, which adjoins the top side of the base semiconductor body 1'. The drift layer 11 and / or the base region 12 may have been formed by implanting dopants. In order to produce laterally spaced base regions 12, a mask may be used during the implantation.

[0079] exist Figure 7 In the next position shown in FIG. 1 , a gate electrode layer 30 is applied to the top side of the base semiconductor body 1 ′. A layer of an electrically isolating material 5 is arranged between the base semiconductor body 1 ′ and the gate electrode layer 30 .

[0080] exist Figure 8 , the gate electrode layer 30 has been structured in such a way that individual gate electrodes 3 are produced which are spaced apart from one another in the first lateral direction L1. The gate electrode 3 is electrically isolated from the base semiconductor body 1' by an electrically isolating material 5 which has been structured together with the gate electrode layer 30. In order to structure the gate electrode layer 30 and the underlying electrically isolating material 5, an etching process may be used which uses a mask.

[0081] exist Fig. 9, an electrically isolating material 5 has been applied to lateral surfaces of the gate electrode 3, which extend obliquely to the main extension plane of the base semiconductor body 1'. For depositing the electrically isolating material 5, a conformal or non-directional deposition method can be used. Any electrically isolating material that may have been deposited on the top side of the semiconductor base body 1' has been removed.

[0082] exist Fig.10 Holes are etched into the base semiconductor body 1 ', i.e. in the region where the contact region and the drift region are to be produced. In the region of the contact region to be produced, the etched holes do not protrude completely through the base region 12, but lead to the base region 12. Alternatively, however, the holes in these regions may have been etched completely through the base region 12. In the region of the drift region to be produced, the etched holes are deeper.

[0083] Fig.11 A position is shown in which a contact region 13 and a drift region 14 are selectively epitaxially grown in the previously etched region. The growth is performed such that the contact region 13 and the drift region 14 eventually protrude beyond the base region 12 at the top side 10 in the vertical direction V. For growing the contact region 13 and the drift region 14, the gate electrode 3 with the electrically isolating material 5 on the corresponding lateral surfaces may have been used as a mask for the selective growth process. The growth of the contact region 13 and the drift region 14 has the advantage that the doping concentration of these regions can be adjusted independently and can be set to be greater than, for example, the doping concentration in an implantation process. Fig.11 , the final position during production of the semiconductor body 1 is shown.

[0084] Fig.12 The position is shown in which a main electrode 2 , for example metallic, is applied to the top side 10 of the semiconductor body 1 and an electrical connection of the main electrode 2 to the contact region 13 is established.

[0085] To finalize the power semiconductor device, a further main electrode can be applied to the back side of the semiconductor body 1 (see Figure 1 ).

[0086] The embodiments shown in the figures as stated represent exemplary embodiments of the improved power semiconductor device and the improved method for manufacturing the power semiconductor device; therefore, they do not constitute a complete list of all embodiments according to the improved power semiconductor device and method. For example, the actual power semiconductor device and method may differ from the embodiments shown in terms of arrangement, elements, order of method steps.

[0087] Reference numerals

[0088] 1Semiconductor body

[0089] 1' substrate semiconductor body

[0090] 2 Main electrode

[0091] 3. Gate electrode

[0092] 5 Electrical isolation materials

[0093] 6 Additional main electrode

[0094] 10 Top side

[0095] 11 Drift layer

[0096] 12 Base region

[0097] 12a Channel section

[0098] 13. Contact area

[0099] 14 Drift Zone

[0100] 15 Substrate

[0101] 30 Gate electrode layer

[0102] 100 Power semiconductor devices

[0103] L1 First lateral direction

[0104] V vertical direction

[0105] Si method steps

Claims

1. A power semiconductor device (100), comprising: - a semiconductor body (1) having a top side (10), - a main electrode (2) located on said top side (10), and - a gate electrode (3) located on the top side (10) and arranged next to the main electrode (2) in a first lateral direction (L1), wherein: The semiconductor body (1) comprises: - a drift layer (11) of a first conductivity type, - a base region (12) of a second conductivity type arranged vertically between the drift layer (11) and the top side (10), - a contact region (13) of the first conductivity type arranged vertically between the drift layer (11) and the top side (10), wherein the contact region (13) adjoins the base region (12) and the top side (10), a drift region (14) of the first conductivity type arranged beside the base region (12) and adjoining the base region (12) in the first lateral direction (L1), - the main electrode (2) is in electrical contact with the contact area (13), - in a plan view of the top side (10), the gate electrode (3) at least partially covers a channel portion (12a) of the base region (12), the channel portion being located between the contact region (13) and the drift region (14) along the first lateral direction (L1), - at the top side (10), at least one of the contact region (13) and the drift region (14) protrudes beyond the base region (12) in a vertical direction (V).

2. The power semiconductor device (100) according to claim 1, wherein: - At least one of the contact region (13) and the drift region (14) is epitaxially grown.

3. The power semiconductor device (100) according to claim 2, wherein: At least one of the epitaxially grown regions (13, 14) has: - an inverse doping profile, wherein the doping concentration decreases in a direction from the interior of the semiconductor body (1) towards the top side (10), or -Uniform doping profile.

4. The power semiconductor device (100) according to any one of the preceding claims, wherein: - at the top side (10), the drift region (14) protrudes beyond the base region (12) in a vertical direction (V), - in a plan view of the top side (10), the gate electrode (3) covers at most a portion of the drift region (14).

5. The power semiconductor device (100) according to any one of the preceding claims, wherein: - the contact area (13) and the channel portion (12a) are at least partially aligned along the vertical direction (V).

6. The power semiconductor device (100) according to any one of the preceding claims, wherein: - The drift region (14) has a greater doping concentration than the drift layer (11).

7. The power semiconductor device (100) according to any one of the preceding claims, wherein: - In a plan view of the top side (10), the gate electrode (3) partially covers the contact area (13).

8. The power semiconductor device (100) according to any one of the preceding claims, wherein: - The power semiconductor device is a MOSFET or an IGBT or a MISFET.

9. The power semiconductor device (100) according to any one of the preceding claims, wherein: The semiconductor body (1) is based on a wide bandgap semiconductor.

10. The power semiconductor device (100) according to any one of the preceding claims, wherein: - at least one of the contact region (13) and the drift region (14) protruding beyond the base region (12), and the gate electrode (3) are at least partially aligned along a vertical direction (V).

11. A method for manufacturing a power semiconductor device (100), comprising: - producing a semiconductor body (1) having a top side (10), such that the semiconductor body (1) has: - a drift layer (11) of a first conductivity type, - a base region (12) of a second conductivity type arranged vertically between the drift layer (11) and the top side (10), a contact region (13) of the first conductivity type arranged vertically between the drift layer (11) and the top side (10) and adjoining the base region (12) and the top side (10), a drift region (14) of the first conductivity type arranged beside the base region (12) and adjoining the base region (12) in a first lateral direction (L1), - applying a main electrode (2) to the top side (10) and establishing an electrical contact between the main electrode (2) and the contact area (13), - manufacturing a gate electrode (3) such that, finally, the gate electrode (3) is arranged on the top side (10) and beside the main electrode (2) in the first lateral direction (L1), and such that, in a plan view of the top side (10), the gate electrode (3) overlaps at least a channel portion (12a) of the base region (12), the channel portion being located between the contact region (13) and the drift region (14) in the first lateral direction (L1), wherein: The semiconductor body (1) is manufactured such that, at the top side (10), at least one of the contact region (13) and the drift region (14) protrudes beyond the base region (12) in a vertical direction (V).

12. The method according to claim 11, wherein: - The manufacturing of the semiconductor body (1) comprises: - providing a base semiconductor body (1') having said drift layer (11) and said base region (12), - epitaxially growing at least one of the contact region (13) and the drift region (14) on the base semiconductor body (1').

13. The method according to claim 12, wherein: - generating an inverse doping profile of the epitaxially grown zones (13, 14) by reducing the mass flow of the doping precursors during said epitaxial growth.

14. The method according to claim 12 or 13, wherein: - before growing the contact region (13), removing a portion of the base semiconductor body (1') in the region where the contact region (13) is to be formed, - The contact region (13) is grown in this area.

15. The method according to any one of claims 12 to 14, wherein: - before growing the drift region (14), removing a portion of the base semiconductor body (1') in the region where the drift region (14) is to be formed, - Growing the drift region (14) in this area.

16. The method according to any one of claims 12 to 15, wherein: - forming the gate electrode (3) on the base semiconductor body (1'), - applying an electrically isolating material (5) at least on the lateral surface of the gate electrode (3), - At least one of the contact region (13) and the drift region (14) is selectively grown adjacent to the gate electrode (3) with the applied isolation material (5).

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