Solid-state imaging element and electronic device

Abstract

The present disclosure pertains to a solid-state imaging element and an electronic device that make it possible to further improve resolution. The solid-state imaging element includes: a photoelectric conversion unit that performs photoelectric conversion of light into charge for each pixel; a first FD section that stores the charge transferred from the photoelectric conversion unit through a transfer transistor and converts the charge into a pixel signal; a second FD section connected to the first FD section via a connection transistor; and an inter-line capacitor connected to the second FD section to store charge. The line-to-line capacitor is composed of a first electrode connected to the second FD section and a second electrode facing the first electrode, and a dielectric is sandwiched between the first electrode and the second electrode. A wiring connected to the second electrode is provided so as to cover at least the entire second electrode in a plan view viewed from a logic substrate side stacked on a sensor substrate on which the photoelectric conversion unit is provided. The present technology is applicable, for example, to a CMOS image sensor having a stacked structure.

Description

Technical Field

[0001] The present disclosure relates to a solid-state imaging element and an electronic device, and particularly to a solid-state imaging element and an electronic device capable of achieving higher image quality. Background Art

[0002] Conventionally, a stacked CMOS (Complementary Metal Oxide Semiconductor) image sensor in which a sensor substrate including a photodiode and a logic substrate including a logic circuit are stacked is used as a solid-state imaging device.

[0003] For example, a CMOS image sensor is constructed with a plurality of pixels arranged in a desired pattern in which each pixel is formed by a photodiode and a plurality of transistors (so-called MOS transistors). A CMOS image sensor has also been developed in which an inter-line capacitor is connected to an FD (floating diffusion) portion for accumulating charges transferred from a photodiode for each pixel.

[0004] For example, Patent Document 1 discloses an image sensor in which charges are accumulated in an inter-line capacitor having a MIM (Metal-Insulator-Metal) structure in a third layer provided between a first layer including a photodiode and a second layer including a logic circuit. Citation list Patent Literature

[0005] Patent Document 1 U.S. Patent Application Publication No. 2021 / 0134873 (Specification) (US, A1) Summary of the invention Technical issues

[0006] Incidentally, in the stacked CMOS image sensor as described above, it is known that band noise occurs when the logic substrate is driven, and there is a concern that image quality may be degraded due to the inter-line capacitor being affected by the band noise.

[0007] In view of this situation, the present disclosure aims to achieve higher image quality. Solutions to technical problems

[0008] According to one aspect of the present disclosure, a solid-state imaging element includes, for each pixel, a photoelectric conversion unit that photoelectrically converts light into electric charges; a first FD portion that accumulates electric charges transferred from the photoelectric conversion unit via a transfer transistor to convert the electric charges into a pixel signal; a second FD portion connected to the first FD portion via a connecting transistor; and an inter-line capacitor connected to the second FD portion to accumulate electric charges, wherein the inter-line capacitor is constructed to include a first electrode connected to the second FD portion and a second electrode facing the first electrode via a dielectric, and when observed in a plan view from a logic substrate stacked on a sensor substrate provided with the photoelectric conversion unit, the wiring connected to the second electrode is arranged to cover at least the entire second electrode.

[0009] An electronic device according to one aspect of the present disclosure includes a solid-state imaging element, which includes, for each pixel, a photoelectric conversion unit that photoelectrically converts light into electric charges; a first FD portion that accumulates electric charges transferred from the photoelectric conversion unit via a transfer transistor to convert the electric charges into a pixel signal; a second FD portion connected to the first FD portion via a connecting transistor; and an inter-line capacitor connected to the second FD portion to accumulate electric charges, wherein the inter-line capacitor is constructed to include a first electrode connected to the second FD portion and a second electrode facing the first electrode via a dielectric, and when observed in a plan view from a logic substrate stacked on a sensor substrate provided with the photoelectric conversion unit, the wiring connected to the second electrode is arranged to cover at least the entire second electrode.

[0010] In one aspect of the present disclosure, each pixel includes a photoelectric conversion unit that photoelectrically converts light into electric charge; a first FD portion that accumulates electric charge transferred from the photoelectric conversion unit via a transfer transistor to convert the electric charge into a pixel signal; a second FD portion connected to the first FD portion via a connecting transistor; and an inter-line capacitor connected to the second FD portion to accumulate electric charge. In addition, the inter-line capacitor is configured to include a first electrode connected to the second FD portion and a second electrode facing the first electrode via a dielectric, and when viewed in a plan view from a logic substrate stacked on a sensor substrate provided with the photoelectric conversion unit, a wiring connected to the second electrode is provided to cover at least the entire second electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 is a circuit diagram showing a first embodiment of a pixel included in an image pickup element to which the present technology is applied. Figure 2 An example of a driving signal for driving a pixel is shown. Figure 3 is a diagram showing a configuration example of a pixel in a cross-sectional view. Figure 4 is a diagram showing a configuration example of three pixels in a plan view. Figure 5 is a diagram showing a configuration example of a pixel according to a first modification example in a cross-sectional view. Figure 6 is a diagram showing a configuration example of a pixel according to a second modification example in a cross-sectional view. Figure 7 is a circuit diagram showing a second embodiment of a pixel included in an image pickup element to which the present technology is applied. Figure 8 is a diagram showing a configuration example of a pixel in a cross-sectional view. Fig. 9 is a diagram showing a configuration example of three pixels in a plan view. Fig.10 is a circuit diagram showing a third embodiment of a pixel included in an image pickup element to which the present technology is applied. Fig.11 is a diagram showing a configuration example of a pixel in a cross-sectional view. Fig.12 is a diagram showing a configuration example of an inter-line capacitor having a three-dimensional structure. Fig.13 is a block diagram showing a configuration example of an image pickup device. Fig.14 is a diagram showing an example of use of an image sensor. Fig.15 is a block diagram showing an example of a schematic configuration of a vehicle control system. Fig.16 2 is a diagram showing an example of installation positions of the vehicle exterior information detection unit and the camera unit. DETAILED DESCRIPTION

[0012] Hereinafter, specific embodiments to which the present technology is applied will be described in detail with reference to the accompanying drawings.

[0013] <First Configuration Example of Pixel> Will refer to Figures 1 to 6 A first embodiment of a pixel included in an image pickup element to which the present technology is applied will be described.

[0014] Figure 1 A circuit diagram of a pixel 11 is shown.

[0015] like Figure 1As shown, the pixel 11 includes a photoelectric conversion unit 12, a transfer transistor 13, a first FD portion 14, a connection transistor 15, a second FD portion 16, an inter-line capacitor 17, a reset transistor 18, an amplifier transistor 19, and a selection transistor 20, and outputs a pixel signal via a vertical signal line 21. For example, the pixel 11 is a LOFIC (Lateral Overflow Integrated Capacitance) pixel, and has a structure in which, when the photoelectric conversion element 12 is irradiated with light having an intensity sufficient to exceed the saturation capacity of the photoelectric conversion unit 12, the charge overflowing from the photoelectric conversion unit 12 is laterally guided and accumulated in the inter-line capacitor 17.

[0016] The anode terminal of the photoelectric conversion unit 12 is grounded, and the cathode terminal is connected to the first FD portion 14 via the transfer transistor 13. The photoelectric conversion unit 12 receives light irradiating the light receiving surface of the imaging element and photoelectrically converts the received light into charges corresponding to the light amount.

[0017] The transfer transistor 13 is provided to connect the photoelectric conversion unit 12 and the first FD portion 14. In addition, the transfer transistor 13 is driven according to a transfer signal TG, and transfers the charge photoelectrically converted by the photoelectric conversion unit 12 to the first FD portion 14.

[0018] The first FD portion 14 accumulates the charges transferred from the photoelectric conversion unit 12 via the transfer transistor 13 to convert the charges into a pixel signal.

[0019] The connection transistor 15 is arranged to connect the first FD portion 14 and the second FD portion 16. Furthermore, the connection transistor 15 is driven according to a connection signal FDG to turn on / off the connection between the first FD portion 14 and the second FD portion 16.

[0020] When the connecting transistor 15 is turned on, the second FD portion 16 is connected to the first FD portion 14 , and accumulates charges together with the first FD portion 14 .

[0021] The line capacitor 17 is composed of a capacitor having a Figure 3 The inter-line capacitor 17 is composed of a capacitor of the MIM structure provided between the wirings as described above, and is provided to connect the second FD portion 16 and the signal line MIMVDD. The inter-line capacitor 17 accumulates electric charge in the same manner as the second FD portion 16.

[0022] The reset transistor 18 is arranged to connect the second FD portion 16 to the power supply line VDD. In addition, the reset transistor 18 is driven according to the reset signal RST, and when the connection transistor 15 and the reset transistor 18 are turned on, the charges accumulated in the first FD portion 14, the second FD portion 16 and the inter-line capacitor 17 are discharged to the power supply line VDD, thereby resetting the charges.

[0023] The gate electrode of the amplifier transistor 19 is connected to the first FD portion 14, and is arranged to connect the power supply line VDD and the selection transistor 20. Therefore, the amplifier transistor 19 converts the charge accumulated in the first FD portion 14 or the charge accumulated in the first FD portion 14, the second FD portion 16, and the inter-line capacitor 17 into a pixel signal of a level corresponding to the charge of their respective capacitances.

[0024] The selection transistor 20 is arranged to connect the amplifier transistor 19 and the vertical signal line 21. Further, the selection transistor 20 is driven according to the selection signal SEL, and when the selection transistor 20 is turned on, the pixel signal obtained by conversion of the amplifier transistor 19 is output to the vertical signal line 21.

[0025] Figure 2 An example of a drive signal for driving the pixel 11 is shown.

[0026] like Figure 2 As shown, the pixel 11 operates in the order of shutter driving, a first charge accumulation period, a first CDS (Correlated Double Sampling) driving, a DDS (Double Data Sampling) driving, a second charge accumulation period, and a second CDS driving.

[0027] In shutter driving, the connection transistor 15 , the transfer transistor 13 , and the reset transistor 18 are respectively turned on in a pulse manner according to the connection signal FDG, the transfer signal TG, and the reset signal RST, and the charge in the pixel 11 is reset accordingly.

[0028] In the first charge accumulation period, the pixel 11 is exposed for a long time, and the charges photoelectrically converted by the photoelectric conversion unit 12 by the exposure time longer than the second charge accumulation period are accumulated in the photoelectric conversion unit 12 .

[0029] In the first CDS drive, the connection transistor 15 is kept turned off according to the connection signal FDG, that is, the second FD portion 16 and the inter-line capacitor 17 are not connected to the first FD portion 14, and the pixel signal P-SP_H and the pixel signal D-SP_H based on the charge accumulated in the photoelectric conversion unit 12 during the first charge accumulation period are sequentially read out. The pixel signal P-SP_H is a pixel signal read out when the first FD portion 14 is at a reset level. The pixel signal D-SP_H is a pixel signal read out when the charge transferred from the photoelectric conversion unit 12 is accumulated in the first FD portion 14 in response to the transfer transistor 13 being turned on in a pulsed manner according to the transfer signal TG.

[0030] In the DDS driving, in response to turning on the connection transistor 15 according to the connection signal FDG, the second FD portion 16 and the inter-line capacitor 17 are connected to the first FD portion 14, and the pixel signal D-SP_L and the pixel signal P-SP_L based on the charge accumulated in the photoelectric conversion unit 12 during the first charge accumulation period are sequentially read out. The pixel signal D-SP_L is a pixel signal read out in a state where the charge transferred from the photoelectric conversion unit 12 and the charge overflowing from the photoelectric conversion unit 12 and accumulated in the inter-line capacitor 17 are accumulated in the first FD portion 14 and the second FD portion 16 when the transfer transistor 13 is turned on in a pulsed manner according to the transfer signal TG. The pixel signal P-SP_L is a pixel signal read out when the accumulated charge is released in response to turning on the reset transistor in a pulsed manner according to the reset signal RST and the first FD portion 14, the second FD portion 16, and the inter-line capacitor 17 are at a reset level accordingly.

[0031] In the second charge accumulation period, short-time exposure of the pixel 11 is performed, and the charges photoelectrically converted by the photoelectric conversion unit 12 by the exposure for a period shorter than the first charge accumulation period are accumulated in the photoelectric conversion unit 12 .

[0032] In the second CDS driving, similarly to the first CDS driving, the pixel signal P-SP_H and the pixel signal D-SP_H based on the charges accumulated in the photoelectric conversion unit 12 within the second charge accumulation period are sequentially read out.

[0033] Then, in the pixel 11, before the shutter drive is performed, the potential of the signal line MIMVDD is switched from a low level (Lo level) (for example, lower than the intermediate voltage of the power line VDD) to a high level (Hi level) (for example, the same voltage as the power line VDD), and after the shutter drive is performed, the potential of the signal line MIMVDD is switched from a high level to a low level. Thereafter, in the pixel 11, before the first CDS drive is performed, the potential of the signal line MIMVDD is switched from a low level to a high level, and after the second CDS drive is performed, the potential of the signal line MIMVDD is switched from a high level to a low level. In other words, in the pixel 11, during the first charge accumulation period, the potential of the signal line MIMVDD is controlled to a low level.

[0034] By controlling the potential of the signal line MIMVDD in this way, in the pixel 11 , during the first charge accumulation period in which charges are accumulated in the photoelectric conversion unit 12 for a long time, increase in noise in the charges accumulated in the photoelectric conversion unit 12 can be suppressed.

[0035] Figure 3 is a cross-sectional view showing a configuration example of the pixel 11 .

[0036] like Figure 3As shown, the solid-state imaging element has a stacked structure in which a sensor substrate 31 on which the photoelectric conversion unit 12 is provided and a logic substrate 32 on which a logic circuit is provided are stacked. Figure 3 In FIG. 1 , the bonding surface between the sensor substrate 31 and the logic substrate 32 is indicated by a dotted line.

[0037] The sensor substrate 31 is composed of a semiconductor layer 33 and a wiring layer 34 stacked on the front surface of the semiconductor layer 33, and the back surface ( Figure 3 The logic substrate 32 is composed of a semiconductor layer 36 and a wiring layer 35 stacked on the front surface of the semiconductor layer 36. Then, the wiring layer 34 of the sensor substrate 31 and the wiring layer 35 of the logic substrate 32 are bonded together.

[0038] The semiconductor layer 33 includes a photoelectric conversion unit 12, a first FD portion 14, and a second FD portion 16. In addition, on the front surface of the semiconductor layer 33, a transfer transistor 13 is provided between the photoelectric conversion unit 12 and the first FD portion 14, a connection transistor 15 is provided between the first FD portion and the second FD portion 16, and a reset transistor 18 is provided adjacent to the second FD portion 16.

[0039] The wiring layer 34 is provided with multiple layers of wiring and electrodes connecting the layers of wiring, and the wiring layer 35 is also provided with multiple layers of wiring. The pixel 11 has a configuration in which the inter-line capacitor 17 is provided between the wiring provided in the wiring layer 34 and the wiring layer 35.

[0040] exist Figure 3 In the illustrated configuration example, the line capacitor 17 formed by the lower electrode 41 and the upper electrode 42 and the dielectric film 43 sandwiched therebetween is provided in the wiring layer 34, and the upper wiring 44 connected to the upper electrode 42 is provided in the wiring layer 34. For example, the lower electrode 41 connected to the second FD portion 16 uses Ta / TiN, the upper electrode 42 facing the lower electrode 41 via the dielectric film 43 uses TiN, and the dielectric film 43 uses a high-k film (for example, a ZrO / AlO / ZrO stacked film).

[0041] The lower electrode 41 of the inter-line capacitor 17 is connected to the second FD portion 16 via the wiring and the electrode in the wiring layer 34, and the charge overflowed during the accumulation is accumulated in the inter-line capacitor 17 and the second FD portion 16. The upper electrode 42 of the inter-line capacitor 17 is connected to the upper wiring 44 via an electrode (through hole) formed to pass through the wiring layer 34. The upper wiring 44 is shared by the pixels 11 arranged in the same row, and is connected to the signal line MIMVDD outside the pixel array.

[0042] In addition, for example, when viewed in a plan view from the logic substrate 32, the upper wiring 44 is arranged to cover the inter-line capacitor 17, and is arranged to cover at least the entire upper electrode 42. In other words, the pixel 11 is configured so that the upper electrode 42 is completely hidden by the upper wiring 44 and is not visible when viewed in a plan view from the logic substrate 32. The pixel 11 may be configured so that the lower electrode 41 is hidden by the upper wiring 44 and is not visible when viewed in a plan view from the logic substrate 32, but, for example, the pixel 11 may be configured so that a portion of the lower electrode 41 is exposed from the upper wiring 44.

[0043] Will refer to Figure 4 The structure of the upper wiring 44 will be described. Figure 4 1 is a diagram showing a schematic configuration example of three pixels 11 - 1 to 11 - 3 arranged in the same row when viewed in a plan view viewed from the logic substrate 32 .

[0044] like Figure 4 As shown, the upper wiring 44 is arranged along the pixels 11-1 to 11-3 arranged in the same row. In each of the pixels 11-1 to 11-3, when viewed in a plan view from the logic substrate 32, the lower electrodes 41-1 to 41-3 are formed to have a larger area than the upper electrodes 42-1 to 42-3, and the peripheries of the lower electrodes 41-1 to 41-3 are exposed to the outside from the upper electrodes 42-1 to 42-3, respectively.

[0045] In addition, when viewed in a plan view viewed from the logic substrate 32, the pixels 11-1 to 11-3 have a configuration in which the upper electrodes 42-1 to 42-3 are completely covered by the upper wiring 44 so as not to be visible, and the upper and lower portions of the lower electrodes 41-1 to 41-3 are partially exposed from the upper wiring 44. Specifically, the upper wiring 44 is arranged so that its width is wider than the width of each of the upper electrodes 42-1 to 42-3, and narrower than the width of each of the lower electrodes 41-1 to 41-3. Alternatively, the lower electrodes 41-1 to 41-3 and the upper electrodes 42-1 to 42-3 may be configured to be completely covered by the upper wiring 44.

[0046] As described above, the pixel 11 is constructed so that the upper electrode 42 is completely covered by the upper wiring 44, and so that most of the lower electrode 41 is covered by the upper wiring 44 (the portion of the lower electrode 41 exposed from the upper wiring 44 is minimized), thereby making it possible to suppress the influence of the band noise from the logic substrate 32. In other words, the pixel 11 has a structure in which the lower electrode 41 connected to the second FD portion 16 is covered by the upper wiring 44 connected to the upper electrode 42 to shield the FD node of the inter-line capacitor 17 from the influence of the band noise. In addition, the upper wiring 44 is connected to the signal line MIMVDD, so that the FD node of the inter-line capacitor 17 can be prevented from being affected by the band noise (for example, potential fluctuation due to capacitive coupling with the logic substrate 32).

[0047] The pixel 11 is constructed as described above, and by suppressing the influence of the band noise from the logic substrate 32, it is possible to achieve an improvement in the image quality of the imaging element, and in particular, the image quality at low illumination levels can be expected to be improved. For example, by adding a shielding layer between the logic substrate 32 and the line capacitor 17 to shield the line capacitor 17, it is also possible to suppress the influence of the band noise, but the pixel 11 can be made cheaper than this construction.

[0048] Figure 5 is a cross-sectional view showing a first modification example of a pixel included in an image pickup element. Figure 5 In the pixel 11a shown, Figure 3 The same components as those of the pixel 11 in FIG. 1 are denoted by the same reference numerals, and a detailed description thereof will be omitted.

[0049] like Figure 5 As shown, the imaging element is formed by bonding a wiring layer 34a of a sensor substrate 31a and a wiring layer 35a of a logic substrate 32a.

[0050] Figure 3 The pixel 11 in has a structure such that the line capacitor 17 and the upper wiring 44 are provided in the wiring layer 34, while the pixel 11a is configured such that the line capacitor 17a and the upper wiring 44a are provided in the wiring layer 35a. In the pixel 11a, the Cu-Cu bonding portion 51 is provided on the bonding surface between the sensor substrate 31a and the logic substrate 32a, and the lower electrode 41a of the line capacitor 17a is connected to the second FD portion 16 via the Cu-Cu bonding portion 51.

[0051] As described above, the pixel 11a has a structure in which the inter-line capacitor 17a arranged between the lines provided in the wiring layer 34a and the wiring layer 35a and the upper wiring 44a are arranged on the wiring layer 35a side of the logic substrate 32a. Figure 3 As with the pixel 11, in the pixel 11a, the upper wiring 44a is arranged to cover the inter-line capacitor 17a when viewed in a plan view from the logic substrate 32a, for example, the upper wiring 44a is arranged to cover at least the entire upper electrode 42a.

[0052] Therefore, with Figure 3 Like pixel 11 in FIG. 3 , pixel 11 a is able to suppress the influence of the frequency band noise from logic substrate 32 a.

[0053] Figure 6 is a cross-sectional view showing a second modification example of a pixel included in an image pickup element. Figure 6 In the pixel 11b shown, Figure 3The same components as those of the pixel 11 in FIG. 1 are denoted by the same reference numerals, and a detailed description thereof will be omitted.

[0054] like Figure 6 As shown, the imaging element is formed by bonding a wiring layer 34b of a sensor substrate 31b and a wiring layer 35b of a logic substrate 32b.

[0055] Figure 3 The pixel 11 in has a structure in which the line capacitor 17b and the upper wiring 44 are provided in the wiring layer 34, while the pixel 11b has a structure in which the line capacitor 17b is provided in the wiring layer 34b, and the upper wiring 44b is provided in the wiring layer 35b. In the pixel 11b, the Cu-Cu bonding portion 51 is provided on the bonding surface between the sensor substrate 31b and the logic substrate 32b, and the line capacitor 17b is connected to the upper wiring 44b via the Cu-Cu bonding portion 51.

[0056] As described above, the pixel 11b has a structure in which the inter-line capacitor 17b and the upper line 44b arranged between the lines provided in the wiring layer 34b and the wiring layer 35b are arranged separately in the wiring layer 34b of the sensor substrate 31b and the wiring layer 35b of the logic substrate 32b, respectively. Figure 3 As with pixel 11 in FIG. 1 , in pixel 11 b , upper wiring 44 b is arranged to cover inter-line capacitor 17 b when viewed in a plan view from logic substrate 32 b , for example, upper wiring 44 b is arranged to cover at least the entire upper electrode 42 b .

[0057] Therefore, with Figure 3 Like pixel 11 in FIG. 3 , pixel 11 b is able to suppress the influence of the frequency band noise from logic substrate 32 b.

[0058] <Second Configuration Example of Pixel> Will refer to Figures 7 to 9 A second embodiment of a pixel included in an image pickup element to which the present technology is applied is described. Figures 7 to 9 In the pixel 11A shown, Figures 1 to 4 The same components of the pixel 11 are denoted by the same reference numerals, and a detailed description thereof will be omitted.

[0059] Figure 7 A circuit diagram of the pixel 11A is shown.

[0060] like Figure 7 As shown, Figure 1Like the pixel 11 of FIG. 1 , the pixel 11A is configured to include a photoelectric conversion unit 12, a transfer transistor 13, a first FD portion 14, a connection transistor 15, a second FD portion 16, an inter-line capacitor 17A, a reset transistor 18, an amplifier transistor 19, and a selection transistor 20. In addition, the pixel 11A is configured to include a second photoelectric conversion unit 22, a third FD portion 23, a second connection transistor 24, and a second inter-line capacitor 25.

[0061] The anode terminal of the second photoelectric conversion unit 22 is grounded and the cathode terminal is connected to the third FD portion 23. The second photoelectric conversion unit 22 receives light irradiating the light receiving surface of the imaging element and photoelectrically converts the received light into electric charge corresponding to the amount of light. The second photoelectric conversion unit 22 has a sub-pixel structure in which it has a smaller light receiving area than the light receiving area of ​​the photoelectric conversion unit 12.

[0062] The third FD portion 23 accumulates the charges photoelectrically converted by the second photoelectric conversion unit 22 to convert the charges into a pixel signal.

[0063] The second connection transistor 24 is arranged to connect the second FD portion 16 and the third FD portion 23. The second connection transistor 24 is driven according to the connection signal FCG to turn on / off the connection between the second FD portion 16 and the third FD portion 23.

[0064] The second line capacitor 25 is composed of a capacitor having a structure to be referred to later. Figure 8 The capacitor of the MIM structure provided between the wirings described above is constituted and arranged to connect the third FD portion 23 and the signal line MIMVDD2 . The second inter-line capacitor 25 accumulates electric charge together with the third FD portion 23 .

[0065] Figure 8 is a cross-sectional view showing a configuration example of the pixel 11A.

[0066] like Figure 8 As shown, the imaging element is constituted by bonding the wiring layer 34A of the sensor substrate 31A and the wiring layer 35 of the logic substrate 32. The semiconductor layer 33A of the sensor substrate 31A includes the photoelectric conversion unit 12, the first FD portion 14, the second FD portion 16, and the third FD portion 23. In addition, on the front surface of the semiconductor layer 33, the transfer transistor 13 is provided between the photoelectric conversion unit 12 and the first FD portion 14, the connection transistor 15 is provided between the first FD portion and the second FD portion 16, and the second connection transistor 24 is provided between the second FD portion 16 and the third FD portion 23.

[0067] The pixel 11A is configured such that the inter-line capacitor 17A and the second inter-line capacitor 25 are arranged between the wiring provided in the wiring layer 34A and the wiring layer 35 .

[0068] exist Figure 8 In the construction example shown, Figure 3 Like the inter-line capacitor 17 in FIG. 1 , the inter-line capacitor 17A is provided in the wiring layer 34A, the inter-line capacitor is composed of a lower electrode 41A and an upper electrode 42A and a dielectric film 43A sandwiched therebetween, and an upper wiring 44A connected to the upper electrode 42A is provided in the wiring layer 34A. The lower electrode 41A of the inter-line capacitor 17A is connected to the second FD portion 16 via the wiring and the electrode in the wiring layer 34A, and when the connection transistor 15 is turned on, electric charge is accumulated in the inter-line capacitor 17A and the second FD portion 16.

[0069] The second inter-line capacitor 25 is composed of a lower electrode 61 and an upper electrode 62 and a dielectric film 63 sandwiched therebetween, and an upper wiring 64 connected to the upper electrode 62 is provided in the wiring layer 34A. The lower electrode 61 of the second inter-line capacitor 25 is connected to the third FD portion 23 via the wiring and the electrode in the wiring layer 34A, and the charge photoelectrically converted in the second photoelectric conversion unit 22 is accumulated in the second inter-line capacitor 25 and the third FD portion 23.

[0070] The pixel 11A may be configured such that the inter-line capacitor 17A and the second inter-line capacitor 25 are disposed between the same pair of wirings, or may be configured such that each of them is disposed between different pairs of wirings. In the example shown, the second inter-line capacitor 25 is disposed closer to the logic substrate 32 than the inter-line capacitor 17A, and this arrangement constitutes a configuration in which the inter-line capacitor 17A and the second inter-line capacitor 25 are covered by the upper wiring 64.

[0071] In other words, pixel 11A is constructed so that when viewed in a plan view from logic substrate 32, upper wiring 64 is arranged to cover inter-line capacitor 17A and second inter-line capacitor 25, for example, upper wiring 24 is arranged to cover at least the entire upper electrode 42A and the entire upper electrode 62.

[0072] In the pixel 11A, even if the upper electrode 42A of the inter-line capacitor 17A is not completely covered by the upper wiring 44A, it is sufficient that the upper electrode 42A constituting the inter-line capacitor 17A is completely covered by the upper wiring 64. This prevents the FD node of the inter-line capacitor 17A from being affected by the band noise, for example, thereby enabling the degree of freedom of wiring to be improved.

[0073] Will refer to Fig. 9 The structure of the upper wiring 64 will be described. Fig. 9 11A- 1 to 11A- 3 are diagrams showing a schematic configuration example of three pixels 11A- 1 to 11A- 3 arranged in the same row when viewed in a plan view viewed from the logic substrate 32 .

[0074] like Fig. 9As shown, the upper wiring 64 is arranged along the pixels 11A-1 to 11A-3 arranged in the same row. In the pixels 11A-1 to 11A-3, the lower electrodes 41A-1 to 41A-3 are formed to have a larger area than the upper electrodes 42A-1 to 42A-3, respectively, and the lower electrodes 61-1 to 61-3 are formed to have a larger area than the upper electrodes 62-1 to 62-3, respectively. Therefore, when observed in a plan view observed from the logic substrate 32, the peripheries of the lower electrodes 41-1 to 41-3 are exposed to the outside from the upper electrodes 42-1 to 42-3, respectively, and the peripheries of the lower electrodes 61-1 to 61-3 are exposed to the outside from the upper circuits 62-1 to 62-3, respectively.

[0075] The pixels 11A-1 to 11A-3 have a configuration such that the upper electrodes 42A-1 to 42A-3 and the upper electrodes 62-1 to 62-3 are completely covered by the upper wiring 64 and are not visible when viewed in a plan view viewed from the logic substrate 32. On the other hand, the pixels 11A-1 to 11A-3 have a configuration such that the lower portions of the lower electrodes 41A-1 to 41A-3 and the upper portions of the lower electrodes 61-1 to 61-3 are partially exposed from the upper wiring 64. Alternatively, all of the lower electrodes 41A-1 to 41A-3 and the upper electrodes 42A-1 to 42A-3 and all of the lower electrodes 61-1 to 61-3 and the upper electrodes 62-1 to 62-3 may be configured to be completely covered by the upper wiring 64.

[0076] The pixel 11A is constructed as described above, and Figures 1 to 4 As with the pixel 11, by suppressing the influence of the band noise from the logic substrate 32, it is possible to achieve improved image quality of the imaging element.

[0077] <Third Configuration Example of Pixel> Will refer to Fig.10 and Fig.11 A third embodiment of a pixel included in an image pickup element to which the present technology is applied is described. Fig.10 and Fig.11 In the pixel 11B shown, Figures 1 to 4 The same components of the pixel 11 are denoted by the same reference numerals, and a detailed description thereof will be omitted.

[0078] Fig.10 A circuit diagram of a pixel 11B is shown.

[0079] like Fig.10 As shown, Figure 1Like the pixel 11 of FIG. 1 , the pixel 11B is configured to include a photoelectric conversion unit 12, a transfer transistor 13, a first FD portion 14, a connection transistor 15, a second FD portion 16, an inter-line capacitor 17, a reset transistor 18, an amplifier transistor 19, and a selection transistor 20. In addition, the pixel 11B is configured to include an overflow transistor 26, a third connection transistor 27, and a fourth FD portion 28. For example, the pixel 11B is an OFG (overflow gate) type LOFIC pixel.

[0080] The overflow transistor 26 is arranged to connect the photoelectric conversion unit 12 and the fourth FD portion 28, and when the photoelectric conversion unit 12 is irradiated with light having an intensity sufficient to exceed its saturation capacity, the overflow transistor 26 causes the charge overflowing from the photoelectric conversion unit 12 to overflow into the fourth FD portion 28. In addition, the overflow transistor 26 is driven according to the transfer signal OFG, and transfers the charge photoelectrically converted by the photoelectric conversion unit 12 to the fourth FD portion 28.

[0081] The third connection transistor 27 is arranged to connect the second FD portion 16 and the fourth FD portion 28. Further, the third connection transistor 27 is driven according to the connection signal FCG to turn on / off the connection between the second FD portion 16 and the fourth FD portion 28.

[0082] The fourth FD portion 28 accumulates the charge overflowing from the photoelectric conversion unit 12 via the overflow transistor 26 to convert the charge into a pixel signal. In addition, the line capacitor 17 is connected to the fourth FD portion 28, and the charge is accumulated in the line capacitor 17 and the fourth FD portion 28. When the third connection transistor 27 is turned on, the fourth FD portion 28 is also connected to the second FD portion 16, and the charge is read out together with the second FD portion 16.

[0083] As described above, the pixel 11B has a structure in which, when the photoelectric conversion unit 12 is irradiated with light sufficient to exceed the saturation capacity of the photoelectric conversion unit 12 , charges overflowing from the photoelectric conversion unit 12 overflow via the overflow transistor 26 and are accumulated in the fourth FD portion 28 and the inter-line capacitor 17 .

[0084] Fig.11 is a cross-sectional view showing a configuration example of a pixel 11B.

[0085] like Fig.11As shown, the imaging element is constituted by bonding the wiring layer 34B of the sensor substrate 31B and the wiring layer 35 of the logic substrate 32. The semiconductor layer 33B of the sensor substrate 31B includes the photoelectric conversion unit 12, the first FD unit 14, the second FD unit 16, and the fourth FD unit 28. In addition, on the front surface of the semiconductor layer 33, the transfer transistor 13 is provided between the photoelectric conversion unit 12 and the first FD unit 14, the connection transistor 15 is provided adjacent to the first FD unit 14, the overflow transistor 26 is provided between the photoelectric conversion unit 12 and the fourth FD unit 28, and the third connection transistor 27 is provided between the fourth FD unit 28 and the second FD unit 16.

[0086] The pixel 11B is configured such that the inter-line capacitor 17 is arranged between the wiring provided in the wiring layer 34B and the wiring layer 35, and the lower electrode 41 of the inter-line capacitor 17 is connected to the fourth FD portion 28. Figure 3 The inter-line capacitor 17 and the upper wiring 44 of the pixel 11B are constructed in the same manner as the pixel 11 of FIG. 1 , and the upper wiring 44 is arranged to cover the inter-line capacitor 17 when viewed in a plan view from the logic substrate 32 , for example, the upper wiring 44 is arranged to cover at least the entire upper electrode 42 .

[0087] The pixel 11B is constructed as described above, and Figures 1 to 4 As with the pixel 11, by suppressing the influence of the band noise from the logic substrate 32, it is possible to achieve improved image quality of the imaging element.

[0088] <Configuration Example of Inter-Line Capacitor Having a Three-Dimensional Structure> Will refer to Fig.12 The line capacitor 17C having a three-dimensional structure is described.

[0089] As described above, for example, the inter-line capacitor 17 provided in the pixel 11 has a two-dimensional structure in which the dielectric film 43 is sandwiched between the lower electrode 41 and the upper electrode 42 formed in a plane. Instead of the inter-line capacitor 17 having such a planar structure, the pixel 11 of the above-described embodiment including the modified example may adopt an inter-line capacitor 17C having a three-dimensional structure.

[0090] like Fig.12As shown, for the line capacitor 17C having a three-dimensional structure, for example, a plurality of cylindrical openings are formed in the interlayer film so as to open to reach the wiring 46, and the lower electrode 41C is formed into a three-dimensional shape extending into the inside of the plurality of openings and connected to the lower wiring 46. Next, the dielectric film 43C is formed to be stacked on the lower electrode 41C, and the upper electrode 42C is formed into a three-dimensional shape so as to sandwich the dielectric film 43C between the upper electrode 42C and the lower electrode 41C, and then the upper electrode 42C is connected to the upper wiring 44 via the through electrode 45. As described above, the line capacitor 17C having a three-dimensional structure is three-dimensionally constructed in the plurality of openings formed in the interlayer film, and the dielectric film 43C is sandwiched between the lower electrode 41C and the upper electrode 42C along the cylindrical shape of the opening.

[0091] For example, by adopting the inter-line capacitor 17C having a three-dimensional structure, the sandwiched area of ​​the dielectric film 43C can be increased, and the charge capacity to be accumulated can be increased. In an image pickup element including such a pixel 11, a wider dynamic range can be expected.

[0092] <Configuration Example of Electronic Equipment> An image pickup element including the above-described pixel 11 can be applied to various electronic devices including an image pickup system such as a digital camera and a digital video camera, a cellular phone having an image pickup function, or any other device having an image pickup function.

[0093] Fig.13 is a block diagram of an exemplary configuration of an imaging device installed in an electronic device.

[0094] like Fig. 9 As shown, the imaging device 101 includes an optical system 102, an imaging element 103, a signal processing circuit 104, a monitor 105, and a memory 106, and is capable of capturing still and moving images.

[0095] The optical system 102 is configured to include one or more lenses, guide light (incident light) from a subject to the imaging element 103 , and form an image on a light receiving surface of the imaging element 103 .

[0096] As the imaging element 103, an imaging element including the above-mentioned pixel 11 is used. In the imaging element 103, electrons are accumulated for a certain period of time according to an image formed on a light receiving surface via the optical system 102. Then, a signal corresponding to the electrons accumulated in the imaging element 103 is supplied to the signal processing circuit 104.

[0097] The signal processing circuit 104 performs various types of signal processing on the pixel signal output from the imaging element 103. An image (image data) obtained by the signal processing performed by the signal processing circuit 104 is supplied to the monitor 105 for display or to the memory 106 for storage (recording).

[0098] By applying an image pickup element including the above-described pixels 11 to the image pickup device 101 configured in this way, for example, higher image quality can be achieved.

[0099] <Examples of using image sensors> Fig.14 This is a diagram showing a usage example of how to use the above-mentioned image sensor (imaging element).

[0100] For example, as will be described, the above-described image sensors may be used to sense various conditions of light such as visible light, infrared light, ultraviolet light, and X-rays.

[0101] - Devices that capture images for viewing, such as digital cameras and mobile devices with camera functions. -Devices for transportation, such as on-board sensors that capture images of the front, rear, surroundings, and interior of the vehicle for safe driving purposes such as automatic parking and driver status recognition; surveillance cameras that monitor moving vehicles and roads; ranging sensors that measure the distance between vehicles, etc. - Devices for home appliances (such as TVs, refrigerators, and air conditioners, etc.) to capture images of user gestures and perform device operations according to the gestures. - Devices used in medicine and health care, such as endoscopes and devices that perform angiography by receiving infrared light, etc. -Devices for security, such as surveillance cameras for crime prevention and cameras for personal authentication, etc. - Devices for beauty care, such as skin measurement devices that take images of the skin and microscopes that take images of the scalp. -Devices for sports, such as sports cameras and wearable cameras for sports applications. -Devices for use in agriculture, such as cameras for monitoring the condition of fields and crops.

[0102] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology according to the present disclosure can be implemented as a device installed on any type of mobile body such as a car, an electric car, a hybrid car, a motorcycle, a bicycle, a personal mobile device, an airplane, a drone, a ship, and a robot.

[0103] Fig.15 : is a block diagram showing a schematic configuration example of a vehicle control system as an example of a mobile body control system to which the technology according to the present disclosure can be applied.

[0104] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.15In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. As the functional configuration of the integrated control unit 12050, a microcomputer 12051, a sound and image output unit 12052, and an in-vehicle network I / F (interface) 12053 are shown.

[0105] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 serves as a control device for the following devices: a drive force generating device such as an internal combustion engine or a drive motor for generating a vehicle drive force, a drive force transmitting mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, and a braking device for generating a vehicle braking force.

[0106] The body system control unit 12020 controls the operation of various devices installed in the body according to various programs. For example, the body system control unit 12020 is used as a control device for a keyless entry system, a smart key system, a power window device, or various lights such as a headlight, a reverse light, a brake light, a turn signal light, and a fog light. In this case, a radio wave transmitted from a portable device that replaces the key or a signal of various switches may be input to the body system control unit 12020. The body system control unit 12020 receives the input of the radio wave or the signal, and controls the door lock device, the power window device, and the lights of the vehicle.

[0107] The vehicle exterior information detection unit 12030 detects information about the exterior of the vehicle equipped with the vehicle control system 12000. For example, the camera unit 12031 is connected to the vehicle exterior information detection unit 12030. The vehicle exterior information detection unit 12030 causes the camera unit 12031 to capture an image of the exterior of the vehicle and receives the captured image. Based on the received image, the vehicle exterior information detection unit 12030 can perform object detection processing or distance detection processing for a person, a vehicle, an obstacle, a sign, and characters on the road surface.

[0108] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal according to the amount of light received. The imaging unit 12031 can also output the electrical signal as an image or as distance measurement information. In addition, the light received by the imaging unit 12031 can be visible light or invisible light such as infrared light.

[0109] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. For example, a driver state detection unit 12041 that detects the driver's state is connected to the in-vehicle information detection unit 12040. The driver state detection unit 12041 includes, for example, a camera that photographs the driver, and the in-vehicle information detection unit 12040 can calculate the driver's fatigue or concentration based on the detection information input from the driver state detection unit 12041, or can determine whether the driver is dozing off.

[0110] The microcomputer 12051 may calculate a control target value of a driving force generating device, a steering mechanism, or a braking device based on information about the exterior or interior of the vehicle acquired by the exterior information detecting unit 12030 or the interior information detecting unit 12040, and the microcomputer 12051 may output a control command to the driving system control unit 12010. For example, the microcomputer 12051 may perform cooperative control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including collision avoidance, impact mitigation, follow-up driving based on vehicle-to-vehicle distance, speed-maintaining driving, vehicle collision warning, and vehicle lane departure warning.

[0111] In addition, by controlling the driving force generating device, steering mechanism or braking device, etc. based on the information about the vehicle surroundings obtained by the external information detection unit 12030 or the internal information detection unit 12040, the microcomputer 12051 is able to perform collaborative control such as automatic driving aimed at performing automatic driving without relying on the driver's operation.

[0112] In addition, based on the information outside the vehicle acquired by the vehicle exterior information detection unit 12030, the microcomputer 12051 can output a control command to the body system control unit 12030. For example, the microcomputer 12051 can perform cooperative control aimed at preventing glare, such as by controlling the headlights to change from high beam to low beam, according to the position of the preceding vehicle or the oncoming vehicle detected by the vehicle exterior information detection unit 12030.

[0113] The sound and image output unit 12052 transmits an output signal of at least one of sound and image to an output device capable of visually or auditorily notifying the passenger of the vehicle or the outside of the vehicle of information. Fig.15 In the example of , as output devices, an audio speaker 12061, a display unit 12062, and a dashboard 12063 are shown. For example, the display unit 12062 may include at least one of an in-vehicle display and a head-up display.

[0114] Fig.16 12031 is a diagram showing an example of the installation position of the imaging unit 12031.

[0115] exist Fig.16 In the figure, the camera unit 12031 includes camera units 12101, 12102, 12103, 12104 and 12105.

[0116] Camera units 12101, 12102, 12103, 12104 and 12105 are arranged at the front nose, rearview mirror, rear bumper, rear door, upper part of the front windshield inside the vehicle 12100, etc. The camera unit 12101 arranged at the front nose and the camera unit 12105 arranged at the upper part of the front windshield inside the vehicle mainly obtain images in front of the vehicle 12100. The camera units 12102 and 12103 arranged at the rearview mirror mainly obtain images on both sides of the vehicle 12100. The camera unit 12104 arranged at the rear bumper or rear door mainly obtains rear-view images of the vehicle 12100. The camera unit 12105 arranged at the upper part of the front windshield inside the vehicle is mainly used to detect vehicles in front, pedestrians, obstacles, traffic lights, traffic signs and lanes, etc.

[0117] Fig.16 An example of the imaging ranges of the imaging units 12101 to 12104 is shown. The imaging range 12111 indicates the imaging range of the imaging unit 12101 provided at the front nose, the imaging ranges 12112 and 12113 respectively indicate the imaging ranges of the imaging units 12102 and 12103 provided at the rearview mirrors, and the imaging range 12114 indicates the imaging range of the imaging unit 12104 provided at the rear bumper or the rear door. For example, by superimposing the image data captured by the imaging units 12101 to 12104, a bird's-eye view image observed from above the vehicle 12100 can be obtained.

[0118] At least one of the imaging units 12101 to 12104 may have a function for obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0119] For example, based on the distance information obtained from the camera units 12101 to 12104, the microcomputer 12051 can extract, in particular, the nearest three-dimensional object on the driving path of the vehicle 12100 (which is a three-dimensional object traveling at a predetermined speed (e.g., 0 km / h or higher) in the same direction as the vehicle 12100) as the leading vehicle by obtaining the distance to each three-dimensional object and the time change of the distance (relative speed relative to the vehicle 12100) in the camera ranges 12111 to 12114. The microcomputer 12051 can also set the distance to be ensured from the leading vehicle and perform automatic braking control (including follow-up stop control) and automatic acceleration control (including follow-up start control). Therefore, cooperative control of automatic driving aimed at, for example, autonomous driving without driver operation can be performed.

[0120] For example, based on the distance information obtained from the camera units 12101 to 12104, the microcomputer 12501 can classify and extract the three-dimensional object data about the three-dimensional object into other three-dimensional objects such as two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, and utility poles, and can use the other three-dimensional objects to perform automatic avoidance of obstacles. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be observed by the driver of the vehicle 12100 and obstacles that are difficult to observe. Then, the microcomputer 12051 determines the collision risk indicating the risk of collision with each obstacle, and when the collision risk is equal to or higher than the set value and there is a possibility of collision, a warning is output to the driver via the audio speaker 12061 or the display unit 12062, and forced deceleration or evasive steering is performed by the drive system control unit 12010, and thus driving support for avoiding collision can be performed.

[0121] At least one of the camera units 12101 to 12104 may be an infrared camera that detects infrared light. For example, the microcomputer 12051 may identify a pedestrian by determining whether there is a pedestrian in the camera images of the camera units 12101 to 12104. This identification of pedestrians is performed by, for example, the following steps: a step for extracting feature points in the camera images of the camera units 12101 to 12104 as infrared cameras; and a step for performing pattern matching processing on a series of feature points representing the outline of an object to determine whether the object is a pedestrian. When the microcomputer 12051 determines that there is a pedestrian in the camera images of the camera units 12101 to 12104 and identifies the pedestrian, for emphasis, the sound and image output unit 12052 controls the display unit 12062 so that the identified pedestrian is superimposed and displayed with a square outline. In addition, the sound and image output unit 12052 may control the display unit 12062 so that an icon representing a pedestrian or the like is displayed at a desired position.

[0122] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the camera unit 12031 and the like in the above-mentioned configuration. By applying the technology according to the present disclosure to the camera unit 12031, an image with less noise can be obtained even in a dark environment.

[0123] <Example of structure combination> The present technology can also be configured as follows. (1) A solid-state imaging element, comprising, for each pixel: a photoelectric conversion unit that photoelectrically converts light into electric charges; a first FD (Floating Diffusion) portion that accumulates the charge transferred from the photoelectric conversion unit via the transfer transistor to convert the charge into a pixel signal; a second FD portion connected to the first FD portion via a connecting transistor; and an inter-line capacitor connected to the second FD portion to accumulate the charge, in, The inter-line capacitor is configured to include a first electrode connected to the second FD portion and a second electrode facing the first electrode via a dielectric, and The wiring connected to the second electrode is provided to cover at least the entire second electrode when viewed in a plan view viewed from a logic substrate stacked on a sensor substrate provided with the photoelectric conversion unit. (2) The solid-state imaging element according to (1), having a structure in which the charge overflowing from the photoelectric conversion unit is accumulated in the line capacitor when the photoelectric conversion unit is irradiated with light with an intensity sufficient to exceed the saturation capacity of the photoelectric conversion unit. (3) A solid-state imaging element according to (1) or (2), wherein the potential of the wiring connected to the second electrode of the line capacitor is controlled to a low level during a charge accumulation period in which the pixel is exposed for a long time and the charge is accumulated in the photoelectric conversion unit. (4) The solid-state imaging element according to any one of (1) to (3), wherein the inter-line capacitor and the wiring are arranged in a wiring layer on the sensor substrate side. (5) The solid-state imaging element according to any one of (1) to (3), wherein the inter-line capacitor and the wiring are arranged in a wiring layer on the logic substrate side. (6) The solid-state imaging element according to any one of (1) to (3), wherein the line capacitor is arranged in a wiring layer on the sensor substrate side, and the wiring is arranged in a wiring layer on the logic substrate side. (7) The solid-state imaging element according to any one of (1) to (6), wherein the pixel comprises: a second photoelectric conversion unit having a smaller light receiving area than said photoelectric conversion unit, and a third FD section that accumulates the charges photoelectrically converted by the second photoelectric conversion unit to convert the charges into a pixel signal, in The inter-line capacitor is connected to the third FD portion via a second connection transistor. (8) The solid-state imaging element according to (7), further including a second inter-line capacitor including a third electrode connected to the third FD portion and a fourth electrode facing the third electrode via a dielectric. (9) A solid-state imaging element according to (8), wherein, when observed in a plan view from the logic substrate, the line-to-line capacitor and the second line-to-line capacitor are covered by one of a wiring connected to the second electrode of the line-to-line capacitor and a wiring connected to the third electrode of the second line-to-line capacitor. (10) The solid-state imaging element according to any one of (1) to (6) further includes an overflow transistor, which causes the charge overflowing from the photoelectric conversion unit to overflow and accumulate in the line capacitor when the photoelectric conversion unit is irradiated with light with an intensity sufficient to exceed the saturation capacity of the photoelectric conversion unit. (11) The solid-state imaging element according to any one of (1) to (10), wherein the inter-line capacitor is configured as a three-dimensional structure. (12) An electronic device including a solid-state imaging element, the solid-state imaging element including, for each pixel: a photoelectric conversion unit that photoelectrically converts light into electric charges; a first FD (Floating Diffusion) portion that accumulates the charge transferred from the photoelectric conversion unit via the transfer transistor to convert the charge into a pixel signal; a second FD portion connected to the first FD portion via a connecting transistor; and an inter-line capacitor connected to the second FD portion to accumulate the charge, in, The inter-line capacitor is configured to include a first electrode connected to the second FD portion and a second electrode facing the first electrode via a dielectric, and The wiring connected to the second electrode is provided to cover at least the entire second electrode when viewed in a plan view viewed from a logic substrate stacked on a sensor substrate provided with the photoelectric conversion unit.

[0124] The embodiments of the present disclosure are not limited to the above-described embodiments, and may be modified in various ways without departing from the scope and spirit of the present disclosure. In addition, the effects described in this specification are merely examples and are not restrictive, and other effects may exist. Reference numerals list

[0125] 11 pixels 12 Photoelectric conversion unit 13 Pass transistor 14 1st FD Division 15. Connect the transistor 16 Second FD Section 17 Line capacitors 18 Reset transistor 19 Amplifier transistor 20 Select transistor 21 vertical signal line 22. Second photoelectric conversion unit 23 Third FD Section 24 Second connection transistor 25 Second inter-line capacitor 26 Overflow transistor 27 Third connection transistor 28 Fourth FD Division 31 Sensor substrate 32 Logic board 33 Semiconductor layer 34 Wiring layer 35 Wiring layer 36 Semiconductor layer 41 Lower electrode 42 Upper electrode 43 Dielectric film 44 Upper wiring 45 through electrode 46 Lower wiring 51Cu-Cu joint 61 Lower electrode 62 Upper electrode 63 Upper wiring 64 upper wiring.

Claims

1. A solid-state imaging element, comprising, for each pixel: a photoelectric conversion unit that photoelectrically converts light into electric charges; a first FD (Floating Diffusion) portion that accumulates charges transferred from the photoelectric conversion unit via a transfer transistor to convert the charges into a pixel signal; a second FD portion connected to the first FD portion via a connecting transistor; as well as an inter-line capacitor connected to the second FD portion to accumulate charge, in, The inter-line capacitor is configured to include a first electrode connected to the second FD portion and a second electrode facing the first electrode via a dielectric, and The wiring connected to the second electrode is provided to cover at least the entire second electrode when viewed in a plan view viewed from the side of a logic substrate stacked on the sensor substrate provided with the photoelectric conversion unit.

2. A solid-state imaging element according to claim 1, having a structure in which, when the photoelectric conversion unit is irradiated with light having an intensity sufficient to exceed the saturation capacity of the photoelectric conversion unit, charges overflowing from the photoelectric conversion unit are accumulated in the line capacitor.

3. The solid-state imaging element according to claim 1, wherein During a charge accumulation period in which the pixel is exposed for a long time and charges are accumulated in the photoelectric conversion unit, the potential of the wiring connected to the second electrode of the inter-line capacitor is controlled to a low level.

4. The solid-state imaging element according to claim 1, wherein The inter-line capacitor and the wiring are arranged in a wiring layer on the sensor substrate side.

5. The solid-state imaging element according to claim 1, wherein The inter-line capacitor and the wiring are arranged in a wiring layer on the logic substrate side.

6. The solid-state imaging element according to claim 1, wherein The inter-line capacitor is arranged in a wiring layer on the sensor substrate side, and the wiring is arranged in a wiring layer on the logic substrate side.

7. The solid-state imaging element according to claim 1, wherein The pixels include: a second photoelectric conversion unit having a smaller light receiving area than said photoelectric conversion unit; and a third FD section that accumulates the charges photoelectrically converted by the second photoelectric conversion unit to convert the charges into a pixel signal, in, The inter-line capacitor is connected to the third FD portion via a second connection transistor. 8 . The solid-state imaging element according to claim 7 , further comprising a second inter-line capacitor including a third electrode connected to the third FD portion and a fourth electrode facing the third electrode via a dielectric.

9. The solid-state imaging element according to claim 8, wherein: When viewed in a plan view viewed from the logic substrate side, the inter-line capacitor and the second inter-line capacitor are covered by one of a wiring connected to the second electrode of the inter-line capacitor and a wiring connected to the third electrode of the second inter-line capacitor.

10. The solid-state imaging element according to claim 1, further comprising an overflow transistor which causes charge overflowing from the photoelectric conversion unit to overflow and accumulate in the line capacitor when the photoelectric conversion unit is irradiated with light having an intensity sufficient to exceed a saturation capacity of the photoelectric conversion unit.

11. The solid-state imaging element according to claim 1, wherein The line capacitor is configured as a three-dimensional structure.

12. An electronic device including a solid-state imaging element, the solid-state imaging element including, for each pixel: a photoelectric conversion unit that photoelectrically converts light into electric charges; a first FD (Floating Diffusion) portion that accumulates charges transferred from the photoelectric conversion unit via a transfer transistor to convert the charges into a pixel signal; a second FD portion connected to the first FD portion via a connecting transistor; as well as an inter-line capacitor connected to the second FD portion to accumulate the charge, in, The inter-line capacitor is configured to include a first electrode connected to the second FD portion and a second electrode facing the first electrode via a dielectric, and The wiring connected to the second electrode is provided to cover at least the entire second electrode when viewed in a plan view viewed from the side of a logic substrate stacked on the sensor substrate provided with the photoelectric conversion unit.

Images