Light-emitting element, pixel comprising light-emitting element, and method for manufacturing light-emitting element

Abstract

The light-emitting element of the present invention may include: a first light-emitting element including a first semiconductor layer, an active layer, and a second semiconductor layer sequentially disposed in a first direction; a second light emitting element spaced apart from the first light emitting element and including a first semiconductor layer, an active layer, and a second semiconductor layer sequentially disposed in a direction opposite to the first direction; and an insulating film surrounding a portion of the first light emitting element and a portion of the second light emitting element.

Description

Technical Field

[0001] The present disclosure generally relates to light emitting elements, pixels including light emitting elements, and methods of manufacturing light emitting elements. Background Art

[0002] Recently, as interest in information display increases, research and development of display devices continues. Summary of the invention

[0003] Technical issues

[0004] The embodiment provides a light emitting element that can be used as an effective light source in a pixel regardless of the design of the pixel.

[0005] The embodiment also provides a pixel including a light emitting element and a method for manufacturing the light emitting element.

[0006] However, the objects of the present invention are not limited to the above objects and can be expanded in various ways without departing from the scope of the present invention.

[0007] Technical Solution

[0008] According to aspects of the present disclosure, a light-emitting element is provided, comprising: a first light-emitting element comprising a first semiconductor layer, an active layer, and a second semiconductor layer sequentially arranged in a first direction; a second light-emitting element spaced apart from the first light-emitting element and comprising the first semiconductor layer, the active layer, and the second semiconductor layer sequentially arranged in a direction opposite to the first direction; and an insulating film surrounding a portion of the first light-emitting element and a portion of the second light-emitting element.

[0009] The insulating film may surround at least a portion of an outer peripheral surface of the first light emitting element and at least a portion of an outer peripheral surface of the second light emitting element and fill a space between the first light emitting element and the second light emitting element.

[0010] The insulating film may include: a first insulating film surrounding at least a portion of an outer peripheral surface of the first light emitting element; and a second insulating film surrounding at least a portion of an outer peripheral surface of the second light emitting element and filling a space between the first light emitting element and the second light emitting element.

[0011] The first insulating film and the second insulating film may include the same material.

[0012] The light emitting element may further include an electrode layer disposed on the second semiconductor layer of the first light emitting element and the second semiconductor layer of the second light emitting element.

[0013] Each of the first and second light emitting elements may include a first end and a second end. The electrode layer may be disposed at the first end of each of the first and second light emitting elements, and the first semiconductor layer may be disposed at the second end of each of the first and second light emitting elements.

[0014] The insulating film may expose each of the first end portion and the second end portion of each of the first light emitting element and the second light emitting element.

[0015] The first end of the first light emitting element and the second end of the second light emitting element may be disposed on the same plane.

[0016] The second light emitting element may be disposed while being spaced apart from the first light emitting element in a second direction intersecting the first direction.

[0017] The shape of the first light emitting element may be the same as the shape of the second light emitting element.

[0018] Each of the first semiconductor layers may include GaN doped with an n-type dopant, and each of the second semiconductor layers may include GaN doped with a p-type dopant.

[0019] According to another aspect of the present disclosure, a method for manufacturing a light-emitting element is provided, the method comprising: forming an undoped semiconductor layer on a stacked substrate including a first region and a second region; sequentially forming a first semiconductor layer, an active layer, a second semiconductor layer and an electrode layer on the undoped semiconductor layer; forming a first stacked structure in the first region by removing portions of the first semiconductor layer, the active layer, the second semiconductor layer and the electrode layer corresponding to the second region; forming a first insulating film covering the first stacked structure including the first semiconductor layer, the active layer, the second semiconductor layer and the electrode layer; sequentially forming an electrode layer, a second semiconductor layer, an active layer and the first semiconductor layer in the first region and the second region; forming a second stacked structure by removing portions of each of the first semiconductor layer, the active layer, the second semiconductor layer and the electrode layer in the second region and on the first stacked structure; and forming a second insulating film surrounding at least a portion of a side surface of the second stacked structure.

[0020] The step of forming the second insulating film may include: forming the second insulating film on the entire regions of the first region and the second region; and removing the second insulating film disposed on top surfaces of the first stack structure and the second stack structure.

[0021] The step of forming the first insulating film may include: forming the first insulating film over the entire regions of the first region and the second region; and removing the first insulating film from the second region.

[0022] The second semiconductor layer of the first stacked structure may be disposed at the same layer as the first semiconductor layer of the second stacked structure.

[0023] The step of forming the second stack structure may include removing a first insulating film formed on the electrode layer of the first stack structure.

[0024] The method may further include forming a light emitting stack pattern by separating the first stack structure, the second stack structure, the first insulating film, and the second insulating film from the stack substrate and the undoped semiconductor layer.

[0025] The step of forming the second stack structure includes: forming two second stack structures in the second region.

[0026] According to another aspect of the present disclosure, a pixel is provided, comprising: a first pixel electrode and a second pixel electrode, both disposed on a substrate; a light-emitting element disposed on the first pixel electrode and the second pixel electrode; a first contact electrode electrically connecting the first pixel electrode and the light-emitting element to each other; and a second contact electrode electrically connecting the second pixel electrode and the light-emitting element to each other, wherein each of the light-emitting elements comprises: a first light-emitting element arranged in a first direction; a second light-emitting element arranged in a second direction which is an opposite direction to the first direction; and an insulating film combining the first light-emitting element and the second light-emitting element.

[0027] The first light emitting element may include a first semiconductor layer, an active layer, a second semiconductor layer, and an electrode layer sequentially disposed in a first direction. The second light emitting element may include a first semiconductor layer, an active layer, a second semiconductor layer, and an electrode layer sequentially disposed in a second direction.

[0028] Each of the first and second light emitting elements may include a first end and a second end. The electrode layer may be disposed at the first end of each of the first and second light emitting elements, and the first semiconductor layer may be disposed at the second end of each of the first and second light emitting elements.

[0029] The first end of the first light emitting element and the second end of the second light emitting element may be in electrical contact with the first contact electrode, and the second end of the first light emitting element and the first end of the second light emitting element may be in electrical contact with the second contact electrode.

[0030] Beneficial Effects

[0031] In the light-emitting element and the pixel including the light-emitting element according to the present disclosure, one of the first light-emitting element arranged in the first direction and the second light-emitting element arranged in the opposite direction of the first direction included in the light-emitting element can be provided as an effective light source. Therefore, the effective light sources in the pixel whose number is equal to or greater than the predetermined reference value can be fully ensured. In addition, the effective light sources of the pixel can be uniformly ensured.

[0032] However, the effects of the present invention are not limited to the above-described effects and can be extended in various ways without departing from the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The embodiments will be described more fully with reference to the accompanying drawings. However, the embodiments may be implemented in various different forms and may not be limited thereto. The present disclosure is explained more accurately and completely through examples, and the present disclosure may be provided to fully convey the ideas of the embodiments to those skilled in the art.

[0034] For clarity of illustration, the dimensions in the drawings may be exaggerated. When an element is referred to as being between two elements, it is understood that the element may be the only element between the two elements, or one or more intermediate elements may also be present. The same reference numerals always represent the same elements.

[0035] Figure 1 is a perspective view showing a light emitting element according to an embodiment of the present disclosure.

[0036] Figure 2 It is shown Figure 1 Schematic cross-sectional view of an example of a light emitting element shown in .

[0037] Figure 3 is a schematic plan view showing a display device according to an embodiment of the present disclosure.

[0038] Figure 4 It is shown Figure 3 A circuit diagram of an example of a pixel included in a display device shown in FIG.

[0039] Figure 5 It is shown Figure 3 A schematic plan view of an example of a pixel included in a display device shown in FIG.

[0040] Figure 6 It is shown along Figure 5 A schematic cross-sectional view of the example taken along line II' shown in FIG.

[0041] Figures 7 to 21 is a schematic cross-sectional view illustrating a method for manufacturing a light emitting element according to an embodiment of the present disclosure.

[0042] Figure 22 to Figure 26is a schematic cross-sectional view illustrating a method of manufacturing a display device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0043] Hereinafter, exemplary embodiments of the present disclosure will be described in more detail with reference to the accompanying drawings. Throughout the accompanying drawings, the same reference numerals are given to the same elements, and their repeated description will be omitted.

[0044] When an element or layer is referred to as being "on", "connected to" or "bonded to" another element or layer, the element or layer may be directly connected or bonded to the other element or layer. There may be elements or layers or intervening elements or layers. However, when an element or layer is referred to as being "directly connected", "directly bonded" to another element or layer, there are no intervening elements or layers. For this purpose, the term "connected" may mean a physical, electrical and / or fluid connection with or without intermediate elements. In addition, when an element is referred to as being "in contact with" another element, the element is "electrically in contact with" or "physically in contact with" the other element, or is "indirectly in contact with" or "directly in contact with" the other element.

[0045] In the present specification and claims, the expression "at least one of..." is intended to include "at least one selected from..." in terms of meaning and interpretation. For example, "at least one of A and B" can be understood to mean "A, B, or A and B".

[0046] For purposes of meaning and interpretation, the term "and / or" in the specification and claims is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood as "A, B, or A and B". The terms "and" and "or" may be used in either a conjunctive or disjunctive sense and may be understood to be equivalent to "and / or".

[0047] Spatially relative terms such as "downward," "below," "into," "below," "upward," "above," "beyond," "high," and "side" (e.g., "sidewall") may be used in this specification for explanatory purposes and, therefore, may be used to describe the relationship between one element and other elements as shown in the accompanying drawings. In addition to the orientations depicted in the accompanying drawings, the spatially relative terms are intended to also include different orientations of the device in use, operation, and / or manufacture. For example, if the device in the accompanying drawings is turned over, an element described as "below" or "at the bottom" of other elements or features would be oriented as "above" the other elements or features. Thus, for example, the term "downward" may include both upward and downward directions. Additionally, the device may be oriented in other orientations (e.g., rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein interpreted accordingly.

[0048] As used herein, the term "about" or "approximately" includes both the stated value, the measurement being discussed, and the error associated with the measurement of the particular quantity (e.g., limitations of the measurement system). For example, "about" can mean within one or more standard deviations or within ±30%, ±20%, ±10%, or ±5% of a specified value.

[0049] Unless otherwise defined or implied herein, all terms (including technical and scientific terms) used have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. Terms defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal meaning unless clearly defined in the specification.

[0050] Figure 1 is a perspective view showing a light emitting element according to an embodiment of the present disclosure. Figure 2 It is shown Figure 1 Schematic cross-sectional view of an example of a light emitting element shown in .

[0051] Reference Figure 1 and Figure 2 , the light emitting element LD may include a first light emitting element LDf and a second light emitting element LDr. In an example, the light emitting element LD may include a first light emitting element LDf and a second light emitting element LDr extending in the first direction DR1. In an example, the second light emitting element LDr may be disposed to be spaced apart from the first light emitting element LDf in the second direction DR2. In an example, the light emitting element LD may be a unit in which the first light emitting element LDf and the second light emitting element LDr are integrally formed.

[0052] In an embodiment, the first light emitting element LDf may include a first semiconductor layer SEC1, a second semiconductor layer SEC2, an active layer AL and an electrode layer EL. The second light emitting element LDr may include a first semiconductor layer SEC1_r, a second semiconductor layer SEC2_r, an active layer AL_r and an electrode layer EL_r.

[0053] In an embodiment, the first light emitting element LDf may be implemented as a light emitting stack structure (or stack pattern) in which the first semiconductor layer SEC1, the active layer AL, the second semiconductor layer SEC2, and the electrode layer EL are sequentially stacked in the first direction DR1. The second light emitting element LDr may be implemented as a light emitting stack structure (or stack pattern) in which the first semiconductor layer SEC1_r, the active layer AL_r, the second semiconductor layer SEC2_r, and the electrode layer EL_r are sequentially stacked in a direction opposite to the first direction DR1.

[0054] In another example, the electrode layer EL or EL_r may be omitted. In the first light emitting element LDf, the first semiconductor layer SEC1, the active layer AL, and the second semiconductor layer SEC2 may be sequentially stacked in the first direction DR1. In the second light emitting element LDr, the first semiconductor layer SEC1_r, the active layer AL_r, and the second semiconductor layer SEC2_r may be sequentially stacked in the reverse direction of the first direction DR1.

[0055] In the embodiment, since the first semiconductor layer SEC1, the active layer AL, and the second semiconductor layer SEC2 are sequentially disposed along the first direction DR1, the first light emitting element LDf of the light emitting element LD may be designated as a forward light emitting element. Since the first semiconductor layer SEC1_r, the active layer AL_r, and the second semiconductor layer SEC2_r are sequentially disposed along the opposite direction (or reverse direction) of the first direction DR1, the second light emitting element LDr of the light emitting element LD may be designated as a reverse light emitting element.

[0056] In an embodiment, the first light emitting element LDf and the second light emitting element LDr may be symmetrical to each other in the second direction DR2. For example, the first light emitting element LDf may have an inverted mirror image of the second light emitting element LDr. The first semiconductor layer SEC1, the active layer AL, the second semiconductor layer SEC2, and the electrode layer EL included in the first light emitting element LDf may be symmetrical with the first semiconductor layer SEC1_r, the active layer AL_r, the second semiconductor layer SEC2_r, and the electrode layer EL_r included in the second light emitting element LDr in the second direction DR2.

[0057] In an embodiment, the electrode layer EL of the first light emitting element LDf and the electrode layer EL_r of the second light emitting element LDr may be disposed in opposite directions to each other. In an example, the first semiconductor layer SEC1 of the first light emitting element LDf and the first semiconductor layer SEC1_r of the second light emitting element LDr may be disposed in opposite directions to each other.

[0058] In the embodiment, the first light emitting element LDf and the second light emitting element LDr may be provided in a shape extending in the first direction DR1. When it is assumed that the extending direction of the first light emitting element LDf is the length direction, the first light emitting element LDf may include a first end EP1 and a second end EP2. The second light emitting element LDr may include a first end EP1 and a second end EP2.

[0059] In an embodiment, the electrode layer EL or EL_r may be located at the first end EP1 of each of the first and second light emitting elements LDf and LDr, and the first semiconductor layer SEC1 or SEC1_r may be located at the second end EP2 of each of the first and second light emitting elements LDf and LDr.

[0060] In an embodiment, the first end portion EP1 of the first light emitting element LDf may be disposed on the same layer as the second end portion EP2 of the second light emitting element LDr. The second end portion EP2 of the first light emitting element LDf may be disposed on the same layer as the first end portion EP1 of the second light emitting element LDr.

[0061] In an embodiment, the electrode layer EL or EL_r may be exposed through the first end EP1 of each of the first light emitting element LDf and the second light emitting element LDr. The first semiconductor layer SEC1 or SEC1_r may be exposed through the second end EP2 of each of the first light emitting element LDf and the second light emitting element LDr. In an example, the electrode layer EL of the first light emitting element LDf may be disposed at the same layer as the first semiconductor layer SEC1_r of the second light emitting element LDr. The first semiconductor layer SEC1 of the first light emitting element LDf may be disposed at the same layer as the electrode layer EL_r of the second light emitting element LDr.

[0062] In the embodiment, the first semiconductor layer SEC1 of the first light emitting element LDf may be disposed on the same layer (plane) as the second semiconductor layer SEC2_r of the second light emitting element LDr. The second semiconductor layer SEC2 of the first light emitting element LDf may be disposed on the same layer (plane) as the first semiconductor layer SEC1_r of the second light emitting element LDr.

[0063] In an embodiment, the first light emitting element LDf and the second light emitting element LDr may be provided in various shapes. In an example, each of the first light emitting element LDf and the second light emitting element LDr may have a rod-like shape, a strip-like shape, a column-like shape, etc. that is long in its length direction (i.e., its aspect ratio is greater than 1). In another example, each of the first light emitting element LDf and the second light emitting element LDr may have a rod-like shape, a strip-like shape, a column-like shape, etc. that is short in its length direction (i.e., its aspect ratio is less than 1). In yet another example, each of the first light emitting element LDf and the second light emitting element LDr may have a rod-like shape, a strip-like shape, a column-like shape, etc. with an aspect ratio of 1.

[0064] In embodiments, the first and second light emitting elements LDf and LDr may include, for example, light emitting diodes (LEDs) fabricated small enough to have a diameter D and / or a length L ranging from nanometer (or nanometer) to micrometer (micrometer).

[0065] In an embodiment, when each of the first light emitting element LDf and the second light emitting element LDr is long in its length direction (i.e., its aspect ratio is greater than 1), the diameter D of each of the first light emitting element LDf and the second light emitting element LDr may be about 0.5 μm to about 6 μm, and the length L of each of the first light emitting element LDf and the second light emitting element LDr may be about 1 μm to about 10 μm. The aspect ratio of the light emitting element LD including the first light emitting element LDf and the second light emitting element LDr may become less than 1. However, the diameter D and the length L of each of the first light emitting element LDf and the second light emitting element LDr are not limited thereto, and the size of the light emitting element LD may be changed according to the required conditions (or design conditions) of the lighting device or the self-luminous display device to which the first light emitting element LDf and the second light emitting element LDr are applied.

[0066] In an embodiment, the first semiconductor layer SEC1 or SEC1_r may be a first conductive type semiconductor layer. The first semiconductor layer SEC1 or SEC1_r may include at least one n-type semiconductor layer. The first semiconductor layer SEC1 or SEC1_r may include at least one semiconductor material among InAlGaN, GaN, AlGaN, InGaN, AlN and InN. The first semiconductor layer SEC1 or SEC1_r may be an n-type semiconductor layer doped with a first conductive dopant (or n-type dopant) such as silicon (Si), germanium (Ge) or tin (Sn). The material constituting the first semiconductor layer SEC1 or SEC1_r is not limited thereto. In addition, the first semiconductor layer SEC1 or SEC1_r may include various materials.

[0067] In an embodiment, the first semiconductor layer SEC1 may include an upper surface and a lower surface, the active layer AL is disposed on the upper surface along the length direction of the first light emitting element LDf, and the lower surface is exposed to the outside in the opposite direction of the first direction DR1. The first semiconductor layer SEC1 may be one end (or bottom end) of the light emitting element LD.

[0068] In an embodiment, the first semiconductor layer SEC1_r may include a lower surface and an upper surface, the active layer AL_r is disposed on the lower surface in a direction opposite to the length direction of the second light emitting element LDr, and the upper surface is exposed to the outside in the first direction DR1. The first semiconductor layer SEC1_r may be one end portion (or top end portion) of the light emitting element LD.

[0069] In an embodiment, the active layer AL or AL_r may be respectively disposed between the first semiconductor layer SEC1 or SEC1_r and the second semiconductor layer SEC2 or SEC2_r. In an embodiment, the active layer AL of the first light emitting element LDf may be disposed between the first semiconductor layer SEC1 and the second semiconductor layer SEC2. The active layer AL_r of the second light emitting element LDr may be disposed between the first semiconductor layer SEC1_r and the second semiconductor layer SEC2_r. In an example, the active layer AL or AL_r is formed on the first semiconductor layer SEC1 or SEC1_r and may be formed in a single or multiple quantum well structures. In an example, when the active layer AL or AL_r is formed in a multiple quantum well structure, the barrier layer, the strain enhancement layer and the well layer constituting a unit may be periodically repeatedly stacked in the active layer AL or AL_r. The strain enhancement layer may have a lattice constant smaller than that of the barrier layer to reduce strain (e.g., compressive strain applied to the well layer). However, the structure of the active layer AL or AL_r is not limited to the above-described embodiments.

[0070] In an embodiment, the active layer AL or AL_r may emit light having a wavelength of about 400 nm to about 900 nm and use a double heterostructure. The active layer AL or AL_r may include a first surface contacting the first semiconductor layer SEC1 or SEC1_r and a second surface contacting the second semiconductor layer SEC2 or SEC2_r.

[0071] In an embodiment, the active layer AL of the first light emitting element LDf may include a lower surface in contact with the first semiconductor layer SEC1 and an upper surface in contact with the second semiconductor layer SEC2 .

[0072] In an embodiment, the active layer AL_r of the second light emitting element LDr may include an upper surface in contact with the first semiconductor layer SEC1_r and a lower surface in contact with the second semiconductor layer SEC2_r.

[0073] In an embodiment, light may be emitted from the active layer AL of the first light emitting element LDf and / or the active layer AL_r of the second light emitting element LDr. The color (or light output color) of the light emitting element LD may be determined according to the wavelength of light emitted from the active layer AL of the first light emitting element LDf and / or the active layer AL_r of the second light emitting element LDr. The color of the light emitting element LD may determine the color of the pixel corresponding thereto. For example, the light emitting element LD may emit red light, green light, or blue light through the active layer AL of the first light emitting element LDf and / or the active layer AL_r of the second light emitting element LDr.

[0074] In an embodiment, when an electric field having a predetermined (selectable) voltage or more is applied to both ends of each of the first light emitting element LDf and the second light emitting element LDr, electron-hole pairs may be combined in the active layer AL of the first light emitting element LDf and / or the active layer AL_r of the second light emitting element LDr, and the first light emitting element LDf and / or the second light emitting element LDr may emit light. The light emitting element LD including the first light emitting element LDf and the second light emitting element LDr may be used as a light source (or light emitting source) for various light emitting devices (including pixels of a display device).

[0075] In an embodiment, the second semiconductor layer SEC2 or SEC2_r may include a second conductive type semiconductor layer different from the first conductive type semiconductor layer of the first semiconductor layer SEC1 or SEC1_r. The second semiconductor layer SEC2 or SEC2_r may include at least one p-type semiconductor layer. The second semiconductor layer SEC2 or SEC2_r may include at least one semiconductor material among InAlGaN, GaN, AlGaN, InGaN, AlN and InN, and include a p-type semiconductor layer doped with a second conductive dopant (or p-type dopant) such as magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr) or barium (Ba). However, the material constituting the second semiconductor layer SEC2 or SEC2_r is not limited thereto. The second semiconductor layer SEC2 or SEC2_r may include various materials.

[0076] In an embodiment, the second semiconductor layer SEC2 may include a lower surface in contact with the second surface of the active layer AL along the length direction of the first light emitting element LDf and an upper surface in contact with the electrode layer EL.

[0077] In an embodiment, the second semiconductor layer SEC2_r may include an upper surface in contact with the second surface of the active layer AL_r in an opposite direction to the length direction of the first light emitting element LDf and a lower surface in contact with the electrode layer EL_r.

[0078] In an embodiment, the electrode layer EL or EL_r may include a metal or a conductive metal oxide. In an example, the electrode layer EL or EL_r may include at least one of chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni) and any oxide or alloy thereof, a transparent electrode material (such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO) or indium tin zinc oxide (ITZO)). The electrode layer EL or EL_r may be substantially transparent. Therefore, the light generated in the first light emitting element LDf and / or the second light emitting element LDr can be emitted to the outside of the first light emitting element LDf and / or the second light emitting element LDr by transmitting through the electrode layer EL or EL_r.

[0079] In an embodiment, the electrode layer EL may include a lower surface on which the second semiconductor layer SEC2 is disposed and an upper surface exposed to the outside in the first direction DR1. The electrode layer EL may be one end portion (or top end portion) of the light emitting element LD.

[0080] In an embodiment, the electrode layer EL_r may include an upper surface on which the second semiconductor layer SEC2_r is disposed and a lower surface exposed to the outside in a direction opposite to the first direction DR1. The electrode layer EL_r may be one end (or bottom end) of the light emitting element LD.

[0081] In an embodiment, the first semiconductor layer SEC1 or SEC1_r and the second semiconductor layer SEC2 or SEC2_r may have different thicknesses in the length direction of the light emitting element LD. For example, the first semiconductor layer SEC1 or SEC1_r may have a relatively thicker thickness than the second semiconductor layer SEC2 or SEC2_r. Therefore, the active layer AL of the first light emitting element LDf may be arranged to be closer to the upper surface of the second semiconductor layer SEC2 than the lower surface of the first semiconductor layer SEC1. The active layer AL_r of the second light emitting element LDr may be arranged to be closer to the lower surface of the second semiconductor layer SEC2_r than the upper surface of the first semiconductor layer SEC1_r.

[0082] Although it is shown that each of the first semiconductor layer SEC1 or SEC1_r and the second semiconductor layer SEC2 or SEC2_r is Figure 1 and Figure 2 In the embodiment, each of the first semiconductor layer SEC1 or SEC1_r and the second semiconductor layer SEC2 or SEC2_r may further include at least one layer (e.g., a cladding layer and / or a tensile strain barrier reduction (TSBR) layer) according to the material of the active layer AL or AL_r. The TSBR layer may be a strain reduction layer disposed between semiconductor layers having different lattice structures to perform a buffer function for reducing lattice constant differences. The TSBR layer may be composed of a p-type semiconductor layer such as p-GAInP, p-AlInP or p-AlGaInP, but the present disclosure is not limited thereto.

[0083] In an embodiment, the insulating film INF may surround the outer peripheral surfaces of the first light emitting element LDf and the second light emitting element LDr. In an embodiment, the insulating film INF may surround a portion of the first light emitting element LDf and a portion of the second light emitting element LDr.

[0084] In an embodiment, the insulating film INF may include a first insulating film INF1 and a second insulating film INF2. In an example, the first insulating film INF1 may surround the outer peripheral surface of the first semiconductor layer SEC1, the active layer AL, the second semiconductor layer SEC2, and the electrode layer EL of the first light emitting element LDf. The second insulating film INF2 may surround the outer peripheral surface of the first semiconductor layer SEC1_r, the active layer AL_r, the second semiconductor layer SEC2_r, and the electrode layer EL_r of the second light emitting element LDr. In an example, the second insulating film INF2 may combine the first light emitting element LDf and the second light emitting element LDr.

[0085] In an embodiment, the insulating film INF may expose the first end portion EP1 and the second end portion EP2 of each of the first light emitting element LDf and the second light emitting element LDr.

[0086] In the embodiment, in the first light emitting element LDf, a region of the first semiconductor layer SEC1 corresponding to the second end portion EP2 and a region of the electrode layer EL corresponding to the first end portion EP1 may be exposed from the first insulating film INF1. In the second light emitting element LDr, a region of the first semiconductor layer SEC1_r corresponding to the second end portion EP2 and a region of the electrode layer EL_r corresponding to the first end portion EP1 may be exposed from the second insulating film INF2.

[0087] In an embodiment, the insulating film INF can minimize surface defects of the first light emitting element LDf and the second light emitting element LDr, thereby improving the life span and luminous efficiency of the first light emitting element LDf and the second light emitting element LDr. The insulating film INF can prevent an electrical short circuit that may occur when the active layer AL or AL_r contacts a conductive material other than the first semiconductor layer SEC1 or SEC1_r and the second semiconductor layer SEC2 or SEC2_r.

[0088] In the embodiment, it has been described that the insulating film INF entirely surrounds the outer peripheral surface of the light emitting stack structure of the first light emitting element LDf and the second light emitting element LDr However, the present disclosure is not limited thereto.

[0089] In an embodiment, the insulating film INF may include a transparent insulating material. For example, the insulating film INF may include a material selected from silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum oxide (AlOx), titanium dioxide (TiO2), hafnium oxide (HfOx), titanium strontium oxide (SrTiOx), cobalt oxide (CoxOy), magnesium oxide (MgO), zinc oxide (ZnO), ruthenium oxide (RuOx), nickel oxide (NiO), tungsten oxide (WOx), tantalum oxide (TaOx), gadolinium oxide (GdOx), zirconium oxide (ZrOx), gallium oxide (GdOx), At least one insulating material of the group consisting of (GaOx), vanadium oxide (VxOy), ZnO:Al, ZnO:B, InxOy:H, niobium oxide (NbxOy), magnesium fluoride (MgFx), aluminum fluoride (AlFx), Alucone polymer film, titanium nitride (TiN), tantalum nitride (TaN), aluminum nitride (AlNx), gallium nitride (GaN), tungsten nitride (WN), hafnium nitride (HfN), niobium nitride (NbN), gadolinium nitride (GdN), zirconium nitride (ZrN), vanadium nitride (VN), etc. However, the present disclosure is not limited thereto, and various materials having insulating properties may be used as the material of the insulating film INF.

[0090] In an embodiment, the first insulating film INF1 and the second insulating film INF2 may be provided as a single layer or as a multilayer including at least two layers. In an example, the first insulating film INF1 and the second insulating film INF2 may be formed of the same material. However, this is merely illustrative, and the first insulating film INF1 and the second insulating film INF2 may include different materials.

[0091] Figure 3 is a schematic plan view showing a display device according to an embodiment of the present disclosure.

[0092] exist Figure 3 In the figure, for the convenience of description, the structure of the display device is briefly shown based on the display area DA.

[0093] Reference Figures 1 to 3 The display device may include a substrate SUB, a plurality of pixels PXL disposed on the substrate SUB and each including at least one light emitting element LD, a driving unit disposed on the substrate SUB and driving the pixels PXL, and a line unit connecting the pixels PXL to the driving unit.

[0094] The substrate SUB may include a display area DA and a non-display area NDA.

[0095] The display area DA may be an area in which pixels PXL for displaying an image are disposed. The non-display area NDA may be an area in which a driving unit for driving the pixels PXL and a portion of a line unit connecting the pixels PXL to the driving unit are disposed. Figure 3 Only one pixel PXL is shown in FIG. 1 , but a plurality of pixels PXL may be substantially disposed in the display area DA of the substrate SUB.

[0096] The non-display area NDA may be disposed adjacent to the display area DA. The non-display area NDA may be disposed on at least one side of the display area DA. In an example, the non-display area NDA may surround the periphery (or edge) of the display area DA. A line unit connected to the pixel PXL and a driving unit connected to the line unit and driving the pixel PXL may be disposed in the non-display area NDA.

[0097] The line unit may electrically connect the pixel PXL to the driving unit. The line unit may include a fan-out line connected to a signal line (e.g., a scan line, a data line, an emission control line, etc.), the signal line providing a signal to each pixel PXL and connected to each pixel PXL. In some embodiments, the line unit may include a fan-out line connected to a signal line (e.g., a control line, a sensing line, etc.), the signal line being connected to each pixel PXL so as to compensate for changes in the electrical characteristics of each pixel PXL in real time. The line unit may include a fan-out line connected to a power line, the power line providing a voltage to each pixel PXL and connected to each pixel PXL.

[0098] The substrate SUB may include a transparent insulating material to enable light to be transmitted therethrough. The substrate SUB may be a rigid substrate or a flexible substrate.

[0099] One area of ​​the substrate SUB may be set as a display area DA so that the pixels PXL are disposed in the display area DA, and another area of ​​the substrate SUB may be set as a non-display area NDA. In an example, the substrate SUB may include a display area DA including pixel areas in which the pixels PXL are respectively disposed, and a non-display area NDA disposed at the periphery of the display area DA (or adjacent to the display area DA).

[0100] Each of the pixels PXL may be disposed in the display area DA on the substrate SUB. In an embodiment, the pixels PXL may be arranged in a stripe arrangement structure or a PENTILE™ arrangement structure in the display area DA, but the present disclosure is not limited thereto.

[0101] Each pixel PXL may include at least one light emitting element LD driven by a corresponding scan signal and a corresponding data signal. The light emitting element LD may have a small size ranging from nanometers (or nanometers) to micrometers (micrometers) and may be connected in parallel to a light emitting element disposed adjacent thereto. However, the present disclosure is not limited thereto. The light emitting element LD may constitute a light source for each pixel PXL.

[0102] Each pixel PXL may include at least one light source (eg, a light source that is driven by a signal (eg, a scan signal, a data signal, etc.) and / or a power source (eg, a first driving power source, a second driving power source, etc.). Figure 1 and Figure 2 However, the kind of the light emitting element LD that can be used as the light source of each pixel PXL is not limited thereto.

[0103] The driving unit may supply a signal and power to each pixel PXL through the line unit, and thus, may control driving of the pixel PXL.

[0104] Figure 4 It is shown Figure 3 A circuit diagram of an example of a pixel included in a display device shown in FIG.

[0105] Reference Figure 4 , the pixel PXL may include a pixel circuit PXC and a light emitting unit EMU (or a light emitting portion).

[0106] In an embodiment, the pixel PXL may include a light emitting unit EMU (or a light emitting portion) generating light having brightness corresponding to a data signal. In addition, the pixel PXL may further selectively include a pixel circuit PXC for driving the light emitting unit EMU.

[0107] In an embodiment, the light emitting unit EMU may include a plurality of light emitting elements LD connected in parallel between a first power line PL1 and a second power line PL2, the first power line PL1 being connected to a first driving power source VDD to be applied with a voltage of the first driving power source VDD, and the second power line PL2 being connected to a second driving power source VSS to be applied with a voltage of the second driving power source VSS. For example, the light emitting unit EMU may include a first pixel electrode PE1 connected to the first driving power source VDD via a pixel circuit PXC and the first power line PL1, a second pixel electrode PE2 connected to the second driving power source VSS via the second power line PL2, and a plurality of light emitting elements LD connected in parallel in the same direction between the first pixel electrode PE1 and the second pixel electrode PE2. In an embodiment, the first pixel electrode PE1 may be an anode, and the second pixel electrode PE2 may be a cathode.

[0108] In an embodiment, each of the light emitting elements LD included in the light emitting unit EMU may be an integrated light emitting element unit including a first light emitting element LDf and a second light emitting element LDr.

[0109] In an embodiment, each of the first light emitting element LDf and the second light emitting element LDr included in each light emitting element LD included in the light emitting unit EMU may include one end connected to the first driving power source VDD through the first pixel electrode PE1 and the other end connected to the second driving power source VSS through the second pixel electrode PE2. The first driving power source VDD and the second driving power source VSS may have different potentials. In an example, the first driving power source VDD may be set to a high potential power source, and the second driving power source VSS may be set to a low potential power source. During the emission period of the pixel PXL, the potential difference between the first driving power source VDD and the second driving power source VSS may be set to be equal to or higher than the threshold voltage of the light emitting element LD.

[0110] In an embodiment, one of the first light emitting element LDf and the second light emitting element LDr of the light emitting element LD may be connected between the first pixel electrode PE1 and the second pixel electrode PE2 in the forward direction, and the other of the first light emitting element LDf and the second light emitting element LDr may be connected between the first pixel electrode PE1 and the second pixel electrode PE2 in the reverse direction. Figure 4 , shows that the first light emitting element LDf of the light emitting element LD is connected between the first pixel electrode PE1 and the second pixel electrode PE2 in the forward direction, and the second light emitting element LDr of the light emitting element LD is connected between the first pixel electrode PE1 and the second pixel electrode PE2 in the reverse direction. However, the present disclosure is not limited thereto, and some of the light emitting elements LD between the first pixel electrode PE1 and the second pixel electrode PE2 may have an arrangement in which the second light emitting element LDr is connected in the forward direction and the first light emitting element LDf is connected in the reverse direction.

[0111] When the first light-emitting element LDf of the light-emitting element LD is connected in the forward direction between the first pixel electrode PE1 and the second pixel electrode PE2 and the second light-emitting element LDr of the light-emitting element LD is connected in the reverse direction between the first pixel electrode PE1 and the second pixel electrode PE2, the first light-emitting element LDf can become an effective light source (emitting light) and the second light-emitting element LDr can become an ineffective light source (non-emitting light).

[0112] In an embodiment, when the light emitting element LD is provided in the pixel PXL, since the light emitting element LD includes both an effective light source and an ineffective light source, the number of light emitting elements forming an effective light source in the light emitting unit EMU and the number of light emitting elements forming an ineffective light source in the light emitting unit EMU may be equal to each other.

[0113] Since one of the first light emitting element LDf and the second light emitting element LDr is an effective light source, the light emitting element LD can emit light through one of the first light emitting element LDf and the second light emitting element LDr.

[0114] In an embodiment, the pixel circuit PXC may be connected to the scan line Si and the data line Dj of the pixel PXL. In addition, the pixel circuit PXC may be connected to the control line CLi and the sensing line SENj of the pixel PXL. In an example, when the pixel PXL is disposed in the i-th row and the j-th column of the display area DA, the pixel circuit PXC of the pixel PXL may be connected to the i-th scan line Si, the j-th data line Dj, the i-th control line CLi, and the j-th sensing line SENj of the display area DA.

[0115] In an embodiment, the pixel circuit PXC may include first to third transistors T1 to T3 and a storage capacitor Cst.

[0116] In an embodiment, the first transistor T1 is a driving transistor for controlling a driving current applied to the light emitting unit EMU, and may be connected between the first driving power supply VDD and the light emitting unit EMU. Specifically, the first terminal of the first transistor T1 may be connected (or coupled) to the first driving power supply VDD via the first power line PL1, the second terminal of the first transistor T1 may be connected to the second node N2, and the gate electrode of the first transistor T1 may be connected to the first node N1. The first transistor T1 may control the amount of driving current applied to the light emitting unit EMU from the first driving power supply VDD through the second node N2 according to the voltage applied to the first node N1. In an embodiment, the first terminal of the first transistor T1 may be a drain electrode, and the second terminal of the first transistor T1 may be a source electrode. However, the present disclosure is not limited thereto. In some embodiments, the first terminal may be a source electrode, and the second terminal may be a drain electrode.

[0117] In an embodiment, the second transistor T2 is a switching transistor that selects the pixel PXL in response to the scan signal and activates the pixel PXL, and can be connected between the data line Dj and the first node N1. The first terminal of the second transistor T2 can be connected to the data line Dj, the second terminal of the second transistor T2 can be connected to the first node N1, and the gate electrode of the second transistor T2 can be connected to the scan line Si. The first terminal and the second terminal of the second transistor T2 are different terminals. For example, when the first terminal is a drain electrode, the second terminal can be a source electrode.

[0118] When a scan signal having a gate-on voltage (e.g., a high level voltage) is supplied from the scan line Si, the second transistor T2 may be turned on to electrically connect the data line Dj and the first node N1 to each other. The first node N1 is a point at which the second terminal of the second transistor T2 and the gate electrode of the first transistor T1 are connected to each other, and the second transistor T2 may transmit a data signal to the gate electrode of the first transistor T1.

[0119] In an embodiment, the third transistor T3 connects the first transistor T1 to the sensing line SENj to obtain a sensing signal through the sensing line SENj and detects the characteristics of the pixel PXL (including the threshold voltage of the first transistor, etc.) by using the sensing signal. Information about the characteristics of the pixel PXL can be used to convert image data so that characteristic deviations between pixels PXL can be compensated. The second terminal of the third transistor T3 can be connected to the second terminal of the first transistor T1, the first terminal of the third transistor T3 can be connected to the sensing line SENj, and the gate electrode of the third transistor T3 can be connected to the control line CLi.

[0120] In an embodiment, a first terminal of the third transistor T3 may be connected to an initialization power source. The third transistor T3 is an initialization transistor capable of initializing the second node N2. When a control signal is supplied from the control line CLi, the third transistor T3 may be turned on to transmit the voltage of the initialization power source to the second node N2. Therefore, the second capacitor electrode of the storage capacitor Cst connected to the second node N2 may be initialized.

[0121] In an embodiment, a first capacitor electrode of the storage capacitor Cst may be connected to the first node N1, and a second capacitor electrode of the storage capacitor Cst may be connected to the second node N2. The storage capacitor Cst charges a data voltage corresponding to a data signal supplied to the first node N1 during one frame period. Therefore, the storage capacitor Cst may store a voltage corresponding to a difference between a voltage of the gate electrode of the first transistor T1 and a voltage of the second node N2.

[0122] Despite Figure 4 , the embodiment in which all the light-emitting elements LD constituting the light-emitting unit EMU are connected in parallel has been shown, but the present disclosure is not limited thereto. In some embodiments, the light-emitting unit EMU may be constructed to include at least one series stage (or stage), which includes a plurality of light-emitting elements LD connected in parallel to each other. That is, the light-emitting unit EMU may be constructed in a series / parallel hybrid structure.

[0123] Figure 5 It is shown Figure 3 A schematic plan view of an example of a pixel included in a display device shown in FIG.

[0124] Figure 5 is a view showing some components included in the pixel PXL.

[0125] Reference Figure 5 The display device may include a first pixel electrode PE1, a second pixel electrode PE2, a first connection electrode CNL1, a second connection electrode CNL2, a first contact electrode CNE1, a second contact electrode CNE2, a first contact portion CNT1, a second contact portion CNT2, and a light emitting element LD to constitute a pixel PXL.

[0126] In an embodiment, the pixel PXL may include a first pixel electrode PE1 and a second pixel electrode PE2. In an example, the first pixel electrode PE1 and the second pixel electrode PE2 may be used as electrodes for aligning the light emitting element LD and electrodes for applying a predetermined voltage.

[0127] In an embodiment, the first pixel electrode PE1 and the second pixel electrode PE2 may serve as alignment electrodes with respect to the light emitting elements LD including the first light emitting element LDf and the second light emitting element LDr. For example, the light emitting element LD may be arranged in response to an electrical signal provided from the first pixel electrode PE1 and the second pixel electrode PE2.

[0128] In the embodiment, the light emitting element LD is a light emitting element unit including a first light emitting element LDf and a second light emitting element LDr, and a plurality of light emitting elements LD may be arranged. In the example, the plurality of light emitting elements LD may be arranged in a parallel structure along the second direction DR2. However, the arrangement structure of the light emitting element LD is not limited thereto.

[0129] In an embodiment, when viewed on a plane, the light emitting element LD may be disposed between the first pixel electrode PE1 and the second pixel electrode PE2. The light emitting element LD may be disposed on the first pixel electrode PE1 and the second pixel electrode PE2.

[0130] In an embodiment, the first light emitting element LDf and the second light emitting element LDr of the light emitting element LD may be electrically connected to the first pixel electrode PE1 through the first contact electrode CNE1.

[0131] In an embodiment, the first end EP1 of the first light emitting element LDf and the second end EP2 of the second light emitting element LDr may be electrically connected to the first contact electrode CNE1. The second semiconductor layer SEC2 of the first light emitting element LDf and the first semiconductor layer SEC1_r of the second light emitting element LDr may be electrically connected to the first contact electrode CNE1.

[0132] In an embodiment, the first light emitting element LDf and the second light emitting element LDr of the light emitting element LD may be electrically connected to the second pixel electrode PE2 through the second contact electrode CNE2.

[0133] In an embodiment, the second end EP2 of the first light emitting element LDf and the first end EP1 of the second light emitting element LDr may be electrically connected to the second contact electrode CNE2. The first semiconductor layer SEC1 of the first light emitting element LDf and the second semiconductor layer SEC2_r of the second light emitting element LDr may be electrically connected to the second contact electrode CNE2.

[0134] In an embodiment, the first pixel electrode PE1 and the second pixel electrode PE2 may be electrically connected to the pixel circuit PXC and / or the power line. For example, the first pixel electrode PE1 may be electrically connected to the pixel circuit PXC and / or the first power line PL1 through a first contact portion CNT1 formed in the first connection electrode CNL1, and the second pixel electrode PE2 may be electrically connected to the pixel circuit PXC and / or the second power line PL2 through a second contact portion CNT2 formed in the second connection electrode CNL2.

[0135] In an embodiment, each of the first semiconductor layers SEC1 and SEC1_r of the first light emitting element LDf and the second light emitting element LDr may be an n-type conductive semiconductor layer, and the second semiconductor layers SEC2 and SEC2_r of the first light emitting element LDf and the second light emitting element LDr may be p-type conductive semiconductor layers. When the light emitting element LDf or LDr is disposed between the first pixel electrode PE1 and the second pixel electrode PE2, when the second semiconductor layer SEC2 or SEC2_r of the light emitting element LDf or LDr is electrically connected to the first pixel electrode PE1 and the first semiconductor layer SEC1 or SEC1_r of the light emitting element LDf or LDr is electrically connected to the second pixel electrode PE2, the light emitting element LDf or LDr is disposed in the forward direction. Therefore, the corresponding light emitting element may correspond to a light emitting element forming an effective light source. On the contrary, when the first semiconductor layer SEC1 or SEC1_r of the light emitting element LDf or LDr is electrically connected to the first pixel electrode PE1 and the second semiconductor layer SEC2 or SEC2_r of the light emitting element LDf or LDr is electrically connected to the second pixel electrode PE2, the light emitting element LDf or LDr is disposed in the reverse direction. Therefore, the corresponding light emitting element may correspond to a light emitting element forming an ineffective light source.

[0136] Reference Figure 5, when the light emitting element LD is provided in the pixel PXL, one of the first light emitting element LDf and the second light emitting element LDr included in the light emitting element LD may be connected between the first pixel electrode PE1 and the second pixel electrode PE2 in the forward direction, and the other of the first light emitting element LDf and the second light emitting element LDr may be connected between the first pixel electrode PE1 and the second pixel electrode PE2 in the reverse direction. In the example, the first light emitting element LDf may be provided between the first pixel electrode PE1 and the second pixel electrode PE2 in the forward direction, and the second light emitting element LDr may be provided between the first pixel electrode PE1 and the second pixel electrode PE2 in the reverse direction. That is, the first light emitting element LDf may form an effective light source, and the second light emitting element LDr may form an ineffective light source.

[0137] In another example, when the first semiconductor layer SEC1 of the first light emitting element LDf of the light emitting element LD is electrically connected to the first pixel electrode PE1 and the second semiconductor layer SEC2 of the first light emitting element LDf is electrically connected to the second pixel electrode PE2, the first light emitting element LDf may form an ineffective light source. When the second semiconductor layer SEC2_r of the second light emitting element LDr is electrically connected to the first pixel electrode PE1 and the first semiconductor layer SEC1_r of the second light emitting element LDr is electrically connected to the second pixel electrode PE2, the second light emitting element LDr may form an effective light source.

[0138] In an embodiment, each of the light emitting elements LD provided in the pixel PXL may be provided as one light emitting element unit configured with a first light emitting element LDf provided in the first direction DR1 and a second light emitting element LDr provided in the opposite direction of the first direction DR1. Since one of the first light emitting element LDf and the second light emitting element LDr included in the light emitting element LD is provided as an effective light source between the first pixel electrode PE1 and the second pixel electrode PE2, it is possible to sufficiently ensure that the number of effective light sources in the pixel PXL is equal to or greater than the reference. It is also possible to uniformly ensure the effective light sources of a plurality of pixels.

[0139] In an embodiment, the first pixel electrode PE1 and the second pixel electrode PE2 may extend in the second direction DR2. The first pixel electrode PE1 and the second pixel electrode PE2 may be disposed while being spaced apart from each other in the first direction DR1.

[0140] In an embodiment, the first connection electrode CNL1 may be disposed in the same layer as the first pixel electrode PE1 to be integrally formed with the first pixel electrode PE1.

[0141] In an embodiment, in a cross-sectional view, the first contact electrode CNE1 may be disposed on the first pixel electrode PE1 to be electrically connected to the first pixel electrode PE1. The first contact electrode CNE1 may electrically connect the first pixel electrode PE1 and the light emitting element LD to each other.

[0142] In an embodiment, in a cross-sectional view, the second contact electrode CNE2 may be disposed on the second pixel electrode PE2 to be electrically connected to the second pixel electrode PE2. The second contact electrode CNE2 may electrically connect the second pixel electrode PE2 and the light emitting element LD to each other.

[0143] In an embodiment, the first contact electrode CNE1 may overlap the first end portion EP1 of the first light emitting element LDf and the second end portion EP2 of the second light emitting element LDr when viewed on a plane.

[0144] In an embodiment, the second contact electrode CNE2 may overlap the second end portion EP2 of the first light emitting element LDf and the first end portion EP1 of the second light emitting element LDr when viewed on a plane.

[0145] In an embodiment, the first connection electrode CNL1 may be connected to the pixel circuit layer (eg, Figure 6 The bridge pattern of the pixel circuit layer PCL shown in FIG. Figure 6 The bridging pattern BRP shown in FIG.

[0146] Figure 6 It is shown along Figure 5 A schematic cross-sectional view of the example taken along line II' shown in FIG.

[0147] Reference Figure 4 , Figure 5 and Figure 6 The pixel PXL may include a substrate SUB, a pixel circuit layer PCL, and a display element layer DPL. Hereinafter, for the convenience of description, the first transistor T1 among the first to third transistors T1 to T3 will be mainly described.

[0148] In an embodiment, the substrate SUB may constitute a substrate member of the display device. The substrate SUB may be a rigid or flexible substrate or film, but the present disclosure is not limited to a specific example. In an example, the substrate SUB may include polyimide. The substrate SUB may be provided as a base surface so that the pixel circuit layer PCL and the display element layer DPL are provided on the substrate SUB.

[0149] In an embodiment, the pixel circuit layer PCL may be disposed on the substrate SUB. The pixel circuit layer PCL may include a lower electrode layer BML, a buffer layer BFL, a first transistor T1, a gate insulating layer GI, a first interlayer insulating layer ILD1, a second interlayer insulating layer ILD2, a bridge pattern BRP, a second power line PL2, a protection layer PSV, a first contact portion CNT1, and a second contact portion CNT2.

[0150] In an embodiment, the lower electrode layer BML may be disposed on the substrate SUB to be covered by the buffer layer BFL. When viewed on a plane, a portion of the lower electrode layer BML may overlap the first transistor T1.

[0151] In an embodiment, the lower electrode layer BML may include a conductive material so as to serve as a path through which an electrical signal provided to the pixel circuit layer PCL and the display element layer DPL moves. For example, the lower electrode layer BML may include at least one of aluminum (Al), copper (Cu), titanium (Ti), and molybdenum (Mo).

[0152] In an embodiment, a buffer layer BFL may be disposed on the substrate SUB. The buffer layer BFL may prevent impurities from diffusing from the outside. The buffer layer BFL may include at least one of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), and a metal oxide such as aluminum oxide (AlOx).

[0153] In an embodiment, the first transistor T1 may be electrically connected to the light emitting element LD. The first transistor T1 may be electrically connected to the bridge pattern BRP. However, the present disclosure is not limited to the above example. The first transistor T1 may be electrically connected to the first connection electrode CNL1 without passing through the bridge pattern BRP.

[0154] In an embodiment, the first transistor T1 may include an active layer ACT, a first transistor electrode TE1, a second transistor electrode TE2, and a gate electrode GE.

[0155] In an embodiment, the active layer ACT may mean a semiconductor layer. The active layer ACT may be disposed on the buffer layer BFL. For example, the active layer ACT may include at least one of low temperature polysilicon (LTPS), polysilicon, amorphous silicon, and an oxide semiconductor.

[0156] In an embodiment, the active layer ACT may include a first contact region contacting the first transistor electrode TE1 and a second contact region contacting the second transistor electrode TE2. The first contact region and the second contact region may correspond to a semiconductor pattern doped with impurities. The region between the first contact region and the second contact region may be a channel region. The channel region may correspond to an intrinsic semiconductor pattern not doped with impurities.

[0157] In an embodiment, the gate electrode GE may be disposed on the gate insulating layer GI. The position of the gate electrode GE may correspond to the position of the channel region of the active layer ACT. For example, the gate electrode GE may be disposed on the channel region of the active layer ACT, and the gate insulating layer GI is disposed between the gate electrode GE and the active layer ACT. In an example, the gate electrode GE may include any one of aluminum (Al), copper (Cu), titanium (Ti), and molybdenum (Mo).

[0158] In an embodiment, the gate insulating layer GI may be disposed on the active layer ACT. The gate insulating layer GI may include an inorganic material. In an example, the gate insulating layer GI may include at least one of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx).

[0159] In embodiments, the first interlayer insulating layer ILD1 may be disposed on the gate electrode GE. Like the gate insulating layer GI, the first interlayer insulating layer ILD1 may include at least one of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx).

[0160] In an embodiment, the first transistor electrode TE1 and the second transistor electrode TE2 may be disposed on the first interlayer insulating layer ILD1. The first transistor electrode TE1 may contact the first contact region of the active layer ACT while penetrating the gate insulating layer GI and the first interlayer insulating layer ILD1, and the second transistor electrode TE2 may contact the second contact region of the active layer ACT while penetrating the gate insulating layer GI and the first interlayer insulating layer ILD1. In an example, the first transistor electrode TE1 may be a drain electrode, and the second transistor electrode TE2 may be a source electrode. However, the present disclosure is not limited thereto.

[0161] In an embodiment, a second interlayer insulating layer ILD2 may be disposed on the first transistor electrode TE1 and the second transistor electrode TE2. Like the first interlayer insulating layer ILD1 and the gate insulating layer GI, the second interlayer insulating layer ILD2 may include an inorganic material. The inorganic material may include at least one of the materials exemplified as materials constituting the first interlayer insulating layer ILD1 and the gate insulating layer GI (e.g., silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx)).

[0162] In an embodiment, a bridge pattern BRP may be disposed on the second interlayer insulating layer ILD2. The bridge pattern BRP may be connected to the first transistor electrode TE1 through a contact hole penetrating the second interlayer insulating layer ILD2. The bridge pattern BRP may be electrically connected to the first connection electrode CNL1 through a first contact portion CNT1 formed in the protection layer PSV.

[0163] In an embodiment, the second power line PL2 may be disposed on the second interlayer insulating layer ILD2. The second power line PL2 may be electrically connected to the second connection electrode CNL2 through the second contact portion CNT2 formed in the protective layer PSV. The second power line PL2 may provide a second power source (or cathode signal) to the light emitting element LD through the second pixel electrode PE2.

[0164] In an embodiment, the protection layer PSV may be located on the second interlayer insulating layer ILD2. The protection layer PSV may cover the bridge pattern BRP and the second power line PL2. The protection layer PSV may be a via layer.

[0165] In an embodiment, the protection layer PSV may be provided in a form including an organic insulating layer, an inorganic insulating layer, or an organic insulating layer disposed on an inorganic insulating layer, but the present disclosure is not limited thereto.

[0166] In an embodiment, a first contact portion CNT1 connected to one region of the bridge pattern BRP and a second contact portion CNT2 connected to one region of the second power line PL2 may be formed in the protection layer PSV.

[0167] In an embodiment, the display element layer DPL may be disposed on the pixel circuit layer PCL. The display element layer DPL may include a first insulating pattern INP1, a second insulating pattern INP2, a bank BNK, a first connection electrode CNL1, a second connection electrode CNL2, a first pixel electrode PE1, a second pixel electrode PE2, a first insulating layer INS1, a light emitting element LD (a first light emitting element LDf), a second insulating layer INS2, a first contact electrode CNE1, a second contact electrode CNE2, and a third insulating layer INS3.

[0168] In an embodiment, the first insulating pattern INP1 and the second insulating pattern INP2 may be disposed on the protective layer PSV. The first insulating pattern INP1 and the second insulating pattern INP2 may have a shape protruding in a display direction (e.g., a third direction DR3) of the display device. In an example, the first insulating pattern INP1 and the second insulating pattern INP2 may include an organic material and / or an inorganic material, but the present disclosure is not limited thereto.

[0169] In an embodiment, the first connection electrode CNL1 and the second connection electrode CNL2 may be disposed on the protection layer PSV. The first connection electrode CNL1 may be connected to the first pixel electrode PE1. The first connection electrode CNL1 may be electrically connected to the bridge pattern BRP through the first contact portion CNT1. The first connection electrode CNL1 may electrically connect the bridge pattern BRP and the first pixel electrode PE1 to each other. The second connection electrode CNL2 may be connected to the second pixel electrode PE2. The second connection electrode CNL2 may be electrically connected to the second power line PL2 through the second contact portion CNT2. The second connection electrode CNL2 may electrically connect the second power line PL2 and the second pixel electrode PE2.

[0170] In an embodiment, the first pixel electrode PE1 and the second pixel electrode PE2 may be disposed on the protective layer PSV. According to an embodiment, at least a portion of the first pixel electrode PE1 may be disposed on the first insulating pattern INP1, at least a portion of the second pixel electrode PE2 may be disposed on the second insulating pattern INP2, and both may serve as reflective partition walls.

[0171] In an embodiment, the first pixel electrode PE1 may be electrically connected to the first light emitting element LDf. The first pixel electrode PE1 may be electrically connected to the first contact electrode CNE1 through a contact hole formed in the first insulating layer INS1. The first pixel electrode PE1 may provide an anode signal to the first light emitting element LDf.

[0172] In an embodiment, the second pixel electrode PE2 may be electrically connected to the first light emitting element LDf. The second pixel electrode PE2 may be electrically connected to the second contact electrode CNE2 through a contact hole formed in the first insulating layer INS1. The second pixel electrode PE2 may apply a cathode signal (eg, a ground signal) to the first light emitting element LDf.

[0173] In an embodiment, the first pixel electrode PE1 and the second pixel electrode PE2 may include a conductive material. For example, the first pixel electrode PE1 and the second pixel electrode PE2 may include at least one of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and alloys thereof. However, the present disclosure is not limited to the above examples.

[0174] In an embodiment, a first insulating layer INS1 may be disposed on the protective layer PSV. The first insulating layer INS1 may cover the first pixel electrode PE1 and the second pixel electrode PE2. The first insulating layer INS1 may stabilize the connection between the electrode assemblies and reduce external influences. The first insulating layer INS1 may include at least one of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx).

[0175] In an embodiment, the bank BNK may be disposed on the first insulating layer INS1. The first light emitting element LDf may be disposed in a space defined by the bank BNK. The bank BNK may have a shape protruding in a display direction (eg, a third direction DR3) of the display device. In an example, the bank BNK may include an organic material or an inorganic material, but the present disclosure is not limited thereto.

[0176] In an embodiment, the first light emitting element LDf may be disposed on the first insulating layer INS1 to emit light by an electrical signal provided from the first and second contact electrodes CNE1 and CNE2.

[0177] In an embodiment, a light emitting element LD (eg, Figure 5 The first light emitting element LDf among the light emitting elements LD shown in FIG. 1 may include the first end portion EP1 and the second end portion EP2 as described above.

[0178] In an embodiment, the first end portion EP1 of the first light emitting element LDf may be electrically connected to the first contact electrode CNE1. The second end portion EP2 of the first light emitting element LDf may be electrically connected to the second contact electrode CNE2.

[0179] In an embodiment, the second semiconductor layer SEC2 of the first light emitting element LDf may be disposed adjacent to the first pixel electrode PE1 and the first contact electrode CNE1, and the first semiconductor layer SEC1 of the first light emitting element LDf may be disposed adjacent to the second pixel electrode PE2 and the second contact electrode CNE2.

[0180] In an embodiment, the first light emitting element LDf included in the light emitting element LD may be connected between the first pixel electrode PE1 and the second pixel electrode PE2 in a forward direction.

[0181] In an embodiment, the second insulating layer INS2 may be disposed on the first light emitting element LDf. The second insulating layer INS2 may cover the active layer AL of the first light emitting element LDf. In an example, the second insulating layer INS2 may include at least one of an organic material and an inorganic material. In an example, at least a portion of the second insulating layer INS2 may fill a gap (or cavity) formed at the bottom of the first light emitting element LDf.

[0182] In an embodiment, the first contact electrode CNE1 and the second contact electrode CNE2 may be disposed on the first insulating layer INS1. The first contact electrode CNE1 may electrically connect the first pixel electrode PE1 to the first end EP1 of the first light emitting element LDf, and the second contact electrode CNE2 may electrically connect the second pixel electrode PE2 to the second end EP2 of the first light emitting element LDf.

[0183] In an embodiment, the first contact electrode CNE1 may provide an anode signal to the first end portion EP1 of the first light emitting element LDf, and the second contact electrode CNE2 may provide a cathode signal to the second end portion EP2 of the first light emitting element LDf.

[0184] In an embodiment, the first contact electrode CNE1 and the second contact electrode CNE2 may include a conductive material. According to an embodiment, the first contact electrode CNE1 and the second contact electrode CNE2 may be formed by the same process and include the same material. For example, the first contact electrode CNE1 and the second contact electrode CNE2 may include a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), and indium tin zinc oxide (ITZO), but the present disclosure is not limited thereto.

[0185] In an embodiment, a third insulating layer INS3 may be disposed over the first contact electrode CNE1, the second contact electrode CNE2, and the second insulating layer INS2 to protect components of the display element layer DPL from external influences (e.g., moisture, etc.). For example, the third insulating layer INS3 may include at least one of silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiOxNy), and aluminum oxide (AlOx).

[0186] However, the structure of the pixel PXL is not limited to the above-mentioned Figure 6 Examples are described, and various modified embodiments can be implemented.

[0187] Figures 7 to 21 is a schematic cross-sectional view illustrating a method for manufacturing a light emitting element according to an embodiment of the present disclosure.

[0188] Reference Figure 7 , an undoped semiconductor layer USEC may be formed on the stack substrate SS. A first semiconductor layer SEC1 , an active layer AL, a second semiconductor layer SEC2 , and an electrode layer EL may be sequentially disposed on the undoped semiconductor layer USEC.

[0189] In an embodiment, the stacking substrate SS may be a substrate for stacking a target material. The stacking substrate SS may be a wafer for epitaxial growth of a target material. In an example, the stacking substrate SS may be a sapphire substrate, a GaAs substrate, a Ga substrate, or an InP substrate, but the present disclosure is not limited thereto. For example, when a specific material satisfies the selectivity for manufacturing the first light emitting element LDf and the epitaxial growth of the material is smoothly performed, the specific material may be selected as the material of the stacking substrate SS. The shape of the stacking substrate SS may be a polygonal shape including a rectangular shape or a circular shape, but the present disclosure is not limited thereto.

[0190] In an embodiment, the undoped semiconductor layer USEC may be a semiconductor layer in which no dopant is provided in order to suppress the occurrence of defects in the highly doped semiconductor layer of the first semiconductor layer SEC1. In an example, the undoped semiconductor layer USEC may include any one of semiconductor materials such as InAlGa, GaN, AlGaN, InGaN, AlN, and InN, and no separate dopant may be provided in the undoped semiconductor layer USEC. The etching rate of the undoped semiconductor layer USEC in which no dopant is provided may be different from the etching rate of the first semiconductor layer SEC1.

[0191] In embodiments, the undoped semiconductor layer USEC may be formed by processes such as metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), vapor phase epitaxy (VPE), and liquid phase epitaxy (LPE).

[0192] In embodiments, the first semiconductor layer SEC1 , the active layer AL, and the second semiconductor layer SEC2 may be formed by epitaxial growth, and may be provided by any one of the processes exemplarily listed as processes for forming the undoped semiconductor layer USEC.

[0193] In an embodiment, an electrode layer EL may be formed on the second semiconductor layer SEC2. The electrode layer EL may be stacked on the second semiconductor layer SEC2 by a deposition process. The electrode layer EL may minimize the loss of light output from the active layer AL to be released outside the light emitting element LD. In an example, the electrode layer EL may include a transparent metal oxide to improve the effect of current diffusion to the second semiconductor layer SEC2.

[0194] Reference Figure 8 , the stack substrate SS may include a first area EA1 and a second area EA2 .

[0195] The first area EA1 may be where a first light emitting element (eg, Figure 1 The second region EA2 may be a region where the second light emitting element (eg, Figure 1The region of the second light emitting element LDr) shown in FIG.

[0196] In an embodiment, a first stacked structure SP1 may be formed by etching a portion of the first semiconductor layer SEC1, the active layer AL, the second semiconductor layer SEC2, and the electrode layer EL corresponding to the second area EA2 using a mask (not shown). The etching process for forming the first stacked structure SP1 may be a dry etching process. The dry etching process may be any one of reactive ion etching (RIE), reactive ion beam etching (RIBE), and inductively coupled plasma reactive ion etching (ICP-RIE).

[0197] In an embodiment, when the portions of the first semiconductor layer SEC1, the active layer AL, the second semiconductor layer SEC2, and the electrode layer EL corresponding to the second area EA2 are removed, a first stacked structure SP1 including the first semiconductor layer SEC1, the active layer AL, the second semiconductor layer SEC2, and the electrode layer EL may be formed at both sides of the second area EA2. The first stacked structure SP1 may be formed with a first light emitting element (e.g., Figure 1 The stacked structure of the first light-emitting element LDf) shown in FIG.

[0198] Reference Fig. 9 A first insulating film INF1 may be formed to cover the first semiconductor layer SEC1, the active layer AL, the second semiconductor layer SEC2, and the electrode layer EL. For example, the first insulating film INF1 may be integrally formed on the first area EA1 and the second area EA2 and cover the first stacked structure SP1.

[0199] Reference Fig.10 , a portion of the first insulating film INF1 corresponding to the second area EA2 may be removed. The first insulating film INF1 may cover only the first stacked structure SP1.

[0200] Reference Fig.11 and Fig.12 , after the electrode layer EL_r is entirely deposited in the regions corresponding to the first area EA1 and the second area EA2 , a portion of the electrode layer EL_r corresponding to the first area EA1 may be removed.

[0201] Reference Figures 13 to 15 , the second semiconductor layer SEC2_r, the active layer AL_r, and the first semiconductor layer SEC1_r may be sequentially formed on the first insulating film INF1 and the electrode layer EL_r. The active layer AL_r may be disposed on the second semiconductor layer SEC2_r, and the first semiconductor layer SEC1_r may be disposed on the active layer AL_r. In an example, the process of forming the first semiconductor layer SEC1_r, the active layer AL_r, and the second semiconductor layer SEC2_r may be the same as that of the reference Figure 7The processes for forming the first semiconductor layer SEC1, the active layer AL and the second semiconductor layer SEC2 are the same. In an example, the first semiconductor layer SEC1_r, the active layer AL_r and the second semiconductor layer SEC2_r may be formed by epitaxial growth and may be provided by any of the processes exemplarily listed as the processes for forming the undoped semiconductor layer USEC.

[0202] Reference Fig.16 , part of the second area EA2 and the first semiconductor layer SEC1_r, the active layer AL_r, the second semiconductor layer SEC2_r, and the first insulating film INF1 on the first stacked structure SP1 may be removed. The first semiconductor layer SEC1_r, the active layer AL_r, the second semiconductor layer SEC2_r, and the first insulating film INF1 disposed on the electrode layer EL may be removed by etching.

[0203] Reference Fig.17 The stacked substrate SS may include a first light emitting element (eg, Figure 1 , and a first region EA1 in which a second light emitting element (eg, Figure 1 The second region EA2 of the second light emitting element LDr shown in FIG. The second region EA2 in which the second light emitting element LDr is formed may include a 2_1 region EA2_1, a 2_2 region EA2_2, and a 2_3 region EM2_3. The 2_2 region EA2_2 may be a region in which the second stacked structure SP2 of the second light emitting element LDr is formed. The 2_1 region EA2_1 and the 2_3 region EA2_3 may be regions in which the second insulating film INF2 is filled.

[0204] In an embodiment, the 2_1st area EA2_1 may have the same width as the first area EA1 in which the first light emitting element LDf is formed.

[0205] In the example, the regions of the first semiconductor layer SEC1_r, the active layer AL_r, the second semiconductor layer SEC2_r, and the electrode layer EL_r corresponding to the 2_1 region EA2_1 and the 2_3 region EA2_3 may be removed by using a mask (not shown). In the example, when the first semiconductor layer SEC1_r, the active layer AL_r, the second semiconductor layer SEC2_r, and the electrode layer EL_r corresponding to the 2_1 region EA2_1 and the 2_3 region EA2_3 are removed, a second stacked structure SP2 may be formed by the electrode layer EL_r, the second semiconductor layer SEC2_r, the active layer AL_r, and the first semiconductor layer SEC1_r sequentially stacked in the 2_2 region EA2_2. The second stacked structure SP2 may be formed with a second light emitting element (e.g., Figure 1The stacking structure of the second light-emitting element LDr) shown in FIG.

[0206] In an embodiment, two second stack structures SP2 may be formed in the second area EA2. The two second stack structures SP2 may be disposed between the first stack structures SP1.

[0207] In an embodiment, the second semiconductor layer SEC2 of the first stacked structure SP1 may be disposed at the same layer as the first semiconductor layer SEC1_r of the second stacked structure SP2.

[0208] Reference Fig.18 A second insulating film INF2 covering the first insulating film INF1, the first semiconductor layer SEC1_r, the active layer AL_r, the second semiconductor layer SEC2_r, and the electrode layer EL_r may be formed. The second insulating film INF2 may be entirely deposited in regions corresponding to the first area EA1 and the second area EA2.

[0209] Reference Fig.17 and Fig.19 , the second insulating film INF2 on the first stacked structure SP1 and the second stacked structure SP2 may be removed. The second insulating film INF2 may have the same height as the first insulating film INF1.

[0210] Reference Fig. 20 , the light emitting stack pattern SP may provide a light emitting element LD' while being separated from a portion of the first semiconductor layer SEC1, the stack substrate SS, and the undoped semiconductor layer USEC. The light emitting stack pattern SP separated from the stack substrate SS and the undoped semiconductor layer USEC may be provided as a light emitting element LD'. The light emitting stack pattern SP may include a first stack structure SP1 and a second stack structure SP2. The first stack structure SP1 may be a stack structure for forming a first light emitting element LDf, and the second stack structure SP2 may be a stack structure for forming a second light emitting element LDr.

[0211] Reference Fig.21 , the light emitting stack pattern SP set as the light emitting element LD' may include a plurality of first light emitting elements LDf and a plurality of second light emitting elements LDr. The light emitting stack pattern SP set as the light emitting element LD' may be separated into a first light emitting element unit LD1 and a second light emitting element unit LD2. Each of the first light emitting element unit LD1 and the second light emitting element unit LD2 may include a first light emitting element LDf and a second light emitting element LDr. The first light emitting element unit LD1 and the second light emitting element unit LD2 may be set as Figure 1 The light emitting element LD shown in FIG.

[0212] Figure 22 to Figure 26is a schematic cross-sectional view illustrating a method of manufacturing a display device according to an embodiment of the present disclosure.

[0213] Figure 22 to Figure 24 It mainly shows Figure 7 , which is a cross-sectional view of an emission area EMA shown in FIG. 1 , and is a process cross-sectional view illustrating a method of manufacturing a display device according to an embodiment of the present disclosure.

[0214] Reference Fig. 22 A substrate SUB may be provided, and a pixel circuit layer PCL may be disposed on the substrate SUB. A first insulating pattern INP1 and a second insulating pattern INP2 may be disposed on the pixel circuit layer PCL, a first pixel electrode PE1 and a second pixel electrode PE2 may be disposed on the first insulating pattern INP1 and the second insulating pattern INP2, and a first insulating layer INS1 may be disposed on the first pixel electrode PE1 and the second pixel electrode PE2.

[0215] The respective components of the pixel circuit layer PCL disposed on the substrate SUB may be formed by patterning a conductive layer (or a metal layer), an inorganic material, an organic material, etc. through a general process using a mask.

[0216] First and second insulating patterns INP1 and INP2 may be formed (or deposited) on the pixel circuit layer PCL. According to an embodiment, the first and second insulating patterns INP1 and INP2 may have a shape protruding in a display direction (eg, third direction DR3) so that a reflective surface may be formed.

[0217] Although not shown in any separate drawing, the first pixel electrode PE1 and the second pixel electrode PE2 may be provided by etching at least a portion of a base electrode after depositing the base electrode on the pixel circuit layer PCL.

[0218] The first pixel electrode PE1 and the second pixel electrode PE2 may be formed to cover the first and second insulating patterns INP1 and INP2, respectively. Therefore, at least a portion of each of the first pixel electrode PE1 and the second pixel electrode PE2 may be provided as a reflective partition wall or a reflective bank.

[0219] A first insulating layer INS1 may be formed (or deposited) to cover the first pixel electrode PE1 and the second pixel electrode PE2 .

[0220] Reference Fig.23 , ink INK may be provided on the substrate SUB. The ink INK may be provided by a printing device 300 capable of providing (or ejecting) a fluid.

[0221] According to an embodiment, the printing apparatus 300 may include a nozzle portion configured to discharge a liquid fluid to the outside. Ink INK defined in this specification may mean a liquid mixture that may be discharged by the printing apparatus 300 .

[0222] The printing apparatus 300 may eject the ink INK to a region where the light emitting element LD is to be arranged.

[0223] According to an embodiment, the ink INK may include a solvent SLV and a light emitting element LD. The light emitting element LD may be provided in plurality in the ink INK to be dispersed and provided in the solvent SLV having fluidity. In an example, the solvent SLV may mean a liquid phase material in which the light emitting element LD is dispersed and provided, rather than a solid phase material.

[0224] The ink INK may be accommodated in a predetermined (selectable) area. In an example, the ink INK may be disposed in an area (or space) defined by the bank BNK.

[0225] The light emitting elements LD may be provided in random orientations. In an embodiment, the light emitting element LD may be provided as a light emitting element unit in which the first light emitting element LDf and the second light emitting element LDr are integrally formed.

[0226] Reference Fig.24 , a light emitting element LD may be disposed between the first pixel electrode PE1 and the second pixel electrode PE2.

[0227] The light emitting element LD may be moved to a region where the light emitting element LD is to be disposed by a dielectrophoresis (DEP) force generated by an electrical signal supplied to the first pixel electrode PE1 and the second pixel electrode PE2. Therefore, the first light emitting element LDf and the second light emitting element LDr included in the light emitting element LD may be integrally disposed between the first pixel electrode PE1 and the second pixel electrode PE2.

[0228] An electrical signal may be provided to the first pixel electrode PE1 and the second pixel electrode PE2 so that an electric field is formed between the first pixel electrode PE1 and the second pixel electrode PE2 .

[0229] According to an embodiment, a first electrical signal may be provided to the first pixel electrode PE1, and a second electrical signal may be provided to the second pixel electrode PE2. In addition, the light emitting element LD may be arranged based on an electric field according to the first electrical signal and the second electrical signal. In an example, each of the first electrical signal and the second electrical signal is an AC signal, and may be any one of a sine wave, a triangle wave, a square wave, a trapezoidal wave, and a pulse wave. However, the present disclosure is not limited to a specific example.

[0230] Any one light emitting element selected from the first light emitting element LDf and the second light emitting element LDr included in the light emitting element LD may be arranged in the forward direction, and another light emitting element selected from the first light emitting element LDf and the second light emitting element LDr may be arranged in the reverse direction. For example, the second semiconductor layer SEC2 of the first light emitting element LDf and the first semiconductor layer SEC1_r of the second light emitting element LDr may be arranged to face the first pixel electrode PE1, and the first semiconductor layer SEC1 of the first light emitting element LDf and the second semiconductor layer SEC2_r of the second light emitting element LDr may be arranged to face the second pixel electrode PE2. The first light emitting element LDf may be arranged in the forward direction, and the second light emitting element LDr may be arranged in the reverse direction.

[0231] Reference Fig.25 , a second insulating layer INS2 may be disposed on the first light emitting element LDf (and the second light emitting element LDr), and a base contact electrode CNE0 may be disposed on the first insulating layer INS1 and the second insulating layer INS2.

[0232] In a plan view, the second insulating layer INS2 may be disposed to overlap the active layer AL of the first light emitting element LDf.

[0233] The base contact electrode CNE0 may cover the first insulating layer INS1 and the second insulating layer INS2. The base contact electrode CNE0 may be electrically connected to the first light emitting element LDf. For example, when viewed on a plane, a portion of the base contact electrode CNE0 may overlap with a first end portion of the first light emitting element LDf, and when viewed on a plane, another portion of the base contact electrode CNE0 may overlap with a second end portion EP2 of the first light emitting element LDf.

[0234] Reference Fig.26 , the first contact electrode CNE1 and the second contact electrode CNE2 may be formed by etching the base contact electrode CNE0.

[0235] At this stage, as at least a portion of the base contact electrode CNE0 is removed, at least a portion of the second insulating layer INS2 may be exposed, and the first and second contact electrodes CNE1 and CNE2 spaced apart from each other may be formed.

[0236] According to an embodiment, the first contact electrode CNE1 and the second contact electrode CNE2 may be simultaneously formed as parts of the base contact electrode CNE0. Therefore, the first contact electrode CNE1 and the second contact electrode CNE2 may include the same material.

[0237] The first contact electrode CNE1 may electrically contact the second semiconductor layer SEC2 of the first light emitting element LDf, and the second contact electrode CNE2 may electrically contact the first semiconductor layer SEC1 of the first light emitting element LDf. In an example, the first light emitting element LDf may form an effective light source of the light emitting element LD.

[0238] One of the first light emitting element LDf and the second light emitting element LDr included in the light emitting element LD can be set as an effective light source between the first pixel electrode PE1 and the second pixel electrode PE2, so that a light emitting element that forms a constant effective light source in the pixel PXL can be ensured. A light emitting element that forms an effective light source uniformly between the plurality of pixels PXL can be ensured.

[0239] Although not in Fig.26 , but a third insulating layer INS3 may be disposed (or formed) on the first contact electrode CNE1 and the second contact electrode CNE2 to form a display element layer DPL. In some embodiments, a color conversion layer CCL, an optical layer OPL, a color filter layer CFL, etc. may be formed on the display element layer DPL to form a display device according to an embodiment of the present disclosure.

[0240] The above description is an example of the technical features of the present invention, and various modifications and variations will be feasible for those skilled in the art, and thus the embodiments of the present invention described above may be implemented individually or in combination with each other.

[0241] Therefore, the embodiments disclosed in the present specification are not intended to limit the technical idea of ​​the present specification but are intended to explain the technical idea of ​​the present specification, and the scope of the technical idea of ​​the present specification is not limited by these embodiments.

Claims

1. A light-emitting element, comprising: A first light emitting element includes a first semiconductor layer, an active layer, and a second semiconductor layer sequentially arranged in a first direction; a second light emitting element spaced apart from the first light emitting element and comprising a first semiconductor layer, an active layer, and a second semiconductor layer sequentially disposed in a direction opposite to the first direction; as well as An insulating film surrounds a portion of the first light emitting element and a portion of the second light emitting element.

2. The light-emitting element according to claim 1, wherein The insulating film surrounds at least a portion of an outer peripheral surface of the first light emitting element and at least a portion of an outer peripheral surface of the second light emitting element, and fills a space between the first light emitting element and the second light emitting element.

3. The light-emitting element according to claim 2, wherein The insulating film includes: a first insulating film surrounding at least a portion of the outer peripheral surface of the first light emitting element; and a second insulating film surrounding at least a portion of the outer peripheral surface of the second light emitting element and filling the space between the first light emitting element and the second light emitting element.

4. The light-emitting element according to claim 3, wherein The first insulating film and the second insulating film include the same material.

5. The light-emitting element according to claim 2, further comprising: The electrode layer is provided on the second semiconductor layer of the first light emitting element and the second semiconductor layer of the second light emitting element.

6. The light-emitting element according to claim 5, wherein Each of the first light emitting element and the second light emitting element includes a first end and a second end, and The electrode layer is provided at the first end of each of the first light emitting element and the second light emitting element, and the first semiconductor layer is provided at the second end of each of the first light emitting element and the second light emitting element.

7. The light-emitting element according to claim 6, wherein The insulating film exposes each of the first end portion and the second end portion of each of the first light emitting element and the second light emitting element.

8. The light emitting element according to claim 6, wherein The first end of the first light emitting element and the second end of the second light emitting element are arranged on the same plane.

9. The light-emitting element according to claim 1, wherein The second light emitting element is disposed while being spaced apart from the first light emitting element in a second direction intersecting the first direction.

10. The light emitting element according to claim 1, wherein The shape of the first light emitting element is the same as the shape of the second light emitting element.

11. The light emitting element according to claim 1, wherein Each of the first semiconductor layers includes GaN doped with an n-type dopant, and Each of the second semiconductor layers includes GaN doped with a p-type dopant.

12. A method for manufacturing a light-emitting element, the method comprising: forming an undoped semiconductor layer on the stacked substrate including the first region and the second region; sequentially forming a first semiconductor layer, an active layer, a second semiconductor layer and an electrode layer on the undoped semiconductor layer; forming a first stacked structure in the first region by removing the first semiconductor layer, the active layer, the second semiconductor layer, and the portion of the electrode layer corresponding to the second region; forming a first insulating film covering the first stacked structure including the first semiconductor layer, the active layer, the second semiconductor layer and the electrode layer; sequentially forming an electrode layer, a second semiconductor layer, an active layer and a first semiconductor layer in the first region and the second region; forming a second stacked structure by removing a portion of each of the first semiconductor layer, the active layer, the second semiconductor layer, and the electrode layer in the second region and on the first stacked structure; as well as A second insulating film is formed surrounding at least a portion of a side surface of the second stack structure.

13. The method according to claim 12, wherein: The step of forming the second insulating film includes: forming the second insulating film over the entire areas of the first region and the second region; and The second insulating film disposed on the top surface of the first stack structure and the top surface of the second stack structure is removed.

14. The method according to claim 12, wherein: The step of forming the first insulating film includes: forming the first insulating film over the entire areas of the first region and the second region; and The first insulating film in the second region is removed.

15. The method according to claim 12, wherein: The second semiconductor layer of the first stacked structure and the first semiconductor layer of the second stacked structure are arranged on the same layer.

16. The method according to claim 12, wherein: The step of forming the second stack structure includes removing the first insulating film formed on the electrode layer of the first stack structure. 17 . The method of claim 12 , further comprising forming a light emitting stack pattern by separating the first stack structure, the second stack structure, the first insulating film, and the second insulating film from the stack substrate and the undoped semiconductor layer.

18. The method according to claim 12, wherein: The step of forming the second stack structure includes: forming two second stack structures in the second region.

19. A pixel, comprising: A first pixel electrode and a second pixel electrode are both disposed on a substrate; A light emitting element, disposed on the first pixel electrode and the second pixel electrode; a first contact electrode, electrically connecting the first pixel electrode and the light emitting element to each other; as well as a second contact electrode electrically connecting the second pixel electrode and the light emitting element to each other, Each of the light emitting elements includes: a first light emitting element arranged in a first direction; a second light emitting element arranged in a second direction which is an opposite direction to the first direction; and an insulating film combining the first light emitting element and the second light emitting element.

20. The pixel according to claim 19, wherein: The first light emitting element includes a first semiconductor layer, an active layer, a second semiconductor layer, and an electrode layer sequentially arranged in the first direction, and The second light emitting element includes a first semiconductor layer, an active layer, a second semiconductor layer and an electrode layer which are sequentially arranged in the second direction.

21. The pixel according to claim 20, wherein: Each of the first light emitting element and the second light emitting element includes a first end and a second end, and The electrode layer is provided at the first end of each of the first light emitting element and the second light emitting element, and the first semiconductor layer is provided at the second end of each of the first light emitting element and the second light emitting element.

22. The pixel according to claim 21, wherein: The first end of the first light emitting element and the second end of the second light emitting element are in electrical contact with the first contact electrode, and The second end portion of the first light emitting element and the first end portion of the second light emitting element are in electrical contact with the second contact electrode.

Images