Non-forming resistive random access memory (RRAM) device

Abstract

The present disclosure provides a method for fabricating a non-forming resistive random access memory (RRAM) device. The method includes fabricating an RRAM cell and annealing the RRAM cell. An RRAM cell includes a bottom electrode, a switching oxide layer including at least one transition metal oxide, a top electrode, and an interface layer fabricated between the top electrode and the switching oxide layer. In some embodiments, the at least one transition metal oxide includes at least one of HfOx or TaOy, where x < = 2.0, and y < = 2.5. The interface layer includes a layer of at least one of Al2O3, MgO, Y2O3, or La2O3. The non-forming RRAM device can be switched to a multi-stage resistance without a forming process.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to a resistive random access memory (RRAM) device, and more particularly, to a non-formational RRAM device and methods of manufacturing and operating the non-formational RRAM device. Background Art

[0002] RRAM devices are two-terminal passive devices with adjustable and non-volatile resistance. The resistance of the RRAM device can be electrically switched between a high resistance state (HRS) and a low resistance state (LRS) by applying a suitable programming signal to the RRAM device. RRAM devices can be used to form crossbar arrays, which can be used to implement in-memory computing applications, non-volatile solid-state memory, image processing applications, neural networks, etc. Summary of the invention

[0003] The following is a brief summary of the present disclosure, which is used to provide a basic understanding of some aspects of the present disclosure. The summary is not an extensive overview of the present disclosure. The summary is not intended to identify the key or important elements of the present disclosure, nor is it intended to illustrate any scope of a particular implementation of the present disclosure or any scope of the claims. The sole purpose of the summary is to present some concepts of the present disclosure as a language simplification of a more detailed description presented subsequently.

[0004] According to one or more aspects of the present disclosure, a method for manufacturing a non-formation-type resistive random access memory (RRAM) device is provided, wherein the method comprises manufacturing a RRAM cell having a designed interface layer and annealing the RRAM cell.

[0005] In some embodiments, manufacturing the RRAM cell includes: manufacturing a switching oxide layer including at least one transition metal oxide on a bottom electrode; manufacturing an interface layer including a material more chemically stable than the at least one transition metal oxide on the switching oxide layer; manufacturing a top electrode on the interface layer;

[0006] In some embodiments, the RRAM cell is annealed in a forming gas environment comprising N 2 and H 2 .

[0007] In some embodiments, the RRAM cell is annealed at an annealing temperature between 350°C and 450°C.

[0008] In some embodiments, one or more interconnect layers are fabricated on the RRAM cell, wherein the RRAM cell is annealed together with the one or more interconnect layers.

[0009] In some embodiments, fabricating the one or more interconnect layers includes fabricating metal pads or metal vias of the one or more interconnect layers on a top electrode of the RRAM cell.

[0010] In some embodiments, the RRAM cell and the one or more interconnect layers are annealed in a plurality of annealing processes, wherein the RRAM cell and the one or more interconnect layers are annealed in a forming gas at a temperature between 350° C. and 450° C. in each of the plurality of annealing processes.

[0011] In some embodiments, a thickness of the interface layer is determined based on a device size of the RRAM cell and a thermal budget associated with annealing, wherein the interface layer may be configured to reduce diffusion and reaction between the top electrode and the switching oxide layer.

[0012] According to one or more aspects of the present disclosure, a non-formational resistive random access memory (RRAM) device is provided. The non-formational RRAM device includes: a bottom electrode; a switching oxide layer including at least one transition metal oxide; a top electrode; and an interface layer fabricated between the top electrode and the switching oxide layer. The interface layer includes a material that is more chemically stable than the at least one transition metal oxide. The non-formational RRAM device is configured to be switched to a plurality of resistances without a formation process that generates conductive filaments in the switching oxide layer.

[0013] In some embodiments, the at least one transition metal oxide comprises HfO x or TaO y At least one of , wherein x≤2.0, and y≤2.5.

[0014] In some embodiments, the interface layer includes a layer of at least one of Al2O3, MgO, Y2O3, or La2O3.

[0015] In some embodiments, the thickness of the interface layer is between 0.2 nm and 1 nm.

[0016] In some embodiments, the thickness of the interfacial layer is greater than 1 nm.

[0017] In some embodiments, the initial resistance of the RRAM device is between 1 kΩ and 1 MΩ.

[0018] According to one or more aspects of the present disclosure, a method for operating a non-formation RRAM device is provided. The method includes: performing a first read operation on a first non-formation RRAM device in an initial state to determine a first initial resistance of the first non-formation RRAM device; performing a first reset operation on the first non-formation RRAM device to switch the first non-formation RRAM device from the first initial resistance to a first target resistance. The first target resistance is greater than the first initial resistance. The first read operation and the first reset operation are performed without pre-forming a conductive filament in the first non-formation RRAM device during a formation process.

[0019] In some embodiments, a first reset current passing through the first non-formation RRAM device during the first reset operation is no greater than 500 μA.

[0020] In some embodiments, the method of operating a non-formation RRAM device further includes: performing a first set operation on the first non-formation RRAM device to switch the first non-formation RRAM device from the first target resistance to a second target resistance. In some embodiments, performing the first set operation includes applying a first set voltage to the first non-formation RRAM device, wherein the first set voltage is no greater than 1.0V.

[0021] In some embodiments, performing a first reset operation on the first non-formation RRAM device includes applying a first reset voltage to the first non-formation RRAM device, and the first set voltage and the first reset voltage have opposite polarities.

[0022] In some embodiments, the method of operating a non-formation RRAM device further includes: performing a second read operation on a second non-formation RRAM device to determine a second initial resistance of the second non-formation RRAM device; and performing a second set operation on the second non-formation RRAM device to switch the second non-formation RRAM device from the second initial resistance to a third target resistance, wherein the third target resistance is less than the second initial resistance. The second read operation and the second set operation are performed without pre-forming a conductive filament in the second non-formation RRAM device during formation.

[0023] In some embodiments, the method of operating a non-formational RRAM device further includes: applying a second reset voltage to the second non-formational RRAM device to switch the second non-formational RRAM device from a third target resistance to a fourth target resistance. In some embodiments, performing the second set operation on the second non-formational RRAM device includes applying a second set voltage to the second non-formational RRAM device, wherein the second reset voltage and the second set voltage have opposite polarities.

[0024] In some embodiments, a second reset current through the second non-formation RRAM device in response to the second reset voltage is no greater than 500 μA, and the second reset voltage is no greater than 1.0V. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The present disclosure will be more fully understood from the detailed description given below and the accompanying drawings of various embodiments of the present disclosure. However, the accompanying drawings should not be used to limit the present disclosure to specific embodiments, but are only for explanation and understanding.

[0026] Figure 1A is a schematic diagram showing an example of a crossbar switch circuit according to some embodiments of the present disclosure.

[0027] Figure 1B is a schematic diagram showing an example of a cross-point device according to some embodiments of the present disclosure.

[0028] Figure 2A , 2B 2C show cross-sectional views of conventional RRAM devices that require a formation process to operate.

[0029] Figure 2D , 2E and 2F shows the combination Figure 2A , 2B and the current-voltage (IV) characteristics of a conventional RRAM device as described in 2C.

[0030] Figure 3 is a schematic diagram showing a cross-sectional view of an example of a non-formation-type RRAM device according to some embodiments of the present disclosure.

[0031] Figure 4 is a schematic diagram showing a cross-sectional view of a semiconductor device including an example of a non-formed RRAM device according to some embodiments of the present disclosure.

[0032] Figures 5A-5D is a graph showing IV characteristics of a first example of a non-formation-type RRAM device according to some embodiments of the present disclosure.

[0033] Figures 6A-6Dis a graph showing IV characteristics of a second example of a non-formation-type RRAM device according to some embodiments of the present disclosure.

[0034] Fig. 7A , 7B 7C are flowcharts illustrating an example of a process for operating a non-formed RRAM device according to some embodiments of the present disclosure.

[0035] Figure 8 is a flowchart showing an example of a process for manufacturing a non-formed RRAM device according to some embodiments of the present disclosure.

[0036] Figures 9A-9E Included are graphs showing IV characteristics of example RRAM devices having different device sizes and fabricated under the same annealing conditions.

[0037] Figures 9F-9J Included are graphs showing IV characteristics of example RRAM devices having the same device dimensions and fabricated under varying annealing conditions.

[0038] Fig.10 is an IV curve showing simulated behavior of an example non-formational RRAM device according to some embodiments of the present disclosure.

[0039] Fig.11 is a graph showing device read current characteristics over time for an example of a non-formed RRAM device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0040] Aspects of the present disclosure provide non-formational resistive random access memory (RRAM) devices and methods for manufacturing and operating non-formational RRAM devices.

[0041] The RRAM device is a two-terminal passive device with programmable resistance. The RRAM device may include a bottom electrode, a top electrode, and a switching oxide layer located between the bottom electrode and the top electrode. The bottom electrode may include a non-reactive metal, such as platinum (Pt), palladium (Pd), etc. The top electrode may include a reactive metal, such as tantalum (Ta), titanium (Ti), etc. The switching oxide layer may include a transition metal oxide, such as hafnium oxide (HfO x ) or tantalum oxide (TaO x ).

[0042] A conventional RRAM device behaves as an insulator in its original state (i.e., before appropriate stimulation after manufacturing). The conventional RRAM device can be transformed into a conductive state by a formation process including applying a high formation voltage (e.g., a voltage of 1.7V) to the conventional RRAM device. During the formation process, a conductive filament is formed in the conventional RRAM device. The RRAM device can then switch between two resistance states, such as a high resistance state (HRS) and a low resistance state (LRS), in response to a suitable programming signal (e.g., a voltage or current signal). The switching event from the HRS to the RRAM device is called a set process. The switching event from the LRS to the RRAM device is called a reset process. In a crossbar switch array circuit including an RRAM array, the programming signal can be provided to a specified RRAM device through a selector, such as a transistor.

[0043] Because the formation process involves the initial breakdown of the metal oxide in the switching oxide layer, the formation of the initial conductive filament during the formation process is a sudden process and requires a high formation voltage (e.g., a voltage of 1.7V). In some embodiments, the formation voltage may be higher than 2V to 3V to form a RRAM device with a thicker switching oxide layer. Due to the difficulty in controlling the size of the conductive filaments formed during the formation process, the formation process generally does not produce the desired device resistance. Conventional RRAM devices may need to be tuned in a subsequent reset process (also referred to as an "initial reset process") to obtain the desired device resistance. During the initial reset process, a high reset current is required to break the conductive filament. Therefore, conventional RRAM devices operate at high currents (e.g., currents higher than 1mA), which results in high power consumption and the need for relatively large transistors that can provide such high operating currents. The formation process is also time-consuming. For example, it may take several minutes to form a 256*256 RRAM array, resulting in a more time-consuming process for forming a crossbar switch circuit containing multiple 256*256 RRAM arrays. Furthermore, the formation of the initial conductive filaments during the formation process and the breaking of the initial conductive filaments during the initial reset process are both abrupt, which may lead to performance variations between devices.

[0044] Therefore, the present disclosure provides a non-formational RRAM and a method for marking and operating the non-formational RRAM. Unlike conventional RRAMs that require a formation process to be conductive, the non-formational RRAM described herein is conductive in its initial state and can be operated without forming a conductive filament. The non-formational RRAM device can have a medium to low resistance in its initial state, which can be read for determining appropriate programming parameters for subsequent operations (e.g., set operations, reset operations, etc.).

[0045] In some embodiments, the non-forming RRAM device may include an RRAM cell. The RRAM cell includes a bottom electrode, a top electrode, a switching oxide layer fabricated between the bottom electrode and the top electrode, and an interface layer fabricated between the switching oxide layer and the top electrode. The switching oxide layer may include one or more transition metal oxides, such as hafnium oxide, tantalum oxide, and the like. The interface layer may include one or more layers of a metal oxide that is more chemically stable than the transition metal oxide, such as aluminum oxide. The metal oxide in the interface layer does not react with the top electrode or the switching oxide. Therefore, the interface layer may control the reaction and diffusion between the top electrode and the switching oxide layer. The interface layer may include one or more continuous or discontinuous aluminum oxide layers.

[0046] The RRAM cell can be annealed to achieve non-formative behavior. For example, the RRAM cell can be annealed in one or more annealing processes, each of which involves annealing the RRAM cell in a forming gas environment (e.g., a mixture of N2 and H2) at an annealing temperature between 350 and 450°C for a suitable time (e.g., 15-30 minutes). The annealing can enhance diffusion and reaction between the top electrode and the switching oxide, while the interface layer can reduce diffusion and reaction between the top electrode and the switching oxide layer. The interface layer and the annealing conditions (e.g., temperature, annealing time, etc.) can be optimized by the device size (e.g., critical size) of the RRAM device to achieve the desired initial resistance of the RRAM device.

[0047] The resistance of the non-formed RRAM device can be programmed to multiple levels without a formation process. For example, in order to program the non-formed RRAM device to a target resistance, a read operation can be performed on the non-formed RRAM device to determine the initial resistance of the non-formed RRAM device. In some embodiments where the initial resistance is greater than the target resistance, the non-formed RRAM device can be programmed to the target resistance by applying a set voltage (e.g., a voltage of 0.6V) to the non-formed RRAM device without performing a formation process in advance. In some embodiments where the target resistance is greater than the initial resistance of the non-formed RRAM device, the non-formed RRAM device can be programmed to the target resistance by applying a reset voltage to the non-formed RRAM device. The reset current through the RRAM device may be 200μA. Reset is performed without performing a formation process or an initial setting process on the RRAM device in advance. The set voltage and the reset voltage may be of opposite polarity (e.g., positive and negative polarity). The non-formational RRAM device can switch between a high-resistance state and a low-resistance state in response to an ultra-low set voltage (eg, a voltage less than 1 V) and a reset current (eg, a reset peak current less than 200 μA).

[0048] Thus, the present disclosure provides a mechanism for fabricating and operating a non-formational RRAM device. By balancing material factors (e.g., thickness of the interface layer) and annealing factors (e.g., annealing conditions), the mechanism described herein provides a non-formational RRAM device that includes desirable properties, such as low power switching, low device-to-device performance variation, ultra-low operating current and voltage, high I on / I off The non-formed RRAM device described herein can enhance the stability of a crossbar array of RRAM devices, and can realize high-density memory and / or computing applications with low power consumption.

[0049] Figure 1A 1 is a schematic diagram showing an example 100 of a crossbar switch circuit according to some embodiments of the present disclosure. As shown in the figure, the crossbar switch circuit 100 may include a plurality of interconnected conductive lines for a crossbar array of n rows by m columns, such as one or more row lines 111a, 111b, ..., 111i, ..., 111n and column lines 113a, 113b, ..., 113j, ..., 113m. The crossbar switch circuit 100 may further include crosspoint devices 120a, 120b, ..., 120z, etc. Each crosspoint device may connect a row line and a column line. For example, the crosspoint device 120ij may connect a row line 111i and a column line 113j. In some embodiments, the crossbar switch circuit 100 may further include a digital-to-analog converter (DAC, not shown), an analog-to-digital converter (ADC, not shown), a switch (not shown), and one or more suitable circuit components for implementing a crossbar-based device. The number of column lines 113a-m and the number of row lines 111a-n may be the same or different.

[0050] The row lines 111 may include a first row line 111a, a second row line 111b, ..., 111i, ..., and an nth row line 111n. Each row line 111a, ..., 111n may be and / or include any suitable conductive material. In some embodiments, each row line 111a-n may be a metal line.

[0051] The column lines 113 may include a first column line 113a, a second column line 113b, ... and an mth column line 113m. Each column line 113a-m may be and / or include any suitable conductive material. In some embodiments, each column line 113a-m may be a metal line.

[0052] Each cross-point device 120 may be and / or include any suitable device having an adjustable resistance, such as a memristor, a phase change memory (PCM) device, a floating gate, a spintronic device, a resistive random access memory (RRAM), a static random access memory (SRAM), etc. In some embodiments, one or more of the cross-point devices 120 may include, for example, a combination of Figure 3-11 RRAM devices are described.

[0053] The crossbar switch circuit 100 can perform parallel weighted voltage multiplication and current summation. For example, an input voltage signal can be applied to one or more rows (e.g., one or more selected rows) of the crossbar switch circuit 100. The input signal can flow through the crosspoint devices of the rows of the crossbar switch circuit 100. The conductance of the crosspoint device can be adjusted to a specific value (also referred to as a "weighted value"). According to Ohm's law, the input voltage is multiplied by the crosspoint conductance and generates a current flowing through the crosspoint device. According to Kirchhoff's law, the sum of the currents through the devices on each column generates a current as an output signal, which can be read from the column (e.g., the output of an ADC). According to Ohm's law and Kirchhoff's current law, the input-output relationship of the crossbar array can be expressed as I=VG, where I is the output signal matrix, expressed as current; V is the input signal matrix, expressed as voltage; and G is the conductance matrix of the crosspoint device. Therefore, the input signal is weighted by its conductance at each crosspoint device according to Ohm's law. The weighted current is output through each column line and accumulated according to Kirchhoff's current law. This can be achieved by implementing parallel multiplication and summation in the crossbar array to achieve in-memory computing (IMC).

[0054] Figure 1B 1 is a schematic diagram showing an example 1200 of a crosspoint device according to some embodiments of the present disclosure. As shown in the figure, the crosspoint device 1200 can connect a bit line (BL) 1211, a select line (SEL) 1213, and a word line (WL) 1215. The bit line 1211 and the word line 1215 can be respectively connected to each other. Figure 1A The column and row lines are shown.

[0055] The cross-point device 1200 may include a RRAM device 1201 and a transistor 1203. The transistor is a three-terminal device, which may be labeled as a gate (G), a source (S), and a drain (D). The transistor 1203 may be connected in series to the RRAM device 1201. Figure 1BAs shown, the bottom electrode of the RRAM device 1201 can be connected to the drain of the transistor 1203. The top electrode of the RRAM device 1201 can be connected to the bit line 1211. The source of the transistor 1203 can be connected to the word line 1215. The gate of the transistor 1203 can be connected to the select line 1213. The RRAM device 1201 can include a combination of the following Figure 2A -5M describes one or more RRAM devices. The cross-point device 1200 may also be referred to as a one-transistor-one-resistor (1T1R) configuration. The transistor 1203 may be used as a selector and a current controller, which may set the current compliance of the RRAM device 1201 during programming. The gate voltage of the transistor 1203 may set the current compliance of the cross-point device 1200 during programming, and thus control the conductance and analog behavior of the cross-point device 1200. For example, when the cross-point device 1200 is set from a high-resistance state to a low-resistance state, a setting signal (e.g., a voltage signal, a current signal) may be provided via a bit line (BL) 1211. Another voltage, also referred to as a select voltage or a gate voltage, may be applied to the transistor gate via a select line (SEL) 1213 to turn on the gate and set the current compliance, while a word line (WL) 1215 may be set to ground. When the cross-point device 1200 is reset from a low-resistance state to a high-resistance state, a gate voltage may be applied to the gate of the transistor 1203 via a select line 1213 to turn on the transistor gate. At the same time, a reset signal may be sent to the RRAM device 1201 via the word line 1215 , while the bit line 1211 may be set to ground.

[0056] Figure 2A , 2B 200a and 200b respectively show cross-sectional views of conventional RRAM devices that require a forming process operation. RRAM devices 200a, 200b, and 200c may correspond to RRAM devices in an initial state, a low resistance state, and a high resistance state, respectively.

[0057] like Figure 2A As shown, the RRAM device 200a may include a bottom electrode 210, a switching oxide layer 220, and a top electrode 230. The bottom electrode 210 may include a suitable material that is electronically conductive and non-reactive to the switching oxide, such as Pt, Pd, etc. The switching oxide layer 220 may include one or more transition metal oxides such as TaO in binary oxides, ternary oxides, or higher-order oxides. x , HfO x 、TiO x 、NbO x 、ZrO xIn some embodiments, the chemical stability of the non-reactive metal in the bottom electrode 210 is higher than the chemical stability of the transition metal oxide in the switching oxide layer 220. The top electrode 230 may include any suitable metal material that is electronically conductive and reactive to the switching oxide. For example, the metal material in the top electrode 230 may include Ta, Hf, Ti, etc.

[0058] The RRAM device 200a can have a high initial resistance (e.g., several gigaohms or GΩ) and can therefore be considered an insulator in an initial state. The initial resistance of the RRAM device 200a can be changed, and the RRAM device 200a can be switched to a low resistance state through a formation process. For example, a formation voltage can be applied to the RRAM device 200a. The application of the voltage applied to the RRAM device 200a can cause the metal material in the top electrode to absorb oxygen ions in the switching oxide layer 220 and generate oxygen vacancies in the switching oxide layer. As a result, a conductive path (e.g., a conductive filament) rich in oxygen vacancies can be formed in the switching oxide layer 220. For example, as Figure 2B As shown, a conductive filament 225a is formed in the switching oxide layer 220. As shown, the conductive filament 225a can be formed across the switching oxide layer 220 from the top electrode 230 to the bottom electrode 210. The RRAM device 200b can be reset to a high resistance state. For example, a reset signal (e.g., a voltage signal or a current signal) can be applied to the RRAM device 200b during the reset process. In some embodiments, the set signal and the reset signal can have opposite polarities, i.e., a positive signal and a negative signal, respectively. The application of the reset signal can trigger the oxygen ions to migrate back to the switching oxide layer 220 and recombine with one or more oxygen vacancies. For example, during the reset process, a conductive filament 225a can be formed in the switching oxide layer 220 as shown. Figure 2C The conductive filament 225b is shown as interrupted. As shown, the conductive filament can be interrupted by interrupting the oxide gap between the conductive filament 225b and the bottom electrode 210. The lateral dimension of the conductive filament 225b can be smaller than the lateral dimension of the conductive filament 225a. The conductive filament 225b cannot continuously connect the bottom electrode 210 and the top electrode 230. The RRAM device 200b-c can be electrically switched between a high resistance state and a low resistance state by applying a suitable programming signal (e.g., a voltage signal, a current signal, etc.) to the RRAM device.

[0059] Figure 2D , 2E and 2F is shown in conjunction with Figure 2A-2C Graphs 200d, 200e, and 200f of current versus voltage (IV) characteristics of a conventional RRAM device are depicted. Figure 2D200d is an IV curve of a conventional RRAM device in its original state. As shown in the figure, the initial resistance of the conventional device is about 1.3GΩ at 0.2V. Therefore, the conventional RRAM device can be regarded as an insulator in its initial state. Figure 2E As shown, the voltage V can be applied to the RRAM device. form The formation process is performed by applying a reset voltage range 261. The formation voltage may be approximately 1.7 V. After the formation process, the RRAM device may be reset to a high impedance state in a reset process (also referred to as an "initial reset process") by applying a reset voltage range 261. During the initial reset process, the reset peak current through the RRAM device is approximately 1 mA. Figure 2F As shown, the RRAM device can be switched between a high resistance state and a low resistance state by applying a set voltage within a suitable voltage range 263 and a reset voltage within a voltage range 261, respectively. The set voltage shown can be approximately 0.7V. The reset peak current can be approximately 100μA. Therefore, forming a conventional RRAM device requires applying a high forming voltage. The reset peak current during the initial reset process is high. Conventional RRAM devices operate at a high operating current. The resistance of conventional RRAM devices cannot be switched without a forming process.

[0060] Figure 3 is a cross-sectional view showing an example of a non-formation-type RRAM cell 300 according to some embodiments of the present disclosure, where the RRAM cell 300 is also referred to herein as an RRAM device.

[0061] As shown, the RRAM cell 300 may include a substrate 310, a bottom electrode 320, a switching oxide layer 330, an interface layer 340, and a top electrode 350. The interface layer 340 is fabricated between the top electrode 350 and the switching oxide layer 330.

[0062] The substrate 310 may include one or more layers of any suitable material that can be used as a substrate for an RRAM device, such as silicon (Si), silicon dioxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), aluminum nitride (AlN), etc. In some embodiments, the substrate 310 may include diodes, transistors, interconnects, integrated circuits, etc. In some embodiments, the substrate may include one or more drive circuits (e.g., a circuit matrix) that can be individually controlled. In some embodiments, the drive circuit may include one or more complementary metal oxide semiconductor (CMOS) drivers.

[0063] Bottom electrode 320 may be and / or include any suitable material that is electronically conductive and non-reactive to the switching oxide, such as platinum (Pt), palladium (Pd), iridium (Ir), titanium nitride (TiN), tantalum nitride (TaN), etc.

[0064] The switching oxide layer 330 may include one or more transition metal oxides among binary oxides, ternary oxides, and advanced oxides, such as TaO x , HfO x 、TiO x ,NbO x 、ZrO x etc., where x can be used to indicate that the oxide is oxygen-deficient compared to its full (or terminal) oxide, and the value of x can vary depending on the oxygen to metal atomic ratio in the stoichiometry of the full oxide, such as HfO x x≤2.0 (where HfO2 is a full oxide) and TaO x x≤2.5 (where Ta2O5 is a full oxide). As an example, the switching oxide layer 330 may include Ta2O5 and / or HfO2.

[0065] The top electrode 350 may include any suitable metal material that is electronically conductive and reactive to the switching oxide. For example, the metal material in the top electrode 350 may include Ta, Hf, Ti, TiN, TaN, etc. The top electrode 350 may react to the switching oxide and have a suitable oxygen solubility to absorb part of the oxygen ions from the switching oxide layer 330 and generate oxygen vacancies in the switching oxide layer 330. That is, the reactive metal material in the top electrode 350 may have a suitable oxygen solubility and / or oxygen mobility. In some embodiments, the top electrode 350 is not only capable of generating oxygen vacancies in the switching oxide layer 330 (e.g., by scavenging oxygen), but may also be used as an oxygen storage or oxygen source for the switching oxide layer 330 during cell programming.

[0066] In one embodiment, the top electrode 350 may include one or more alloys. Each alloy may include two or more metal elements. Each of the alloys may include a binary alloy (e.g., an alloy including two metal elements), a ternary alloy (e.g., an alloy including three metal elements), a quaternary alloy (e.g., an alloy including four metal elements), a quinary alloy (e.g., an alloy including five metal elements), and / or a high-order alloy (e.g., an alloy containing more than six metal elements). In some embodiments, the top electrode 350 may include one or more alloys including a first metal element and one or more second metal elements. The reactivity of each second metal element to the transition metal oxide in the switching oxide layer may be lower or higher than that of the first metal element. In some embodiments, the first metal element may be Ta. The second metal element may include one or more of W, Hf, Mo, Nb, Zr, etc.

[0067] The interface layer 340 is in thermochemical equilibrium with the top electrode 350 and the switching oxide layer 330, and does not react with any of the top electrode 350 and the switching oxide layer 330. Therefore, the interface layer 340 can reduce diffusion and reaction with the top electrode 350 and the switching oxide layer 330. The interface layer 340 can be and / or include a film of a material that is more chemically stable than the transition metal oxide in the switching oxide layer. As a result, the material does not react with the transition metal oxide in the switching oxide layer 330. For example, the transition metal oxide in the switching oxide layer can be and / or include HfO x and / or TaO y , where x≤2.0 and y≤2.5, the interface layer 340 may include one or more layers of Al2O3, MgO, Y2O3, La2O3, etc. In some embodiments, the interface layer 340 may include a continuous film (e.g., a film having a thickness greater than or equal to 1 nm) of a material that is more chemically stable than a transition metal oxide. In some embodiments, the interface layer 340 may be discontinuous (e.g., a film having a thickness of 0.2 nm-0.6 nm).

[0068] The RRAM cell 300 may be annealed in one or more annealing processes to achieve the desired non-formative behavior. Each annealing process may involve annealing the RRAM device in a forming gas environment at a suitable temperature (e.g., 350-450°C) for a suitable period of time (e.g., 15-30 minutes). The forming gas may include a mixture of nitrogen (N2) and hydrogen (H2) in a suitable ratio (e.g., 95:5, 90:10, etc.). The thickness of the interface layer 340 may be determined based on the RRAM cell 300 (critical dimensions, device area, etc.) and annealing conditions. Smaller device sizes may require longer annealing times and / or thinner interface layers 340 to reduce the initial resistance of the non-formative RRAM.

[0069] Annealing can enhance diffusion and reaction between the top electrode 350 and the switching oxide layer 330, while the interface layer 340 can reduce diffusion and reaction between the top electrode 350 and the switching oxide layer 330. In view of the device size of the RRAM cell 300, balancing and / or optimizing the interface layer 340 and the thermal budget associated with annealing (e.g., annealing temperature, annealing time, etc.) can control the initial resistance of the RRAM cell 300 within a desired target range, and can achieve desired device behaviors, such as non-forming, low power switching, low device-to-device performance variation, etc. As combined Figures 9A-9JIn a more detailed description, the thickness of the interface layer 340 can be determined based on the device size and thermal budget of the RRAM cell 300. In some embodiments, the initial resistance of the non-formed RRAM cell 300 can be between about 1 kΩ and about 1 MΩ. In some embodiments, the initial resistance of the RRAM cell 300 can be hundreds of ohms to thousands of ohms (e.g., 500Ω-5 kΩ).

[0070] In some embodiments, the RRAM device 300 may be fabricated during a CMOS process. The thermal budget for annealing the RRAM cell 300 may be determined based on annealing conditions associated with the CMOS process. For example, Figure 4 As shown, the semiconductor device 400 may include a transistor 403 fabricated on a substrate 401 . The transistor 403 may include a source 403 a , a gate 403 b , and a drain 403 c . An interconnect layer 410 may be fabricated on the transistor 403 and the substrate 401 .

[0071] Each of the interconnection layers 410 may provide electrical connections between the transistor 403 and / or one or more other devices (e.g., one or more other transistors, the RRAM cell 300, one or more other RRAM devices, etc.). The interconnection layer 410 may include, for example, via layers (or via layers) 411, 412, 413, 414, and 415 and metal layers (or pad layers) 421, 423, 424, and 425. Each via layer may include one or more metal vias. Each metal via may include a suitable metal material, such as Al, Cu, W, etc. Each metal layer may include one or more metal pads and / or one or more metal lines. Each metal pad may include a suitable metal material, such as Al, Cu, W, etc. For example, the via layer 411 may include metal vias 411a, 411b, and 411c, which may be connected to the source 403a, gate 403b, and drain 403c of the transistor 403, respectively. In some embodiments, the via layer 411 may include a tungsten (W) via and a doped polycrystalline Si (poly-Si) terminal, wherein the polycrystalline Si terminal may be in direct contact with the gate 403b, the source 403a, and the drain 403c of the transistor 403. The tungsten via may be in direct contact with the poly-Si terminal. Other via layers and the metal layer above the via layer 411 may be made of Cu, W, Al, etc. The metal layer 421 may include metal pads 421a, 421b, and 421c. The metal pads 421a, 421b, and 421c may be connected to the metal vias 411a, 411b, and 411c, respectively. The metal layer 422 may include metal pads 422a, 422b, and 422c. The metal pads 422a, 422b, and 422c may be connected to the metal vias 412a, 412b, and 412c, respectively. As shown, a pair of adjacent metal layers may be connected via a via layer fabricated between the adjacent metal layers.

[0072] Fabricating the interconnect layer 410 may include fabricating a dielectric material layer using a suitable deposition technique, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), sputtering, etc. The dielectric layer may be patterned to produce one or more vias. One or more suitable metal materials may be deposited in the vias and patterned to fabricate one or more metal vias and / or metal pads. The metal vias and / or metal pads may then be annealed in a forming gas environment. In some embodiments, the via layer and the metal layer may be fabricated in a dual damascene fabrication process, wherein the metal vias and metal pads are fabricated and annealed together during the same metal deposition and patterning process.

[0073] For example, to fabricate the first via layer 411, a dielectric layer 451 may be fabricated on the substrate 401 and the transistor 403. The dielectric layer 451 may include any suitable dielectric material, such as silicon nitride (Si3N4), silicon dioxide (SiO2), etc. The dielectric layer 452 may be processed using any suitable deposition technique. For example, the dielectric layer 451 may be patterned and filled by metal deposition to fabricate metal vias 411a, 411b, and 411c in the dielectric layer 452.

[0074] The RRAM cell 300 can be manufactured during the manufacturing process of the interconnect layer 410, and thus can be referred to as a CMOS compatible RRAM device. For example, the RRAM cell 300 can be manufactured on a metal pad or metal via of the top interconnect layer of the first interconnect layer 410a. Then one or more second interconnect layers 410b can be manufactured on the RRAM cell 300 and the first interconnect layer 410a. More specifically, for example, a metal pad or metal via of the bottom interconnect layer of the second interconnect layer 410b can be manufactured on the RRAM cell 300 and can directly contact the RRAM cell.

[0075] Fabricating each second interconnect layer 410b may include annealing the second interconnect layer associated with the RRAM cell 300. In some embodiments, the via layer and the metal layer may be fabricated in a dual damascene fabrication process, wherein the metal via and the metal pad are fabricated and annealed together during the same metal deposition and patterning process. The interface layer 340 may have a suitable thickness to achieve the desired forming gas annealing (FGA) resistance. For example, a relatively thick interface layer may be more resistant to FGA than a relatively thin interface layer. In this way, the thermal budget for annealing the RRAM cell 300 may be determined based on the location of the RRAM cell, the number of second interconnect layers to be fabricated on the RRAM cell, and / or the annealing conditions for annealing the second interconnect layer. The thickness of the interface layer 340 may then be optimized based on the annealing conditions and the device size of the RRAM cell 300.

[0076] Although Figure 4 4. Certain interconnect layers (e.g., metal layers and via layers) are shown in FIG. 4, but this is merely illustrative. The first interconnect layer 410a and the second interconnect layer 410b may include any suitable number of interconnect layers. For example, in some embodiments, the RRAM cell 300 may be fabricated on the metal layer 413. In some embodiments, the semiconductor device 400 and / or the interconnect layer 410 may be fabricated using techniques described in U.S. patent application Ser. No. 17 / 848,238, filed on June 23, 2022, which is incorporated herein by reference.

[0077] Figures 5A-5D5 are graphs showing IV curves 500A, 500B, 500C, and 500D of a first example of a non-formational RRAM according to some embodiments of the present disclosure.

[0078] Figure 5A An IV curve 500A of an RRAM in an original state is shown. The horizontal axis of the IV curve 500A represents the read voltage applied to the RRAM device in the original state. The vertical axis of the IV curve 500A represents the current through the RRAM device during the application of the read voltage. As shown, the initial resistance of the RRAM device is about 4.5 kΩ at 0.2V.

[0079] like Figure 5B As shown, a reset voltage within a voltage range 511 may be applied to the RRAM device to switch the RRAM device from an initial resistance to a target resistance (also referred to as a "first target resistance") greater than the initial resistance. The initial resistance of the RRAM device is reset without performing a formation process or an initial setting process on the RRAM device in advance. For example, the resistance of the RRAM device may be reset to approximately 127 kΩ. Figure 5B As shown, the reset peak current through the RRAM device is less than 200 μA, and is significantly lower than the reset current required to reset a conventional RRAM device after formation.

[0080] After the reset process, the resistance of the RRAM device can be set to a second target resistance greater than the first target resistance. Figure 5C As shown, during the setting process, a setting voltage within a voltage range 513 can be applied to the RRAM device. In some embodiments, the setting voltage is about 0.6V. The setting voltage and the reset voltage have opposite polarities. In some embodiments, the resistance of the RRAM device is about 5.2kΩ at 0.2V after the setting process.

[0081] like Figure 5D As shown, at a set voltage within a voltage range 513 or a reset voltage within a voltage range 511, the resistance of the RRAM device can switch between a high resistance state 521 and a low resistance state 523. The set voltage may be about 0.6V. The reset peak current is about or less than 200μA. In some embodiments, the reset peak current is about or less than 500μA. Figures 5A-5D As shown, without the pre-forming process and the initial reset process, the RRAM device can be reset to the desired target resistance at a low initial reset peak current. on / I off than down-switching and operates at ultra-low current.

[0082] Figures 6A-6D6 is a graph showing current-voltage curves (IV curves) 600A, 600B, 600C, and 600D of a second example of a non-formational RRAM according to some embodiments of the present disclosure.

[0083] Fig. 6A An IV curve 600A of an RRAM in an initial state is shown. The horizontal axis of the IV curve 600A represents the read voltage applied to the RRAM device in the original state. The vertical axis of the IV curve 600A represents the current through the RRAM device during the application of the read voltage. The initial resistance of the RRAM device is about 19 kΩ at 0.2V.

[0084] like Figure 6B As shown, by applying a setting voltage within a voltage range 611, the RRAM device can be switched from an original state 621 to a low resistance state 623. For example, the setting voltage can be about 0.6V, which is much lower than the formation voltage required to electrically form a conventional RRAM device. After the setting process, the resistance of the RRAM device is about 8kΩ at 0.2V.

[0085] After the setup process, the RRAM device can be reset to a higher resistance by applying a reset voltage within a voltage range 613 to the RRAM device. The reset peak current may be less than 200 μA, which is significantly lower than the reset peak current required to reset a conventional device after formation. After reset, the resistance of the RRAM device may be approximately 100 kΩ.

[0086] like Figure 6C and 6D As shown, the RRAM device can be repeatedly turned on and off at a set voltage within a voltage range 611 or a reset voltage within a voltage range 613. For example, by applying a set voltage of 0.7V to the RRAM device, the resistance of the RRAM device can be set to about 5kΩ. In some embodiments, the set voltage can be about or less than 1V. As another example, the resistance of the RRAM device can be reset to about 100kΩ at a reset peak current of about or less than 200μA. Figures 6A-6D As shown, the RRAM device can be reset to a desired target resistance at a set voltage that is significantly lower than the formation voltage required during the formation process, and operate at low voltage and low current during subsequent switching events.

[0087] Fig. 7A is a flow chart illustrating an example process 700a for operating a non-formation RRAM device according to some embodiments of the present disclosure. The resistance of the non-formation RRAM device can be switched to one of multiple levels of resistance without a formation process.

[0088] At 710, a read operation may be performed to determine an initial resistance of the RRAM device. For example, one or more read voltages may be applied to the RRAM device in an initial state to determine the initial resistance of the RRAM device. The read voltage may be, for example, a voltage between 0.05-0.5V. It should be noted that, without previously performing a formation process, a read operation may not be performed on a conventional RRAM because the conventional RRAM is not conductive in its initial state.

[0089] At 720, the initial resistance may be compared to the target resistance to determine whether the initial resistance is greater than the target resistance. The target resistance may be a desired resistance or a weight to which the RRAM device is programmed.

[0090] In some embodiments, the target resistance may be greater than the initial resistance of the RRAM device. In such embodiments, step 700a may proceed to 730, and a reset operation may be performed to program the RRAM device to the target resistance. For example, a reset voltage may be applied to the RRAM device. The reset current may be hundreds of microamperes (μA). In combination with Figures 2A-2F Unlike the conventional RRAM device described above, the non-forming RRAM device can be programmed to a target resistance without a forming process and an initial reset process after the forming process.

[0091] In some embodiments, the initial resistance of the RRAM device may be greater than the target resistance. In such an embodiment, step 700a may proceed to 735, and a set operation may be performed on the RRAM device to program the RRAM device to the target resistance. For example, a set voltage may be applied to the RRAM device. In some embodiments, the set voltage may be approximately 0.3-0.7V. In some embodiments, the set voltage may be approximately 0.5-1V. Thus, the non-formation RRAM device may be set to a target resistance without requiring a formation process to generate a conductive filament in the RRAM device.

[0092] Figure 7B is a flow chart illustrating an example process 700b for operating a non-formational RRAM device (also referred to as a “first non-formational RRAM device”) according to some embodiments of the present disclosure.

[0093] At 740, a first read operation may be performed on the first non-formation RRAM device in an initial state to determine a first initial resistance of the first non-formation RRAM device. The first initial resistance represents a resistance of the first non-formation RRAM device in an initial state without undergoing a formation process. Performing the first read operation on the first non-formation RRAM device in the initial state includes applying one or more read voltages (e.g., a voltage of about 0.2 V) to the first non-formation RRAM device.

[0094] At 750, a first reset operation may be performed to program the first non-formed RRAM device to a first target resistance greater than the first original resistance. Performing the first reset operation may include applying a reset signal (e.g., a voltage signal, a current signal, etc.) to the first non-formed RRAM device. During the first reset operation, a reset peak current (also referred to as a "first reset current") through the first non-formed RRAM device may be about or less than 200 μA. In some embodiments, the first reset current may be about or less than 500 μA. The reset operation is performed without previously forming the first non-formed RRAM device in the formation process.

[0095] At 760, a first set operation may be performed on the first non-formed RRAM device to switch the first non-formed RRAM device from a first target resistance to a second target resistance. The first target resistance is greater than the second target resistance. Performing the first set operation may include applying a first set voltage to the first non-formed RRAM device. In some embodiments, the first set voltage is no greater than 0.7V. In some embodiments, the first set voltage is no greater than 1V.

[0096] refer to Figure 7C , a flow chart showing an example process 700c for operating a non-formation RRAM device having a medium resistance (“second non-formation RRAM device”) according to some embodiments of the present disclosure.

[0097] At 770, a second read operation may be performed on the second non-formed RRAM device in the initial state to determine an initial resistance of the second non-formed RRAM device ("second initial resistance"). The second initial resistance represents the resistance of the second non-formed RRAM device in an initial state without undergoing a formation process. Performing the second read operation on the second non-formed RRAM device includes applying one or more read voltages to the second non-formed RRAM device in the initial state.

[0098] At 780, a second setup operation may be performed to switch the second RRAM device from the second initial resistance to the third target resistance. The second initial resistance is greater than the third target resistance. The second setup operation is performed without previously performing a formation process on the second non-formed RRAM device. Performing the second setup operation may include applying a second setup voltage to the second non-formed RRAM device. In some embodiments, the second setup voltage is no greater than 0.7V.

[0099] At 790, a second reset operation may be performed to switch the second non-formed RRAM device from the third target resistance to a fourth target resistance. The fourth target resistance may be less than the third target resistance. The reset operation is performed without previously performing a formation process on the second non-formed RRAM device.

[0100] Figure 8 is a flow chart illustrating an example process 800 for fabricating a non-formational RRAM device according to some embodiments of the present disclosure.

[0101] At 810, a RRAM cell may be fabricated. The RRAM cell may include a bottom electrode, a switching oxide layer, a top electrode, and an interface layer fabricated between the switching oxide layer and the top electrode. The RRAM cell may be Figure 3 RRAM cell 300. In particular, at 811, a bottom electrode may be fabricated on the substrate. Fabricating the first electrode may include depositing one or more layers of one or more inactive metals, such as Pt, Pd, Ir, etc., using a physical vapor deposition (PVD) technique, a chemical vapor deposition technique, a sputtering deposition technique, an atomic layer deposition (ALD) technique, and / or any other suitable deposition technique. In some embodiments, fabricating the bottom electrode may involve depositing one or more layers of metal nitrides, such as TiN or TaN. The bottom electrode may be and / or include the above combined Figure 3 The bottom electrode 320 is described.

[0102] At 813, a switching oxide layer may be fabricated on the bottom electrode. The switching oxide layer may include one or more transition metal oxides. The transition metal oxide may include, for example, TaO x , HfO x 、TiO x 、NbO x 、ZrO x Etc. The switching oxide layer may be deposited using PVD, CVD, ALD, and / or any other suitable deposition technique.

[0103] At 815, an interfacial layer may be fabricated on the switching oxide layer. Fabricating the interfacial layer may include depositing a material that is more chemically stable than the transition metal oxide in the switching oxide layer, such as Al2O3, MgO, Y2O3, La2O3, etc. In one embodiment, fabricating the interfacial layer may include depositing a continuous layer of Al2O3, MgO, Y2O3, La2O3, etc. In another embodiment, fabricating the interfacial layer may include depositing a layer of material having a suitable thickness (e.g., a thickness between about 0.2 nm and about 0.6 nm) to form a discontinuous film of Al2O3, MgO, Y2O3, La2O3, etc. The interfacial layer may be deposited using PVD, CVD, ALD, and / or any other suitable deposition technique.

[0104] At 817, a top electrode may be fabricated on the interface layer. Fabricating the top electrode may include depositing one or more suitable metal materials that are conductive and react with the switching oxide in the switching oxide layer, such as Ta, Hf, Ti, TiN, TaN, etc. The top electrode may include one or more alloys. The top electrode may be fabricated using PVD, CVD, ALD, and / or any other suitable deposition technique.

[0105] The RRAM cell may be annealed at 830. For example, the RRAM cell may be annealed in one or more annealing processes, each of which may include annealing the RRAM cell in a forming gas environment (e.g., a mixture of N2 and H2) at a suitable annealing temperature (e.g., 350-450° C.) for a suitable time period (e.g., 15-30 minutes) for each annealing process.

[0106] In some embodiments, process 800 may further include 820, wherein one or more interconnect layers are fabricated on the top electrode. In such an embodiment, at 830, the RRAM cell may be annealed together with the interconnect layer. Fabricating each interconnect layer may include fabricating a dielectric material layer, such as Si3N4, SiO2, etc., using a suitable deposition technique, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma enhanced chemical vapor deposition (PECVD), sputtering, etc. The dielectric layer may be patterned to produce one or more vias. One or more suitable metal materials may be deposited in the vias and patterned to fabricate one or more metal vias and / or metal pads.

[0107] Figures 9A-9E is a graph showing IV characteristics of example RRAM devices having different device sizes and fabricated under the same annealing conditions.

[0108] IV curves 911, 913, and 915 show IV characteristics of a RRAM device having a critical dimension of 0.18 μm. IV curves 921, 923, and 925 show IV characteristics of a RRAM device having a critical dimension of 0.24 μm. IV curves 931, 933, and 935 show IV characteristics of a RRAM device having a critical dimension of 0.28 μm. The RRAM devices corresponding to IV curves 911, 921, and 931 do not include an interface layer. Each of the RRAM devices corresponding to IV curves 913, 923, and 933 includes a thin interface layer (e.g., a layer of 0.2nm–0.6nm). In some embodiments, the thin interface layer may be and / or include a discontinuous layer. Each of the RRAM devices corresponding to IV curves 915, 925, and 935 includes a thick interface layer (e.g., a layer of approximately or greater than 1 nm). As Fig. 9AAs shown, the RRAM device exhibits a varying resistance. The RRAM devices corresponding to IV curves 921, 931, 913, 923, and 933 are non-formed RRAM devices, and their initial resistances are approximately 549Ω, 543Ω, 7.5kΩ, 465Ω, and 460Ω, respectively.

[0109] Figures 9F-9J is a graph showing IV characteristics of example RRAM devices having the same device size (eg, a critical dimension of 0.24 μm) fabricated under different annealing conditions.

[0110] The RRAM devices corresponding to IV curves 941, 943, and 945 are manufactured without annealing. The RRAM devices corresponding to IV curves 951, 953, and 955 are manufactured under conditions of short annealing. The RRAM devices corresponding to IV curves 961, 963, and 965 are manufactured under conditions of long annealing. Each of the RRAM devices corresponding to IV curves 941, 951, and 961 does not include an interface layer. Each of the RRAM devices corresponding to IV curves 943, 953, and 963 includes a thin interface layer (e.g., a layer of 0.2nm–0.6nm). In some embodiments, the thin interface layer can be and / or include a discontinuous layer. Each of the RRAM devices corresponding to IV curves 945, 955, and 965 includes a thick interface layer (e.g., a layer of about or greater than 1nm). The RRAM devices corresponding to IV curves 951, 953, 961, and 963 are non-formed RRAM devices as described herein, and have initial resistances of approximately 549Ω, 460Ω, 389Ω, and 239Ω, respectively. Figures 9A-9B , the annealing conditions and the thickness of the interfacial layer can be optimized considering the device size to achieve the desired initial resistance.

[0111] Fig.10 1 is an IV curve 1000 showing analog behavior of an example of a non-formation RRAM device according to some embodiments of the present disclosure. As shown, the non-formation RRAM device exhibits desirable analog behavior, i.e., the device resistance can be tuned to multiple levels (or analog behavior) without a formation process by controlling the current compliance, and the current is linearly proportional to the voltage (or linear behavior) at each resistance state.

[0112] Fig.111100 is a graph showing device read current characteristics over time of an example non-formed RRAM device according to some embodiments of the present disclosure. Graph 1100 shows device read current characteristics of an example RRAM device at 135°C. Graph 1100 may represent device retention test results of the ability of the non-formed RRAM device to maintain resistance levels over time. Graph 1100 may also represent results of a read stability test as the RRAM device is under constant read (with a read voltage of 0.2V) due to its ability to maintain resistance levels over time.

[0113] For the sake of brevity of explanation, the method of the present disclosure is depicted and described as a series of actions. However, actions according to the present disclosure can occur in various orders and / or simultaneously, and occur together with other actions that are not proposed and described in the present disclosure. In addition, not all actions of explanation can be required to realize the method according to the disclosed subject matter. In addition, those skilled in the art will understand and recognize that the method can be represented as a series of mutual states via state diagrams or events alternatively.

[0114] As used herein, the terms "approximately," "about," and "substantially" may refer to within a normal tolerance range in the art, such as within 2 standard deviations of the mean, within ±20% of a target size in some embodiments, within ±10% of a target size in some embodiments, within ±5% of a target size in some embodiments, within ±2% of a target size in some embodiments, within ±1% of a target size in some embodiments, and within ±0.1% of a target size in some embodiments. The terms "approximately" and "about" may include a target size. Unless otherwise specified or apparent from the context, all numerical values ​​described herein are modified by the term "about."

[0115] As used herein, a range includes all values ​​within the range. For example, a range of 1 to 10 may include any number, combination of numbers, sub-ranges of numbers from 1, 2, 3, 4, 5, 6, 7, 8, 9 and 10, and fractions thereof.

[0116] The present disclosure has mentioned many details in the above description. However, it is obvious that the present disclosure can also be implemented without these specific details. In some examples, in order to highlight the content of the present invention, well-known structures and devices are shown in the form of block diagrams rather than specific details.

[0117] The terms "first", "second", "third", "fourth", etc. used in this document are marks used to distinguish different components and may not necessarily have the ordinal meaning of the numerical numbers used.

[0118] The word "example" or "exemplary" as used herein means serving as an example, instance or illustration. Any aspect or design described herein as "example" or "exemplary" is not necessarily to be understood as being more preferred or advantageous than other aspects or designs. On the contrary, the purpose of using the words "example" or "exemplary" is to present the concept in a concrete way. In this application, the term "or" means including "or" rather than excluding "or". That is, unless otherwise specified or as can be seen from the context, "X includes A or B" means any natural inclusive permutation and combination. That is, if X includes A; X includes B; or X includes A and B at the same time, then in any of the above cases, "X includes A or B" is satisfied. In addition, "one" and "an" used in this application and the appended claims should generally be understood as "one or more", unless otherwise specified or as can be clearly indicated from the context as being directed to a singular form. "One embodiment" or "an embodiment" mentioned in this specification means that a specific feature, structure or characteristic associated with the embodiment is included in at least one embodiment. Therefore, the phrases "one embodiment" or "an embodiment" appearing in different places in this specification do not necessarily all refer to the same embodiment.

[0119] As used herein, when an element or layer is referred to as being “on” another element or layer, the element or layer may be directly on the other element or layer, or intervening elements or layers may be present. In contrast, when an element or layer is referred to as being “directly on” another element or layer, there are no intervening elements or layers present.

[0120] Although it is obvious to those skilled in the art that additional changes and modifications may be made to the present disclosure after understanding the above description, it should be understood that any specific embodiments shown and described by way of illustration should not be considered limiting. Therefore, the details of various embodiments are not intended to limit the scope of the claims, which themselves merely describe the disclosed technical features.

Claims

1. A method for manufacturing a non-formation resistive random access memory (RRAM) device, comprising: Fabrication of the RRAM cell, including: fabricating a switching oxide layer comprising at least one transition metal oxide on the bottom electrode; fabricating an interfacial layer on the switching oxide layer, the interfacial layer comprising a material that is more chemically stable than the at least one transition metal oxide; fabricating a top electrode on the interface layer; The RRAM cell is annealed.

2. The method of claim 1, wherein the RRAM cell is annealed in a forming gas environment comprising N2 and H2. 3 . The method of claim 1 , wherein the RRAM cell is annealed at an annealing temperature between 350° C. and 450° C.

4. The method according to claim 1, further comprising: One or more interconnect layers are fabricated on the RRAM cell, wherein the RRAM cell is annealed together with the one or more interconnect layers. 5 . The method of claim 4 , wherein fabricating the one or more interconnect layers comprises fabricating metal pads or metal vias of the one or more interconnect layers on a top electrode of the RRAM cell.

6. The method of claim 4, wherein the RRAM cell and the one or more interconnect layers are annealed in a plurality of annealing processes, wherein the RRAM cell and the one or more interconnect layers are annealed in a forming gas at a temperature between 350° C. and 450° C. in each of the plurality of annealing processes.

7. The method of claim 1, wherein a thickness of the interface layer is determined based on a device size of the RRAM cell and a thermal budget associated with annealing, wherein the interface layer is configured to reduce diffusion and reaction between the top electrode and the switching oxide layer.

8. A non-formation resistive random access memory (RRAM) device comprising: bottom electrode; a switching oxide layer comprising at least one transition metal oxide; Top electrode; and an interfacial layer fabricated between the top electrode and the switching oxide layer, wherein the interfacial layer comprises a material that is more chemically stable than the at least one transition metal oxide, wherein the non-formational RRAM device is configured to be switched to a plurality of resistances in the absence of a formation process that generates conductive filaments in the switching oxide layer. 9 . The non-formational RRAM device of claim 8 , wherein the at least one transition metal oxide comprises at least one of HfO x or TaO y , wherein x≤2.0, and y≤2.

5.

10. The non-formational RRAM device of claim 9, wherein the interface layer comprises a layer of at least one of Al2O3, MgO, Y2O3, or La2O3. 11 . The non-formation-type RRAM device according to claim 10 , wherein the thickness of the interface layer is between 0.2 nm and 1 nm. 12 . The non-formation-type RRAM device according to claim 10 , wherein the thickness of the interface layer is greater than 1 nm. 13 . The non-formation RRAM device of claim 8 , wherein an initial resistance of the RRAM device is between 1 kΩ and 1 MΩ.

14. A method of operating a non-formation RRAM device, comprising: performing a first read operation on a first non-formation RRAM device in an initial state to determine a first initial resistance of the first non-formation RRAM device; A first reset operation is performed on the first non-formation RRAM device to switch the first non-formation RRAM device from a first initial resistance to a first target resistance, wherein the first target resistance is greater than the first initial resistance, and the first read operation and the first reset operation are performed without pre-forming a conductive filament in the first non-formation RRAM device during a formation process. 15 . The method of claim 14 , wherein a first reset current passing through the first non-formation RRAM device during the first reset operation is no greater than 500 μA.

16. The method according to claim 14, further comprising: A first set operation is performed on the first non-formation RRAM device to switch the first non-formation RRAM device from the first target resistance to a second target resistance, wherein performing the first set operation includes applying a first set voltage to the first non-formation RRAM device, and the first set voltage is not greater than 1.0V. 17 . The method of claim 16 , wherein performing a first reset operation on the first non-formation type RRAM device comprises applying a first reset voltage to the first non-formation type RRAM device, and the first set voltage and the first reset voltage have opposite polarities.

18. The method according to claim 14, further comprising: performing a second read operation on the second non-formation RRAM device to determine a second initial resistance of the second non-formation RRAM device; A second set operation is performed on the second non-formed RRAM device to switch the second non-formed RRAM device from a second initial resistance to a third target resistance, wherein the third target resistance is less than the second initial resistance, and the second read operation and the second set operation are performed without pre-forming a conductive filament in the second non-formed RRAM device during formation.

19. The method according to claim 18, further comprising: A second reset voltage is applied to the second non-formational RRAM device to switch the second non-formational RRAM device from a third target resistance to a fourth target resistance, wherein performing the second set operation on the second non-formational RRAM device includes applying a second set voltage to the second non-formational RRAM device, and the second reset voltage and the second set voltage have opposite polarities. 20 . The method of claim 19 , wherein a second reset current through the second non-formation RRAM device in response to the second reset voltage is no greater than 500 μA, and the second reset voltage is no greater than 1.0V.

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