Motor controller fault handling method, system, vehicle and storage medium

Abstract

This invention relates to the field of motor controller technology, specifically to a motor controller fault handling method, system, vehicle, and storage medium. The method includes: responding to the motor controller being in the power-on or running phase, and detecting a fault in the drive circuit through the main control chip of the motor controller, performing a fault recovery operation, and detecting whether the drive circuit fault has been cleared; if the drive circuit fault is detected to be cleared, the motor controller operates normally; if the drive circuit fault is detected to be not cleared, and the number of fault recovery operations performed is less than a preset threshold, then the fault recovery operation continues; if the drive circuit fault is detected to be not cleared, and the number of fault recovery operations performed is greater than or equal to the preset threshold, then a response action is performed according to a preset strategy based on the operating phase of the motor controller. This can eliminate the impact of drive chip and power module failures on electric drive operation, avoiding interference with the vehicle's current driving state.

Description

Technical Field

[0001] This invention relates to the field of motor controller technology, and specifically to a motor controller fault handling method, system, vehicle, and storage medium. Background Technology

[0002] Currently, motors are widely used in various application scenarios, and the stability and reliability of the motor controller, as one of the key devices for controlling motor operation, are crucial to the operation of the entire system. However, due to changes in the external environment or problems with the equipment itself, the power modules of the motor controller (such as insulated gate bipolar transistors, hereinafter referred to as IGBTs) may experience various abnormal states during operation, such as IGBT upper bridge power module failure, lower bridge power module failure, power module voltage failure, and power module current failure. The motor controller driver chip may also experience various failures during operation, such as driver chip overvoltage failure, driver chip overcurrent failure, and driver chip overheating failure. All of these failures directly affect the regulation capability of the motor control system, leading to a decrease in control accuracy. Furthermore, they may cause safety hazards such as overcurrent, overheating, and electrical fires, seriously affecting the normal operation of the motor system and, during driving, even endangering the driver's life.

[0003] Therefore, to eliminate the impact of control circuit faults on motor operation and prevent interference from drive chip and power module failures on motor operation, real-time monitoring of the motor controller's drive status and timely recovery through effective control are of significant theoretical and practical importance to avoid disturbing the vehicle's operating state.

[0004] CN202311567026 discloses a scheduling method, apparatus, and device. This method cyclically detects hardware fault signals and determines whether the cyclically detected hardware fault signals indicate a fault. If the cyclically detected hardware fault signals indicate a fault, the main control chip is controlled to enter an emergency interrupt. The emergency interrupt includes shutting down all control signals output by the main control chip, determining the fault type of the power conversion module, and executing a corresponding strategy based on the fault type. If the drive circuit is faulty, a strategy is executed to control the power conversion module to enter an active short-circuit state; if the drive circuit is not faulty, the power conversion module is controlled to switch from the active short-circuit state of the lower bridge arm to a shutdown state. This method only determines the fault of the motor controller and does not implement related fault recovery measures, which has the following drawbacks:

[0005] 1. Continuously detecting hardware fault signals causes the chip load rate of the control circuit to be too high, which wastes chip resources.

[0006] 2. The above-mentioned invention method enters an emergency interrupt after detecting a drive circuit fault, shutting down all control signals output by the main control chip, which causes significant interference to the vehicle's operating status and threatens driving safety, and requires a considerable amount of time to recover. Summary of the Invention

[0007] The purpose of this invention is to provide a method, system, vehicle, and storage medium for handling motor controller faults, which can eliminate the impact of drive chip and power module failures on electric drive operation and avoid interference with the current driving status of the vehicle.

[0008] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0009] In a first aspect, the present invention provides a method for handling motor controller faults, characterized in that it includes:

[0010] In response to the motor controller being in the power-on or running phase, and the main control chip of the motor controller detecting a fault in the drive circuit, a fault recovery operation is performed, and it is checked whether the fault in the drive circuit has been cleared.

[0011] If the fault in the drive circuit has been cleared, the motor controller will operate normally.

[0012] If the fault in the drive circuit is not cleared and the number of fault recovery operations performed is less than the preset threshold, then the fault recovery operation will continue.

[0013] If a fault in the drive circuit is detected and not cleared, and the number of fault recovery operations performed is equal to the preset threshold, then a response action will be executed according to the preset strategy based on the working stage of the motor controller.

[0014] Furthermore, the power-on phase of the motor controller includes, in sequence, a preliminary detection phase, a fault register detection phase, a driver chip self-test phase, and a parameter register configuration phase;

[0015] In response to the motor controller entering the preliminary detection stage, the main control chip of the motor controller detects whether there is a fault in the output I / O port level of the drive circuit; if so, a reset operation is performed on the register of the drive circuit, and it is checked whether the fault in the output I / O port level of the drive circuit is cleared; if not, the motor controller enters the fault register detection stage.

[0016] In response to the motor controller entering the fault register detection phase, the main control chip of the motor controller reads the parameters in the fault register to determine whether there is a fault in the fault register; if so, the motor controller is powered down and then powered on again; if not, the motor controller enters the driver chip self-test phase.

[0017] In response to the motor controller entering the driver chip self-test stage, the main control chip of the motor controller controls the driver chip of the drive circuit to enter the self-test mode to determine whether there is a fault in the self-test result; if so, the motor controller is powered down and then powered on again; if not, the motor controller enters the parameter register configuration stage.

[0018] In response to the motor controller entering the parameter register configuration stage, the target parameters and set levels in the parameter register of the driver chip are configured through the main control chip of the motor controller. After the configuration is completed, a timer is started and the configuration is judged to be successful. If successful, the motor controller is powered on. If not, the target parameters in the parameter register are read again and compared with the preset parameters.

[0019] Furthermore, in response to the motor controller being in the preliminary detection stage and the number of times the register of the drive circuit is reset is equal to a preset threshold, the motor controller is powered on again after being powered off.

[0020] When the motor controller is in the preliminary detection stage, fault register detection stage, or driver chip self-test stage, and the number of times the motor controller is powered on and off after being powered off is equal to the preset number threshold, the motor controller enters the parameter register configuration stage.

[0021] In response to the motor controller being in the parameter register configuration stage and the number of times the target parameter in the parameter register is read again equal to the preset number threshold, it is determined whether the timing time is less than the preset time threshold. If so, the motor controller is powered off and then powered on again; otherwise, the motor controller is powered on.

[0022] Furthermore, in response to the motor controller being in operation and the main control chip of the motor controller detecting a fault in the drive circuit, and identifying the fault type as a recoverable or unrecoverable fault, the corresponding fault recovery operation is performed according to the fault type.

[0023] Furthermore, in response to a recoverable fault, the corresponding fault recovery operation is as follows: clear the fault code corresponding to the recoverable fault in the fault register and reconfigure the parameter register of the drive circuit.

[0024] Furthermore, in response to an unrecoverable fault and a wheel speed less than a preset threshold, the corresponding fault recovery operation is as follows: control the battery to supply power to the motor, clear the fault code corresponding to the unrecoverable fault in the fault register, and reconfigure the parameter register of the drive circuit.

[0025] In response to an unrecoverable fault type and a wheel speed greater than or equal to a preset threshold, the corresponding fault recovery operation is as follows: the main control chip stops sending control signals to the drive chip of the drive circuit.

[0026] Furthermore, in response to the motor controller being in the power-on or running phase, and when the main control chip of the motor controller detects a fault in the drive circuit, the main control chip stops sending control signals to the drive chip of the drive circuit; after the fault is cleared, the main control chip resends control signals to the drive chip.

[0027] Secondly, the present invention provides a motor controller fault handling system, including a fault detection module and a fault handling module. The fault detection module is arranged in the main control chip of the motor controller and is used to detect whether there is a fault in the drive circuit; and after performing a fault recovery operation, it detects whether the drive circuit fault is cleared; if the drive circuit fault is cleared, the motor controller operates normally; if the drive circuit fault is not cleared and the number of fault recovery operations is less than a preset threshold, the fault recovery operation continues; if the drive circuit fault is not cleared and the number of fault recovery operations is greater than or equal to the preset threshold, a response action is performed according to a preset strategy based on the working stage of the motor controller; the fault handling module, in response to the motor controller being in the power-on or running stage and detecting a fault in the drive circuit through the main control chip of the motor controller, performs a fault recovery operation.

[0028] Thirdly, the present invention provides a vehicle including the aforementioned motor controller fault handling system.

[0029] Fourthly, the present invention provides a computer-readable storage medium storing computer-readable instructions thereon, which, when executed by a computer's processor, cause the computer to perform the aforementioned motor controller fault handling method.

[0030] The present invention has the following unexpected beneficial effects:

[0031] 1. This invention detects whether there is a fault in the drive circuit through the main control chip of the motor controller, avoiding the excessive load rate caused by the drive chip of the drive circuit repeatedly detecting hardware fault signals, which would waste the drive chip resources.

[0032] 2. This invention performs fault monitoring of the drive circuit during both power-on and operation phases, effectively reducing the risk of motor controller failure during operation. Furthermore, when a motor controller failure occurs, it not only performs fault recovery operations to avoid interfering with the vehicle's current driving state, but also records and limits the number of fault recovery operations to prevent repeated fault recovery from damaging the motor controller module, thus ensuring the continuity and reliability of the motor controller. Attached Figure Description

[0033] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention.

[0034] Figure 1 A flowchart of a motor controller fault handling method provided in an embodiment of the present invention is shown;

[0035] Figure 2 A flowchart of a fault handling method for a motor controller during the power-on phase, provided in an embodiment of the present invention, is shown.

[0036] Figure 3 A flowchart of a fault handling method for a motor controller during operation, provided in an embodiment of the present invention, is shown.

[0037] Figure 4 A general framework diagram of the motor controller provided in an embodiment of the present invention is shown;

[0038] Figure 5 A schematic diagram of the motor controller fault handling system provided in an embodiment of the present invention is shown. Detailed Implementation

[0039] The embodiments of the present invention will be described below with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are only for illustrating the present invention and not for limiting the scope of protection of the present invention.

[0040] In one embodiment, see Figure 1 As shown, the present invention provides a method for handling motor controller faults, including:

[0041] In response to the motor controller being in the power-on or running phase, and the main control chip of the motor controller detecting a fault in the drive circuit, a fault recovery operation is performed, and it is checked whether the fault in the drive circuit has been cleared.

[0042] If the fault in the drive circuit has been cleared, the motor controller will operate normally.

[0043] If the fault in the drive circuit is not cleared and the number of fault recovery operations performed is less than the preset threshold, then the fault recovery operation will continue.

[0044] If a fault in the drive circuit is detected and not cleared, and the number of fault recovery operations performed is greater than or equal to a preset threshold, then a response action will be executed according to a preset strategy based on the working stage of the motor controller.

[0045] The motor controller fault handling method described in this invention mainly consists of three core steps: fault detection, fault recovery attempt, and power-down hibernation if the fault remains unresolved. This phased approach can restore the system to a normal state as much as possible, and also take protective measures after multiple failed attempts, that is, execute response actions according to a preset strategy based on the current operating stage of the motor controller to prevent further damage or safety risks.

[0046] The specific steps are explained in detail below.

[0047] Fault Detection: When the motor controller is powered on or running, the main control chip continuously monitors the status of the drive circuit. Because this invention uses the main control chip of the motor controller to detect faults in the drive circuit, it avoids the drive chip repeatedly detecting hardware fault signals, which could lead to excessive load and waste of drive chip resources.

[0048] Once a fault is detected in the drive circuit (such as short circuit, open circuit, overcurrent, etc.), the main control chip will immediately trigger the fault handling process.

[0049] Fault recovery operations: Once a fault is confirmed, the main control chip will execute preset fault recovery operations. These operations may include reconfiguring the driver logic or attempting a software reset, designed to eliminate or bypass the current fault.

[0050] After performing the fault recovery operation, the main control chip will check the status of the drive circuit again to confirm whether the fault has been cleared.

[0051] Fault clearance confirmation and follow-up processing: If the fault has been cleared, it means that the fault recovery operation was effective and the motor controller will continue to operate normally. At the same time, the fault handling process is recorded for subsequent analysis.

[0052] If the fault is not cleared and the number of recovery attempts is less than the preset threshold, it indicates that the current fault recovery operation has not completely resolved the problem, but it is still necessary to try again. Therefore, the main control chip will repeatedly execute the fault recovery operation until the preset maximum number of attempts is reached or the fault is successfully cleared.

[0053] If the fault is not cleared and the number of recovery attempts reaches or exceeds a preset threshold, the main control chip will execute a response action based on the current operating stage of the motor controller according to a preset strategy to avoid further damage or safety risks caused by continuous fault handling. This response action includes, but is not limited to, powering on and off the motor controller, or stopping the motor controller. This step ensures the safety and stability of the system when the fault cannot be recovered, and also provides a basis for subsequent troubleshooting and maintenance.

[0054] This invention performs fault monitoring of the drive circuit during both the power-on and operation phases of the motor controller, effectively reducing the risk of motor controller failure during operation. Furthermore, when a motor controller failure occurs, it not only performs fault recovery operations to avoid interfering with the vehicle's current driving state, but also records and limits the number of fault recovery operations to prevent repeated fault recovery from damaging the motor controller module, thus ensuring the continuity and reliability of the motor controller.

[0055] In summary, the motor controller fault handling method provided by this invention not only improves the reliability and safety of the motor control system, but also reduces maintenance costs and downtime risks, and has broad application prospects.

[0056] In a preferred embodiment, the power-on phase of the motor controller includes a preliminary detection phase, a fault register detection phase, a driver chip self-test phase, and a parameter register configuration phase, which are set sequentially.

[0057] See Figure 2 As shown, in response to the motor controller entering the preliminary detection stage, the main control chip of the motor controller detects whether there is a fault in the output I / O port level of the drive circuit; if so, a reset operation, i.e., a fault recovery operation, is performed on the register of the drive circuit, and it is checked whether the fault in the output I / O port level of the drive circuit is cleared; if not, the motor controller enters the fault register detection stage.

[0058] In response to the motor controller entering the fault register detection phase, the main control chip of the motor controller reads the parameters in the fault register to determine whether a fault exists in the fault register. If so, the motor controller is powered down and then powered on again; otherwise, the motor controller enters the driver chip self-test phase. It should be noted that before the motor controller enters the driver chip self-test phase, the fault register is configured with parameters according to a preset strategy to ensure that the fault register can monitor the fault status of the driver chip in real time when the motor controller is working.

[0059] In response to the motor controller entering the driver chip self-test stage, the main control chip of the motor controller controls the driver chip of the drive circuit to enter the self-test mode to determine whether there is a fault in the self-test result; if so, the motor controller is powered down and then powered on again; if not, the motor controller enters the parameter register configuration stage.

[0060] In response to the motor controller entering the parameter register configuration stage, information related to the reset operation in the driver chip is first cleared to prevent it from being identified as a motor controller malfunction later. Then, the target parameters and set levels in the parameter register of the driver chip are configured through the main control chip of the motor controller. After configuration, a timer is started to determine whether the configuration is successful; if so, the motor controller is powered on; if not, the target parameters in the parameter register are reread and compared with the preset parameters.

[0061] Further, see Figure 2 As shown, in response to the motor controller being in the preliminary detection phase and the number of times the drive circuit registers are reset equal to a preset threshold, the motor controller is powered down and then powered on again. Conversely, after resetting the drive circuit registers, the drive circuit output I / O port is re-detected for faults. For example, the preset threshold for the preliminary detection phase is three times.

[0062] When the motor controller is in the preliminary detection stage, fault register detection stage, or driver chip self-test stage, and the number of times the motor controller is powered on and off after power-off equals a preset threshold, the motor controller enters the parameter register configuration stage. This avoids the motor controller repeatedly powering on and off, which would affect fault handling efficiency.

[0063] In response to the motor controller being in the parameter register configuration phase and the number of times the target parameter in the parameter register is reread equal to a preset threshold, it is determined whether the timing time is less than a preset time threshold. If so, the motor controller is powered down and then powered on again; otherwise, the motor controller is powered on. For example, the preset threshold for the number of times the target parameter in the parameter register is reread during the parameter register configuration phase is three, and the preset time threshold is three seconds.

[0064] In summary, this segmented power-on phase and extended fault handling logic not only improve the stability and reliability of the motor controller, but also enhance its self-diagnosis and self-recovery capabilities, helping to reduce downtime caused by hardware failures or configuration errors.

[0065] In a preferred embodiment, see Figure 3 As shown, in response to the motor controller being in operation and the main control chip of the motor controller detecting a fault in the drive circuit, and identifying the fault type as a recoverable fault or an unrecoverable fault, the corresponding fault recovery operation is performed according to the fault type.

[0066] Furthermore, in response to a recoverable fault, the corresponding fault recovery operation involves reconfiguring the registers of the drive circuit. This reconfiguration may involve adjusting control parameters, changing the operating mode, or applying a backup configuration to eliminate or bypass the current fault, enabling the drive circuit to resume normal operation.

[0067] Furthermore, in response to an unrecoverable fault, the main control chip will determine what recovery operation to take based on the wheel's rotational speed.

[0068] In response to an unrecoverable fault and a wheel speed below a preset threshold, the main control chip will, to minimize the impact on vehicle operation, direct the battery to supply power directly to the motor while attempting to reconfigure the drive circuit registers. This setup aims to maintain the motor's basic operational capability, even if the drive circuit itself may not fully recover. Direct battery power supply ensures the vehicle can be slowly driven to a safe area or undergo further repairs.

[0069] In response to an unrecoverable fault type and a wheel speed greater than or equal to a preset threshold, it indicates that the vehicle is traveling at a relatively high speed. At this point, continuing to attempt to restore the drive circuit could pose a greater safety risk. Therefore, the main control chip will take a more conservative approach: disconnecting from the drive chip and ceasing to send control signals to the drive circuit's drive chip to ensure the safety of the vehicle and passengers. This also provides an opportunity for subsequent troubleshooting and repair.

[0070] For example, the preset threshold for the wheel speed is set to 100 r / min.

[0071] In a preferred embodiment, see Figure 4 As shown, the motor controller includes a main control chip and a drive circuit connected to the main control chip. The main control chip includes an output processing module, a parameter setting module, a fault reporting module, a fault detection module, and a fault handling module. The main control chip controls six drive chips in the drive circuit through six channels of PWM (Pulse Width Modulation). Each drive chip individually controls an IGBT. By controlling the on / off state of each IGBT, the DC-to-AC conversion is achieved, thereby driving the motor. The status of the drive circuit is acquired through a communication bus, and the level changes of the drive circuit's output I / O ports are acquired through AD converters. Faults during motor operation are triggered by an external interrupt pin in the drive circuit.

[0072] The output processing module controls the output I / O port of the main control chip to send a pulse width modulation waveform to the drive circuit. The drive circuit then controls the switching of the IGBT through the drive module according to the PWM frequency.

[0073] The parameter setting module configures the parameters of each part of the drive chip based on the working characteristics of the motor controller itself and the requirements of the control system to ensure that the motor controller can operate normally.

[0074] The fault reporting module inputs fault information during the power-on or operation phase of the motor controller to the main control chip to monitor the current fault status of the motor controller.

[0075] After the motor controller is powered on or running, the fault detection module monitors the operating status of the entire drive circuit in real time. When a fault occurs, it monitors and classifies the real-time fault data to prepare for subsequent fault handling and take further targeted measures.

[0076] The fault handling module processes abnormal situations according to different fault types and a preset control strategy.

[0077] In a preferred embodiment, the measure of stopping the main control chip from sending control signals to the drive chip of the drive circuit when the motor controller is in the power-on or running phase and the main control chip of the motor controller detects a fault in the drive circuit is intended to prevent the drive circuit in a faulty state from continuing to operate after receiving the control signal, which could lead to further damage or safety risks.

[0078] Stopping the transmission of control signals prevents further damage, ensures safety, and facilitates troubleshooting. Continuing to send control signals to a faulty drive circuit may perpetuate or even worsen the fault, leading to more serious hardware damage. Stopping control signal transmission ensures that the motor and its drive system do not operate in unsafe conditions, thus protecting the safety of the vehicle and its passengers. After stopping control signal transmission, the cause of the drive circuit fault becomes easier to locate and analyze, facilitating subsequent troubleshooting and repair.

[0079] After the fault is cleared, the main control chip resends control signals to the drive chip, enabling the motor controller to resume normal operation. This recovery process typically involves a comprehensive inspection and testing of the drive circuitry to ensure it has been fully restored to normal operating condition.

[0080] The main control chip needs to continuously monitor the status of the drive circuit, including key parameters such as voltage, current, and temperature, to promptly detect potential faults. Once a fault is detected, the main control chip should react quickly, ceasing to send control signals to the drive chip and potentially triggering a fault alarm mechanism simultaneously. Furthermore, the main control chip should record the time, type, and location of the fault for subsequent analysis and improvement. Before the fault is cleared and control signals are resent, the drive circuit should undergo a comprehensive inspection and testing to ensure it has returned to a reliable operating state.

[0081] In this way, the motor controller can respond more intelligently to drive circuit failures, improving the reliability and safety of the system.

[0082] In a preferred embodiment, the drive circuit fault includes a drive circuit power module fault and a drive circuit driver chip fault. For example, the drive circuit power module fault includes an IGBT upper bridge power module fault, a lower bridge power module fault, a power module voltage fault, and a power module current fault; the drive circuit driver chip fault includes a driver chip overvoltage fault, a driver chip overcurrent fault, and a driver chip overheating fault.

[0083] In one embodiment, the present invention provides a motor controller fault handling system, see [link to relevant documentation]. Figure 5 As shown, the fault handling system 10 includes a fault detection module 11 and a fault handling module 12. The fault detection module 11 is located in the main control chip of the motor controller and is used to detect whether a fault exists in the drive circuit; and after performing a fault recovery operation, it detects whether the drive circuit fault has been cleared; if the drive circuit fault is cleared, the motor controller operates normally; if the drive circuit fault is not cleared and the number of fault recovery operations is less than a preset threshold, the fault recovery operation continues; if the drive circuit fault is not cleared and the number of fault recovery operations is greater than or equal to the preset threshold, a response action is executed according to a preset strategy based on the operating stage of the motor controller. The fault handling module 12 responds to the motor controller being in the power-on or running stage, and when a fault is detected in the drive circuit through the main control chip of the motor controller, it performs a fault recovery operation.

[0084] In one embodiment, the present invention also provides a vehicle including the above-described motor controller fault handling system.

[0085] In one embodiment, the present invention also provides a computer-readable storage medium storing computer-readable instructions thereon, which, when executed by a computer's processor, cause the computer to perform the above-described motor controller fault handling method.

[0086] The above embodiments are merely preferred embodiments provided to fully illustrate the present invention, and the scope of protection of the present invention is not limited thereto. Equivalent substitutions or modifications made by those skilled in the art based on the present invention are all within the scope of protection of the present invention.

Claims

1. A method for handling motor controller faults, characterized in that, include: In response to the motor controller being in the power-on or running phase, and the main control chip of the motor controller detecting a fault in the drive circuit, a fault recovery operation is performed, and it is checked whether the fault in the drive circuit has been cleared. If the fault in the drive circuit has been cleared, the motor controller will operate normally. If the fault in the drive circuit is not cleared and the number of fault recovery operations performed is less than the preset threshold, then the fault recovery operation will continue. If a fault in the drive circuit is detected and not cleared, and the number of fault recovery operations is equal to the preset threshold, then a response action will be executed according to the preset strategy based on the working stage of the motor controller. The power-on phase of the motor controller includes, in sequence, a preliminary detection phase, a fault register detection phase, a driver chip self-test phase, and a parameter register configuration phase. In response to the motor controller entering the preliminary detection stage, the main control chip of the motor controller detects whether there is a fault in the output I / O port level of the drive circuit; if so, a reset operation is performed on the register of the drive circuit, and it is checked whether the fault in the output I / O port level of the drive circuit is cleared; if not, the motor controller enters the fault register detection stage. In response to the motor controller entering the fault register detection phase, the main control chip of the motor controller reads the parameters in the fault register to determine whether there is a fault in the fault register; if so, the motor controller is powered down and then powered on again. If not, the motor controller enters the driver chip self-test stage; In response to the motor controller entering the self-test stage of the drive chip, the main control chip of the motor controller controls the drive chip of the drive circuit to enter the self-test mode to determine whether there is a fault in the self-test result; If so, the motor controller will be powered off and then powered on again; If not, the motor controller enters the parameter register configuration stage; In response to the motor controller entering the parameter register configuration stage, the target parameters and set levels in the parameter register of the driver chip are configured through the main control chip of the motor controller. After the configuration is completed, a timer is started and the configuration is judged to be successful. If successful, the motor controller is powered on. If not, the target parameters in the parameter register are read again and compared with the preset parameters.

2. The motor controller fault handling method according to claim 1, characterized in that: If the motor controller is in the initial detection stage and the number of times the register of the drive circuit is reset is equal to the preset number threshold, the motor controller will be powered off and then powered on again. When the motor controller is in the preliminary detection stage, fault register detection stage, or driver chip self-test stage, and the number of times the motor controller is powered on and off after being powered off is equal to the preset number threshold, the motor controller enters the parameter register configuration stage. In response to the motor controller being in the parameter register configuration stage and the number of times the target parameter in the parameter register is read again equal to the preset number threshold, it is determined whether the timing time is less than the preset time threshold. If so, the motor controller is powered off and then powered on again; otherwise, the motor controller is powered on.

3. The motor controller fault handling method according to claim 1, characterized in that: In response to the motor controller being in operation and the main control chip of the motor controller detecting a fault in the drive circuit, and identifying the fault type as either a recoverable or unrecoverable fault, the corresponding fault recovery operation is performed according to the fault type.

4. The motor controller fault handling method according to claim 3, characterized in that: In response to a fault type that is recoverable, the corresponding fault recovery operation is to clear the fault code corresponding to the recoverable fault in the fault register and reconfigure the parameter register of the drive circuit.

5. The motor controller fault handling method according to claim 3, characterized in that: In response to an unrecoverable fault and a wheel speed less than a preset threshold, the corresponding fault recovery operation is as follows: control the battery to supply power to the motor, clear the fault code corresponding to the unrecoverable fault in the fault register, and reconfigure the parameter register of the drive circuit. In response to an unrecoverable fault type and a wheel speed greater than or equal to a preset threshold, the corresponding fault recovery operation is as follows: the main control chip stops sending control signals to the drive chip of the drive circuit.

6. The motor controller fault handling method according to claim 1, characterized in that: When the motor controller is powered on or running, and the main control chip of the motor controller detects a fault in the drive circuit, the main control chip stops sending control signals to the drive chip of the drive circuit; after the fault is cleared, the main control chip resumes sending control signals to the drive chip.

7. A motor controller fault handling system, characterized in that, include: The fault detection module, located in the main control chip of the motor controller, is used to detect whether there is a fault in the drive circuit. And after performing the fault recovery operation, check whether the drive circuit fault has been cleared; If the drive circuit fault is detected to have been cleared, the motor controller will operate normally; if the drive circuit fault is detected to have not been cleared, and the number of fault recovery operations performed is less than the preset threshold, the fault recovery operation will continue; if the drive circuit fault is detected to have not been cleared, and the number of fault recovery operations performed is greater than or equal to the preset threshold, the response action will be executed according to the preset strategy based on the working stage of the motor controller. The fault handling module, in response to the motor controller being in the power-on or running phase, and detecting a fault in the drive circuit through the main control chip of the motor controller, performs a fault recovery operation; The power-on phase of the motor controller includes, in sequence, a preliminary detection phase, a fault register detection phase, a driver chip self-test phase, and a parameter register configuration phase. In response to the motor controller entering the preliminary detection stage, the main control chip of the motor controller detects whether there is a fault in the output I / O port level of the drive circuit; if so, a reset operation is performed on the register of the drive circuit, and it is checked whether the fault in the output I / O port level of the drive circuit is cleared; if not, the motor controller enters the fault register detection stage. In response to the motor controller entering the fault register detection phase, the main control chip of the motor controller reads the parameters in the fault register to determine whether there is a fault in the fault register; if so, the motor controller is powered down and then powered on again. If not, the motor controller enters the driver chip self-test stage; In response to the motor controller entering the self-test stage of the drive chip, the main control chip of the motor controller controls the drive chip of the drive circuit to enter the self-test mode to determine whether there is a fault in the self-test result; If so, the motor controller will be powered off and then powered on again; If not, the motor controller enters the parameter register configuration stage; In response to the motor controller entering the parameter register configuration stage, the target parameters and set levels in the parameter register of the driver chip are configured through the main control chip of the motor controller. After the configuration is completed, a timer is started and the configuration is judged to be successful. If successful, the motor controller is powered on. If not, the target parameters in the parameter register are read again and compared with the preset parameters.

8. A vehicle, characterized in that, Includes the motor controller fault handling system as described in claim 7.

9. A computer-readable storage medium, characterized in that, It stores computer-readable instructions, which, when executed by the computer's processor, cause the computer to perform the motor controller fault handling method as described in any one of claims 1 to 6.

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