Silicon wafer defect detection method

Abstract

The invention relates to a silicon wafer defect detection method. The method comprises the following steps: providing a silicon wafer sample with oxygen concentration lower than 9ppma; carrying out first heat treatment on the silicon wafer sample under a first preset condition so as to generate oxygen evolution nucleation in a P-band region, a B-band region and / or an IDP region; performing secondary heat treatment on the silicon wafer sample under a second preset condition to generate oxygen evolution nucleation in a VDP region; performing third-time heat treatment on the silicon wafer sample under a third preset condition, so that oxygen evolution nuclei generated in the first-time heat treatment and the second-time heat treatment grow; and carrying out minority carrier lifetime test on the silicon wafer sample. Through a three-section heat treatment method, the oxygen precipitation amount of a part of crystal characteristic areas is increased, so that crystal characteristic area boundary distinguishing can be clearly carried out on a silicon wafer with the oxygen concentration below 9ppma.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor product manufacturing, and in particular to a silicon wafer defect detection method. Background Art

[0002] Since growth defects such as COP (Crystal Originated Particles) and LDP (Interstitial Dominant Pure) in CZ-Si (silicon crystal grown by the Czochralski method) are directly related to device failures such as leakage current or oxide breakdown, the wafer containing areas where growth defects are likely to occur is removed as much as possible during the crystal growth process.

[0003] Therefore, while controlling the growth defect occurrence area, it is necessary to understand the distribution of point defects in the defect-free area in advance during the crystal growth stage, and to accurately distinguish the boundaries of the P-band, VDP (Vacancy Dominant Pure, vacancy-dominated area) area and IDP (Interstitial Dominant Pure, interstitial-dominated area). In particular, the currently commercialized COP-free Wafer (silicon wafer with defect-free area) is not only VDP and IDP. In order to distinguish the boundaries of all defect-free areas including P-band, MCLT (Minority Carrier Lifetime) measurement after two-stage heat treatment and Cu Decoration (a method of revealing defects or structural features by copper deposition or decoration on the surface or inside of the material) are currently used.

[0004] However, the measurement methods such as MCLT and Cu Decoration after two-stage heat treatment, which are currently widely used in the silicon wafer industry, have very low oxygen precipitation and BMD (Bulk Micro Defect) produced after heat treatment when the oxygen concentration of the silicon wafer is lower than 9ppma (new ASTM standard). Therefore, it is impossible to distinguish between crystal defects such as COP and LDP that appear in the crystal growth stage and the boundaries of defect-free areas such as VDP, IDP, and P-band. Summary of the invention

[0005] In order to solve the above technical problems, the present invention provides a silicon wafer defect detection method to solve the problem that the boundaries of various defect areas are not obvious in low oxygen.

[0006] In order to achieve the above-mentioned purpose, the technical solution adopted in the embodiment of the present invention is: a silicon wafer defect detection method, comprising:

[0007] Provide silicon wafer samples with oxygen concentration below 9ppma;

[0008] The silicon wafer sample is subjected to a first heat treatment under a first preset condition to generate oxygen precipitation nuclei in the P-band region, the B-band region and / or the IDP region;

[0009] The silicon wafer sample is subjected to a second heat treatment under a second preset condition to generate oxygen precipitation nuclei in the VDP region;

[0010] performing a third heat treatment on the silicon wafer sample under a third preset condition, so that the oxygen precipitation nuclei generated in the first heat treatment and the second heat treatment grow;

[0011] The minority carrier lifetime test is performed on the silicon wafer sample.

[0012] Optionally, the oxygen concentration of the silicon wafer sample is 7.84 ppma.

[0013] Optionally, the first preset condition includes: a temperature of 680° C. to 750° C., and a heat treatment time of 4 hours.

[0014] Optionally, the first preset condition includes: temperature of 720° C., heat treatment time of 4 hours.

[0015] Optionally, the second preset condition includes: a temperature of 780° C. to 900° C., and a heat treatment time of 4 hours.

[0016] Optionally, the second preset condition includes: temperature of 800° C., heat treatment time of 4 hours.

[0017] Optionally, the third preset condition includes: a temperature of 1000° C. to 1100° C., and a heat treatment time of 16 hours.

[0018] Optionally, the third preset condition includes: temperature of 1000° C., heat treatment time of 16 hours.

[0019] Optionally, before the silicon wafer sample is subjected to the first heat treatment, the method further comprises:

[0020] The silicon wafer sample is cleaned and dried.

[0021] Optionally, the silicon wafer sample is cleaned with a hydrofluoric acid solution.

[0022] The beneficial effects of the present invention are as follows: by using a three-stage heat treatment method, the amount of oxygen precipitation in some crystal characteristic regions is increased, so that the boundaries of the crystal characteristic regions of silicon wafers with an oxygen concentration below 9 ppma can be clearly distinguished. By distinguishing the boundaries of the crystal characteristic regions, the quality grade of silicon wafers with an oxygen concentration below 9 ppma can be determined more quickly. By distinguishing the boundaries of the crystal characteristic regions, the crystal growth process of low-oxygen COP Free silicon wafers with an oxygen concentration below 9 ppma can be quality controlled. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It represents the Lifetime Map of the sample measured by the two-stage heat treatment method;

[0024] Figure 2 It represents LifetimeMap of a sample measured by the silicon wafer defect detection method provided by an embodiment of the present invention;

[0025] Figure 3 It represents LifetimeMap of a sample measured by the silicon wafer defect detection method provided by an embodiment of the present invention;

[0026] Figure 4 It represents LifetimeMap of a sample measured by the silicon wafer defect detection method provided by an embodiment of the present invention;

[0027] Figure 5 Schematic diagram showing the trend of oxygen evolution in the IDP region as a function of temperature;

[0028] Figure 6 Schematic diagram showing the trend of oxygen precipitation in the B-band area with temperature;

[0029] Figure 7 Schematic diagram showing the trend of oxygen precipitation in the p-band region changing with temperature;

[0030] Figure 8 Schematic diagram showing the trend of oxygen precipitation in the VDP region with temperature;

[0031] Fig. 9 A schematic flow chart of a silicon wafer defect detection method according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0032] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0033] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0034] The features such as "parallel", "perpendicular", and "same" used in the embodiments of the present disclosure include the features such as "parallel", "perpendicular", and "same" in a strict sense, as well as the cases where "approximately parallel", "approximately perpendicular", "approximately the same", etc. include certain tolerances, taking into account the tolerances associated with the measurement of specific quantities (e.g., the limitations of the measurement system), and are expressed as being within an acceptable range of deviations for a specific value determined by a person of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within 3% or 5% of the value.

[0035] In addition, in this document, unless otherwise defined, the terms "substantially", "substantially", "approximately" and "about" are used to describe and explain small changes. When used with an event or situation, these terms can cover situations where the event or situation occurs exactly, and can also cover situations where the event or situation occurs approximately. For example, when used with a numerical value, these terms can include a range of variation of less than or equal to 10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, less than or equal to ±0.05%. The term "substantially coplanar" can refer to two surfaces being arranged along the same plane in the micrometer range, for example, arranged along the same plane within 40μm, 30μm, 20μm, 10μm or 1μm.

[0036] When single crystal silicon is produced using the CZ method, in the Voronkov theory related to growth rate (V) / temperature gradient (G), the following crystal defect regions may appear depending on the concentration of point defects mixed in during the growth process.

[0037] For example, when single crystal silicon grows at a high rate above the V / G critical value, a V-rich region with void defects may occur. In addition, when single crystal silicon grows at a rate above the V / G critical value and below the V-rich value, an OISF (Oxidation Induced Stacking Fault) defect may appear as a ring-shaped P-band at the edge or center area. In addition, when single crystal silicon grows at a low rate below the V / G critical value, a spontaneously generated I-rich region may appear, that is, an LDP (Large Dislocation Pit) defect region caused by the pinning of dislocation loops. Moreover, there may be a defect-free region between the V-rich region and the I-rich region where point defects have not aggregated. According to the properties of the point defects contained, these defect-free regions can be divided into VDP (Vacancy Dominant Pure) regions dominated by vacancies and IDP (Interstitial Dominant Pure) regions dominated by interstitial atoms (self-interstitial).

[0038] Since the growth defects such as COP (Crystal Originated Particles) and LDP in CZ-Si are directly related to device failures such as leakage current or oxide breakdown, the wafer containing areas with a high probability of growth defects is removed as much as possible during the crystal growth process.

[0039] Therefore, while controlling the growth defect occurrence area, it is necessary to understand the distribution of point defects in the defect-free area in advance during the crystal growth stage, and to accurately distinguish the boundaries of the P-band, VDP area, and IDP area. In particular, the currently commercialized COP-free Wafer is not only VDP and IDP, but in order to distinguish the boundaries of all defect-free areas including P-band, the MCLT (Minority Carrier Lifetime) measurement after two-stage heat treatment and Cu Decoration are currently used.

[0040] However, the measurement methods such as MCLT and Cu Decoration after two-stage heat treatment, which are widely used in the silicon wafer industry, are very low in oxygen precipitation and BMD (Bulk Micro Defect) after heat treatment when the oxygen concentration of the silicon wafer is lower than 9ppma (new ASTM standard), so it is impossible to distinguish the crystal defects appearing in the crystal growth stage such as COP and LDP and the boundaries of defect-free areas such as VDP, IDP, and P-band. Therefore, in the embodiment of the present invention, in order to more effectively analyze the crystal defects and defect-free areas in Low Oi Wafer with an oxygen concentration below 9ppma, a three-step heat treatment method for MCLT measurement is provided.

[0041] In an exemplary implementation, this embodiment provides a silicon wafer defect detection method, comprising:

[0042] Provide silicon wafer samples with oxygen concentration below 9ppma;

[0043] The silicon wafer sample is subjected to a first heat treatment under a first preset condition to generate oxygen precipitation nuclei in the P-band region, the B-band region and / or the IDP region;

[0044] The silicon wafer sample is subjected to a second heat treatment under a second preset condition to generate oxygen precipitation nuclei in the VDP region;

[0045] performing a third heat treatment on the silicon wafer sample under a third preset condition, so that the oxygen precipitation nuclei generated in the first heat treatment and the second heat treatment grow;

[0046] The minority carrier lifetime test is performed on the silicon wafer sample.

[0047] The silicon wafer defect detection method in this embodiment processes and analyzes silicon wafer samples with an oxygen concentration lower than 9 ppma, and performs a minority carrier lifetime test on the silicon wafer after performing three heat treatments on the silicon wafer samples. During the three heat treatments, the first heat treatment is used to cause oxygen precipitation nuclei to occur in the P-band region, the B-band region and / or the IDP region of the silicon wafer sample, the second heat treatment is used to cause oxygen precipitation nuclei to occur in the VDP region, and the third heat treatment is performed to cause the oxygen precipitation nuclei generated in the first heat treatment and the second heat treatment to grow.

[0048] The MCLT (minority carrier lifetime) measurement method is to place a silicon wafer in a diffusion furnace and measure the lifetime (minority carrier lifetime) after heat treatment. By comparing the differences in lifetime values ​​caused by differences in oxygen precipitates or BMD concentrations generated inside the silicon during the heat treatment, this method is used to analyze the boundaries of crystal characteristic regions such as VDP, IDP, P-band, B-band, and LDP in the silicon wafer.

[0049] In the related art, the heat treatment before the minority carrier lifetime test is generally a secondary heat treatment. However, when the oxygen concentration of the silicon wafer is lower than 9ppma (new ASTM standard), the amount of oxygen precipitation and BMD (Bulk Micro Defect) generated after the secondary heat treatment are very low, so it is impossible to distinguish the boundaries of crystal defects such as COP and LDP that appear in the crystal growth stage and the non-defective areas such as VDP, IDP, and P-band. In this embodiment, three heat treatments are performed to increase the amount of oxygen precipitation in at least part of the crystal defect or non-defective area, so that the crystal characteristic area boundary can be clearly distinguished for silicon wafers with an oxygen concentration below 9ppma.

[0050] It should be noted that the minority carrier lifetime test was performed in this embodiment using the u-PCD Lifetime measurement method (ultra-high sensitivity photon counting lifetime measurement method).

[0051] Figure 1 The Lifetime Map is a diagram of the lifespan of samples measured by the two-stage heat treatment method. Figure 1There is no crystal characteristic region in the image, and the images of each region are blurred. This is because the oxygen concentration inside the silicon wafer sample is 8.21ppma. When the oxygen concentration is below 9ppma, the heat treatment temperature conditions are insufficient, and the resulting oxygen precipitation and BMD concentration are very low, which leads to the problem that the Lifetime Map obtained by the minority carrier lifetime test after the second stage heat treatment cannot distinguish the various crystal characteristic regions.

[0052] Figure 2 The Lifetime Map is obtained by using the silicon wafer defect detection method provided by the embodiment of the present invention (i.e., performing a minority carrier lifetime test after a three-stage heat treatment method) to measure the silicon wafer sample. Figure 2 In the result diagram shown, the VDP and IDP regions can be clearly seen, and the boundaries between the regions are quite obvious. Figure 2 In the Lifetime Map shown, the area represented by the blue in the middle is the VDP area, which means that the oxygen precipitation concentration during the three-stage heat treatment is high, so the BMD concentration produced is high, thereby reducing the Lifetime value. The area represented by the red ring area is the IDP area, where the oxygen precipitation concentration during the three-stage heat treatment is relatively low, so the BMD concentration produced is low and the Lifetime value is high.

[0053] Figure 3 The Lifetime Map is obtained by using the silicon wafer defect detection method provided by the embodiment of the present invention (i.e., performing a minority carrier lifetime test after a three-stage heat treatment method) to measure the silicon wafer sample. Figure 2 In the result diagram shown, the p-band region and the VDP region can be clearly seen, and the boundaries between the regions are quite obvious. Figure 3 In the Lifetime Map shown, the area represented by blue in the middle is the VDP area, and the ring-shaped red area indicates the p-band area.

[0054] Figure 4 The Lifetime Map is obtained by using the silicon wafer defect detection method provided by the embodiment of the present invention (i.e., performing a minority carrier lifetime test after a three-stage heat treatment method) to measure the silicon wafer sample. Figure 4 In the result diagram shown, the B-band region and the IDP region can be clearly seen, and the boundaries between the regions are quite obvious. Figure 4 In the Lifetime Map shown, the red ring area near the center represents the B-band area, and the red ring area near the edge represents the IDP area.

[0055] Will Figure 2-Figure 4 The Lifetime Map and Figure 1 By comparing with the Lifetime Map shown in FIG. 1 , it is obvious that by using the silicon wafer defect detection method provided in the embodiment of the present invention to analyze the silicon wafer, the boundaries of at least the B-band region, the p-band region, the VDP region and the IDP region can be clearly defined.

[0056] It should be noted that the defects of silicon wafers are not necessarily the same; Figure 2-Figure 4 Only part of the defect area is shown in each schematic diagram.

[0057] In an exemplary embodiment, the oxygen concentration of the silicon wafer sample is 7.84 ppma, but it is not limited thereto. The oxygen concentration of the silicon wafer sample can be selected as long as it is lower than 9 ppma, so that the silicon wafer with low oxygen concentration can be tested and analyzed.

[0058] In an exemplary embodiment, the first preset condition includes: a temperature of 680° C. to 750° C., and a heat treatment time of 4 hours.

[0059] It should be noted that Figure 5 The figure shows the trend of oxygen precipitation in the IDP region as a function of temperature. Figure 5 It can be obtained that when the amount of oxygen precipitation in the IDP region is large, the corresponding optimal temperature is 680℃-750℃; therefore, in order to increase the amount of oxygen precipitation in the IDP region, the first preset conditions for the first heat treatment of the silicon wafer sample include a temperature of 680℃~750℃ and a heat treatment time of 4 hours.

[0060] It should be noted that Figure 6 The figure shows the trend of oxygen precipitation in the B-band area with temperature. Figure 6 It can be obtained that when the amount of oxygen precipitation in the B-band area is large, the corresponding optimal temperature is 680℃-750℃; therefore, in order to increase the amount of oxygen precipitation in the B-band area, the first preset condition for the first heat treatment of the silicon wafer sample includes a temperature of 680℃~750℃ and a heat treatment time of 4 hours.

[0061] It should be noted that Figure 7 The figure shows the trend of oxygen precipitation in the p-band region with temperature. Figure 7 It can be obtained that when the amount of oxygen precipitation in the p-band region is large, the corresponding optimal temperature is 680℃-750℃; therefore, in order to increase the amount of oxygen precipitation in the p-band region, the first preset condition for the first heat treatment of the silicon wafer sample includes a temperature of 680℃~750℃ and a heat treatment time of 4 hours.

[0062] In an exemplary embodiment, the first preset condition includes: a temperature of 720° C. and a heat treatment time of 4 hours.

[0063] In an exemplary embodiment, in order to promote the formation of oxygen precipitation nuclei in the IDP region, B-and region, and p-band region, the first heat treatment is performed in an oxygen atmosphere, and the oxygen flow rate may be 5 lpm, but is not limited thereto.

[0064] refer to Figure 5-Figure 7 When the temperature is 720°C, the oxygen precipitation amounts in the IDP region, B-and region, and p-band region are all in the optimal state. Therefore, in a preferred embodiment, the first preset condition includes: the temperature is 720°C and the heat treatment time is: 4 hours.

[0065] In an exemplary embodiment, the second preset condition includes: a temperature of 780° C. to 900° C., and a heat treatment time of 4 hours.

[0066] Figure 8 The figure shows the trend of oxygen precipitation in the VDP region with temperature. Figure 8 It can be obtained that when the amount of oxygen precipitation in the VDP area is large, the corresponding optimal temperature is 780℃~900℃; therefore, in order to increase the amount of oxygen precipitation in the VDP area, the first preset condition for the first heat treatment of the silicon wafer sample includes a temperature of 780℃~900℃ and a heat treatment time of 4 hours.

[0067] In a preferred embodiment, the second preset condition includes: a temperature of 800° C. and a heat treatment time of 4 hours.

[0068] In an exemplary embodiment, in order to promote the formation of oxygen precipitation nuclei in the VDP region, the second heat treatment is performed in an oxygen atmosphere, and the flow rate of oxygen may be 5 lpm, but is not limited thereto.

[0069] In an exemplary embodiment, the third preset condition includes: a temperature of 1000° C. to 1100° C., and a heat treatment time of 16 hours.

[0070] In this embodiment, the silicon wafer sample is subjected to three-stage heat treatment so that the oxygen precipitates in the corresponding defective regions are nucleated in a low-temperature environment and grow in a high-temperature environment, thereby clearly distinguishing the boundaries of the corresponding defective regions.

[0071] In an exemplary embodiment, the third preset condition includes: a temperature of 1000° C. and a heat treatment time of 16 hours.

[0072] In an exemplary embodiment, in order to facilitate the growth of oxygen precipitation nuclei generated in the first heat treatment and the second heat treatment and not be affected by other factors, the third heat treatment is performed in a nitrogen atmosphere to form a protective environment. Exemplarily, the flow rate of nitrogen can be 1-lpm, but is not limited thereto.

[0073] It should be noted that, in the third heat treatment, the material forming the gas atmosphere for protecting the environment may be nitrogen or other inert gases such as argon, which is not limited here.

[0074] In an exemplary embodiment, before the silicon wafer sample is subjected to the first heat treatment, the method further comprises:

[0075] The silicon wafer sample is cleaned and dried.

[0076] In a specific implementation, a cleaning solution composed of HF+H2O is used to clean the silicon wafer sample, that is, the two surfaces of the silicon wafer sample are first cleaned with hydrofluoric acid to prevent impurities that may exist on the surface of the silicon wafer sample from affecting the accuracy of detection.

[0077] For example, after cleaning, drying may be performed using a rotary blower or nitrogen gas.

[0078] In some embodiments of the present invention, the concentration of hydrofluoric acid used for cleaning is 4% to 20%, and the cleaning time is 1 to 15 minutes to ensure the cleaning effect, but it is not limited thereto.

[0079] In order to verify that the silicon wafer defect detection method provided by the embodiment of the present invention can clearly distinguish the boundaries of the crystal characteristic areas, this embodiment also uses a silicon wafer sample with an oxygen concentration of 8.21 ppma for two-stage heat treatment and conducts detection for comparison.

[0080] The process of the second stage heat treatment is as follows:

[0081] In the first heat treatment stage: in an oxygen gas atmosphere, the temperature is raised to 800° C. and maintained at 800° C. for 4 hours;

[0082] In the second heat treatment stage: in a nitrogen atmosphere, the temperature is raised to 1000° C. and maintained at 1000° C. for 16 hours.

[0083] Then, the minority carrier lifetime of the silicon wafer sample after the second stage heat treatment was tested to obtain Figure 1 The Lifetime Map (Lifetime Schematic Diagram) shown in the figure shows Figure 1 The boundaries between the various defect areas are blurred and cannot be distinguished.

[0084] In the embodiment of the present invention, the silicon wafer sample is subjected to three-stage heat treatment, and the oxygen concentration of the silicon wafer sample is 7.84 ppma. That is, the silicon wafer sample with a lower oxygen concentration is used in the embodiment of the present invention. Due to the heat treatment method of the three-stage heat treatment in this embodiment, the silicon wafer sample is analyzed and the obtained Figure 2-Figure 4 The Lifetime Map shown in Figure 1 In contrast, it is obvious that the silicon wafer defect detection method provided in this embodiment can clearly distinguish the boundaries of the B-band region, the p-band region, the VDP region and the IDP region.

[0085] It should be noted that, in order to improve the accuracy of the comparison results, the difference between the method of analysis using two-stage heat treatment and the method of analysis using three-stage heat treatment in this embodiment is that the oxygen concentration of the silicon wafer samples is different, the heat treatment process is different, and the other process steps are the same.

[0086] There are a few points to note:

[0087] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to the general design.

[0088] (2) For the sake of clarity, in the drawings used to describe the embodiments of the present disclosure, the thickness of layers or regions is exaggerated or reduced, that is, these drawings are not drawn according to the actual scale. It is understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, the element may be "directly" "on" or "under" the other element or there may be intermediate elements.

[0089] (3) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0090] It is to be understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of the present invention, but the present invention is not limited thereto. For those of ordinary skill in the art, various modifications and improvements can be made without departing from the spirit and essence of the present invention, and these modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A silicon wafer defect detection method, characterized in that: include: Provide silicon wafer samples with oxygen concentration below 9ppma; The silicon wafer sample is subjected to a first heat treatment under a first preset condition to generate oxygen precipitation nuclei in the P-band region, the B-band region and / or the IDP region; The silicon wafer sample is subjected to a second heat treatment under a second preset condition to generate oxygen precipitation nuclei in the VDP region; performing a third heat treatment on the silicon wafer sample under a third preset condition, so that the oxygen precipitation nuclei generated in the first heat treatment and the second heat treatment grow; The minority carrier lifetime test is performed on the silicon wafer sample.

2. The method for detecting silicon wafer defects according to claim 1, characterized in that: The oxygen concentration of the silicon wafer sample was 7.84 ppma.

3. The method for detecting silicon wafer defects according to claim 1, characterized in that: The first preset conditions include: a temperature of 680° C. to 750° C., and a heat treatment time of 4 hours.

4. The method for detecting silicon wafer defects according to claim 3, characterized in that: The first preset conditions include: a temperature of 720° C. and a heat treatment time of 4 hours.

5. The method for detecting silicon wafer defects according to claim 1, characterized in that: The second preset conditions include: a temperature of 780° C. to 900° C., and a heat treatment time of 4 hours.

6. The method for detecting silicon wafer defects according to claim 1, characterized in that: The second preset conditions include: a temperature of 800° C. and a heat treatment time of 4 hours.

7. The method for detecting silicon wafer defects according to claim 1, characterized in that: The third preset condition includes: a temperature of 1000° C. to 1100° C., and a heat treatment time of 16 hours.

8. The method for detecting silicon wafer defects according to claim 7, characterized in that: The third preset condition includes: a temperature of 1000° C. and a heat treatment time of 16 hours.

9. The method for detecting silicon wafer defects according to claim 1, characterized in that: Before the silicon wafer sample is subjected to the first heat treatment, the method further comprises: The silicon wafer sample is cleaned and dried.

10. The method for detecting silicon wafer defects according to claim 9, characterized in that: The silicon wafer sample is cleaned with a hydrofluoric acid solution.

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