Storage space processing method and device, electronic equipment and storage medium

Abstract

The invention provides a storage space processing method, and relates to the technical field of artificial intelligence, in particular to the technical field of single-instruction multi-data and the technical field of code compiling. According to the specific implementation scheme, a plurality of storage spaces to be optimized are determined from a plurality of initial storage spaces for a plurality of instruction blocks, the instruction blocks comprise a first instruction block and a second instruction block, the first instruction block comprises a conditional branch instruction, and the second instruction block is a target instruction block of the conditional branch instruction; according to a plurality of to-be-optimized storage spaces for a second instruction block and a target storage space for the second instruction block, updating a plurality of to-be-processed instructions corresponding to the plurality of to-be-optimized storage spaces into a plurality of processed instructions, the operation used for execution by the processed instruction comprises at least one of the following operations: reading data in the target storage space and writing the data into the target storage space; and distributing a physical storage space for the target storage space. The invention further provides a storage space processing device, equipment and a medium.

Description

Technical Field

[0001] The present disclosure relates to the field of artificial intelligence technology, and in particular to the technical fields of single instruction multiple data, single instruction multiple threads (SIMT), code compilation, etc. More specifically, the present disclosure provides a storage space processing method, device, electronic device, and storage medium. Background Art

[0002] With the development of artificial intelligence technology, the application of SIMD programs is increasing. The control flow of SIMD programs can execute different or the same instructions based on different threads. Summary of the invention

[0003] The present disclosure provides a storage space processing method, apparatus, device and storage medium.

[0004] According to one aspect of the present disclosure, a storage space processing method is provided, the method comprising: determining a plurality of storage spaces to be optimized from a plurality of initial storage spaces for a plurality of instruction blocks, wherein the plurality of instruction blocks comprise a first instruction block and a second instruction block, the first instruction block comprises a conditional branch instruction, and the second instruction block is a destination instruction block of the conditional branch instruction; updating a plurality of to-be-processed instructions corresponding to the plurality of storage spaces to be optimized into a plurality of processed instructions according to the plurality of storage spaces to be optimized and the target storage space for the second instruction block, wherein the operations performed by the processed instructions comprise at least one of the following: reading data in the target storage space and writing data to the target storage space; allocating physical storage space to the target storage space.

[0005] According to another aspect of the present disclosure, a storage space processing device is provided, which includes: a determination module, used to determine a plurality of storage spaces to be optimized from a plurality of initial storage spaces for a plurality of instruction blocks, wherein the plurality of instruction blocks include a first instruction block and a second instruction block, the first instruction block includes a conditional branch instruction, and the second instruction block is a destination instruction block of the conditional branch instruction; an update module, used to update a plurality of to-be-processed instructions corresponding to the plurality of storage spaces to be optimized into a plurality of processed instructions according to the plurality of storage spaces to be optimized for the second instruction block and the target storage space for the second instruction block, wherein the operations performed by the processed instructions include at least one of the following: reading data in the target storage space and writing data to the target storage space; an allocation module, used to allocate physical storage space to the target storage space.

[0006] According to another aspect of the present disclosure, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method provided according to the present disclosure.

[0007] According to another aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided. The computer instructions are used to cause a computer to execute the method provided according to the present disclosure.

[0008] According to another aspect of the present disclosure, a computer program product is provided, including a computer program, and when the computer program is executed by a processor, the method provided according to the present disclosure is implemented.

[0009] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The accompanying drawings are used to better understand the present solution and do not constitute a limitation of the present disclosure.

[0011] Figure 1 is a schematic diagram of an exemplary system architecture to which a storage space processing method and apparatus can be applied according to an embodiment of the present disclosure;

[0012] Figure 2 is a flowchart of a method for processing a storage space according to an embodiment of the present disclosure;

[0013] Figure 3 is a schematic diagram of multiple instruction blocks according to an embodiment of the present disclosure;

[0014] Figure 4 is a block diagram of a storage space processing device according to an embodiment of the present disclosure; and

[0015] Figure 5 is a block diagram of an electronic device to which a storage space processing method can be applied according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0016] The following is a description of exemplary embodiments of the present disclosure in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding, which should be considered as merely exemplary. Therefore, it should be recognized by those of ordinary skill in the art that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0017] In a SIMD program, the control flow can be structured to cope with the situation where different threads execute different or the same instructions. These structured control flows can correspond to more code basic blocks. In the actual operation process, due to the existence of vector predicates, each code basic block will only occupy a part of the hardware resources. These hardware resources can include computing resources and storage resources. Storage resources can include registers. A code basic block can occupy a part of the register space. The other part of the register space is difficult to be occupied by other code basic blocks, resulting in insufficient reuse of register resources, which in turn leads to waste of register resources. When too many register resources are occupied, the stack space of the program will be occupied, resulting in waste of resources of off-chip storage units (such as video memory) and additional memory access resource overhead.

[0018] In order to reduce the register resource overhead or storage resource overhead of SIMD programs, branches can be reduced during programming to reduce control flow. However, it is difficult to reduce branches during programming and the application scenarios are relatively limited. In some complex algorithms or algorithms where the input range cannot be determined, it may not be possible to completely eliminate the control flow of the program.

[0019] In order to reduce the register resource overhead or storage resource overhead of SIMD programs, inline assembly can also be used in key statements of the code to avoid the compiler automatically allocating registers, thereby avoiding register resource waste in the control flow. Although inline assembly is more flexible, it significantly increases the difficulty of programming and is highly dependent on the programmer's experience. In addition, inline assembly will also reduce the reusability of the code, and different logics in different algorithms must be handled according to actual conditions.

[0020] Therefore, in order to effectively utilize the register resources and storage resources of the hardware, the present disclosure provides a method for processing a storage space, which will be described below.

[0021] Figure 1 is a schematic diagram of an exemplary system architecture to which a storage space processing method and device can be applied according to an embodiment of the present disclosure. It should be noted that: Figure 1 What is shown is merely an example of a system architecture to which the embodiments of the present disclosure can be applied, in order to help those skilled in the art understand the technical content of the present disclosure, but it does not mean that the embodiments of the present disclosure cannot be used in other devices, systems, environments or scenarios.

[0022] like Figure 1As shown, the system architecture 100 according to this embodiment may include terminal devices 101, 102, 103, a network 104 and a server 105. The network 104 is used to provide a medium for communication links between the terminal devices 101, 102, 103 and the server 105. The network 104 may include various connection types, such as wired and / or wireless communication links, etc.

[0023] Users can use terminal devices 101, 102, 103 to interact with server 105 through network 104 to receive or send messages, etc. Terminal devices 101, 102, 103 can be various electronic devices with display screens and supporting web browsing, including but not limited to smart phones, tablet computers, laptops, desktop computers, etc.

[0024] The server 105 may be a server that provides various services, such as a background management server (only as an example) that provides support for websites browsed by users using the terminal devices 101, 102, and 103. The background management server may analyze and process the received data such as user requests, and feed back the processing results (such as web pages, information, or data obtained or generated according to user requests) to the terminal device.

[0025] It should be noted that the storage space processing method provided in the embodiment of the present disclosure can generally be executed by the server 105 or the terminals 101, 102, 103. Accordingly, the storage space processing device provided in the embodiment of the present disclosure can generally be set in the server 105 or the terminals 101, 102, 103. The storage space processing method provided in the embodiment of the present disclosure can also be executed by a server or a server cluster that is different from the server 105 and can communicate with the terminal devices 101, 102, 103 and / or the server 105. Accordingly, the storage space processing device provided in the embodiment of the present disclosure can also be set in a server or a server cluster that is different from the server 105 and can communicate with the terminal devices 101, 102, 103 and / or the server 105.

[0026] Figure 2 is a flowchart of a method for processing a storage space according to an embodiment of the present disclosure.

[0027] like Figure 2 As shown, the method 200 may include operations S210 to S230.

[0028] In operation S210 , a plurality of storage spaces to be optimized are determined from a plurality of initial storage spaces for a plurality of instruction blocks.

[0029] In the disclosed embodiment, the compiler may compile the program code into multiple hardware instructions. The program code may include multiple code blocks. The code block may correspond to multiple operations. Among the multiple operations corresponding to the code block, except for the operation at the end, one or more operations at the beginning and the middle do not include a branch operation. The operation corresponding to the code at the end of the code block may include a branch operation. After compilation, an instruction block corresponding to the code block may be obtained. The branch operation may be an operation that causes the instruction execution flow to jump from the current instruction block to other instruction blocks.

[0030] In the disclosed embodiment, the compiler may also convert variables in the program code into logical registers. The number of logical registers may be unlimited. The initial storage space may be the logical registers of the hardware instructions.

[0031] In the embodiment of the present disclosure, the storage space used for the instruction block may be the storage space to be read and / or written by the instructions in the instruction block.

[0032] In an embodiment of the present disclosure, the plurality of instruction blocks may include a first instruction block and a second instruction block. The first instruction block may include a conditional branch instruction. Based on the conditional branch instruction, the execution flow of the instruction may jump to a plurality of destination instruction blocks. The second instruction block may be a destination instruction block of the conditional branch instruction.

[0033] In the embodiment of the present disclosure, multiple initial storage spaces used for the second instruction block may be used as multiple storage spaces to be optimized.

[0034] In operation S220, a plurality of to-be-processed instructions corresponding to the plurality of storage spaces to be optimized are updated into a plurality of processed instructions according to the plurality of storage spaces to be optimized for the second instruction block and the target storage space for the second instruction block.

[0035] In the embodiment of the present disclosure, a new storage space may be created as the target storage space. For example, a new logical register may be created as the target storage space for the second instruction block.

[0036] In the embodiment of the present disclosure, the operations that can be performed by the processed instruction include at least one of the following: reading data in the target storage space and writing data to the target storage space. For example, based on the instruction to be processed, data can be read from the storage space to be optimized or written to the storage space to be optimized. Based on the processed instruction, data can be read from the target storage space or written to the target storage space.

[0037] In operation S230, a physical storage space is allocated to the target storage space.

[0038] In the disclosed embodiment, a physical storage space may be allocated to a logical target storage space. For example, the target storage space may be a logical register. A physical register on hardware may be allocated to the logical register. A physical register may be the smallest storage unit on hardware, may store the operand of an instruction, has a fast read and write speed, and is limited in number.

[0039] Through the embodiments of the present disclosure, when a conditional branch exists in a single instruction multiple data program, multiple storage spaces to be optimized for the second instruction block of the program can be merged into a target storage space, which can effectively reduce the occupation of hardware storage resources and increase the reuse rate of hardware storage resources. In addition, through the embodiments of the present disclosure, the storage resource overhead can be reduced without the programmer modifying the program code, which helps to reduce the programming difficulty and improve the reusability of the code.

[0040] It can be understood that the method of the present disclosure is described above. Figure 3 The method of the present disclosure is further described.

[0041] Figure 3 is a schematic diagram of multiple instruction blocks according to an embodiment of the present disclosure.

[0042] In the disclosed embodiment, the program code is compiled to obtain multiple code segments. The multiple code segments may include at least one of a loop code segment and a non-loop code segment. The code segment may include multiple code blocks. The code segment may correspond to an instruction segment. The multiple instruction segments may include at least one of a loop instruction segment and a non-loop instruction segment. The instruction block may include multiple instruction blocks.

[0043] like Figure 3 As shown, the multiple instruction blocks include instruction block i310, instruction block i321, instruction block i322, instruction block i331, instruction block i332, instruction block i341 and instruction block i342. It can be understood that the multiple instruction blocks can also include other instruction blocks. For simplicity, Figure 3 Not all instruction blocks are shown.

[0044] In the embodiment of the present disclosure, the first instruction block can be determined from multiple instruction blocks. For example, the instruction block including the conditional branch instruction can be used as the first instruction block. Figure 3 As shown, instruction block i310 includes a conditional branch instruction and can be used as a first instruction block. When the condition of the conditional branch instruction is met, it can jump to instruction block i321. When the condition of the conditional branch instruction is not met, it can jump to instruction block i322. Instruction block i321 and instruction block i322 can be the destination instruction blocks of the conditional branch instruction of instruction block i311, and can be used as second instruction blocks respectively.

[0045] In the embodiment of the present disclosure, the plurality of instruction blocks may further include a third instruction block. The third instruction block may be a destination instruction block of a branch instruction of the second instruction block. Figure 3 As shown, instruction block i331 can be the destination instruction block of the conditional branch instruction of instruction block i321, and can be used as the third instruction block corresponding to instruction block i321. Instruction block i332 can be the destination instruction block of the conditional branch instruction of instruction block i322, and can be used as the third instruction block corresponding to instruction block i322. It can be understood that Figure 3 Only part of the target instruction blocks of the instruction block i321 or the instruction block i322 is shown, and all the target instruction blocks are not shown.

[0046] In the embodiment of the present disclosure, the multiple instruction blocks may further include a fourth instruction block. The fourth instruction block may be an instruction block in the third instruction block other than the second instruction block. For example, a subsequent instruction block may be jumped to according to a branch instruction. Instructions of the multiple instruction blocks may also be executed sequentially in the order specified by the program. Figure 3 As shown, after executing the instructions of instruction block i321, the instructions of instruction block i341 can also be executed in the order specified by the program. After executing the instructions of instruction block i341, the output of instruction block i341 obtained can be used as the input of instruction block i332. That is, instruction block i341 can be used as the predecessor instruction block of instruction block i332. Instruction block i341 may not include branch instructions and can be used as the fourth instruction block. In addition, instruction block i342 can also be used as the fourth instruction block.

[0047] In some embodiments, in some implementations of the above operation S210, determining a plurality of storage spaces to be optimized from a plurality of initial storage spaces for a plurality of instruction blocks may include: determining at least one initial instruction block defining a plurality of first storage spaces to be screened.

[0048] In the embodiment of the present disclosure, at least one of the third instruction block and the fourth instruction block can be used as the instruction block to be filtered. For example, the instruction block i331 and the instruction block i332 can be used as the instruction block to be filtered, or the instruction block i341 and the instruction block i342 can be used as the instruction block to be filtered.

[0049] In the embodiment of the present disclosure, the initial storage space used by the instructions to be filtered of the instruction block to be filtered can be used as the first storage space to be filtered. The use may include at least one of reading and writing. The instruction to be filtered can be a collection instruction of the third instruction block, or it can be an initial instruction of the fourth instruction block. The initial instruction can be an instruction that needs to read and / or write a storage space. The collection instruction can be an instruction to read data from multiple storage spaces. For example, the collection instruction in the instruction block i331 can be used as the instruction to be filtered. The initial instruction in the instruction block i341 can also be used as the instruction to be filtered. For another example, if the instruction to be filtered needs to read, write, or read and write an initial storage space, the initial storage space can be used as the first storage space to be filtered.

[0050] In the disclosed embodiment, the initial instruction block defining the first storage space to be screened may be an instruction block that writes data to the first storage space to be screened for the first time. For example, in order to execute the first initial instruction in the instruction block, data needs to be written into the first register. The number of the first register has not appeared before, and a logical register may be defined as the first register. The first register may serve as the first storage space to be screened.

[0051] In some embodiments, in some implementations of the above operation S210, determining multiple storage spaces to be optimized from multiple initial storage spaces for multiple instruction blocks may also include: determining at least one second storage space to be filtered from multiple first storage spaces to be filtered based on the relationship between the first instruction block and the initial instruction block and the relationship between the second instruction block and the initial instruction block.

[0052] In the embodiment of the present disclosure, it can be determined whether the relationship between the initial instruction block and the first instruction block satisfies the first preset condition, it can also be determined whether the relationship between the initial instruction block and the second instruction block satisfies the second preset condition, and it can also be determined whether any initial instruction in the third instruction block does not use the storage space to be optimized. The first preset condition may include: the initial instruction block is the same as the first instruction block or the initial instruction block is the predecessor instruction block of the first instruction block. The second preset condition includes: the initial instruction block and the second instruction block belong to the same loop instruction segment or the initial instruction block and the second instruction block belong to a non-loop instruction segment. For example, if both instruction blocks are in the same loop instruction segment, it can be determined that the two instruction blocks meet the second preset condition. If both instruction blocks are not in the loop instruction segment, it can also be determined that the two instruction blocks meet the second preset condition. If the two instruction blocks belong to different loop instruction segments, it can be determined that the two instruction blocks do not meet the second preset condition.

[0053] In the embodiment of the present disclosure, in response to determining that the relationship between the initial instruction block and the first instruction block satisfies the first preset condition, the relationship between the initial instruction block and the second instruction block satisfies the second preset condition, and any initial instruction in the third instruction block does not use the first storage space to be screened, the first storage space to be screened is determined as the second storage space to be screened. For example, the initial instruction in the instruction block i341 can read the data in the above-mentioned first register. If the initial instruction block defining the first register is the above-mentioned instruction block i310, the instruction block i310 and the instruction block i321 belong to the non-circular instruction segment, and any initial instruction in the instruction block i331 does not read the data in the first register, the first register can be determined as a second storage space to be screened. For another example, for example, the collection instruction in the instruction block i331 can read the data in the second register. If the initial instruction block defining the second register is the above-mentioned instruction block i310, the instruction block i310 and the instruction block i321 belong to the non-circular instruction segment, and any initial instruction in the instruction block i331 does not read the data in the second register, the second register can be determined as another second storage space to be screened. It can be understood that in this embodiment, the disclosure is explained by taking the initial instruction block and the first instruction block as an example of the same instruction block. However, the disclosure is not limited to this. If the initial instruction block is the predecessor instruction block of the first instruction block, it can also be determined that the relationship between the initial instruction block and the first instruction block satisfies the first preset condition. Through the embodiment of the present disclosure, the second storage space to be screened that may need to be optimized can be determined from a large amount of storage space, which helps to quickly determine the storage space to be optimized.

[0054] In another embodiment of the present disclosure, in response to determining that the relationship between the initial instruction block and the first instruction block does not satisfy the first preset condition, the relationship between the initial instruction block and the second instruction block does not satisfy the second preset condition, or at least one initial instruction in the third instruction block uses the first storage space to be screened, the first storage space to be screened is skipped. For example, for the first storage space to be screened that does not satisfy the first preset condition or the second preset condition, the first storage space to be screened may no longer be processed, and it is determined whether other first storage spaces to be screened can be used as second storage spaces to be screened.

[0055] It can be understood that the above describes a method for determining the second storage space to be screened according to the first storage space to be screened, and the following describes a method for determining the storage space to be optimized.

[0056] In some embodiments, in some implementations of the above operation S210, determining a plurality of storage spaces to be optimized from a plurality of initial storage spaces for a plurality of instruction blocks may further include: determining a storage space to be optimized from at least one second storage space to be screened.

[0057] In the embodiment of the present disclosure, it may be determined whether the second storage space to be screened satisfies a third preset condition. The third preset condition may include: the instruction block using the second storage space to be screened is not the second instruction block or the third instruction block.

[0058] In an embodiment of the present disclosure, in response to determining that the second storage space to be screened satisfies the third preset condition, the second storage space to be screened can be determined as a storage space to be optimized. For example, if the instruction block that reads or writes the first register does not include instruction block i331 and instruction block i321, the first register can be used as a storage space to be optimized. For another example, if the instruction block that reads or writes the second register does not include instruction block i331 and instruction block i321, the second register can be used as a storage space to be optimized. Through the embodiment of the present disclosure, depending on whether the instruction block using the second storage space to be screened is the second instruction block or the third instruction block, the storage space to be optimized can be quickly determined while avoiding data dependency conflicts (such as read-after-write and write-after-read conflicts).

[0059] In another embodiment of the present disclosure, in response to determining that the second storage space to be screened does not meet the third preset condition, the second storage space to be screened may be skipped. For example, for the second storage space to be screened that does not meet the third preset condition, the second storage space to be screened may no longer be processed, and it is determined whether other second storage spaces to be screened can be used as storage spaces to be optimized.

[0060] It can be understood that the above describes the method of determining the storage space to be optimized, and the following describes some methods of updating the instructions to be processed.

[0061] In some embodiments, the instruction to be processed may be an instruction that uses a storage space to be optimized.

[0062] In some embodiments, in some implementations of the above operation S220, based on the multiple storage spaces to be optimized for the second instruction block and the target storage space for the second instruction block, updating the multiple pending instructions corresponding to the multiple storage spaces to be optimized into multiple processed instructions may include: adding a target collection instruction in the second instruction block corresponding to the multiple storage spaces to be optimized. For example, for the above first register and the second register, the target collection instruction may be added in the instruction block i321.

[0063] In some embodiments, in some implementations of the above operation S220, based on the multiple storage spaces to be optimized for the second instruction block and the target storage space for the second instruction block, updating the multiple pending instructions corresponding to the multiple storage spaces to be optimized to multiple processed instructions may also include: determining multiple target instruction parameters of the target collection instruction. The target instruction parameters include the identifier of the storage space to be optimized and the identifier of the first instruction block corresponding to the second instruction block. For example, the target instruction parameters corresponding to the first register may include the number of the first register and the identifier of the instruction block i310. For another example, the target instruction parameters corresponding to the second register may include the number of the second register and the identifier of the instruction block i310.

[0064] In some embodiments, in some embodiments, in some implementations of the above operation S220, based on the multiple storage spaces to be optimized for the second instruction block and the target storage space for the second instruction block, updating the multiple pending instructions corresponding to the multiple storage spaces to be optimized to multiple processed instructions may also include: using the target storage space to update the multiple pending instructions corresponding to the multiple storage spaces to be optimized to obtain multiple processed instructions. For example, the target storage space may be a target register. If the instruction to read or write the first register is an instruction in the instruction block i341, the number of the first register in the instruction may be replaced with the number of the target register. For another example, if the instruction to read the second register is a collection instruction of the instruction block i331, the number of the second register in the collection instruction may be replaced with the number of the target register.

[0065] In an embodiment of the present disclosure, the target storage space may include multiple target storage subspaces. The multiple target storage subspaces may correspond to multiple storage spaces to be optimized respectively. For example, the first register may store 16 data. The second register may store 16 data. The target register may store 32 data, for example. The 32 data may include 16 data in the first register and 16 data in the second register.

[0066] Next, the above operation S230 may be performed to allocate physical storage space for the target storage space. For example, the target register may be a physical register. Thus, the two physical registers allocated for the first register and the second register are reduced to one physical register, which can make full use of the register resources of the chip, reduce the storage resource overhead, greatly reduce the memory resource overhead between the chip and the off-chip storage resources, and improve the memory access efficiency.

[0067] It can be understood that the third preset condition includes that the instruction block using the second storage space to be filtered is not the second instruction block or the third instruction block as an example to illustrate the present disclosure. However, the present disclosure is not limited thereto, which will be explained below.

[0068] In other embodiments, the third preset condition may include: the instruction block using the second storage space to be screened is the second instruction block, the pending instruction corresponding to the second storage space to be screened in the second instruction block is a collection instruction, and the instruction parameter corresponding to the second storage space to be screened in the collection instruction includes the identifier of the first instruction block. For example, the instruction parameter of the collection instruction includes the identifier of the storage space and the identifier of the instruction block. If the instruction block reading the second storage space to be screened is the second instruction block, the instruction reading the instruction block of the second storage space to be screened is the collection instruction, and an instruction parameter of the collection instruction includes the identifier of the second storage space to be screened and the identifier of the first instruction block corresponding to the second instruction block, it can be determined that the second storage space to be screened meets the third preset condition. For another example, instruction block i310 can be used as the first instruction block corresponding to instruction block i321.

[0069] In other embodiments, the third preset condition may include: the instruction block using the second storage space to be screened is the third instruction block, the pending instruction corresponding to the second storage space to be screened in the third instruction block is a collection instruction, and the instruction parameter corresponding to the second storage space to be screened in the collection instruction does not include the identifier of the first instruction block. For example, if the instruction block reading the second storage space to be screened is the third instruction block, the instruction reading the instruction block of the second storage space to be screened is a collection instruction, and an instruction parameter of the collection instruction includes the identifier of the second storage space to be screened and the identifier of the second instruction block corresponding to the third instruction block, it can be determined that the second storage space to be screened meets the third preset condition. For another example, instruction block i321 can be used as the second instruction block corresponding to instruction block i331.

[0070] It can be understood that the conditional branch instruction of the first instruction block may not be a loop branch instruction.

[0071] It can be understood that the method of the present disclosure is described above, and the storage space of the present disclosure will be described below.

[0072] In the disclosed embodiment, the storage space may be a register. A physical register may be allocated to a logical register according to the life cycle of the logical register. For example, the moment when an instruction writes data to a register may be used as the starting point of the life cycle of the register. The moment when the last instruction reads the register may be used as the end point of the life cycle of the register. When allocating physical registers to multiple different logical registers, if the life cycles of the multiple logical registers do not overlap, the same physical register may be allocated to the multiple logical registers. If the life cycles of the multiple logical registers overlap, different physical registers may be allocated to the multiple logical registers.

[0073] It can be understood that the above describes the manner in which the present disclosure allocates physical registers, and the following will further describe the collect instruction and the single instruction multiple data program of the present disclosure.

[0074] In some embodiments of the present disclosure, the collection instruction corresponds to a φ node operation. The φ node operation includes: when a branch operation (such as the operation corresponding to the above-mentioned conditional branch instruction) occurs, one or more operations corresponding to the beginning of the code basic block of the branch convergence can collect the outputs of different branches and return the real output according to the real branch execution path at runtime. The output of the collection instruction is a register. The input of the collection instruction is a pair of multiple registers and basic blocks, expressed in the form of {register, basic block}.

[0075] In the disclosed embodiment, for a single instruction multiple data program, different threads can execute the same instruction using different data. All threads or some threads can be used to execute instructions. An instruction can correspond to a mask value (mask), which can indicate the actual thread that needs to execute the instruction. The actual thread can read the data in the register, and the thread that does not need to execute the instruction may not read the data. For example, the first register can store 32 data, of which 16 data can be read by 16 actual threads.

[0076] It can be understood that the method of the present disclosure is described above, and the device of the present disclosure will be described below.

[0077] Figure 4 is a block diagram of a storage space processing device according to an embodiment of the present disclosure.

[0078] like Figure 4 As shown, the apparatus 400 may include a determination module 410 , an update module 420 , and an allocation module 430 .

[0079] The determination module 410 is used to determine a plurality of storage spaces to be optimized from a plurality of initial storage spaces for a plurality of instruction blocks.

[0080] In an embodiment of the present disclosure, the multiple instruction blocks include a first instruction block and a second instruction block, the first instruction block includes a conditional branch instruction, and the second instruction block is a destination instruction block of the conditional branch instruction.

[0081] The updating module 420 is used to update the multiple to-be-processed instructions corresponding to the multiple storage spaces to be optimized into multiple processed instructions according to the multiple storage spaces to be optimized for the second instruction block and the target storage space for the second instruction block.

[0082] In the embodiment of the present disclosure, the operation executed by the processed instruction includes at least one of the following: reading data in the target storage space and writing data to the target storage space.

[0083] The allocation module 430 is used to allocate physical storage space to the target storage space.

[0084] In some embodiments, the multiple instruction blocks further include a third instruction block and a fourth instruction block, the third instruction block is the destination instruction block of the branch instruction of the second instruction block, and the fourth instruction block is an instruction block other than the second instruction block among the multiple predecessor instruction blocks of the third instruction block. The determination module includes: a first determination submodule, which is used to determine at least one initial instruction block defining multiple first storage spaces to be screened. The first storage space to be screened is the initial storage space used by the instruction to be screened of the instruction block to be screened, the instruction block to be screened is at least one of the third instruction block and the fourth instruction block, and the instruction to be screened is the collection instruction of the third instruction block or the initial instruction of the fourth instruction block. The second determination submodule is used to determine at least one second storage space to be screened from the multiple first storage spaces to be screened according to the relationship between the first instruction block and the initial instruction block and the relationship between the second instruction block and the initial instruction block. The third determination submodule is used to determine the storage space to be optimized from at least one second storage space to be screened.

[0085] In some embodiments, the multiple instruction blocks come from multiple instruction segments, and the multiple instruction segments include at least one of a cyclic instruction segment and a non-cyclic instruction segment. The second determination submodule includes: a first determination unit, which is used to determine the first storage space to be screened as the second storage space to be screened in response to determining that the relationship between the initial instruction block and the first instruction block meets the first preset condition, the relationship between the initial instruction block and the second instruction block meets the second preset condition, and any initial instruction in the third instruction block does not use the first storage space to be screened. The first preset condition includes: the initial instruction block is the same as the first instruction block or the initial instruction block is the predecessor instruction block of the first instruction block. The second preset condition includes: the initial instruction block and the second instruction block belong to the same cyclic instruction segment or the initial instruction block and the second instruction block belong to the non-cyclic instruction segment.

[0086] In some embodiments, the third determination submodule includes: a second determination unit, which is used to determine the second storage space to be screened as the storage space to be optimized in response to determining that the second storage space to be screened satisfies the third preset condition. . The third preset condition includes at least one of the following: the instruction block using the second storage space to be screened is not the second instruction block or the third instruction block. The instruction block using the second storage space to be screened is the second instruction block, the pending instruction corresponding to the second storage space to be screened in the second instruction block is a collection instruction, and the instruction parameter corresponding to the second storage space to be screened in the collection instruction includes the identifier of the first instruction block. The instruction block using the second storage space to be screened is the third instruction block, the pending instruction corresponding to the second storage space to be screened in the third instruction block is a collection instruction, and the instruction parameter corresponding to the second storage space to be screened in the collection instruction does not include the identifier of the first instruction block.

[0087] In some embodiments, the update module includes: an adding submodule, used to add a target collection instruction in a second instruction block corresponding to a plurality of storage spaces to be optimized. A fourth determining submodule, used to determine a plurality of target instruction parameters of the target collection instruction, wherein the target instruction parameters include an identifier of the storage space to be optimized and an identifier of a first code block corresponding to the second instruction block. An updating submodule, used to update a plurality of to-be-processed instructions corresponding to the plurality of storage spaces to be optimized using the target storage space, to obtain a plurality of processed instructions.

[0088] In some embodiments, the target storage space includes a plurality of target storage subspaces, and the plurality of target storage subspaces respectively correspond to a plurality of storage spaces to be optimized.

[0089] In the technical solution of the present disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved are in compliance with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0090] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium and a computer program product.

[0091] Figure 5 A schematic block diagram of an example electronic device 500 that can be used to implement an embodiment of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present disclosure described and / or required herein.

[0092] like Figure 5 As shown, the device 500 includes a computing unit 501, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 502 or a computer program loaded from a storage unit 508 to a random access memory (RAM) 503. In the RAM 503, various programs and data required for the operation of the device 500 can also be stored. The computing unit 501, the ROM 502, and the RAM 503 are connected to each other via a bus 504. An input / output (I / O) interface 505 is also connected to the bus 504.

[0093] A number of components in the device 500 are connected to the I / O interface 505, including: an input unit 506, such as a keyboard, a mouse, etc.; an output unit 507, such as various types of displays, speakers, etc.; a storage unit 508, such as a disk, an optical disk, etc.; and a communication unit 509, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 509 allows the device 500 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0094] The computing unit 501 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 501 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSP), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 501 performs the various methods and processes described above, such as a text processing method and / or a deployment method of a deep learning framework. For example, in some embodiments, the text processing method and / or the deployment method of a deep learning framework may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 508. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 500 via the ROM 502 and / or the communication unit 509. When the computer program is loaded into RAM 503 and executed by computing unit 501, one or more steps of the text processing method and / or the method for deploying a deep learning framework described above may be performed. Alternatively, in other embodiments, computing unit 501 may be configured to execute the text processing method and / or the method for deploying a deep learning framework in any other appropriate manner (e.g., by means of firmware).

[0095] Various embodiments of the systems and techniques described above herein may be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard parts (ASSPs), system on chip systems (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0096] The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0097] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or device, or any suitable combination of the foregoing. More specific examples of machine-readable storage media may include electrical connections based on one or more lines, portable computer disks, hard disks, random access memories, read-only memories, erasable programmable read-only memories (EPROM) or flash memories, optical fibers, portable compact disk read-only memories (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0098] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a cathode ray tube (CRT) display or a liquid crystal display (LCD)) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or a trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0099] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a Local Area Network (LAN), a Wide Area Network (WAN), and the Internet.

[0100] A computer system may include clients and servers. Clients and servers are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship to each other.

[0101] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0102] The above specific implementations do not constitute a limitation on the protection scope of the present disclosure. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present disclosure shall be included in the protection scope of the present disclosure.

Claims

1. A storage space processing method, comprising: Determining a plurality of storage spaces to be optimized from a plurality of initial storage spaces for a plurality of instruction blocks, wherein the plurality of instruction blocks include a first instruction block and a second instruction block, the first instruction block includes a conditional branch instruction, and the second instruction block is a destination instruction block of the conditional branch instruction; According to the plurality of storage spaces to be optimized for the second instruction block and the target storage space for the second instruction block, a plurality of pending instructions corresponding to the plurality of storage spaces to be optimized are updated into a plurality of processed instructions, wherein the operations performed by the processed instructions include at least one of the following: reading data in the target storage space and writing data to the target storage space; A physical storage space is allocated to the target storage space.

2. The method according to claim 1, wherein: The plurality of instruction blocks further include a third instruction block and a fourth instruction block, the third instruction block being a destination instruction block of a branch instruction of the second instruction block, the fourth instruction block being an instruction block other than the second instruction block among a plurality of predecessor instruction blocks of the third instruction block, Determining a plurality of storage spaces to be optimized from a plurality of initial storage spaces for a plurality of instruction blocks comprises: Determine at least one initial instruction block defining a plurality of first storage spaces to be screened, wherein the first storage space to be screened is the initial storage space used by the instructions to be screened of the instruction block to be screened, the instruction block to be screened is at least one of the third instruction block and the fourth instruction block, and the instruction to be screened is a collection instruction of the third instruction block or an initial instruction of the fourth instruction block; Determining at least one second storage space to be screened from a plurality of first storage spaces to be screened according to a relationship between the first instruction block and the initial instruction block and a relationship between the second instruction block and the initial instruction block; The storage space to be optimized is determined from at least one of the second storage spaces to be screened.

3. The method according to claim 2, wherein: The plurality of instruction blocks are from a plurality of instruction segments, wherein the plurality of instruction segments include at least one of a cyclic instruction segment and a non-cyclic instruction segment. Determining at least one second storage space to be screened from a plurality of first storage spaces to be screened according to the relationship between the first instruction block and the initial instruction block and the relationship between the second instruction block and the initial instruction block comprises: In response to determining that the relationship between the initial instruction block and the first instruction block satisfies a first preset condition, the relationship between the initial instruction block and the second instruction block satisfies a second preset condition, and any initial instruction in the third instruction block does not use the first storage space to be screened, the first storage space to be screened is determined as the second storage space to be screened, wherein the first preset condition includes: the initial instruction block is the same as the first instruction block or the initial instruction block is a predecessor instruction block of the first instruction block, and the second preset condition includes: the initial instruction block and the second instruction block belong to the same cyclic instruction segment or the initial instruction block and the second instruction block belong to a non-cyclic instruction segment.

4. The method according to claim 2, wherein: The determining the storage space to be optimized from at least one of the second storage spaces to be screened comprises: In response to determining that the second storage space to be screened meets a third preset condition, determining the second storage space to be screened as a storage space to be optimized, The third preset condition includes at least one of the following: The instruction block using the second storage space to be filtered is not the second instruction block or is not the third instruction block; The instruction block using the second storage space to be screened is the second instruction block, the to-be-processed instruction corresponding to the second storage space to be screened in the second instruction block is a collection instruction, and the instruction parameter corresponding to the second storage space to be screened in the collection instruction includes an identifier of the first instruction block; The instruction block using the second storage space to be filtered is the third instruction block, the to-be-processed instruction corresponding to the second storage space to be filtered in the third instruction block is a collection instruction, and the instruction parameters corresponding to the second storage space to be filtered in the collection instruction do not include the identifier of the first instruction block.

5. The method according to claim 1, wherein: The updating of the plurality of to-be-processed instructions corresponding to the plurality of storage spaces to be optimized into a plurality of processed instructions according to the plurality of storage spaces to be optimized for the second instruction block and the target storage space for the second instruction block comprises: Adding a target collection instruction in the second instruction block corresponding to the plurality of storage spaces to be optimized; Determining a plurality of target instruction parameters of the target collection instruction, wherein the target instruction parameters include an identifier of the storage space to be optimized and an identifier of the first code block corresponding to the second instruction block; The target storage space is used to update a plurality of instructions to be processed corresponding to the plurality of storage spaces to be optimized, so as to obtain a plurality of processed instructions.

6. The method according to claim 1, wherein: The target storage space includes a plurality of target storage subspaces, and the plurality of target storage subspaces respectively correspond to a plurality of the storage spaces to be optimized.

7. A storage space processing device, comprising: A determination module, configured to determine a plurality of storage spaces to be optimized from a plurality of initial storage spaces for a plurality of instruction blocks, wherein the plurality of instruction blocks include a first instruction block and a second instruction block, the first instruction block includes a conditional branch instruction, and the second instruction block is a destination instruction block of the conditional branch instruction; an updating module, configured to update a plurality of pending instructions corresponding to the plurality of storage spaces to be optimized into a plurality of processed instructions according to the plurality of storage spaces to be optimized for the second instruction block and the target storage space for the second instruction block, wherein the operations performed by the processed instructions include at least one of the following: reading data in the target storage space and writing data to the target storage space; The allocation module is used to allocate physical storage space to the target storage space.

8. The device according to claim 7, wherein: The plurality of instruction blocks further include a third instruction block and a fourth instruction block, the third instruction block being a destination instruction block of a branch instruction of the second instruction block, the fourth instruction block being an instruction block other than the second instruction block among a plurality of predecessor instruction blocks of the third instruction block, The determination module comprises: A first determination submodule is used to determine at least one initial instruction block defining a plurality of first storage spaces to be screened, wherein the first storage space to be screened is the initial storage space used by the instructions to be screened of the instruction block to be screened, the instruction block to be screened is at least one of the third instruction block and the fourth instruction block, and the instruction to be screened is a collection instruction of the third instruction block or an initial instruction of the fourth instruction block; A second determining submodule, configured to determine at least one second storage space to be screened from a plurality of first storage spaces to be screened according to a relationship between the first instruction block and the initial instruction block and a relationship between the second instruction block and the initial instruction block; The third determining submodule is used to determine the storage space to be optimized from at least one of the second storage spaces to be screened.

9. The device according to claim 8, wherein: The plurality of instruction blocks are from a plurality of instruction segments, wherein the plurality of instruction segments include at least one of a cyclic instruction segment and a non-cyclic instruction segment. The second determining submodule includes: A first determining unit is configured to determine the first storage space to be screened as the second storage space to be screened in response to determining that the relationship between the initial instruction block and the first instruction block satisfies a first preset condition, the relationship between the initial instruction block and the second instruction block satisfies a second preset condition, and any initial instruction in the third instruction block does not use the first storage space to be screened, wherein the first preset condition includes: the initial instruction block is the same as the first instruction block or the initial instruction block is a predecessor instruction block of the first instruction block, and the second preset condition includes: the initial instruction block and the second instruction block belong to the same cyclic instruction segment or the initial instruction block and the second instruction block belong to a non-cyclic instruction segment.

10. The device according to claim 8, wherein: The third determining submodule comprises: a second determining unit, configured to determine the second storage space to be screened as a storage space to be optimized in response to determining that the second storage space to be screened satisfies a third preset condition; The third preset condition includes at least one of the following: The instruction block using the second storage space to be filtered is not the second instruction block or is not the third instruction block; The instruction block using the second storage space to be screened is the second instruction block, the to-be-processed instruction corresponding to the second storage space to be screened in the second instruction block is a collection instruction, and the instruction parameter corresponding to the second storage space to be screened in the collection instruction includes an identifier of the first instruction block; The instruction block using the second storage space to be filtered is the third instruction block, the to-be-processed instruction corresponding to the second storage space to be filtered in the third instruction block is a collection instruction, and the instruction parameters corresponding to the second storage space to be filtered in the collection instruction do not include the identifier of the first instruction block.

11. The device according to claim 7, wherein: The update module includes: An adding submodule, configured to add a target collection instruction in the second instruction block corresponding to the plurality of storage spaces to be optimized; a fourth determination submodule, configured to determine a plurality of target instruction parameters of the target collection instruction, wherein the target instruction parameters include an identifier of the storage space to be optimized and an identifier of the first code block corresponding to the second instruction block; An updating submodule is used to use the target storage space to update a plurality of instructions to be processed corresponding to the plurality of storage spaces to be optimized, so as to obtain a plurality of processed instructions.

12. The device according to claim 7, wherein: The target storage space includes a plurality of target storage subspaces, and the plurality of target storage subspaces respectively correspond to a plurality of the storage spaces to be optimized.

13. An electronic device comprising: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 6.

14. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to cause the computer to execute the method according to any one of claims 1 to 6.

15. A computer program product comprising a computer program, which, when executed by a processor, implements the method according to any one of claims 1 to 6.

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