FPGA graph generation device supporting OpenGL function drawing

Abstract

The invention relates to the technical field of graph generation, and discloses an FPGA graph generation device supporting OpenGL function drawing, which comprises a graph drawing processor, an FPGA chip, a BRAM, an SRAM and a DDR, the graph drawing processor comprises symbol generation software and a software and hardware interface unit; the symbol generation software is used for calling a graph drawing function to draw a symbol graph, and the software and hardware interface unit is used for sending a drawing instruction to the BRAM and sending drawing data to the SRAM; the FPGA chip comprises an instruction analysis unit, a graph drawing unit and a display output unit; the instruction analysis unit is used for analyzing and packaging the drawing data according to the drawing instruction to form a primitive structure body and writing the primitive structure body into the SRAM; the graph drawing unit is used for sequentially reading the primitive structural bodies from the SRAM, carrying out data processing according to information in the primitive structural bodies, generating a pixel picture result and writing the pixel picture result into the DDR; and the display output unit is used for reading the data in the DDR and outputting a video picture according to a set video output time sequence.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of computer graphics generation, and in particular to an FPGA graphics generation device that supports OpenGL function drawing. Background Art

[0002] The core function of the airborne display system is to draw symbol images based on the received flight parameters and display them through the HUD and head-up display. This process relies on the graphics generation platform composed of display drivers and hardware computing resources. The current airborne display system mainly uses three types of methods to complete the graphics generation function, namely commercial graphics processors (GPUs), CPU-based graphics generation devices, and FPGA-based graphics generation devices.

[0003] There are relatively few commercial GPUs to choose from, and they need to be used with CPUs and FPGA chips, which have disadvantages such as high power consumption and large size. The CPU-based graphics generation device completes the graphics drawing function in the CPU and outputs the video screen through the FPGA chip. It is suitable for SCADE model software drawing, but it also has disadvantages such as high power consumption, low frame rate, and large latency. The FPGA chip-based graphics generation device completes the graphics drawing and video output functions in the FPGA chip and uses the CPU to send drawing instructions, but it is incompatible with the general OpenGL function interface and is not suitable for SCADE model software drawing. It is not portable and has the disadvantage of poor versatility. Summary of the invention

[0004] In view of this, an embodiment of the present application proposes an FPGA graphics generation device that supports OpenGL drawing, which uses a graphics drawing processor to send drawing instructions and drawing data to the FPGA chip according to the graphics drawing function. The FPGA chip implements instruction parsing, graphics drawing, display output and other functions based on the received drawing instructions and drawing data, supports OpenGL function drawing, and has the advantages of high versatility, low power consumption and high integration.

[0005] In order to achieve the above-mentioned purpose, an embodiment of the present application proposes an FPGA graphics generation device that supports OpenGL function drawing, the device comprising: a graphics drawing processor, an FPGA chip, a drawing instruction cache BRAM, a drawing data cache SRAM and a graphics display memory DDR, the graphics drawing processor is connected to the BRAM and SRAM respectively, and the FPGA chip is connected to the BRAM, SRAM and DDR respectively; the graphics drawing processor is composed of symbol generation software and a software and hardware interface unit; the symbol generation software is used to call the graphics drawing function to draw symbol graphics, and the software and hardware interface unit is used to send drawing instructions to the BRAM according to the graphics drawing function, and send drawing data to the SRAM; wherein the graphics drawing function includes an OpenGL function, a display window setting function and a display output setting function. Function; The FPGA chip consists of an instruction parsing unit, a graphics drawing unit and a display output unit; the instruction parsing unit is used to read drawing instructions from BRAM, read drawing data from SRAM, parse and pack the drawing data according to the drawing instructions, form a primitive structure, and write it to the specified address of SRAM, and write a feedback instruction to the specified address of BRAM to indicate that the parsing is completed; the graphics drawing unit is used to read the primitive structure from the specified address of SRAM in sequence, perform data processing including geometry processing, rasterization processing and fragment post-processing according to the information in the primitive structure, generate a pixel screen result, and write it to the specified address of DDR; the display output unit is used to read the data in the specified address of DDR, and output the video screen according to the set video output timing.

[0006] In order to achieve the above-mentioned purpose, an embodiment of the present application also proposes an FPGA graphics generation method that supports OpenGL function drawing, comprising the following steps: a graphics drawing processor calls a graphics drawing function to draw a symbolic graphic, and sends drawing data to a drawing instruction cache BRAM and a drawing data cache SRAM according to the graphics drawing function; an FPGA chip reads drawing instructions from the BRAM, reads drawing data from the SRAM, parses and packages the drawing data according to the drawing instructions to form a primitive structure, and writes it to a specified address of the SRAM, and writes a return instruction to the specified address of the BRAM to indicate that the parsing is complete; the primitive structure is read from the specified address of the SRAM in sequence, and data processing including geometry processing, rasterization processing and fragment post-processing is performed according to the information in the primitive structure to generate a pixel screen result, and writes it to a specified address of the graphics display memory DDR; the data in the specified address of the DDR is read, and the video screen is output according to the set video output timing.

[0007] The embodiment of the present application proposes an FPGA graphics generation device that supports OpenGL function drawing, which is specifically composed of a graphics drawing processor (CPU), an FPGA chip, a drawing instruction cache BRAM, a drawing data cache SRAM and a graphics display memory DDR. The symbol generation software of the graphics drawing processor can call graphics drawing functions including OpenGL functions to draw symbol graphics, which enables the device to support OpenGL function drawing, especially support SCADE model generation symbol generation software drawing, and can be widely used in various types of aviation airborne display systems. The graphics drawing processor, FPGA chip, drawing instruction cache BRAM, drawing data cache SRAM and graphics display memory DDR are all low-power devices, so the power consumption of the device is also at a relatively low level. The device realizes seamless coupling of drawing instruction sending and receiving functions, instruction parsing functions, graphics drawing functions, and display output functions, has high integration, and provides strong support for the graphic design of aviation airborne display systems.

[0008] In some optional embodiments, the drawing instructions include primitive drawing class drawing instructions and parameter setting class drawing instructions, and the parameter setting class drawing instructions include coordinate transformation matrix setting, rendering parameter setting, texture parameter setting, fragment parameter setting, display window setting and display output setting.

[0009] In some optional embodiments, the drawing data includes a vertex coordinate array, a color array, a texture coordinate array, an index array, and a texture map.

[0010] In some optional embodiments, the primitive structure includes a drawing information header, a vertex structure, a matrix structure, a rendering parameter structure, a fragment parameter structure, and a texture object structure.

[0011] In some optional embodiments, the drawing information header in the primitive structure includes primitive type, number of vertices, vertex structure index, matrix structure index, rendering parameter index, texture object index and fragment parameter index, and the primitive types specifically include points, lines, triangles, polygons, circles and arcs.

[0012] In some optional embodiments, the geometric processing in the graphics drawing unit includes: reading vertex data from a vertex structure and reading matrix data from a matrix structure according to a drawing information header; performing matrix transformations including rotation, translation, and scaling on the vertices to obtain transformed vertex data; and assembling the transformed vertex data into primitive data according to the primitive type.

[0013] In some optional embodiments, the rasterization processing in the graphics drawing unit includes: reading primitive data, and allocating the primitive data to the corresponding rasterization calculation module according to the corresponding primitive type; reading rendering parameters from the rendering parameter structure according to the index value in the drawing information header; performing rasterization calculation on the primitive data in the rasterization calculation module according to the rendering parameters, and performing anti-aliasing processing to obtain fragment data.

[0014] In some optional embodiments, fragment post-processing in the graphics drawing unit includes: reading fragment data, reading fragment parameters and texture parameters from the fragment parameter structure and the texture object structure respectively according to the index value in the drawing information header; performing template test operation, texture mapping operation, Alpha test operation and color blending operation on the fragment data in sequence to obtain a pixel picture result; wherein the texture information required for the texture mapping operation is obtained by reading the texture map in the SRAM according to the texture parameters.

[0015] In some optional embodiments, the video output timing set in the display output unit includes VESA timing, LVDS timing, digital RGB timing and ARINC818 timing. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the related technologies, the drawings required for use in the embodiments of the present application or the related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0017] Figure 1 It is a structural schematic diagram of an FPGA graphics generation device supporting OpenGL function drawing provided in one embodiment of the present application;

[0018] Figure 2 is a schematic diagram of the working principle of a graphics rendering processor provided in one embodiment of the present application;

[0019] Figure 3 is a schematic diagram of the division of drawing instructions in a BRAM provided in one embodiment of the present application;

[0020] Figure 4 is a schematic diagram of the division of drawing data in SRAM provided in one embodiment of the present application;

[0021] Figure 5 It is a schematic diagram of the working principle of the instruction parsing unit of the FPGA chip provided in one embodiment of the present application;

[0022] Figure 6It is a schematic diagram of the working principle of the graphics drawing unit of the FPGA chip provided in one embodiment of the present application;

[0023] Figure 7 It is a flowchart of an FPGA graphics generation method supporting OpenGL function drawing provided in another embodiment of the present application. DETAILED DESCRIPTION

[0024] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below in conjunction with the accompanying drawings. However, it will be appreciated by those skilled in the art that in the present application, many technical details are proposed in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present application can also be implemented. The division of the following embodiments is for the convenience of description, and the specific implementation of the present application should not be construed as any limitation, and the various embodiments can be combined and referenced with each other under the premise of no contradiction.

[0025] An embodiment of the present application proposes an FPGA graphics generation device that supports OpenGL function drawing. The implementation details of the FPGA graphics generation device that supports OpenGL function drawing proposed in this embodiment are specifically described below. The following content is only the implementation details provided for the convenience of understanding and is not necessary for the implementation of this solution.

[0026] The specific structure of the FPGA graphics generation device supporting OpenGL function drawing proposed in this embodiment can be as follows: Figure 1 As shown, it includes: a graphics rendering processor 10, an FPGA chip 20, a drawing instruction cache BRAM30, a drawing data cache SRAM40 and a graphics display memory DDR50. The graphics rendering processor 10 is connected to the drawing instruction cache BRAM30 and the drawing data cache SRAM40 respectively, and the FPGA chip 20 is connected to the drawing instruction cache BRAM30, the drawing data cache SRAM40 and the graphics display memory DDR50 respectively.

[0027] In a specific implementation, the graphics drawing processor 10 is composed of a symbol generation software 11 and a software and hardware interface unit 12. The symbol generation software 11 is used to call a graphics drawing function to draw a symbol graphic, and the software and hardware interface unit 12 is used to send a drawing instruction to a drawing instruction cache BRAM 30 according to the graphics drawing function, and send drawing data to a drawing data cache SRAM 40. Among them, the software and hardware interface unit 12 needs to obtain a graphics drawing function from the symbol generation software 11, and the graphics drawing function includes an OpenGL function, a display window setting function, and a display output setting function.

[0028] In one example, the OpenGL function is a function specified by OpenGL SC 1.0.1 version.

[0029] In one example, the working principle of the symbol generation software and the hardware and software interface unit can be as follows: Figure 2 As shown, the drawing instructions include primitive drawing instructions and parameter setting instructions. The parameter setting instructions include but are not limited to coordinate conversion matrix settings, rendering parameter settings, texture parameter settings, fragment parameter settings, display window settings, and display output settings. The drawing data includes but is not limited to vertex coordinate arrays, color arrays, texture coordinate arrays, index arrays, and texture maps.

[0030] In one example, a drawing instruction consists of an instruction header and drawing parameters. The instruction header is specifically an identifier of an OpenGL function instruction, which is used for the instruction parsing unit to identify and process. The drawing parameters are the content of the OpenGL function instruction. Depending on the instruction, the number of parameters is between 1 and 16. The division of drawing instructions in BRAM can be as follows: Figure 3 shown.

[0031] In one example, the drawing data in SRAM can be divided as follows: Figure 4 shown.

[0032] In a specific implementation, the FPGA chip 20 is specifically composed of an instruction parsing unit 21, a graphics drawing unit 22, and a display output unit 23. The instruction parsing unit 21 is used to read drawing instructions from the drawing instruction cache BRAM30, read drawing data from the drawing data cache SRAM40, parse and pack the drawing data according to the drawing instructions, form a primitive structure, and write it into the specified address of the drawing data cache SRAM40, and write a return instruction into the specified address of the drawing instruction cache BRAM30. The return instruction is used to indicate that the parsing is completed, and the value of the return instruction is the instruction header of the drawing instruction + 0xA00. The graphics drawing unit 22 is used to read the primitive structure from the specified address of the drawing data cache SRAM40 in sequence, perform data processing including but not limited to geometric processing, rasterization processing, and fragment post-processing according to the information in the primitive structure, generate a pixel screen result, and write it into the specified address of the graphics memory DDR50. The display output unit 23 is used to read the data in the specified address of the graphics memory DDR50, and output the video screen according to the set video output timing.

[0033] In one example, the instruction parsing unit works as follows: Figure 5As shown, the primitive structure formed by the instruction parsing unit includes a drawing information header, a vertex structure, a matrix structure, a rendering parameter structure, a fragment parameter structure, and a texture object structure. The drawing information header in the primitive structure includes a primitive type, a vertex number, a vertex structure index, a matrix structure index, a rendering parameter index, a texture object index, and a fragment parameter index. The primitive types specifically include points, lines, triangles, polygons, circles, and arcs.

[0034] In one example, the graphics drawing unit may work as follows: Figure 6 shown.

[0035] When the graphics drawing unit performs geometric processing, it first needs to read vertex data from the vertex structure according to the drawing information header, read matrix data from the matrix structure, and then perform matrix transformations including rotation, translation, and scaling on the vertices to obtain transformed vertex data. Finally, the transformed vertex data is assembled into primitive data according to the primitive type.

[0036] When the graphics drawing unit performs rasterization processing, it first needs to read the primitive data, and distribute the primitive data to the corresponding rasterization calculation module according to the corresponding primitive type. The rasterization calculation module includes a point rasterization calculation module, a line rasterization calculation module, a triangle rasterization calculation module, a polygon rasterization calculation module, a circular rasterization calculation module, and an arc rasterization calculation module. Then, the rendering parameters are read from the rendering parameter structure according to the index value in the drawing information header, and then the primitive data in the rasterization calculation module are rasterized and anti-aliased according to the rendering parameters, so as to obtain the fragment data.

[0037] When the graphics drawing unit performs post-processing of the fragment, it first needs to read the fragment data, read the fragment parameters and texture parameters from the fragment parameter structure and texture object structure respectively according to the index value in the drawing information header, and then perform template test operation, texture mapping operation, alpha test operation, color mixing operation and other operations on the rasterized fragment data in sequence to obtain the pixel screen result, and finally write the pixel screen result to the specified address of the graphics memory DDR. Among them, the texture information required for the texture mapping operation is obtained by reading the texture map in the SRAM according to the texture parameters.

[0038] In one example, the video output timing set in the display output unit includes VESA timing, LVDS timing, digital RGB timing and ARINC818 timing.

[0039] The present embodiment proposes an FPGA graphics generation device that supports OpenGL function drawing, which is specifically composed of a graphics drawing processor, an FPGA chip, a drawing instruction cache BRAM, a drawing data cache SRAM, and a graphics display memory DDR. The symbol generation software of the graphics drawing processor can call graphics drawing functions including OpenGL functions to draw symbol graphics, which enables the device to support OpenGL function drawing, especially support the drawing of symbol generation software generated by SCADE models, and can be widely used in various types of aviation airborne display systems. The graphics drawing processor, FPGA chip, drawing instruction cache BRAM, drawing data cache SRAM, and graphics display memory DDR are all low-power devices, so the power consumption of the device is also at a relatively low level. The device realizes seamless coupling of drawing instruction sending and receiving functions, instruction parsing functions, graphics drawing functions, and display output functions, has a high degree of integration, and provides strong support for the graphic design of aviation airborne display systems.

[0040] It is worth mentioning that all modules involved in this embodiment are logic modules. In practical applications, a logic unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. In addition, in order to highlight the innovative part of this application, this embodiment does not introduce units that are not closely related to solving the technical problems proposed by this application, but this does not mean that there are no other units in this embodiment.

[0041] Another embodiment of the present application proposes an FPGA graphics generation method that supports OpenGL function drawing. The implementation details of the FPGA graphics generation method that supports OpenGL function drawing proposed in this embodiment are specifically described below. The following content is only the implementation details provided for the convenience of understanding and is not necessary for the implementation of this solution.

[0042] The specific process of the FPGA graphics generation method supporting OpenGL function drawing proposed in this embodiment can be as follows: Figure 7 As shown, including:

[0043] S1, the graphics drawing processor calls the graphics drawing function to draw the symbol graphics, and sends the drawing data to the drawing instruction cache BRAM and the drawing data cache SRAM according to the graphics drawing function.

[0044] S2, the FPGA chip reads the drawing instructions from the BRAM, reads the drawing data from the SRAM, parses and packages the drawing data according to the drawing instructions, forms a primitive structure, and writes it to the specified address of the SRAM. At the same time, a feedback instruction is written to the specified address of the BRAM to indicate that the parsing is completed.

[0045] S3, reads the primitive structure from the specified address of SRAM in sequence, performs data processing including geometry processing, rasterization processing and fragment post-processing according to the information in the primitive structure, generates a pixel image result, and writes it to the specified address of the graphics memory DDR.

[0046] S4, reading the data in the designated address of the graphics display memory DDR, and outputting the video screen according to the set video output timing.

[0047] The step division of the above methods is only for clear description. When implemented, they can be combined into one step or some steps can be split and decomposed into multiple steps. As long as they include the same logical relationship, they are all within the scope of protection of this application; adding insignificant modifications to the algorithm or process or introducing insignificant designs without changing the core design of the algorithm and process are all within the scope of protection of this application.

[0048] It is not difficult to find that this embodiment is a method = embodiment corresponding to the above embodiment, and this embodiment can be implemented in conjunction with the above embodiment. The relevant technical details and technical effects mentioned in the above embodiment are still valid in this embodiment. In order to reduce repetition, they are not repeated here. Accordingly, the various relevant technical details mentioned in this embodiment can also be applied in the above embodiment.

[0049] Another embodiment of the present application provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it can implement an FPGA graphics generation method that supports OpenGL function drawing as described in the above method embodiment.

[0050] That is, those skilled in the art can understand that all or part of the steps in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a program, and the program is stored in a storage medium, including a number of instructions to enable a device (which can be a single-chip microcomputer, chip, etc.) or a processor to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, referred to as: ROM), random access memory (Random Access Memory, referred to as: RAM), disk or optical disk and other media that can store program codes.

[0051] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present application, and in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present application.

Claims

1. An FPGA graphics generation device supporting OpenGL function drawing, characterized in that: include: A graphics drawing processor, an FPGA chip, a drawing instruction cache BRAM, a drawing data cache SRAM and a graphics display memory DDR, wherein the graphics drawing processor is connected to the BRAM and the SRAM respectively, and the FPGA chip is connected to the BRAM, the SRAM and the DDR respectively; The graphics rendering processor consists of symbol generation software and a hardware and software interface unit; The symbol generation software is used to call the graphics drawing function to draw the symbol graphics, and the software and hardware interface unit is used to send the drawing instruction to the BRAM according to the graphics drawing function, and send the drawing data to the SRAM; wherein the graphics drawing function includes the OpenGL function, the display window setting function and the display output setting function; The FPGA chip consists of an instruction parsing unit, a graphics drawing unit, and a display output unit; The instruction parsing unit is used to read drawing instructions from BRAM, read drawing data from SRAM, parse and pack the drawing data according to the drawing instructions, form a primitive structure, and write it into the specified address of SRAM, and write a feedback instruction into the specified address of BRAM to indicate that the parsing is completed; The graphics drawing unit is used to read the primitive structure from the specified address of SRAM in sequence, perform data processing including geometry processing, rasterization processing and fragment post-processing according to the information in the primitive structure, generate pixel screen results, and write them into the specified address of DDR; The display output unit is used to read the data in the specified address of DDR and output the video screen according to the set video output timing.

2. The FPGA graphics generation device supporting OpenGL function drawing according to claim 1, characterized in that: Drawing instructions include primitive drawing class drawing instructions and parameter setting class drawing instructions. Parameter setting class drawing instructions include coordinate conversion matrix setting, rendering parameter setting, texture parameter setting, fragment parameter setting, display window setting and display output setting.

3. The FPGA graphics generation device supporting OpenGL function drawing according to claim 1, characterized in that: Drawing data includes vertex coordinate array, color array, texture coordinate array, index array and texture map.

4. The FPGA graphics generation device supporting OpenGL function drawing according to claim 1, characterized in that: The primitive structure includes a drawing information header, a vertex structure, a matrix structure, a rendering parameter structure, a fragment parameter structure, and a texture object structure.

5. The FPGA graphics generation device supporting OpenGL function drawing according to claim 4, characterized in that: The drawing information header in the primitive structure includes primitive type, number of vertices, vertex structure index, matrix structure index, rendering parameter index, texture object index and fragment parameter index. Primitive types specifically include point, line, triangle, polygon, circle and arc.

6. The FPGA graphics generation device supporting OpenGL function drawing according to claim 5, characterized in that: Geometry processing in the graphics rendering unit, including: Read vertex data from the vertex structure and matrix data from the matrix structure according to the drawing information header; Perform matrix transformations including rotation, translation, and scaling on vertices to obtain transformed vertex data; Assemble the transformed vertex data into primitive data according to the primitive type.

7. The FPGA graphics generation device supporting OpenGL function drawing according to claim 6, characterized in that: Rasterization processing in the graphics drawing unit, including: Read the metadata and assign the metadata to the corresponding rasterization calculation module according to the corresponding primitive type; Read rendering parameters from the rendering parameter structure according to the index value in the drawing information header; The image metadata in the rasterization calculation module is rasterized and anti-aliased according to the rendering parameters to obtain the fragment metadata.

8. The FPGA graphics generation device supporting OpenGL function drawing according to claim 7, characterized in that: Fragment post-processing in the graphics rendering unit, including: Read the fragment data, and read the fragment parameters and texture parameters from the fragment parameter structure and texture object structure respectively according to the index value in the drawing information header; Performing template test operation, texture mapping operation, Alpha test operation and color blending operation on the piece data in sequence to obtain a pixel image result; The texture information required for the texture mapping operation is obtained by reading the texture map in the SRAM according to the texture parameters.

9. An FPGA graphics generation device supporting OpenGL function drawing according to any one of claims 1 to 8, characterized in that: The video output timing set in the display output unit includes VESA timing, LVDS timing, digital RGB timing and ARINC818 timing.

10. A method for generating FPGA graphics supporting OpenGL function drawing, characterized in that: include: The graphics drawing processor calls the graphics drawing function to draw the symbol graphics, and sends the drawing data to the drawing instruction cache BRAM and the drawing data cache SRAM according to the graphics drawing function; The FPGA chip reads the drawing instructions from the BRAM and the drawing data from the SRAM, parses and packages the drawing data according to the drawing instructions to form a primitive structure, and writes it to the specified address of the SRAM. At the same time, a feedback instruction is written to the specified address of the BRAM to indicate that the parsing is completed; Read the primitive structure from the specified address of SRAM in sequence, perform data processing including geometry processing, rasterization processing and fragment post-processing according to the information in the primitive structure, generate pixel screen results, and write them to the specified address of the graphics memory DDR; Read the data in the specified address of DDR and output the video screen according to the set video output timing.

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