A method and apparatus for coroutine implementation for GPU programming
The coroutine implementation method automates the division and scheduling of GPU programming tasks, solves the problem of low parallel execution efficiency in GPU programming, and achieves efficient parallel execution and optimization of hardware resources.
Patent Information
- Application Number
- CN202411478663.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-22
- Publication Date
- 2025-10-10
- Estimated Expiration
- 2044-10-22
AI Technical Summary
In existing technologies, the parallel execution of high-workload and complex tasks in GPU programming is inefficient, manual segmentation and scheduling are complex and error-prone, and there is a lack of a unified automated solution.
This paper provides a coroutine implementation method for GPU programming. It obtains the coroutine program code written by the user, uses suspended nodes to split the computing tasks, converts it into an intermediate representation and performs data flow analysis, automatically divides it into subroutines and coroutine frames, and executes them in parallel in multiple threads of the GPU based on the coroutine frames.
It achieves efficient parallel execution of a large number of coroutines, simplifies the developer's scheduling logic design, improves hardware utilization and program operation efficiency, and simplifies development difficulty.
Smart Images
Figure CN119556990B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of computer graphics and programming languages, and in particular to a method and device for implementing a coroutine for GPU programming. Background Art
[0002] Modern GPUs have evolved into powerful general-purpose parallel computing devices capable of handling increasingly complex rendering tasks. However, while it is feasible to implement high-volume, complex tasks such as path tracing in a single large kernel (mega-kernel), this straightforward implementation leads to poor hardware utilization due to thread divergence in control flow and memory access. As a result, graphics developers are often forced to refactor rendering tasks into multiple smaller GPU kernels and manually schedule their execution to improve performance. A classic example is wavefront path tracing, which decomposes the path tracing process of a large kernel into multiple sub-kernels. However, manually partitioning and scheduling large kernels is quite complex and error-prone, which has led us to seek a unified, automated solution that expands the expressiveness of the original programming model so that developers can focus on algorithm design and avoid investing energy in complex scheduling logic design.
[0003] How to efficiently execute a large number of coroutines in parallel is a technical problem that needs to be solved. Summary of the Invention
[0004] The present invention provides a coroutine implementation method and device for GPU programming, which are used to solve the defects in the prior art.
[0005] The present invention provides a coroutine implementation method for GPU programming, comprising the following steps:
[0006] Obtaining a coroutine program code written by a user based on a GPU programming language; wherein the coroutine program code includes at least one suspend node, and the suspend node is used to define the suspend behavior and resume behavior of the coroutine;
[0007] The computing task corresponding to the coroutine is divided according to the suspension node of the coroutine program code to obtain a plurality of subroutines and a plurality of coroutine frames; wherein the coroutine frame is used to transmit information between the plurality of subroutines;
[0008] Based on the multiple coroutine frames, the divided multiple subroutines are respectively allocated to multiple threads of the GPU for parallel execution.
[0009] According to a coroutine implementation method for GPU programming provided by the present invention, the computing task corresponding to the coroutine is divided according to the suspension node of the coroutine program code to obtain multiple subroutines, including:
[0010] Converting the coroutine program code into an intermediate representation;
[0011] Based on the intermediate representation and the suspended nodes of the coroutine program code, multiple preset calculation rules are executed to obtain multiple subroutines that are divided based on the calculation tasks corresponding to the coroutine.
[0012] According to a coroutine implementation method for GPU programming provided by the present invention, converting the coroutine program code into an intermediate representation includes:
[0013] The abstract syntax tree corresponding to the coroutine program code is converted into a control flow graph, and the control flow graph is simplified to obtain a simplified control flow graph; wherein the simplified control flow graph is used to describe the overall control flow process of the coroutine, and the simplified control flow graph includes: basic nodes, control flow nodes and termination nodes.
[0014] According to a coroutine implementation method for GPU programming provided by the present invention, the method includes executing multiple preset calculation rules based on the intermediate representation and the suspended node of the coroutine program code to obtain multiple subroutines divided based on the computing tasks corresponding to the coroutine, including:
[0015] Traversing the simplified control flow graph, determining a plurality of potential subroutines, and forming a reachable node set based on a reachable node of each potential subroutine in the plurality of potential subroutines;
[0016] Based on the reachable node set and the suspended nodes of the coroutine program code, a plurality of subroutines are obtained which are divided based on the computing tasks corresponding to the coroutine.
[0017] According to a coroutine implementation method for GPU programming provided by the present invention, the computing task corresponding to the coroutine is divided according to the suspension node of the coroutine program code to obtain multiple coroutine frames, including:
[0018] Splitting the computing task corresponding to the coroutine according to the suspension node of the coroutine program code, and performing data flow analysis on the split coroutine to obtain the activity status of each of the multiple split points;
[0019] Based on the active state of each of the multiple split points, a corresponding plurality of coroutine frames are obtained.
[0020] According to a coroutine implementation method for GPU programming provided by the present invention, the data flow analysis includes: internal usage definition parsing and cross-domain active state analysis;
[0021] The data flow analysis is performed on the split coroutine to obtain the active status of each of the multiple split points, including:
[0022] Perform internal usage definition analysis and cross-domain active status analysis on the split coroutines to obtain the active status of each split point.
[0023] The internal usage definition parsing is used to extract the internal calls and external references of each subroutine in the multiple subroutines; and the cross-domain active state analysis is used to determine the storage relationship and loading relationship between the subroutines.
[0024] The present invention also provides a coroutine implementation device for GPU programming, comprising the following modules:
[0025] An acquisition module is configured to acquire a coroutine program code written by a user based on a GPU programming language; wherein the coroutine program code includes at least one suspend node, and the suspend node is configured to define the suspend behavior and resume behavior of the coroutine;
[0026] A splitting module, configured to split the computing task corresponding to the coroutine according to the suspended nodes of the coroutine program code to obtain a plurality of subroutines and a plurality of coroutine frames; wherein the coroutine frame is used to transfer information between the plurality of subroutines;
[0027] The scheduling module is used to allocate the divided subroutines to multiple threads of the GPU for parallel execution based on the multiple coroutine frames.
[0028] According to a coroutine implementation device for GPU programming provided by the present invention, the segmentation module is specifically used to:
[0029] Converting the coroutine program code into an intermediate representation;
[0030] Based on the intermediate representation and the suspended nodes of the coroutine program code, multiple preset calculation rules are executed to obtain multiple subroutines that are divided based on the calculation tasks corresponding to the coroutine.
[0031] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the computer program, the processor implements any of the above-described coroutine implementation methods for GPU programming.
[0032] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements any of the above-described coroutine implementation methods for GPU programming.
[0033] The present invention also provides a computer program product, comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements any of the above-described coroutine implementation methods for GPU programming.
[0034] The present invention provides a coroutine implementation method and device for GPU programming, which obtains a coroutine program code written by a user based on a GPU programming language; wherein the coroutine program code includes at least one suspension node, and the suspension node is used to define the suspension behavior and recovery behavior of the coroutine; the computing task corresponding to the coroutine is divided according to the suspension node of the coroutine program code to obtain multiple subroutines and multiple coroutine frames; wherein the coroutine frame is used to transfer information between the multiple subroutines; based on the multiple coroutine frames, the multiple subroutines after division are respectively assigned to multiple threads of the GPU for parallel execution. It can be seen from this that the present invention automatically processes the division of subroutines and determines the coroutine frame for storing intermediate data according to the coroutine program code written by the user, runs the coroutine according to the parsing result, and can efficiently execute a large number of coroutines in parallel. BRIEF DESCRIPTION OF THE DRAWINGS
[0035] In order to more clearly illustrate the technical solutions in the present invention or the prior art, a brief introduction is given below to the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0036] Figure 1 This is a flow chart of the coroutine implementation method for GPU programming provided by the present invention.
[0037] Figure 2 This is an overall flow chart of the coroutine implementation method for GPU programming provided by the present invention.
[0038] Figure 3 This is a schematic diagram of an example of using the GPU programming language provided by the present invention.
[0039] Figure 4 It is a transformation diagram of the parser provided by the present invention.
[0040] Figure 5 It is a schematic diagram of a subroutine conversion diagram of the parser provided by the present invention.
[0041] Figure 6 It is a structural diagram of the coroutine implementation device for GPU programming provided by the present invention.
[0042] Figure 7 It is a structural schematic diagram of the electronic device provided by the present invention. DETAILED DESCRIPTION
[0043] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only some of the embodiments of the present invention, not all of them. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.
[0044] The following combination Figure 1-Figure 7 A method and device for implementing a coroutine for GPU programming according to the present invention are described.
[0045] Figure 1 This is a flow chart of the coroutine implementation method for GPU programming provided by the present invention, such as Figure 1 As shown, the method includes the following:
[0046] Step 100: Obtain a coroutine program code written by a user based on a GPU programming language; wherein the coroutine program code includes at least one suspend node, and the suspend node is used to define the suspend behavior and resume behavior of the coroutine.
[0047] It should be noted that a GPU (Graphics Processing Unit) is a processor specifically designed for efficient parallel processing of large amounts of data. This embodiment of the present invention implements GPU coroutine programming through three modules: a coroutine programming model for GPU programming and its corresponding domain-specific language (DSL) (i.e., the aforementioned GPU programming language); a parser for the coroutine programming model; and a scheduler for coroutine tasks. These modules are specific logic execution modules, not hardware structures.
[0048] Specifically, embodiments of the present invention provide an asymmetric, stackless coroutine programming model. The coroutine language features and runtime support provided by this embodiment are based on Luisa to reuse its constructs while avoiding platform-specific details. Figure 2 This is the overall flow chart of the coroutine implementation method for GPU programming provided by the present invention, such as Figure 2As shown in the figure, the implementation adds two new function categories, Coroutine and Generator, based on the original domain-specific language. Coroutine provides a basic function category declaration. The $suspend keyword can be used to mark the suspension location within it, allowing the parser to divide subroutines or identify specific subroutines. Other coroutines can also be called using the $await keyword to form recursive coroutine calls. Users can use the $promise keyword to explicitly store intermediate process values in the coroutine frame and use them in the calling function; they can also use .target_token and .coro_id to obtain the running status of the coroutine frame, the corresponding thread index and other information. Figure 3 This is a schematic diagram of the use of the GPU programming language provided by the present invention. For specific use cases, see Figure 3 .
[0049] The DOM also includes a high-level function pattern called Generator, which is a function object that produces a sequence only when called. Generators can suspend the return value through the $yield keyword.
[0050] Step 200: Split the computing task corresponding to the coroutine according to the suspension node of the coroutine program code to obtain multiple subroutines and multiple coroutine frames; wherein the coroutine frame is used to transfer information between the multiple subroutines.
[0051] It should be noted that step 200 is specifically implemented by the parser of the coroutine programming model. Figure 4 is a transformation diagram of the parser provided by the present invention, Figure 5 This is a schematic diagram of the subroutine conversion diagram of the parser provided by the present invention, such as Figure 4 and Figure 5 As shown, the main purpose of the parser is to convert the coroutine code into subroutines expressed in the backend shader language and organized as follows Figure 5 The subroutine transition graph shown in Figure 1 is shown. Specifically, the program entry point and each suspend point are each associated with a partitioned subroutine, represented as a node in the graph. These subroutines are extracted as executable functions on the device. At the beginning, a subroutine resumes the suspended program state from the corresponding coroutine frame and then executes the program instructions after the suspend point. When execution reaches the next suspend point, the subroutine saves the current program state to the coroutine frame and returns execution control to the caller, thus suspending. The transition relationship between subroutines is modeled by directed edges in the graph. Each edge connects a source and target subroutine pair with a suspend-resume relationship. In addition, each edge embeds coroutine frame information, recording the fields in the coroutine frame that need to be stored when the source subroutine is suspended and the fields that need to be loaded when the target subroutine resumes. The scheduler can use the subroutine transition graph to plan and optimize the execution of coroutines, thereby improving parallel efficiency and resource utilization.
[0052] Specifically, step 200 divides the computing task corresponding to the coroutine according to the suspension node of the coroutine program code to obtain multiple subroutines, including:
[0053] Step 210: Convert the coroutine program code into an intermediate representation.
[0054] Step 210 specifically includes:
[0055] The abstract syntax tree corresponding to the coroutine program code is converted into a control flow graph, and the control flow graph is simplified to obtain a simplified control flow graph; wherein the simplified control flow graph is used to describe the overall control flow process of the coroutine, and the simplified control flow graph includes: basic nodes, control flow nodes and termination nodes.
[0056] Step 220: Based on the intermediate representation and the suspended nodes of the coroutine program code, execute multiple preset calculation rules to obtain multiple subroutines divided based on the computing tasks corresponding to the coroutine.
[0057] Step 220 specifically includes:
[0058] Step 221: traverse the simplified control flow graph to determine multiple potential subroutines, and form a reachable node set based on the reachable nodes of each potential subroutine in the multiple potential subroutines.
[0059] Step 222: Based on the reachable node set and the suspended nodes of the coroutine program code, obtain a plurality of subroutines divided based on the computing tasks corresponding to the coroutine.
[0060] Furthermore, step 200 divides the computing task corresponding to the coroutine according to the suspension node of the coroutine program code to obtain multiple coroutine frames, including:
[0061] Step 230: Split the computing task corresponding to the coroutine according to the suspended nodes of the coroutine program code, and perform data flow analysis on the split coroutine to obtain the activity status of each of the multiple split points.
[0062] It should be noted that the data flow analysis includes: internal usage definition parsing and cross-domain active status analysis.
[0063] Step 230 specifically includes:
[0064] Perform internal usage definition analysis and cross-domain active status analysis on the split coroutines to obtain the active status of each split point.
[0065] The internal usage definition parsing is used to extract the internal calls and external references of each subroutine in the multiple subroutines; and the cross-domain active state analysis is used to determine the storage relationship and loading relationship between the subroutines.
[0066] Step 240: Based on the activity status of each of the multiple split points, obtain corresponding multiple coroutine frames.
[0067] In one embodiment, the parser converts the abstract syntax tree (AST) corresponding to a coroutine written in a domain-specific language into a fluent static single assignment (SSA) intermediate representation (IR). The parser then performs multiple computations to generate the subroutines that are split into the coroutine. This process is described in detail below.
[0068] 1. Preprocessing
[0069] 1) First, through control flow normalization, the parser will simplify complex control flows such as GenericLoop, Break, Continue, and Return into if and do-while loops. Redundant statements will be simplified so that only Loops have reverse edges in the control flow graph (CFG).
[0070] 2) To reduce the active state at each suspension point, active state simplification is performed. Variables are shortened to their lifetime by declaring them in the latest basic block, reducing the load of aggregates.
[0071] 2. Subroutine extraction.
[0072] First, the original coroutine is expressed as a CFG graph, which describes the overall control flow of the coroutine, including base nodes, control flow nodes, and termination nodes. By traversing the CFG, the reachable nodes of each subroutine are determined. Finally, to ensure the correctness and simplicity of the control flow after partitioning, the parser performs conditional replay, restarting the subroutine from the suspension points in the nested loops. Through these operations, the nodes in the CFG are appropriately assigned to the different suspension points and entry points of the corresponding subroutines.
[0073] 3. Coroutine frame concretization.
[0074] In order to ensure that different subroutines can run correctly after suspension, the program context, i.e., the coroutine frame, needs to be passed between subroutines. Directly storing all variables will result in excessive memory overhead, so only necessary data is saved in the coroutine frame: the values used by the current subroutine that reference external definitions need to be loaded, and the values loaded by other subroutines defined by the current subroutine need to be stored. To this end, this embodiment performs two data flow analysis processes: internal use-definition parsing and cross-domain active state analysis, and finally merges all variable sets to form a coroutine frame.
[0075] 1) Internal use-definition resolution extracts all internal calls and external references within a subroutine. While the standard SSA form generally captures this information, the local storage operations of Local instructions still require special handling. For each subroutine scope, the traversal maintains the set of variables covered up to a certain node, the set of variables referenced by external definitions, and the set of variables that may be modified.
[0076] 2) Cross-domain active state analysis ultimately determines the store-load relationships between subroutines. All subroutines are first organized into a coroutine transition graph. The active state of each subroutine is then determined during the traversal process, and the variables read and stored by each subroutine are inferred from this.
[0077] 4. Post-processing.
[0078] After the above processing, the subroutine will be instantiated as a function, the CFG will be reconstructed into an intermediate representation, and the inherent keywords related to the coroutine will be reduced to operations such as reading and loading the coroutine frame.
[0079] Step 300: Based on the multiple coroutine frames, the multiple subroutines after segmentation are respectively assigned to multiple threads of the GPU for parallel execution.
[0080] It should be noted that step 300 is specifically implemented through the scheduler of the coroutine task. The scheduler is responsible for actually executing the coroutine task and managing related resources. Users can design a special-purpose scheduler according to their needs, or directly call the built-in general high-performance scheduler. For a custom scheduler, the user needs to implement the _dispatch method in the inherited class, which is used to create and assign a certain number of coroutine instances to the instruction stream. This embodiment provides two built-in general high-performance schedulers, the wavefront scheduler and the persistent thread scheduler.
[0081] Wavefront Scheduler: A direct generalization of the wavefront path tracing technique. The basic idea is to decompose the state machine into multiple subkernels, each handling a subroutine. Coroutine frames are stored in a global buffer, loaded by the subroutine when it resumes and updated when it suspends. Transitions between subroutines are tracked using the suspend location field in the frame.
[0082] In each iteration, the running thread index is established from the global frame buffer. This embodiment uses a stable multi-splitting algorithm to cluster the indexes according to the suspension location field, ensuring physical consistency and reducing scheduling overhead. The scheduler then dispatches the subroutine kernel to process the instance corresponding to the index. When the coroutine reaches termination, a new instance is generated in the original frame buffer block. This embodiment provides various detailed settings to further improve performance in some cases:
[0083] 1. Structure of Arrays (SoA) layout. The SoA layout is the transpose of the Array of Structures (AoS) layout, storing each field of the state frame as a separate scalar buffer. This enables subkernels to load and store only the necessary state frame fields based on information in the subroutine transformation graph, reducing required memory bandwidth and making it more suitable for cache units on modern GPUs. However, this may also affect random access performance.
[0084] 2. Frame buffer compression. Coroutine instances often have uneven lifecycles and therefore terminate at different times, leaving gaps in the frame buffer and compromising memory access locality. Users can enable compression to gather all active instances to the beginning of the buffer when the number of unterminated coroutine instances (the percentage of non-terminated coroutine instances) falls below a certain threshold. However, relocating a large number of frames can consume considerable memory bandwidth.
[0085] Persistent Thread Scheduler: In modern GPU architectures, threads are organized into blocks on streaming multiprocessors. Therefore, the persistent thread scheduler attempts to leverage fast block-shared memory to store state frames, rather than frequent and expensive global memory accesses. The scheduler also batches coroutine instances to run the state machine within a block, improving thread consistency within the block. With this scheduling approach, a thread's lifecycle persists across multiple task batches until a set of tasks completes.
[0086] Task acquisition: When a thread block decides to generate a new task, it acquires a batch of pending tasks. This request is made by the leader thread in the block to the global task index counter.
[0087] In-block state machine execution: Subroutines are organized into a single kernel state machine and executed synchronously within a block. At each step, the leader thread checks the subroutine counter and selects the most common subroutine to continue in the block. Important instance indices are collected into a queue but stored in fast shared memory. All threads then run the same subroutine, processing the collected instances. The relevant frames are loaded from shared memory into local storage before the call and written back afterward. This scheduler also offers several customization options:
[0088] 1. Conflict-avoiding SoA layout: When threads within a thread cluster simultaneously access different addresses in the same memory cache, bank conflicts occur in the GPU shared memory, resulting in performance degradation. To alleviate this issue, the persistent thread scheduler of this embodiment can be configured to use a SoA memory layout to store state frames, reducing the possibility of bank overlap caused by alignment structures.
[0089] 2. Global Memory Expansion: If a persistent thread implementation only keeps all frames in shared memory, the available shared memory size will partially limit parallelism, as only a portion of the threads in a block may participate in execution. To circumvent this limitation, this embodiment uses a global buffer as an extension of the state frame storage, which, together with shared memory, holds enough frames to ensure that all threads in the entire block are filled in each iteration. When the shared memory size is insufficient to accommodate the frames of all instances selected in a state machine step, some currently unused frames are swapped to global memory. This expansion sacrifices a small amount of global bandwidth for better thread utilization.
[0090] The coroutine implementation method for GPU programming provided by the embodiment of the present invention expands the basic capabilities of GPU programming and realizes support for coroutines; it can automatically divide and schedule the computing tasks expressed by coroutines, improve the program running efficiency and simplify the maintenance difficulty for developers; it simplifies the programming difficulty of inserting additional processes into the original task; and adds asynchronous programming capabilities to GPU programming.
[0091] The above is a description of the steps of the coroutine implementation method for GPU programming provided by the present invention. From the description of the above steps, it can be seen that according to the coroutine implementation method for GPU programming provided by the present invention, by obtaining the coroutine program code written by the user based on the GPU programming language; wherein, the coroutine program code includes at least one suspension node, and the suspension node is used to define the suspension behavior and recovery behavior of the coroutine; according to the suspension node of the coroutine program code, the computing task corresponding to the coroutine is divided to obtain multiple subroutines and multiple coroutine frames; wherein, the coroutine frame is used to transfer information between the multiple subroutines; based on the multiple coroutine frames, the multiple subroutines after division are respectively allocated to the multiple threads of the GPU for parallel execution. It can be seen from this that the present invention automatically processes the subroutines and determines the coroutine frames for storing intermediate data according to the coroutine program code written by the user, runs the coroutine according to the parsing results, and can efficiently execute a large number of coroutines in parallel.
[0092] The following describes a coroutine implementation device for GPU programming provided by the present invention. The coroutine implementation device for GPU programming described below and the coroutine implementation method for GPU programming described above can refer to each other.
[0093] Figure 6 This is a schematic diagram of the structure of the coroutine implementation device for GPU programming provided by the present invention, such as Figure 6 As shown, the coroutine implementation device for GPU programming provided by the present invention includes:
[0094] An acquisition module 601 is configured to acquire a coroutine program code written by a user based on a GPU programming language; wherein the coroutine program code includes at least one suspend node, and the suspend node is used to define the suspend behavior and resume behavior of the coroutine;
[0095] A splitting module 602 is configured to split the computing task corresponding to the coroutine according to the suspended nodes of the coroutine program code to obtain multiple subroutines and multiple coroutine frames; wherein the coroutine frame is used to transmit information between the multiple subroutines;
[0096] The scheduling module 603 is used to allocate the divided subroutines to multiple threads of the GPU for parallel execution based on the multiple coroutine frames.
[0097] The present invention provides a coroutine implementation device for GPU programming, which obtains a coroutine program code written by a user based on a GPU programming language; wherein the coroutine program code includes at least one suspension node, and the suspension node is used to define the suspension behavior and recovery behavior of the coroutine; the computing task corresponding to the coroutine is divided according to the suspension node of the coroutine program code to obtain multiple subroutines and multiple coroutine frames; wherein the coroutine frame is used to transfer information between the multiple subroutines; based on the multiple coroutine frames, the multiple subroutines after division are respectively assigned to multiple threads of the GPU for parallel execution. It can be seen from this that the present invention automatically processes the division of subroutines and determines the coroutine frame for storing intermediate data according to the coroutine program code written by the user, runs the coroutine according to the parsing result, and can efficiently execute a large number of coroutines in parallel.
[0098] Based on the above embodiment, in this embodiment, the segmentation module 602 is specifically configured to:
[0099] Converting the coroutine program code into an intermediate representation;
[0100] Based on the intermediate representation and the suspended nodes of the coroutine program code, multiple preset calculation rules are executed to obtain multiple subroutines that are divided based on the calculation tasks corresponding to the coroutine.
[0101] Based on the above embodiment, in this embodiment, the device further includes a conversion module, which is specifically configured to:
[0102] The abstract syntax tree corresponding to the coroutine program code is converted into a control flow graph, and the control flow graph is simplified to obtain a simplified control flow graph; wherein the simplified control flow graph is used to describe the overall control flow process of the coroutine, and the simplified control flow graph includes: basic nodes, control flow nodes and termination nodes.
[0103] Based on the above embodiment, in this embodiment, the segmentation module 602 is specifically configured to:
[0104] Traversing the simplified control flow graph, determining a plurality of potential subroutines, and forming a reachable node set based on a reachable node of each potential subroutine in the plurality of potential subroutines;
[0105] Based on the reachable node set and the suspended nodes of the coroutine program code, a plurality of subroutines are obtained which are divided based on the computing tasks corresponding to the coroutine.
[0106] Based on the above embodiment, in this embodiment, the segmentation module 602 is specifically configured to:
[0107] Splitting the computing task corresponding to the coroutine according to the suspension node of the coroutine program code, and performing data flow analysis on the split coroutine to obtain the activity status of each of the multiple split points;
[0108] Based on the active state of each of the multiple split points, a corresponding plurality of coroutine frames are obtained.
[0109] Based on the above embodiment, in this embodiment, the data flow analysis includes: internal usage definition parsing and cross-domain active status analysis;
[0110] The device also includes an analysis module, specifically configured to:
[0111] Perform internal usage definition analysis and cross-domain active status analysis on the split coroutines to obtain the active status of each split point.
[0112] The internal usage definition parsing is used to extract the internal calls and external references of each subroutine in the multiple subroutines; and the cross-domain active state analysis is used to determine the storage relationship and loading relationship between the subroutines.
[0113] Figure 7 An example of a physical structure diagram of an electronic device is shown below. Figure 7 As shown, the electronic device may be a robot or other electronic device, and may include: a processor 710, a communications interface 720, a memory 730, and a communication bus 740, wherein the processor 710, the communications interface 720, and the memory 730 communicate with each other via the communication bus 740. The processor 710 may call logic instructions in the memory 730 to execute a coroutine implementation method for GPU programming, including:
[0114] Obtaining a coroutine program code written by a user based on a GPU programming language; wherein the coroutine program code includes at least one suspend node, and the suspend node is used to define the suspend behavior and resume behavior of the coroutine;
[0115] The computing task corresponding to the coroutine is divided according to the suspension node of the coroutine program code to obtain a plurality of subroutines and a plurality of coroutine frames; wherein the coroutine frame is used to transmit information between the plurality of subroutines;
[0116] Based on the multiple coroutine frames, the divided multiple subroutines are respectively allocated to multiple threads of the GPU for parallel execution.
[0117] Furthermore, the logic instructions in the aforementioned memory 730 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the portion that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product, stored in a storage medium, includes instructions for enabling a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a mobile hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.
[0118] On the other hand, the present invention further provides a computer program product, comprising a computer program, which may be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the coroutine implementation method for GPU programming provided by the above methods, including:
[0119] Obtaining a coroutine program code written by a user based on a GPU programming language; wherein the coroutine program code includes at least one suspend node, and the suspend node is used to define the suspend behavior and resume behavior of the coroutine;
[0120] The computing task corresponding to the coroutine is divided according to the suspension node of the coroutine program code to obtain a plurality of subroutines and a plurality of coroutine frames; wherein the coroutine frame is used to transmit information between the plurality of subroutines;
[0121] Based on the multiple coroutine frames, the divided multiple subroutines are respectively allocated to multiple threads of the GPU for parallel execution.
[0122] In another aspect, the present invention further provides a non-transitory computer-readable storage medium having a computer program stored thereon. When the computer program is executed by a processor, the coroutine implementation method for GPU programming provided by the above methods is implemented, including:
[0123] Obtaining a coroutine program code written by a user based on a GPU programming language; wherein the coroutine program code includes at least one suspend node, and the suspend node is used to define the suspend behavior and resume behavior of the coroutine;
[0124] The computing task corresponding to the coroutine is divided according to the suspension node of the coroutine program code to obtain a plurality of subroutines and a plurality of coroutine frames; wherein the coroutine frame is used to transmit information between the plurality of subroutines;
[0125] Based on the multiple coroutine frames, the divided multiple subroutines are respectively allocated to multiple threads of the GPU for parallel execution.
[0126] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, i.e., they may be located in one location or distributed across multiple network units. Some or all of the modules may be selected based on actual needs to achieve the objectives of the present embodiment. Persons of ordinary skill in the art will be able to understand and implement the present invention without inventive effort.
[0127] Through the above description of the embodiments, those skilled in the art will clearly understand that each embodiment can be implemented using software plus a necessary general-purpose hardware platform, or of course, hardware. Based on this understanding, the essence of the above technical solution, or the portion that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, a magnetic disk, or an optical disk, and includes a number of instructions for causing a computer device (such as a personal computer, server, or network device) to execute the methods described in each embodiment or certain portions of the embodiments.
[0128] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.
Claims
1. A coroutine implementation method for GPU programming, characterized in that: include: Obtaining a coroutine program code written by a user based on a GPU programming language; wherein the coroutine program code includes at least one suspend node, and the suspend node is used to define the suspend behavior and resume behavior of the coroutine; the GPU programming language is a domain-specific language (DSL) for GPU programming; The computing task corresponding to the coroutine is divided according to the suspension node of the coroutine program code to obtain a plurality of subroutines and a plurality of coroutine frames; wherein the coroutine frame is used to transmit information between the plurality of subroutines; Based on the multiple coroutine frames, the divided multiple subroutines are respectively allocated to multiple threads of the GPU for parallel execution.
2. The coroutine implementation method for GPU programming according to claim 1, characterized in that: The computing task corresponding to the coroutine is divided according to the suspension node of the coroutine program code to obtain multiple subroutines, including: Converting the coroutine program code into an intermediate representation; Based on the intermediate representation and the suspended nodes of the coroutine program code, multiple preset calculation rules are executed to obtain multiple subroutines that are divided based on the calculation tasks corresponding to the coroutine.
3. The coroutine implementation method for GPU programming according to claim 2, characterized in that: Converting the coroutine program code into an intermediate representation includes: The abstract syntax tree corresponding to the coroutine program code is converted into a control flow graph, and the control flow graph is simplified to obtain a simplified control flow graph; wherein the simplified control flow graph is used to describe the overall control flow process of the coroutine, and the simplified control flow graph includes: basic nodes, control flow nodes and termination nodes.
4. The method for implementing a coroutine for GPU programming according to claim 3, wherein: The suspended node based on the intermediate representation and the coroutine program code executes multiple preset calculation rules to obtain multiple subroutines divided based on the computing tasks corresponding to the coroutine, including: Traversing the simplified control flow graph, determining a plurality of potential subroutines, and forming a reachable node set based on a reachable node of each potential subroutine in the plurality of potential subroutines; Based on the reachable node set and the suspended nodes of the coroutine program code, a plurality of subroutines are obtained which are divided based on the computing tasks corresponding to the coroutine.
5. The coroutine implementation method for GPU programming according to claim 1, wherein: The computing task corresponding to the coroutine is divided according to the suspension node of the coroutine program code to obtain multiple coroutine frames, including: Splitting the computing task corresponding to the coroutine according to the suspension node of the coroutine program code, and performing data flow analysis on the split coroutine to obtain the activity status of each of the multiple split points; Based on the active state of each of the multiple split points, a corresponding plurality of coroutine frames are obtained.
6. The coroutine implementation method for GPU programming according to claim 5, characterized in that: The data flow analysis includes: internal usage definition analysis and cross-domain active status analysis; The data flow analysis is performed on the split coroutine to obtain the active status of each of the multiple split points, including: Perform internal usage definition analysis and cross-domain active status analysis on the split coroutines to obtain the active status of each split point. The internal usage definition parsing is used to extract the internal calls and external references of each subroutine in the multiple subroutines; and the cross-domain active state analysis is used to determine the storage relationship and loading relationship between the subroutines.
7. A coroutine implementation device for GPU programming, characterized in that: include: an acquisition module for acquiring a coroutine program code written by a user based on a GPU programming language; wherein the coroutine program code includes at least one suspend node, and the suspend node is used to define the suspend behavior and resume behavior of the coroutine; and the GPU programming language is a domain-specific language (DSL) for GPU programming; A splitting module, configured to split the computing task corresponding to the coroutine according to the suspended nodes of the coroutine program code to obtain a plurality of subroutines and a plurality of coroutine frames; wherein the coroutine frame is used to transfer information between the plurality of subroutines; The scheduling module is used to allocate the divided subroutines to multiple threads of the GPU for parallel execution based on the multiple coroutine frames.
8. The coroutine implementation device for GPU programming according to claim 7, characterized in that: The segmentation module is specifically used to: Converting the coroutine program code into an intermediate representation; Based on the intermediate representation and the suspended nodes of the coroutine program code, multiple preset calculation rules are executed to obtain multiple subroutines that are divided based on the calculation tasks corresponding to the coroutine.
9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the coroutine implementation method for GPU programming according to any one of claims 1 to 6 is implemented.
10. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the coroutine implementation method for GPU programming as claimed in any one of claims 1 to 6 is implemented.