AI accelerator, method and electronic chip for dual-pipeline task collaboration

Abstract

The present invention provides an AI accelerator, method, and electronic chip for dual-pipeline task collaboration, wherein the AI accelerator includes: a task control module and a computing module, the task control module is connected to the computing module, and the computing module includes multiple computing units; the task control module includes a first configuration status register, a first memory direct access unit, a task FIFO unit, and a collaborative control unit, the first configuration status register is connected to an external central processing unit, and the first memory direct access unit is respectively connected to the first configuration status register, the task FIFO unit, and an external main memory; the computing unit includes a second configuration status register and a second memory direct access unit, the second configuration status register is respectively connected to the collaborative control unit and the second memory direct access unit, and the second memory direct access unit is connected to the main memory. The present invention improves the flexibility of AI acceleration task distribution, has a relatively simple design, and takes up less space.

Description

Technical Field

[0001] The present invention relates to the field of processor architecture technology, and in particular to an AI accelerator, method, and electronic chip for dual-pipeline task collaboration. Background Art

[0002] The design of neural networks is primarily inspired by the biological understanding of the nervous system. Neural networks are inspired by the working principles and information processing methods of neurons in the human brain. By combining large numbers of neurons in a specific connection pattern into a neural network, they simulate the brain's information processing process. The structure and algorithm design of neural networks are primarily inspired by biological neural networks. By combining multiple layers of neurons, neural networks can perform high-level abstraction and reasoning, thereby achieving tasks similar to human intelligence, such as speech recognition, image recognition, and natural language processing.

[0003] The multi-layer artificial neural networks used in deep learning are the preferred architecture for today's AI (artificial intelligence) applications. There are two main AI accelerator architectures. One is the dedicated ASIC (Application Specific Integrated Circuit) architecture for AI acceleration. These chips are designed specifically for the characteristics of AI computing and are independent of the instruction set. This approach offers high AI computing performance, with specialized AI accelerators designed for different networks. However, its disadvantages include poor reusability, requiring the CPU for master control, and hardware modifications required for operator expansion, which can lead to hardware lags behind the evolution of AI algorithms. The other is the CPU + Neural Processing Unit (NPU) architecture, which uses a traditional CPU core as the primary core and an NPU as a secondary core to accelerate AI computing. This architecture leverages the full performance of both the CPU and NPU, offering greater flexibility. However, its disadvantages include lower specificity and lower performance.

[0004] One existing implementation is a CNN (Convolutional Neural Networks) hardware accelerator for AI chips. This device is used only for CNN convolution calculations, does not rely on instruction sets, and frequently requires the use of an MCU (Microcontroller Unit) as the main controller.

[0005] Another existing implementation utilizes a processing architecture consisting of a single master core and multiple slave cores, controlled by the RISC-V instruction set. This architecture can split and distribute AI acceleration tasks across multiple slave cores for parallel processing. Specifically, the master core reads AI acceleration instructions and source data based on RV32I-based integer instructions, dispatches the acceleration tasks to the slave cores, and the slave cores read the source data based on the dispatched acceleration tasks. This implementation still relies on the instruction set, making the design more complex.

[0006] Another existing solution consists of a controller and multiple computing units of different structural types. The controller is responsible for decomposing the computational graph of the received neural network to be processed into multiple computational subtasks and distributing them to the corresponding task queues of each computing unit. This method requires the controller to decompose the computational graph, which is relatively complex. Summary of the Invention

[0007] The first object of the present invention is to provide an AI accelerator with dual-pipeline task collaboration that is relatively simple in design and highly flexible.

[0008] A second object of the present invention is to provide an electronic chip including the above-mentioned dual-pipeline task collaborative AI accelerator.

[0009] The third object of the present invention is to provide an AI acceleration method for the above-mentioned dual-pipeline task collaboration that occupies less central processing unit master control and has higher flexibility.

[0010] In order to achieve the above-mentioned first purpose, the present invention provides an AI accelerator with dual-pipeline task collaboration, which includes: a task control module and a computing module, the task control module is connected to the computing module, and the computing module includes multiple computing units; the task control module includes a first configuration status register, a first memory direct access unit, a task FIFO unit, and a collaborative control unit, the first configuration status register is connected to an external central processing unit, and the first memory direct access unit is respectively connected to the first configuration status register, the task FIFO unit and the external main memory; the computing unit includes a second configuration status register and a second memory direct access unit, the second configuration status register is respectively connected to the collaborative control unit and the second memory direct access unit, and the second memory direct access unit is connected to the main memory; the central processing unit is used to configure a first data state of the first configuration status register, the first memory direct access unit is used to obtain a task queue from the main memory according to the first data state and to cache tasks in the task queue to the task FIFO unit, the collaborative control unit is used to configure a target second data state of the target second configuration status register according to the status of the target computing unit and the task FIFO unit, and the target second memory direct access unit accesses the main memory according to the target second data state.

[0011] As can be seen from the above scheme, the present invention is provided with a task control module and a computing module. The task control module reads the task queue from the main memory through the first memory direct access unit, greatly reducing the occupation of the central processing unit main control, and distributes tasks to the computing unit of the computing module through the task FIFO unit collaborative control unit, so that the task control module can realize functions similar to the CPU main control, improve the flexibility and parallel processing capabilities of the computing module, and at the same time, the computing unit is highly specialized, so that the computing unit has a fast computing speed, can increase or decrease functions according to different neural network computing requirements, better optimize the area of the AI accelerator, and improve resource utilization. Compared with the prior art, the present invention does not need to be based on an instruction set, and the design is relatively simple and the area is smaller. In addition, the task control module is not the main core and has no AI-related computing functions. It is only used for the distribution and control of the tasks of the computing unit. The design method of the task control module is relatively simple and can ensure that the control has good flexibility.

[0012] A further solution is that the central processing unit is connected to the second configuration status register.

[0013] It can be seen from this that the second data state of the second configuration state register can be configured by the task control module or directly by the central processing unit.

[0014] A further solution is that the task FIFO unit includes a serial task FIFO unit and a parallel task FIFO unit; the task queue includes a serial task queue and a parallel task queue, the tasks of the serial task queue are cached to the serial task FIFO unit, and the tasks of the parallel task queue are cached to the parallel task FIFO unit.

[0015] It can be seen from this that each computing unit can process AI tasks in parallel and serially, greatly reducing the occupancy of the main control.

[0016] A further solution is that a task in a task queue includes at least one configuration instruction of a second configuration status register.

[0017] A further solution is that the computing module includes at least one of the following computing units: a matrix computing unit, a vector computing unit, a pooling computing unit, and an operator computing unit.

[0018] It can be seen that the type and quantity of computing units can be set according to actual needs.

[0019] In order to achieve the second objective mentioned above, the present invention provides an electronic chip, comprising a shell, wherein the shell includes an AI accelerator with dual-pipeline task collaboration as described above.

[0020] In order to achieve the above-mentioned third purpose, the present invention provides an AI acceleration method for dual-pipeline task collaboration, which includes the following steps: after the external central processing unit configures the first data state of the first configuration status register of the task management module, the first memory direct access unit of the task management module obtains the task queue from the external main memory according to the first data state; the first memory direct access unit caches the tasks in the task queue to the task FIFO unit of the task management module; the collaborative control unit of the task management module configures the target second data state of the target second configuration status register of the target computing module according to the status of the target computing module and the task FIFO unit, and the second memory direct access unit of the target computing module accesses the main memory according to the target second data state.

[0021] As can be seen from the above scheme, after the present invention configures the task management module through an external central processing unit, the task management module controls the distribution of main memory tasks to different computing units, reducing the occupation of the central processing unit as the main control, and the task control distribution flexibility is high.

[0022] A further solution is that the task FIFO unit includes a serial task FIFO unit and a parallel task FIFO unit; the first memory direct access unit caches the tasks of the serial task queue in the task queue to the serial task FIFO unit, and caches the tasks of the parallel task queue in the task queue to the parallel task FIFO unit.

[0023] A further solution is that the collaborative control unit configures the target second data state according to the status of the target computing module, the serial task FIFO unit and the parallel task FIFO unit, including the following steps: after determining that the serial task FIFO unit is ready, and determining that the target computing unit corresponding to the current task currently cached by the serial task FIFO unit is idle and the previous cached task of the serial task FIFO unit is completed, configure the target second configuration status register of the target computing unit corresponding to the current task cached by the serial task FIFO unit according to the current task cached by the serial task FIFO unit; after determining that the parallel task FIFO unit is ready, and determining the target computing unit corresponding to the current task currently cached by the parallel task FIFO unit, configure the target second configuration status register of the target computing unit corresponding to the current task cached by the parallel task FIFO unit according to the current task cached by the parallel task FIFO unit.

[0024] It can be seen that parallel and serial collaborative processing of AI tasks is achieved through the parallel task FIFO unit and the serial task FIFO unit.

[0025] A further solution is that the collaborative control unit configures the target second data state of the target second configuration status register of the target computing module according to the target computing module, the status of the task FIFO unit, and the value indicating the priority setting in the first configuration status register.

[0026] It can be seen that, according to the priority setting, it can be determined whether to process the tasks in the parallel task FIFO unit or the tasks in the serial task FIFO unit first. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 This is a diagram of the overall architecture of the AI acceleration processor implemented in the dual-pipeline task collaboration AI accelerator embodiment of the present invention.

[0028] Figure 2 This is a specific architecture diagram of the task control module in the AI accelerator embodiment with dual-pipeline task collaboration of the present invention.

[0029] Figure 3 This is a schematic diagram of the connection relationship between the task control module, computing module and main memory in the embodiment of the dual-pipeline task collaborative AI accelerator of the present invention.

[0030] Figure 4 This is a flowchart of an embodiment of the AI acceleration method for dual-pipeline task collaboration of the present invention.

[0031] Figure 5 yes Figure 4 Specific flow chart of step S3 in FIG.

[0032] Figure 6 yes Figure 5 Specific flow chart of step S34 in FIG.

[0033] The present invention will be further described below with reference to the accompanying drawings and embodiments. DETAILED DESCRIPTION

[0034] In the dual-pipeline task-cooperation AI accelerator of the present invention, each computing unit in the task control module and the computing module is equipped with an independent configuration status register (CSR) and a direct memory access unit (DMA) based on DMA technology. This allows each computing unit to operate independently or in coordination with each other based on the data status of the configuration status register, thereby improving the accelerator's resource and bandwidth utilization. The present invention also provides an electronic chip including the dual-pipeline task-cooperation AI accelerator and a dual-pipeline task-cooperation AI acceleration method.

[0035] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the examples described are only some embodiments of the present invention, not all embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.

[0036] An AI accelerator implementation for dual-pipeline task collaboration:

[0037] See also Figure 1 The dual-pipeline task-coordinated AI accelerator 100 of this embodiment includes a task control module 21 and a computing module 31. The task control module 21 is connected to the computing control module 31. The computing module 31 includes multiple independent computing units.

[0038] The task control module 21 is used to configure each computing unit of the computing module 31. Each computing unit of the computing module 31 is responsible for different computing tasks.

[0039] The task control module 21 is also connected to the external central processing unit 11 and the main memory 41, and the computing module 31 is connected to the external main memory 41. Under the configuration of the external central processing unit 11, the task control module 21 obtains the task queue from the main memory 41 and assigns the tasks in the task queue to the corresponding computing units in the computing module 31 for processing. The computing units in the computing module 31 can access the main memory 41 and perform calculations according to the instructions corresponding to the assigned tasks to complete the assigned tasks.

[0040] See also Figure 2 The task control module 21 includes a first configuration status register 211, a first memory direct access unit 212, a FIFO (First Input First Output) unit 901 and a collaborative control unit 215. The task FIFO unit 901 includes a serial task FIFO unit 213 and a parallel task FIFO unit 214.

[0041] The first configuration status register 211 is connected to the external central processing unit 11 , and the first memory direct access unit 212 is connected to the first configuration status register 211 , the serial task FIFO unit 213 , the parallel task FIFO unit 214 and the main memory 41 respectively.

[0042] Each computing unit in the computing module 31 includes a second configuration status register and a second direct memory access unit. The second configuration status register of each computing unit is respectively connected to the cooperative control unit 215 and the second direct memory access unit, and the second direct memory access unit is connected to the main memory 41.

[0043] The first data state of the first configuration status register 211 is configured by the central processing unit 11 via the Advanced Peripheral Bus (APB). The specific contents of the first configuration status register 211 configured by the central processing unit 11 include the starting address and length of the parallel task queue instructions in the task queue, the starting address and length of the serial task queue instructions in the task queue, the interrupt configuration, the number of tasks, etc.

[0044] The second data state of the second configuration status register is configured by the task control module 21. In other embodiments, the second configuration status register is further connected to the central processing unit 11, and the central processing unit 11 can also configure the second configuration status register through the peripheral bus.

[0045] The first direct memory access unit 212 is configured to directly access the main memory 41 without passing through the central processing unit 11. The first direct memory access unit 212 is configured to obtain a task queue from the main memory 41 according to the first data state, and to cache tasks in the task queue in the task FIFO unit 901. The tasks in the task queue are cached in the task FIFO unit 901 in the form of configuration instructions of the second configuration status register.

[0046] In the task FIFO unit 901, the serial task FIFO unit 213 and the parallel task FIFO unit 214 each cache configuration instructions for the second configuration status register. When the computing unit is not operating and the serial task FIFO unit 213 or the parallel task FIFO unit 214 is ready, the coordinated control unit 215 writes the corresponding configuration data into the corresponding second configuration status register according to the configuration instructions. The computing unit then accesses the main memory 41 to obtain data and performs calculations based on the status in the second configuration status register, and writes the calculated results to the main memory 41.

[0047] For tasks that need to be executed sequentially, they are processed through the serial task FIFO unit 213. The serial task FIFO unit 213 must be used to configure the computing unit for use only after the previous task of the current task is completed and the computing unit corresponding to the configuration instruction is not currently working. For example, after performing convolution calculations, activation calculations are generally required, and the input of the vector computing unit depends on the output data of the matrix computing unit. After the vector computing unit completes the data calculation, it may perform pooling calculations or directly write the data to the main memory through its own second memory direct access unit.

[0048] For tasks that do not need to be executed sequentially, the configuration instructions of the parallel task FIFO unit 214 can be configured into the second configuration status register of the computing unit by the collaborative control unit 215 only when the corresponding computing unit is not currently working, without waiting for the previous task to be completed.

[0049] When the configuration instructions cached in the serial task FIFO unit 213 and the parallel task FIFO unit 214 correspond to the same computing unit, they are configured according to the value indicating the priority setting in the first configuration status register. For example, if the value indicating the priority setting in the first configuration status register is 1, then the serial task FIFO unit 213 takes precedence over the parallel task FIFO unit 214, and the collaborative control unit 215 writes the corresponding configuration data into the second configuration status register of the computing unit according to the configuration instruction in the serial task FIFO unit 213; when the value indicating the priority setting in the first configuration status register is 0, then the parallel task FIFO unit 214 takes precedence over the serial task FIFO unit 213, and the collaborative control unit 215 writes the corresponding configuration data into the second configuration status register of the computing unit according to the configuration instruction in the parallel task FIFO unit 214.

[0050] The input and output of each computing unit of the computing module 31 are determined by the second configuration status register of the computing unit. The second direct memory access unit is used to achieve direct access to the main memory 41 without going through the central processing unit 11. The second direct memory access unit implements, according to the second data state of the second configuration status register: obtaining data from the main memory 41, performing calculations based on the obtained data to obtain output results, and writing the output results to the main memory 41 or outputting them to the next computing unit as the input of the next computing unit. By configuring the second configuration status register, each computing unit can operate interdependently or independently. When operating interdependently, the input of the lower level is generally the output of the upper level. Only when the output of the upper level is ready can the lower level start calculation. And the upper level can only calculate normally when the lower level can receive the calculation results, otherwise it will be subject to back pressure.

[0051] The coordination control unit 215 is configured to determine a target computing unit among the multiple computing units in the computing module 31 based on the current task cached in the FIFO unit 901, and configure a target second data state of a target second configuration state register of the target computing unit based on the state of the target unit and the state of the task FIFO unit 901. The target second memory direct access unit of the target computing unit accesses the main memory based on the target second data state to implement execution of the specific computing task.

[0052] See also Figure 3The computing module 11 of this embodiment includes a matrix computing unit 311, a vector computing unit 312, a pooling computing unit 313, and an operator computing unit 314. The matrix computing unit 311 is connected to the vector computing unit 312, and the vector computing unit 312 is connected to the pooling computing unit 313. The task control module 21 is connected to each computing unit of the computing unit 11, and each computing unit is respectively connected to the external main memory 41.

[0053] The matrix calculation unit 311 is used for matrix multiplication and addition calculations, including convolution, deconvolution, dilated convolution, depthwise separable convolution, etc. Its feature image input and weights are generally read from the main memory 41 through DMA (direct memory access) technology.

[0054] The vector calculation unit 312 is used for various linear and nonlinear operations, including the rectified linear unit (ReLU), the parametric rectified linear unit (PReLU), precision scaling, batch normalization, bias addition, sigmoid function, hyperbolic tangent, etc.

[0055] The pooling calculation unit 313 is used for pooling calculation, including max pooling, min pooling, and mean pooling.

[0056] The operator calculation unit 314 is an operator responsible for independent calculations, and performs data pre-processing, format conversion, quantization, etc. on the data.

[0057] It can be understood that the number and types of computing units in the computing module 31 can be set according to actual needs.

[0058] Electronic chip embodiment:

[0059] The electronic chip of this embodiment includes a shell, and the shell includes the dual-pipeline task collaborative AI accelerator of the above embodiment.

[0060] Optionally, the housing of this embodiment also includes the central processing unit and main memory of the above embodiment.

[0061] Implementation example of an AI acceleration method for dual-pipeline task collaboration:

[0062] This embodiment is implemented based on the above-mentioned dual-pipeline task collaborative AI accelerator embodiment.

[0063] See also Figure 4 , this embodiment includes the following steps:

[0064] S1: Compile the content of neural network calculation through middleware.

[0065] S2: The compiled content of the middleware is formed into a task queue and written into the main memory.

[0066] S3: The AI accelerator performs calculations based on the task queue and completes the tasks in the task queue.

[0067] In steps S1 and S2 above, the neural network calculation content needs to be compiled into a task queue that matches this embodiment through middleware tools. Specifically, the software plans the space required for the calculation and the input data in the main memory, including the neural network input data, weights, parameters, output address space, and task queue instruction space (i.e., the space corresponding to the task queue). The task queue instruction space includes parallel task instruction space and serial task instruction space.

[0068] In the above step S3, the AI accelerator implemented based on the above dual-pipeline task collaboration AI accelerator embodiment performs data conversion, quantization, convolution, activation and other calculations to complete each task in the task queue.

[0069] See also Figure 5 , step S3 specifically includes the following steps:

[0070] S31: After the first configuration status register is configured by the central processing unit, the task queue mode is started.

[0071] S32: The first memory direct access unit reads the task queue from the main memory according to the first data state of the first configuration state register.

[0072] S33: The serial task FIFO unit and the parallel task FIFO unit cache the tasks in the task queue.

[0073] S34: The collaborative control unit configures the target second configuration status register according to the status of the target computing unit, the serial task FIFO unit and the parallel task FIFO unit, and the target second memory direct access unit accesses the main memory according to the target second configuration status register to complete the current task.

[0074] S35: After completing all tasks in the task queue, the collaborative control unit issues an interrupt.

[0075] In step S31, the CPU configures the first data state of the first configuration state register of the task control module, including the starting address and length of the task queue, and initiates the task queue mode. In the task queue mode, the first direct memory access unit of the task control module begins reading tasks from the task queue from the memory and dispatching them to the computing module for execution.

[0076] In the above step S35 , the cooperative control unit turns off all module clocks after all tasks in the task queues are completed.

[0077] See also Figure 6 In the above step S34, the following steps are also included:

[0078] S341: Determine the status of the serial task FIFO unit, the parallel task FIFO unit, and the target computing unit corresponding to the current task.

[0079] S342: Determine whether the serial task FIFO unit is ready.

[0080] After determining that the serial task FIFO is ready, it can be determined that a configuration instruction corresponding to a task in the task queue is cached in the serial task FIFO, and step S343 can be continued to be executed; otherwise, step S345 is executed.

[0081] S343: Determine whether the target computing unit corresponding to the current task is idle and its previous task is completed.

[0082] Since the execution of tasks cached by the serial task FIFO unit has a sequence, it is necessary to determine whether the target computing unit corresponding to the current task currently cached by the serial task FIFO unit is idle and whether the previous task of the current task currently cached by the serial task FIFO unit has been completed. When the judgment result is yes, continue to execute step S344. When the judgment result is no, it is necessary to wait until the previous task of the current task currently cached by the serial task FIFO unit has been completed and / or the target computing unit corresponding to the current task currently cached by the serial task FIFO unit is idle, that is, re-enter step S343.

[0083] S344: The target second configuration status register of the target computing unit is configured according to the current task, and the target computing unit completes the current task according to the target second configuration status register.

[0084] Among them, the target second configuration status register of the target computing unit corresponding to the current task currently cached by the serial task FIFO unit is configured according to the configuration instruction corresponding to the current task currently cached by the serial task FIFO unit, so that the target computing unit completes the current task currently cached by the serial task FIFO unit according to its target second configuration status register, and then jumps to step S348 to determine whether all tasks in the task queue have been completed.

[0085] S345: Determine whether the parallel task FIFO unit is ready.

[0086] After determining that the parallel task FIFO is ready, it can be determined that a configuration instruction corresponding to a task in the task queue is cached in the parallel task FIFO, and step S346 can be continued, otherwise, the process returns to step S341.

[0087] S346: Determine whether there is free space in the target computing unit corresponding to the current task.

[0088] Since the execution of tasks cached by the parallel task FIFO unit does not have a sequential order, it is only necessary to determine whether the target computing unit corresponding to the current task currently cached by the parallel task FIFO unit is free. If the determination result is yes, the process continues with step S347. If the determination result is no, the process waits until the target computing unit corresponding to the current task currently cached by the parallel task FIFO unit is free, i.e., the process re-enters step S346.

[0089] S347: Configure the target second configuration status register of the target computing unit according to the current task, and the target computing unit completes the current task according to the target second configuration status register.

[0090] Among them, the target second configuration status register of the target computing unit corresponding to the current task currently cached by the parallel task FIFO unit is configured according to the configuration instruction corresponding to the current task currently cached by the parallel task FIFO unit, so that the target computing unit completes the current task currently cached by the parallel task FIFO unit according to its target second configuration status register, and then jumps to step S348 to determine whether all tasks in the task queue have been completed.

[0091] S348: Determine whether all tasks in the task queue have been completed.

[0092] If the judgment result is yes, continue to execute step S35, otherwise return to step S341.

[0093] In summary, the dual-pipeline task collaboration architecture of the present invention adopts a coprocessor solution and realizes parallel and serial collaborative processing of tasks by each computing unit of the computing module through the task queue mode of the task control module, thereby improving the flexibility and parallel processing capability of the computing module. The design is relatively simple and has a smaller area. In addition, the design of the task control module is relatively simple and can ensure better flexibility in the distribution of AI tasks.

Claims

1. An AI accelerator with dual-pipeline task collaboration, characterized by: include: A task control module and a computing module, wherein the task control module is connected to the computing module, and the computing module includes a plurality of computing units; The task control module includes a first configuration status register, a first memory direct access unit, a task FIFO unit, and a collaborative control unit, wherein the first configuration status register is connected to an external central processing unit, and the first memory direct access unit is respectively connected to the first configuration status register, the task FIFO unit and an external main memory; The computing unit includes a second configuration status register and a second memory direct access unit, the second configuration status register is connected to the collaborative control unit and the second memory direct access unit respectively, and the second memory direct access unit is connected to the main memory; The central processing unit is used to configure a first data state of the first configuration status register, the first memory direct access unit is used to obtain a task queue from the main memory according to the first data state and to cache the tasks in the task queue to the task FIFO unit, the coordinated control unit is used to configure a target second data state of the target second configuration status register according to the state of the target computing unit and the task FIFO unit, and the target second memory direct access unit accesses the main memory according to the target second data state; The task FIFO unit includes a serial task FIFO unit and a parallel task FIFO unit; The task queue includes a serial task queue and a parallel task queue. Tasks of the serial task queue are cached in the serial task FIFO unit, and tasks of the parallel task queue are cached in the parallel task FIFO unit.

2. The dual-pipeline task collaboration AI accelerator according to claim 1, characterized in that: The central processing unit is connected to the second configuration status register.

3. The dual-pipeline task collaboration AI accelerator according to claim 1, characterized in that: A task in the task queue includes at least one configuration instruction of the second configuration status register.

4. The dual-pipeline task collaboration AI accelerator according to claim 1, wherein: The computing module includes at least one of the following computing units: a matrix computing unit, a vector computing unit, a pooling computing unit and an operator computing unit.

5. An electronic chip, comprising a housing, characterized in that: The shell includes an AI accelerator for dual-pipeline task collaboration as described in any one of claims 1 to 4 above.

6. A dual-pipeline task collaboration AI acceleration method, applied to an AI accelerator, characterized in that: include: The AI accelerator includes a task control module and a computing module, wherein the task control module is connected to the computing module, and the computing module includes multiple computing units; The task control module includes a first configuration status register, a first memory direct access unit, a task FIFO unit, and a collaborative control unit, wherein the first configuration status register is connected to an external central processing unit, and the first memory direct access unit is respectively connected to the first configuration status register, the task FIFO unit and an external main memory; The computing unit includes a second configuration status register and a second memory direct access unit, the second configuration status register is connected to the collaborative control unit and the second memory direct access unit respectively, and the second memory direct access unit is connected to the main memory; After the central processing unit configures the first data state of the first configuration state register, the first memory direct access unit obtains the task queue from the main memory according to the first data state; The first direct memory access unit caches the tasks in the task queue to the task FIFO unit; The collaborative control unit configures a target second data state of a target second configuration state register of the target computing unit according to the state of the target computing unit and the task FIFO unit, and the second memory direct access unit of the target computing unit accesses the main memory according to the target second data state; The task FIFO unit includes a serial task FIFO unit and a parallel task FIFO unit; The first memory direct access unit caches tasks of the serial task queue in the task queue to the serial task FIFO unit, and caches tasks of the parallel task queue in the task queue to the parallel task FIFO unit.

7. The dual-pipeline task collaboration AI acceleration method according to claim 6, characterized in that: The collaborative control unit configures the target second data state according to the states of the target computing unit, the serial task FIFO unit, and the parallel task FIFO unit, including the following steps: After determining that the serial task FIFO unit is ready, and determining that the target computing unit corresponding to the current task currently cached by the serial task FIFO unit is idle and the task last cached by the serial task FIFO unit is completed, configuring a target second configuration status register of the target computing unit corresponding to the current task cached by the serial task FIFO unit according to the current task cached by the serial task FIFO unit; After determining that the parallel task FIFO unit is ready and determining the target computing unit corresponding to the current task currently cached by the parallel task FIFO unit, the target second configuration status register of the target computing unit corresponding to the current task cached by the parallel task FIFO unit is configured according to the current task cached by the parallel task FIFO unit.

8. The dual-pipeline task collaboration AI acceleration method according to claim 7, characterized in that: The cooperative control unit configures a target second data state of a target second configuration status register of the target computing unit according to the target computing unit, the status of the task FIFO unit, and the value indicating the priority setting in the first configuration status register.

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