A GPGPU global memory allocation method, device and medium

Abstract

The present invention discloses a GPGPU global memory allocation method, device and medium, belonging to the technical field of GPGPU memory allocation, and is used to solve the technical problem that in the existing host and GPGPU device data transmission collaborative work process, the real-time performance of the task is easily affected, and a large device memory space may be occupied, thereby causing a waste of memory space. The method includes: performing data block division processing on each input data required for the input task to obtain input data blocks; performing device-side operation processing on the first group of input data to obtain the operation result of the first group of input data; if the operation state of the device end is completed before the host end finishes sending the second group of input data, then performing a first operation completion control on the device end to obtain the first operation result of the second group of input data; if the operation state of the device end is completed after the host end finishes sending the second group of input data, then obtaining the post-operation result of the second group of input data.

Description

Technical Field

[0001] The present application relates to the field of GPGPU memory allocation, and in particular to a GPGPU global memory allocation method, device and medium. Background Art

[0002] In today's computing technology, computing tasks are rapidly developing towards large-scale and high-complexity. From neural network training in deep learning, to complex simulations in scientific research, to massive data processing in big data analysis, these application scenarios have put forward strict requirements on computing performance. In order to meet the needs of this high-performance computing, heterogeneous computing modes that work together with hosts (usually CPU-based) and general-purpose graphics processing units (GPGPU) devices have been widely used.

[0003] In the process of the host and GPGPU devices working together, the importance of data transmission scheduling becomes increasingly prominent. Currently, data transmission between the two faces many challenges. First, data transmission between the host and the device is a long-delay operation. Most of the current data transmission architectures use a mode of performing data transmission first and then performing calculations after the transmission is completed. This may affect the real-time performance of the task and is not friendly to some tasks with high real-time requirements. Secondly, for some tasks with large data volumes, all the data required to transmit the task may occupy a large amount of device memory space, resulting in a waste of memory space, which in turn affects the execution of other tasks. Summary of the invention

[0004] The embodiments of the present application provide a GPGPU global memory allocation method, device and medium for solving the following technical problems: in the existing data transmission collaborative work process between the host and the GPGPU device, it is easy to affect the real-time performance of the task, which may occupy a large device memory space, thereby causing a waste of memory space and affecting the execution of other tasks.

[0005] The present application embodiment adopts the following technical solutions:

[0006] On the one hand, an embodiment of the present application provides a GPGPU global memory allocation method, comprising: according to the size of GPGPU computing resources, performing data block division processing on each input data required for the input task to obtain input data blocks on the host side; based on the number of the input data blocks, determining the number of memory data blocks in the device side; according to the input data blocks and the memory data blocks, performing the device-side computing processing on a first group of input data to obtain computing results of the first group of input data; if the computing state of the device side is completed before the host side finishes sending the second group of input data, performing pre-computation completion control on the device side to obtain pre-computation results of the second group of input data; if the computing state of the device side is completed after the host side finishes sending the second group of input data, performing post-computation completion control on the device side to obtain post-computation results of the second group of input data; and judging the execution of the input task through the pre-computation results and the post-computation results to determine the task execution completion result.

[0007] The embodiment of the present application divides the data required for the computing task into several data blocks, transmits and calculates the data of one data block each time, and executes the computing task on the device side and the data transmission task between the host and the device side in parallel, thereby reducing the occupancy of the device memory during the task execution and improving the task execution efficiency.

[0008] In a feasible implementation, according to the size of GPGPU computing resources, each input data required for the input task is divided into data blocks to obtain the input data blocks of the host side, which specifically includes: through the host side, each input data in the input task is divided into data blocks under the same data element, and each of the data blocks is numbered in turn to obtain the input data blocks of the host side; wherein the number of the data blocks is the product of the number of programmable multiprocessors allocated to the input task and the number of scalar cores in each programmable multiprocessor.

[0009] In a feasible implementation, based on the number of input data blocks, the number of memory data blocks in the device end is determined, specifically including: according to the input data blocks, the memory module of the device end is divided based on the storage space corresponding to the input data blocks and output data blocks on the host side to obtain a unified storage space; wherein the number of data blocks in the unified storage space is twice the number of input data blocks; based on the number of input data blocks, the unified storage space is evenly divided to obtain receiving data memory blocks and storing operation result memory blocks; wherein the storage space of the receiving data memory blocks and the storage operation result memory blocks are the same size; the receiving data memory blocks and the storage operation result memory blocks are integrated to obtain the memory data blocks; wherein each of the memory data blocks can record the first address of the storage space and the memory size.

[0010] In a feasible implementation manner, according to the input data block and the memory data block, the first group of input data is subjected to the device-side operation processing to obtain the operation result of the first group of input data, which specifically includes: through the input data block of the host side and based on the storage address of the device side, the first group of input data in the input task is transferred to the first receiving data memory block of the memory data of the device side; based on the first receiving data memory block, the first group of input data is subjected to data reception completion flag position marking processing; when the device side detects the marked data reception completion flag position, the first group of input data is subjected to operation processing, and the operation result is stored in the first storage operation result memory block of the memory data block to obtain the first storage operation result; based on the first storage operation result, the data reception completion flag position of the first group of input data is eliminated to obtain the flag bit cleared state; the second group of input data in the host side is transferred to the second receiving data memory block of the memory data block in the device side, and the operation completion flag bit in the device side is continuously detected to obtain the state of data to be input; wherein, the operation result includes: the first storage operation result, the flag bit cleared state and the state of data to be input.

[0011] In a feasible implementation manner, if the operation state of the device end is completed before the host end finishes sending the second group of input data, the device end is first controlled to complete the operation to obtain the first operation result of the second group of input data, specifically including: if the first group of input data is in a completed operation state and the second group of input data is in a continuous data transmission state, the operation completion flag position in the device end is marked; when the host end detects the marked operation completion flag position, the operation completion flag position is eliminated; and the first storage operation result stored in the memory data block is read back to the data output of the host end, and the storage address of the memory data block corresponding to the first storage operation result is determined. The bit is in a usable state; when the second group of input data is in the process of completing data transmission, the data reception completion flag position corresponding to the second group of input data is marked; based on the marked data reception completion flag position, the second group of input data is operated and processed, and the second storage operation result is stored in the second storage operation result memory block of the memory data block; wherein, the second storage operation result memory block is an idle storage operation result memory block; the data reception completion flag position corresponding to the second group of input data is eliminated to determine the data state to be input of the third input data; wherein, the first operation result includes: the data state to be input, the data reception completion flag position state and the operation completion flag position state.

[0012] In a feasible implementation manner, if the operation state of the device end is completed after the host end finishes sending the second group of input data, post-operation completion control is performed on the device end to obtain the post-operation result of the second group of input data, specifically including: if the first group of input data is in the operating state and the second group of input data is in the data transmission completion state, the data reception completion mark position of the second group of input data in the device end is marked; through the host end, the operation completion mark position state of the first group of input data is continuously detected; when the operation completion mark position of the first group of input data in the device end is determined to be a marked state, the operation completion mark position of the first group of input data is eliminated through the host end, and the operation result stored in the first storage is cleared. The first storage operation result in the memory block is read back to the data output of the host end; when the device end detects that the data reception completion mark position of the second group of input data is in the mark state, the second group of input data is operated and processed; and the second storage operation result of the second group of input data is stored in the second storage operation result memory block of the memory data block; wherein the second storage operation result memory block is an idle storage operation result memory block; the data reception completion mark position corresponding to the second group of input data is eliminated to determine the state of the data to be input of the third group of input data; based on the state of the data to be input, the third group of input data of the host end is controlled for data transmission; wherein the post-operation result includes: the state of the data reception completion mark position and the second storage operation result.

[0013] In a feasible implementation, the input task is judged for execution through the first calculation result and the second calculation result to determine the completion result of the task execution, specifically including: if the input task is in a continuing execution state, then according to the remaining group of input data, the calculation state of the device end and the transmission state of the previous group of input data on the host end are judged for the execution sequence of the completion time nodes; according to the sequential execution results, the remaining group of input data is subjected to cyclic calculation control until the input task is determined to be in a completed execution state.

[0014] In a feasible implementation, when the storage operation result stored in the storage operation result memory block is read back into the data output of the host end, the current storage operation result memory block is determined to be in an idle state, and the operation result storage address of the current storage operation result memory is increased accordingly after the next operation processing.

[0015] In a second aspect, an embodiment of the present application also provides a GPGPU global memory allocation device, the device comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor so that the at least one processor can execute a GPGPU global memory allocation method described in any of the above embodiments.

[0016] In a third aspect, an embodiment of the present application further provides a non-volatile computer storage medium, which is a non-volatile computer-readable storage medium, and which stores at least one program, each of which includes instructions, which, when executed by a terminal, enable the terminal to execute a GPGPU global memory allocation method described in any of the above-mentioned embodiments.

[0017] The present application provides a GPGPU global memory allocation method, device and medium. Compared with the prior art, the embodiments of the present application have the following beneficial technical effects:

[0018] 1. Improve resource utilization: By dividing data blocks according to the size of GPGPU computing resources, GPU memory and computing resources can be used more effectively to avoid resource waste.

[0019] 2. Optimize data transmission efficiency: By reasonably dividing the data blocks, the number of data transmissions between the host and the device can be reduced, thereby improving data transmission efficiency.

[0020] 3. Improve computing efficiency: By completing the control before and after the calculation, the computing process can be managed more flexibly, the waiting time can be reduced, and the overall computing efficiency can be improved.

[0021] 4. Reduce memory fragmentation: By determining the number and size of memory data blocks on the device side, memory fragmentation can be reduced and memory usage efficiency can be improved.

[0022] 5. Improve the flexibility of task execution: Through the control of pre-calculation and post-calculation, it can better adapt to different task requirements and improve the flexibility of task execution.

[0023] 6. Reduce latency: By optimizing memory allocation and computing processing, you can reduce task execution latency and improve system response speed.

[0024] 7. Enhance system stability: Reasonable data block division and memory management can reduce the possibility of system crash or error and enhance system stability.

[0025] 8. Improvement of parallel processing capabilities: This approach may help improve the parallel processing capabilities of GPGPUs as large amounts of data can be processed more efficiently.

[0026] 9. Adaptability to different types of tasks: This method may be applicable to various types of computing tasks, improving its versatility and adaptability. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0028] Figure 1 A flow chart of a GPGPU global memory allocation method provided in an embodiment of the present application;

[0029] Figure 2 A structural block diagram of a GPGPU global memory allocation method provided in an embodiment of the present application;

[0030] Figure 3 A schematic diagram of the structure of a global memory allocation device for GPGPU provided in an embodiment of the present application. DETAILED DESCRIPTION

[0031] In order to enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments of this specification, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this application.

[0032] The present application embodiment provides a GPGPU global memory allocation method, such as Figure 1 As shown, the global memory allocation method of GPGPU specifically includes steps S101-S106:

[0033] S101. According to the size of GPGPU computing resources, each input data required for the input task is divided into data blocks to obtain input data blocks on the host side.

[0034] Specifically, the host side first divides each input data in the input task into data blocks under the same data element, and numbers each data block in turn to obtain the input data block on the host side. The number of data blocks is the product of the number of programmable multiprocessors assigned to the input task and the number of scalar cores in each programmable multiprocessor.

[0035] In one embodiment, Figure 2 A structural block diagram of a GPGPU global memory allocation method provided in an embodiment of the present application, such as Figure 2 As shown in FIG. 1 , according to the size of the GPGPU computing resources, each input data required by the input task is divided into data blocks of N data elements, and each data block of each data block is numbered in order, and finally the input data block is obtained. Among them, N is the product of the number of programmable multiprocessors allocated by the GPGPU for the task and the number of scalar cores in each programmable multiprocessor.

[0036] S102: Based on the number of input data blocks, determine the number of memory data blocks in the device.

[0037] Specifically, it is also necessary to divide the memory module of the device side according to the input data blocks and the storage space corresponding to the output data blocks of the host side to obtain a unified storage space, wherein the number of data blocks in the unified storage space is twice the number of input data blocks.

[0038] Furthermore, based on the number of input data blocks, the unified storage space is evenly divided to obtain a memory block for receiving data and a memory block for storing calculation results, wherein the storage space of the memory block for receiving data and the memory block for storing calculation results are the same size.

[0039] Furthermore, the memory block for receiving data and the memory block for storing the operation result are integrated to obtain a memory data block, wherein each memory data block can record the first address of the storage space and the memory size.

[0040] In one embodiment, Figure 2 As shown, in the memory module on the device side, a storage space with a size of 2N data elements is allocated for each block of input and output data of the computing task, that is, the divided unified storage space, and the unified storage space is evenly divided into two storage spaces with a size of N data elements, namely, a receiving data memory block and a storage operation result memory block. The receiving data memory block corresponds to the input group data of the host side, and the storage operation result memory block corresponds to the output group data of the host side, and they are collectively referred to as memory data blocks. Finally, the first address and memory size of each storage space are recorded.

[0041] S103: Perform device-side operation processing on the first group of input data according to the input data block and the memory data block to obtain operation results of the first group of input data.

[0042] Specifically, the first group of input data in the input task is transferred to the first receiving data memory block of the memory data of the device side by using the input data block of the host side and based on the storage address of the device side.

[0043] Furthermore, based on the first received data memory block, data reception completion flag position marking processing is performed on the first group of input data.

[0044] Furthermore, when the device detects the marked data reception completion mark position, it performs operation processing on the first group of input data, and stores the operation result in the first storage operation result memory block of the memory data block to obtain a first storage operation result.

[0045] Furthermore, based on the first storage operation result, the data reception completion flag position of the first group of input data is eliminated to obtain a flag cleared state.

[0046] Furthermore, the second group of input data in the host end is transmitted to the second receiving data memory block of the memory data block in the device end, and the operation completion flag in the device end is continuously detected to obtain the state of the data to be input.

[0047] The operation result includes: a first storage operation result, a flag clearing state, and a state of data to be input.

[0048] In one implementation, Figure 2 As shown, after the input task starts to execute, the host side first transfers the first set of input data of the task to the corresponding allocated address in the memory data block of the device side (slave side). After the data transmission is completed, the host side sets the data reception completion flag position to 1 (processing according to the reception completion flag position mark). After the device detects that the data reception completion flag position is 1, it starts the operation, stores the operation result in the first storage operation result memory block, and clears the data reception completion flag position. Then, the host side transmits the second set of input data to the second receiving data memory block of the device side allocated previously, and continuously detects the operation completion flag in the device side.

[0049] S104: If the operation status of the device end is completed before the host end finishes sending the second set of input data, the device end is controlled to complete the operation first to obtain the first operation result of the second set of input data.

[0050] Specifically, if the first set of input data is in a state of completing operation and the second set of input data is in a state of continuous data transmission, the operation completion flag position in the device side is marked.

[0051] Furthermore, when the host detects the marked operation completion flag position, the operation completion flag position is eliminated, and the first storage operation result stored in the memory data block is read back to the data output of the host, and the storage address of the memory data block corresponding to the first storage operation result is positioned as a usable state.

[0052] Furthermore, when the second group of input data is in the process of completing data transmission, a data reception completion mark position corresponding to the second group of input data is marked.

[0053] Further, based on the marked data reception completion flag position, the second set of input data is processed, and the second storage operation result is stored in the second storage operation result memory block of the memory data block, wherein the second storage operation result memory block is an idle storage operation result memory block.

[0054] Furthermore, the data receiving completion mark position corresponding to the second group of input data is eliminated to determine the state of the data to be input of the third input data.

[0055] The first calculation result includes: the state of data to be input, the state of the data receiving completion mark position and the state of the calculation completion mark position.

[0056] In one embodiment, Figure 2 As shown, if the operation on the device side is completed before the host completes sending the second set of input data, that is, if the first set of input data is in the state of completing the operation and the second set of input data is in the state of continuous data transmission, then: the device side sets the operation completion flag position to 1 (the operation completion flag position is marked), the host detects that the operation completion flag position is 1, clears the operation completion flag position, and reads the first storage operation result stored in the first storage operation result memory block on the device side back to the memory (data output memory block) for storing the operation result on the host side, and the storage address of the next storage operation result is increased accordingly. When the host completes sending all the second set of input data, the host side sets the GPGPU data reception completion flag position to 1, the device side detects that the data reception completion flag position is 1, starts the next operation, stores the second storage operation result in the second storage operation result memory block, and clears the data reception completion flag position. At this time, the host starts to transmit the third set of input data blocks to the first receiving data memory block on the device side.

[0057] S105: If the operation state of the device end is completed after the host end finishes sending the second set of input data, post-operation completion control is performed on the device end to obtain the post-operation result of the second set of input data.

[0058] Specifically, if the first group of input data is in a computing state and the second group of input data is in a data transmission completion state, the data reception completion flag position of the second group of input data in the device end is marked.

[0059] Furthermore, the host side continuously detects and processes the position status of the operation completion mark of the first group of input data.

[0060] Furthermore, when the operation completion flag position of the first group of input data in the device end is determined to be in a marked state, the operation completion flag position of the first group of input data is eliminated through the host end, and the first storage operation result stored in the first storage operation result memory block is read back to the data output of the host end.

[0061] Furthermore, when the device detects that the data receiving completion flag position of the second group of input data is in the marked state, the second group of input data is processed, and the second storage operation result of the second group of input data is stored in the second storage operation result memory block of the memory data block; wherein the second storage operation result memory block is an idle storage operation result memory block.

[0062] Furthermore, the data receiving completion mark position corresponding to the second group of input data is eliminated to determine the state of the data to be inputted of the third group of input data.

[0063] Furthermore, based on the state of the data to be input, the third group of input data at the host end is subjected to data transmission control.

[0064] The post-operation result includes: the data receiving completion mark position status and the second storage operation result.

[0065] In one embodiment, Figure 2 As shown, if the operation on the device side is completed after the host completes sending data, that is, if the first group of input data is in the operation state and the second group of input data is in the data transmission completion state, then: the host side sets the GPGPU data reception completion flag position to 1, and then the host continues to detect the operation completion flag position. After the operation on the device side is completed, the operation completion flag position corresponding to the first group of input data is 1, and the host side detects that the operation completion flag position is 1, clears the operation completion flag position to 0, and reads the first storage operation result stored in the first storage operation result memory block back to the host side storage operation result memory, and the next operation result storage address increases accordingly. Then at this time, the device side detects that the data reception completion flag position is 1, and starts the next operation, that is, performs operation processing on the second group of input data, stores the second storage operation result in the second storage operation result memory block, and clears the data reception completion flag position at this time. At this time, the host starts to transfer the third group of input data to the first receiving data memory block.

[0066] S106: Perform an execution judgment on the input task by using the first calculation result and the second calculation result to determine the task execution completion result.

[0067] Specifically, if the input task is in the continuing execution state, the operation state of the device side and the transmission state of the previous set of input data of the host side are sequentially judged based on the completion time nodes according to the remaining set of input data.

[0068] Furthermore, according to the results of the execution in sequence, the remaining groups of input data are subjected to loop operation control until the input task is determined to be in a completed execution state.

[0069] As a feasible implementation method, when the storage operation result stored in the storage operation result memory block is read back to the data output of the host side, the current storage operation result memory block is determined to be in an idle state, and the operation result storage address of the current storage operation result memory is increased accordingly after the next operation processing.

[0070] In one embodiment, Figure 2 As shown in the figure, the GPGPU used has 2 cores, each with 8 scalar cores, and the task to be calculated is a+b=c, where a, b and c are all 64-dimensional vectors. Generally speaking, vector calculation is faster than data transmission from the host to the device, so in most cases, when the first set of input data is in the state of completing the calculation, the second set of input data is still in the state of continuous data transmission, so specifically:

[0071] S1. Divide the memory A, B, and C storing input and output data into 16-dimensional memory blocks A1-A4, B1-B4, and C1-C4, respectively. A and B are used as input data, and C is used as output data.

[0072] S2. The host allocates two 16-byte memories for input data A and B and output data C on the device side, respectively, and records them as MA1, MA2, MB1, MB2, MC1, and MC2, and records the first address and size of each memory block.

[0073] S3. The host transfers the data of memory blocks A1 and B1 from the machine end (device end) to MA1 and MB1 respectively. After the transmission is completed, the data reception completion flag is set to 1.

[0074] S4: The device detects that the data reception completion flag is set to 1, starts the operation, and clears the data reception completion flag to 0.

[0075] S5. The host starts to transfer the data of memory blocks A2 and B2 to MA2 and MB2 respectively, while continuously detecting the operation completion flag.

[0076] S6. Since data transmission is slower than vector calculation, the computing task on the device side is completed first. At this time, the device sets the data computing completion flag of A1 and B1 to 1, and the computing result is stored in MC1.

[0077] S7. The host detects that the operation completion flag is 1, clears the bit, and reads the operation result in MC1 back to C1.

[0078] S8, wait for the A2 and B2 data to be sent, the host sets the GPGPU data reception completion flag to 1, the device detects that the flag is set to 1, starts the next operation, stores the operation results of the A2 and B2 data in MC2, and clears the reception completion flag.

[0079] S9. The host transfers the data of A3 and B3 to MA1 and MB1, and continuously detects the operation completion flag.

[0080] S10. Since data transmission is slower than vector calculation, the computing task on the device side is completed first. At this time, the device sets the computing completion flag to 1, and the computing result is stored in MC2.

[0081] S11, the host detects that the operation completion flag is 1, clears the bit, and reads the operation results of A2 and B2 data in MC2 back to C2.

[0082] S12, wait for A3, B3 data to be sent, the host sets the GPGPU data reception completion flag to 1, the device detects that the flag is set to 1, starts the next operation, stores the operation result in MC1, and clears the reception completion flag.

[0083] S13, the host transmits the data of A4 and B4 to MA2 and MB2, and continuously detects the operation completion flag.

[0084] S14. Since data transmission is slower than vector calculation, the computing task on the device side is completed first. At this time, the device sets the computing completion flag to 1, and the computing result is stored in MC1.

[0085] S15. The host detects that the operation completion flag is 1, clears the bit, and reads the operation results of A3 and B3 data in MC1 back to C3.

[0086] S16, wait for the A4 and B4 data to be sent, the host sets the GPGPU data reception completion flag to 1, the device detects that the flag is set to 1, starts the next operation, stores the A4 and B4 data operation results in MC2, and clears the reception completion flag.

[0087] S17, the host continuously detects the operation completion flag. When the operation task on the device side is completed first and the operation completion flag is set to 1, the host clears the flag and reads the operation results of A4 and B4 data in MC2 back to C4, and the task is completed.

[0088] In addition, the present application embodiment also provides a GPGPU global memory allocation device, such as Figure 3 As shown, the global memory allocation device 300 of GPGPU specifically includes:

[0089] At least one processor 301. And a memory 302 in communication with the at least one processor 301. The memory 302 stores instructions that can be executed by the at least one processor 301, so that the at least one processor 301 can execute:

[0090] According to the size of GPGPU computing resources, each input data required by the input task is divided into data blocks to obtain the input data blocks on the host side;

[0091] Based on the number of input data blocks, determine the number of memory data blocks in the device end;

[0092] According to the input data block and the memory data block, the first group of input data is subjected to device-side operation processing to obtain the operation result of the first group of input data;

[0093] If the computing state of the device side is completed before the host side finishes sending the second set of input data, the device side is controlled to complete computing first, and the computing result of the second set of input data is obtained;

[0094] If the operation state of the device end is completed after the host end finishes sending the second set of input data, the post-operation completion control is performed on the device end to obtain the post-operation result of the second set of input data;

[0095] The input task is judged by the first calculation result and the second calculation result to determine the task execution completion result.

[0096] The embodiment of the present application divides the data required for the computing task into several data blocks, transmits and calculates the data of one data block each time, and executes the computing task on the device side and the data transmission task between the host and the device side in parallel, thereby reducing the occupancy of the device memory during the task execution and improving the task execution efficiency.

[0097] Each embodiment in this application is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device and medium embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.

[0098] The devices and media provided in the embodiments of the present application correspond one-to-one to the methods. Therefore, the devices and media also have similar beneficial technical effects as the corresponding methods. Since the beneficial technical effects of the methods have been described in detail above, the beneficial technical effects of the devices and media will not be repeated here.

[0099] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0100] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or box in the flowchart and / or block diagram, as well as the combination of the processes and / or boxes in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0101] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0102] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0103] In a typical configuration, a computing device includes one or more processors (CPU), input / output interfaces, network interfaces, and memory.

[0104] Memory may include non-permanent storage in a computer-readable medium, in the form of random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.

[0105] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0106] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0107] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the specification of the present application.

Claims

1. A GPGPU global memory allocation method, characterized in that: The method comprises: According to the size of GPGPU computing resources, each input data required by the input task is divided into data blocks to obtain the input data blocks on the host side; Based on the number of the input data blocks, determining the number of memory data blocks in the device end specifically includes: According to the input data blocks, the memory module of the device end is divided based on the storage space corresponding to the input data blocks and the output data blocks of the host end to obtain a unified storage space; wherein the number of data blocks in the unified storage space is twice the number of the input data blocks; Based on the number of the input data blocks, the unified storage space is evenly divided to obtain a memory block for receiving data and a memory block for storing calculation results; wherein the storage space of the memory block for receiving data and the memory block for storing calculation results are the same size; The received data memory block and the storage operation result memory block are integrated to obtain the memory data block; wherein each of the memory data blocks can record the first address and memory size of the storage space; According to the input data block and the memory data block, the device-side operation processing is performed on the first group of input data to obtain the operation result of the first group of input data; If the computing state of the device end is completed before the host end finishes sending the second set of input data, the device end is controlled to complete computing first to obtain the computing result of the second set of input data, specifically including: If the first set of input data is in a state of completing operation and the second set of input data is in a state of continuous data transmission, marking the position of the operation completion mark in the device end; When the host side detects the marked operation completion flag position, the operation completion flag position is eliminated; and the first storage operation result stored in the memory data block is read back to the data output of the host side, and the storage address of the memory data block corresponding to the first storage operation result is positioned as a usable state; When the second group of input data is in the process of completing data transmission, marking a data reception completion flag position corresponding to the second group of input data; Based on the marked data reception completion flag position, perform operation processing on the second group of input data, and store the second storage operation result in the second storage operation result memory block of the memory data block; wherein the second storage operation result memory block is an idle storage operation result memory block; Eliminate the data receiving completion mark position corresponding to the second group of input data to determine the state of the data to be inputted of the third input data; The first calculation result includes: the state of the data to be input, the state of the data receiving completion mark position and the state of the calculation completion mark position; If the computing state of the device end is completed after the host end finishes sending the second set of input data, post-computation completion control is performed on the device end to obtain a post-computation result of the second set of input data, specifically including: If the first set of input data is in a computing state and the second set of input data is in a data transmission completion state, marking a data reception completion flag position of the second set of input data in the device end; By means of the host end, continuously detecting and processing the position status of the operation completion mark of the first group of input data; When the operation completion flag position of the first group of input data in the device end is determined to be in a marked state, the operation completion flag position of the first group of input data is eliminated through the host end, and the first storage operation result stored in the first storage operation result memory block is read back to the data output of the host end; When the device detects that the data receiving completion flag position of the second group of input data is in the marked state, the second group of input data is processed; and the second storage operation result of the second group of input data is stored in the second storage operation result memory block of the memory data block; wherein the second storage operation result memory block is an idle storage operation result memory block; Eliminate the data receiving completion mark position corresponding to the second group of input data to determine the state of the data to be inputted of the third group of input data; Based on the state of the data to be input, controlling data transmission of the third group of input data of the host end; Wherein, the post-operation result includes: the data receiving completion mark position status and the second storage operation result; The input task is judged for execution based on the first calculation result and the second calculation result to determine the task execution completion result.

2. A GPGPU global memory allocation method according to claim 1, characterized in that: According to the size of GPGPU computing resources, each input data required by the input task is divided into data blocks to obtain the input data blocks on the host side, which specifically include: By means of the host side, each input data in the input task is divided into data blocks under the same data element, and each data block is numbered in turn to obtain the input data block of the host side; The number of the data blocks is the product of the number of programmable multiprocessors assigned to the input task and the number of scalar cores in each programmable multiprocessor.

3. The global memory allocation method of GPGPU according to claim 1, characterized in that: According to the input data block and the memory data block, performing the device-side operation processing on the first group of input data to obtain the operation result of the first group of input data specifically includes: The first group of input data in the input task is transferred to a first receiving data memory block of the memory data of the device side through the input data block of the host side and based on the storage address of the device side; Based on the first received data memory block, performing data receiving completion flag position marking processing on the first group of input data; When the device detects the position of the data receiving completion mark after the mark, the device performs operation processing on the first group of input data, and stores the operation result in the first storage operation result memory block of the memory data block to obtain a first storage operation result; Based on the first storage operation result, eliminating the data reception completion flag position of the first group of input data to obtain a flag cleared state; The second group of input data in the host end is transmitted to the second receiving data memory block of the memory data block in the device end, and the operation completion flag bit in the device end is continuously detected to obtain the state of the data to be input; The operation result includes: the first stored operation result, the flag cleared state and the state of the data to be input.

4. The global memory allocation method of GPGPU according to claim 1, characterized in that: The input task is judged by the first calculation result and the second calculation result to determine the task execution completion result, specifically including: If the input task is in the continuing execution state, then according to the remaining set of input data, the operation state of the device end and the transmission state of the previous set of input data of the host end are sequentially judged in terms of the execution order of the completion time nodes; According to the results of the execution in sequence, the remaining groups of input data are subjected to cyclic operation control until the input task is determined to be in a completed execution state.

5. The global memory allocation method of GPGPU according to claim 1, characterized in that: When the storage operation result stored in the storage operation result memory block is read back to the data output of the host end, the current storage operation result memory block is determined to be in an idle state, and the operation result storage address of the current storage operation result memory is increased accordingly after the next operation processing.

6. A GPGPU global memory allocation device, characterized in that: The device comprises: at least one processor; and, a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, so that the at least one processor can execute the global memory allocation method of GPGPU according to any one of claims 1-5.

7. A non-volatile computer storage medium, characterized in that: The storage medium is a non-volatile computer-readable storage medium, and the non-volatile computer-readable storage medium stores at least one program, each of which includes instructions, and when the instructions are executed by the terminal, the terminal executes a GPGPU global memory allocation method according to any one of claims 1-5.

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