Data processing method, processor, system-on-chip, computing device and storage medium

Abstract

The invention discloses a data processing method, a processor, a system on chip, computing equipment and a storage medium. The method is applied to a processor and comprises the steps of obtaining a to-be-executed first instruction; identifying the first instruction, and determining whether the first instruction is a preset prompt instruction; under the condition that it is determined that the first instruction is the preset prompt instruction, a second instruction located after the first instruction is obtained, and the second instruction is used for accessing target data stored in a memory; the cache replacement strategy of the target data is adjusted, and the adjusted cache replacement strategy is used for ensuring that replacement of the target data into the cache is forbidden within a preset time period. According to the method and the device, the technical problems of relatively high access delay and relatively poor overall performance of a processor during instruction processing in related technologies are solved.

Description

Technical Field

[0001] The present application relates to the field of processors, and in particular, to a data processing method, a processor, a system on a chip, a computing device, and a storage medium. Background Art

[0002] The processor in a computer system is responsible for executing instructions in a computer program. The processor processes data, controls the operation of the computer, and communicates with other hardware devices by executing a series of instructions.

[0003] In the related art, when the cache usage capacity in a computer system is close to the upper limit, each additional cache line needs to replace the existing cache line. The cache replacement strategy is used to decide which cache line to replace, and mainly utilizes the temporal locality and spatial locality of program memory access behavior, such as the Least Recently Used (LRU) algorithm and its variants. In actual applications, some critical paths are not executed frequently. For example, the operation of deleting a node from a linked list is not executed frequently, but it is in the critical path, resulting in the data corresponding to the critical path being replaced by the cache replacement strategy. If the cache miss rate is high, the impact on performance will be relatively large, which will lead to delays in the execution of processor instructions and reduced overall performance of the processor, resulting in high access delays for instruction processing by the processor and poor overall performance.

[0004] To address the above-mentioned problems, no effective solution has been proposed yet. Summary of the invention

[0005] The embodiments of the present application provide a data processing method, a processor, a system on chip, a computing device and a storage medium, so as to at least solve the technical problems of high access delay and poor overall performance of the processor in the related art for instruction processing.

[0006] According to one aspect of an embodiment of the present application, a data processing method is provided, which is applied to a processor, and the method includes: obtaining a first instruction to be executed; identifying the first instruction to determine whether the first instruction is a preset prompt instruction; when it is determined that the first instruction is the preset prompt instruction, obtaining a second instruction that follows the first instruction, wherein the second instruction is used to access target data stored in a memory; and adjusting a cache replacement policy for the target data, wherein the adjusted cache replacement policy is used to ensure that the target data is prohibited from being replaced into the cache within a preset time period.

[0007] According to another aspect of the embodiments of the present application, a processor is provided for running a program, wherein the method in each embodiment of the present application is executed when the program is running.

[0008] According to another aspect of the embodiments of the present application, a system on chip is also provided, including the processor in each embodiment of the present application.

[0009] According to another aspect of the embodiments of the present application, a computing device is further provided, including: a memory storing an executable program; and a processor for running the program, wherein the method in each embodiment of the present application is executed when the program is running.

[0010] According to another aspect of the embodiments of the present application, a computer-readable storage medium is further provided, wherein the computer-readable storage medium includes a stored executable program, wherein when the executable program is executed by a processor, the method according to each embodiment of the present application is implemented.

[0011] According to another aspect of the embodiments of the present application, a computer program product is also provided, including computer instructions, which implement the methods in various embodiments of the present application when executed by a processor.

[0012] According to another aspect of an embodiment of the present application, a computer program product is also provided, including a non-volatile computer-readable storage medium, wherein the non-volatile computer-readable storage medium stores computer instructions, and when the computer instructions are executed by a processor, the methods in various embodiments of the present application are implemented.

[0013] According to another aspect of the embodiments of the present application, a computer program is also provided, and when the computer instructions are executed by a processor, the methods in the various embodiments of the present application are implemented.

[0014] In the embodiment of the present application, first, the processor obtains the first instruction to be executed and identifies the first instruction; then, the processor determines whether the instruction is a preset prompt instruction. If it is a preset prompt instruction, the processor will obtain the second instruction after the first instruction, and the second instruction is used to access the target data stored in the memory; finally, the processor can adjust the cache replacement strategy of the target data to ensure that the target data will not be replaced or refreshed to the downstream cache within a preset time period. It is easy to notice that by adding the preset prompt instruction to the second instruction in the critical path or before the second instruction accessing the memory, the processor can determine that the explicit memory access of the second instruction after the preset prompt instruction exhibits reference time locality by identifying the preset prompt instruction, that is, it is determined that the target data in the memory accessed by the second instruction will not be replaced or refreshed to the downstream cache within a preset time period, thereby ensuring that the target data can be retained in the cache for a long time without being replaced by the cache, thereby improving the hit rate of the target data and reducing the cache miss, thereby reducing the delay in data access, improving the data access speed, and thus improving the performance and efficiency of the program, thereby solving the technical problems of high access delay and poor overall performance of the processor in the related art for instruction processing.

[0015] It is easy to notice that the above general description and the following detailed description are only for the purpose of exemplifying and explaining the present application, and do not constitute a limitation of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0017] Figure 1 is a hardware structure block diagram of a RISC-V system for implementing a data processing method according to an embodiment of the present application;

[0018] Figure 2 is a schematic diagram of a RISC-V architecture system on chip according to an embodiment of the present application;

[0019] Figure 3 is a flow chart of a data processing method according to an embodiment of the present application;

[0020] Figure 4 is a schematic diagram of a data processing device according to an embodiment of the present application;

[0021] Figure 5 It is a structural block diagram of a computing device according to an embodiment of the present application. DETAILED DESCRIPTION

[0022] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0023] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0024] First, some nouns or terms that appear in the description of the embodiments of the present application are subject to the following explanations:

[0025] Temporal Locality (TL) means that a memory location that has been referenced once will be referenced multiple times in the future.

[0026] Hints can be used to indicate that the processor is prompted to perform some optimization operations through instructions that have no effect.

[0027] The prefetch instruction may be used to load the data to be used from the main memory into the cache in advance, so as to reduce the delay when executing the instruction accessing the main memory.

[0028] According to an embodiment of the present application, a data processing method is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although a logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0029] The method embodiment provided in Embodiment 1 of the present application can be executed in a RISC-V system, a RISC-V chip or a similar device. Figure 1 FIG. 4 shows a hardware structure block diagram of a RISC-V system for implementing a data processing method. Figure 1As shown, the RISC-V system can be divided from the bottom layer to the upper layer into a reduced instruction set architecture 101 (including a basic instruction set 101-1 and an extended instruction set 101-2), a hardware layer 102 (including a processor 102-1, a peripheral hardware circuit 102-2, etc.), an interface layer 103, an operating system layer 104 (supporting multiple operating systems 104-1, 104-2, ..., 104-n, such as Linux, FreeSBD, RT-Tread, etc.), a middleware and library layer 105 (including a system library 105-1, an API 105-2 and a middleware service 105-3) and an application layer 106 (including multiple user programs and services 106-1, 106-2, ..., 106-n). The RISC-V system also includes a tool chain 107 from the underlying hardware to the application layer. The tool chain may include a compiler and assembler 107-1, a linker 107-2, a debugger 107-3, a simulator and emulator 107-4, an integrated development environment 107-5, a hardware description language tool 107-6, a performance analysis tool 107-7, and a version control system 107-8, etc.

[0030] The instruction set architecture 101 defines the basic operations and instruction sets supported by the processor 102-1, including a basic instruction set and an extended instruction set, wherein the basic instruction set represents a basic integer instruction set, such as RV32I and RV64I, and the extended instruction set can be floating point, atomic operations, compressed instructions, etc.

[0031] The interface layer 103 includes the specific design of the processor, such as pipeline design, cache structure, execution unit, branch prediction, etc. This layer is the process of mapping abstract instructions to physical hardware.

[0032] The operating system layer 104 is located above the hardware and provides a hardware abstraction layer and management mechanism, so that applications can interact with the hardware through system calls. The operating system is responsible for managing processor resources, memory, device drivers, task scheduling, etc.

[0033] The middleware and library layer 105 provides a rich set of services and interfaces to help applications run more efficiently. For example, the standard library provides functions such as file operations and mathematical calculations, while the middleware can provide complex services such as network communications and graphical user interfaces.

[0034] The application layer 106 uses the functions and services provided by the lower layer to implement specific application logic. These applications can be command line tools, graphical interface applications, server-side services, etc.

[0035] The tool chain 107 is a key component that connects the underlying hardware to the upper-level software. Various tools in the tool chain 107 function at different levels to support the entire process from hardware design to software development, ensuring the consistency and effectiveness of the entire system design.

[0036] It should be noted that the layered design of the RISC-V architecture allows decoupling between different layers, so that each layer can be developed and optimized independently.

[0037] In an optional embodiment, Figure 2 Shown using the above Figure 1 The schematic diagram of the RISC-V architecture system on chip (System On Chip, SOC) is shown in FIG. Figure 2 As shown, the SOC includes at least one RISC-V core 202 (only one is shown in the figure), and the RISC-V core 202 is connected to peripheral devices through a bus 204, including but not limited to ROM 206, RAM 208, timer 210, UART (Universal Asynchronous Receiver / Transmitter) 212, GPIO (General Purpose Input / Output) 214, SPI (Serial Peripheral Interface Bus) 216, etc.

[0038] Under the above operating environment, this application provides Figure 3 The data processing method shown is applied to a processor, Figure 3 is a flow chart of a data processing method according to an embodiment of the present application. Figure 3 As shown, the following steps may be specifically included:

[0039] Step S302, obtaining a first instruction to be executed.

[0040] The above-mentioned processor may refer to a processor that is an electronic device in a computer system. The processor may adopt a reduced instruction set computing (RISC) architecture, so that custom instructions may be adopted, that is, pre-defined prompt instructions, and the processor may be responsible for executing instructions in a computer program. The processor processes data, controls the operation of the computer, and communicates with other hardware devices by executing a series of instructions. The processor may include components such as an arithmetic logic unit, a control unit, and a register, wherein the arithmetic logic unit is responsible for performing arithmetic operations and logical operations, the control unit is responsible for controlling the flow of data and the execution order of instructions, and the register is used to store instructions and data. The specific type of the processor can be determined according to actual needs and is not limited here.

[0041] The above-mentioned first instruction can refer to any command or operation to be executed in a computer program, which is used to tell the processor to perform a specific task or operation. The first instruction can be a simple arithmetic operation or a complex logical operation. Different operations can be performed according to different instructions. The first instruction can be determined according to actual needs and is not limited here.

[0042] In an optional embodiment, the processor may obtain an instruction to be executed from an instruction cache or an instruction queue as the first instruction. Specifically, the processor may pre-acquire a certain number of instructions and store them in the instruction cache so that they can be quickly acquired when they are needed for execution, which can reduce the delay in instruction acquisition and improve the execution efficiency of instructions. The processor may decode the pre-acquired instructions and convert them into an internal instruction format that the processor can understand and execute, which may include parsing information such as the opcode and operand of the instruction to facilitate subsequent execution operations, and then the selected instruction may be used as the first instruction. The method for acquiring the first instruction may be determined according to actual needs and is not limited here.

[0043] Step S304: identify the first instruction and determine whether the first instruction is a preset prompt instruction.

[0044] The above-mentioned preset prompt instruction may refer to a prompt instruction preset or defined in the present application, and preferably, may be a customized time local prompt instruction. The preset prompt instruction may be specifically determined according to actual needs and is not limited here.

[0045] The above-mentioned temporal locality hint instruction can be a programming instruction that utilizes the temporal locality (Temporal Locality) in the program to improve the performance of the program. Temporal locality can refer to the characteristic that certain data in the program is accessed multiple times in a short period of time. By arranging the instruction sequence reasonably, the number of memory accesses can be reduced, thereby reducing the running time of the program. The temporal locality hint instruction can be inserted into the source code by the compiler to prompt the processor to consider temporal locality when executing instructions, and can tell the processor which data will be reused in a short period of time. By using the temporal locality hint instruction reasonably, the programmer can optimize the performance of the program, reduce memory access delays, and improve the execution efficiency of the program.

[0046] In an optional embodiment, the first instruction can be identified to determine whether the first instruction is a preset prompt instruction. Specifically, in the processor, the preset prompt instruction can mean that when the instruction is executed, the prediction and optimization of time locality will be triggered, and some specific opcodes or operands can be included to tell the processor what optimization measures should be taken when executing the instruction. In the pipeline of the processor, when a new instruction is taken out and enters the execution stage, the processor can identify the instruction to determine the specific function and operation of the instruction. After identifying the instruction, the processor can determine whether the instruction is a preset prompt instruction according to a preset rule or table. If the instruction is determined to be a preset prompt instruction, the processor can trigger the prediction and optimization of time locality according to a preset optimization strategy to improve the efficiency and performance of program execution. Finally, the processor can execute the instruction according to the results of the prediction and optimization, thereby achieving the effect of optimizing time locality and improving processor performance.

[0047] Step S306, when it is determined that the first instruction is a preset prompt instruction, a second instruction located after the first instruction is obtained, wherein the second instruction is used to access target data stored in the memory.

[0048] The second instruction mentioned above may refer to an instruction that needs to be executed next after the processor executes the first instruction.

[0049] The above-mentioned target data may refer to data stored in the memory and required to be accessed by the second instruction. The specific data content of the target data may be determined according to actual needs and is not limited here.

[0050] In an optional embodiment, when executing the instruction sequence, the processor determines that the first instruction is a preset hint instruction through a certain mechanism, such as hardware prediction or compiler optimization. After executing the first instruction, the processor can obtain the second instruction located after the first instruction according to the preset hint instruction, so as to facilitate the subsequent use of temporal locality to temporarily replace the target data indicated by the second instruction, so as to effectively improve the execution efficiency of the processor.

[0051] Step S308: adjusting the cache replacement policy of the target data, wherein the adjusted cache replacement policy is used to ensure that the target data is prohibited from being replaced into the cache within a preset time period.

[0052] The above-mentioned preset time period can be determined according to the specific type of the processor or other actual needs, and is not limited here. Prohibiting the target data from being replaced or refreshed to the downstream cache during the preset time period can ensure that the target data in the cache is temporarily replaced or refreshed, so as to utilize the temporal locality characteristics to improve the processor execution efficiency.

[0053] The above-mentioned cache replacement policy may refer to the replacement policy originally set by the processor for the target data, which may include but is not limited to the First-In Fist-Out (FIFO) policy, the Least Recently Used (LRU) policy, the Least Frequently Used (LFU) policy and the Random replacement policy (Random), wherein the First-In First-Out policy may indicate that the data that enters the cache first will be replaced first; the Least Recently Used policy may indicate that the data in the cache is replaced according to the time when the data was recently accessed. This policy can retain data that may be accessed again and improve the cache hit rate; the Least Frequently Used policy may indicate that the data in the cache is replaced according to the frequency of data access. Frequently accessed data can be retained, but some data may be frequently replaced; the Random replacement policy may indicate randomly selecting a data to be replaced. The cache replacement policy can be determined according to actual needs and is not limited here.

[0054] In an optional embodiment, in the optimization of the temporal locality of the processor, the cache replacement strategy for the target data can be adjusted. By adjusting the cache replacement strategy, the target data can be prevented from being replaced or refreshed to the downstream cache within a preset time period, thereby improving the access efficiency and performance of the data. Specifically, the target data to be protected can be determined according to the second instruction, or the target data can be determined according to the characteristics of the application and the data access mode, and a suitable cache replacement strategy can be selected according to the characteristics and access mode of the target data. Then, the selected cache replacement strategy can be modified according to the requirement of prohibiting the target data from being replaced or refreshed to the downstream cache, and the parameters of the strategy can be adjusted or additional protection mechanisms can be added according to the characteristics and access mode of the target data. The corresponding algorithm and data structure can also be implemented according to the modified cache replacement strategy, that is, these strategies are implemented in the cache manager to ensure that the target data will not be replaced or refreshed during cache replacement. Finally, the modified cache replacement strategy can be tested and optimized to ensure that the target data will not be replaced or refreshed within the preset time period, and the access efficiency and performance of the data can be improved. Through the above steps, the cache replacement policy of the target data can be adjusted to ensure that the target data is prevented from being replaced or refreshed to the downstream cache within a preset time period, thereby optimizing the temporal locality of the processor.

[0055] The setting of the above steps can enhance the temporal locality of the processor. If the target data is retained in the cache during this period, the hit rate of data access can be effectively improved. By adjusting the cache replacement strategy to ensure that the target data is prevented from being replaced or refreshed to the downstream cache within a preset time period, the storage time of the target data in the cache can be effectively extended, thereby enhancing temporal locality. The original cache replacement strategy is usually based on the least recently used (LRU) or first-in-first-out (FIFO) principles for data replacement, which may cause frequently accessed data to be continuously replaced out of the cache within a period of time, reducing temporal locality, thereby improving the performance and efficiency of the program. Adjusting the cache replacement strategy to ensure that the target data is prevented from being replaced or refreshed to the downstream cache within a preset time period can effectively enhance the temporal locality of the processor, improve the efficiency of data access, and reduce cache misses, thereby optimizing the performance and response speed of the program.

[0056] In the embodiment of the present application, first, the processor obtains the first instruction to be executed and identifies the first instruction; then, the processor determines whether the instruction is a preset prompt instruction. If it is a preset prompt instruction, the processor will obtain the second instruction after the first instruction, and the second instruction is used to access the target data stored in the memory; finally, the processor can adjust the cache replacement strategy of the target data to ensure that the target data will not be replaced or refreshed within the preset time period. It is easy to notice that by adding the preset prompt instruction to the second instruction in the critical path or before the second instruction accessing the memory, the processor can determine that the explicit memory access of the second instruction after the preset prompt instruction exhibits reference time locality by identifying the preset prompt instruction, that is, it is determined that the target data in the memory accessed by the second instruction will not be replaced or refreshed within the preset time period, thereby ensuring that the target data can be retained in the cache for a long time without being replaced by the cache, thereby improving the hit rate of the target data and reducing the cache miss, thereby reducing the delay in data access, improving the data access speed, and thus improving the performance and efficiency of the program, thereby solving the technical problems of high access delay and poor overall performance of the processor in the related art for instruction processing.

[0057] In the above embodiment of the present application, the first instruction is identified to determine whether the first instruction is a preset prompt instruction, including: decoding the first instruction to obtain the operation code, register and immediate number contained in the first instruction; matching the operation code with the preset operation code corresponding to the preset prompt instruction, matching the register with the preset register corresponding to the preset prompt instruction, and matching the immediate number with the preset immediate number corresponding to the preset prompt instruction; when the operation code matches the preset operation code successfully, the register matches the preset register successfully, and the immediate number matches the preset immediate number successfully, it is determined that the first instruction is the preset prompt instruction.

[0058] In an optional embodiment, during the temporal locality prompting process of the processor, the first instruction can be identified and determined whether it is a preset prompt instruction, and the first instruction can be decoded to obtain the opcode, register and immediate value information contained in the instruction. Then, the decoded opcode can be matched with the preset opcode corresponding to the preset prompt instruction. If the opcode matches the preset opcode successfully, the next step is continued; otherwise, the instruction is determined not to be the preset prompt instruction. Then, the decoded register can be matched with the preset register corresponding to the preset prompt instruction. If the register matches the preset register successfully, the next step is continued; otherwise, the instruction is determined not to be the preset prompt instruction. Then, the decoded immediate value can be matched with the preset immediate value corresponding to the preset prompt instruction. If the immediate value matches the preset immediate value successfully, the first instruction is considered to be the preset prompt instruction; otherwise, the instruction is determined not to be the preset prompt instruction. Finally, when the opcode, register and immediate value are all matched successfully, it can be determined that the first instruction is the preset prompt instruction, and the processor can perform corresponding processing based on this information to optimize the temporal locality of instruction execution.

[0059] In the above steps, by decoding and matching the first instruction, it can be determined before execution whether it is a preset prompt instruction. By matching the opcode, register and immediate value, it can be accurately determined whether the first instruction is a preset prompt instruction to avoid misjudgment and misoperation. That is, by identifying and matching the first instruction to determine whether it is a preset prompt instruction, preparations can be made in advance during the instruction execution process, thereby improving execution efficiency and accuracy and facilitating subsequent optimization of temporal locality.

[0060] In the above embodiment of the present application, the cache replacement policy of the target data is adjusted, including: based on the second instruction, determining the target storage area corresponding to the target data, wherein the target storage area is used to represent the storage area in the processor's cache for storing the target data; when the target storage area belongs to a private cache, the cache replacement policy is adjusted.

[0061] In an optional embodiment, during the temporal locality optimization process of the processor, the cache replacement strategy of the target data can be adjusted to improve the access efficiency and hit rate of the data. Specifically, the target storage area corresponding to the target data can be determined based on the second instruction. First, the access mode and frequency of the target data, as well as the size and usage of the data, can be determined by the second instruction, so that the storage location and access requirements of the target data in the cache can be determined more accurately. Then, the target storage area can be determined. After determining the target storage area corresponding to the target data, it can be mapped to the storage area in the processor's cache. The target storage area is used to characterize the storage area in the processor's cache for storing the target data. Finally, the cache replacement strategy can be adjusted. In the case where the target storage area belongs to a private cache, the cache replacement strategy can be adjusted according to the access mode and frequency of the target data. Through the above steps, the cache replacement strategy of the processor can be more effectively optimized, and the access efficiency and hit rate of the target data can be improved, thereby improving the overall performance and response speed of the system.

[0062] In the above steps, by determining the target storage area corresponding to the target data based on the second instruction, and adjusting the cache replacement policy when the target storage area belongs to a private cache, the storage area in the cache can be more effectively utilized to store the target data, and the data can be marked as time-critical, thereby reducing the number of cache replacements, improving the cache hit rate, reducing cache misses, and further reducing the number of main memory accesses, improving the execution efficiency of the program, and better adapting to the specific architecture and workload of the processor, avoiding unnecessary cache replacement operations, and further improving the cache hit rate and performance.

[0063] In the above embodiment of the present application, the cache replacement policy of the target data is adjusted, including: determining whether the second instruction is a cache management operation instruction, wherein the cache management operation instruction is used to move data stored in the processor's cache to the memory; when it is determined that the second instruction is not a cache management operation instruction, the cache replacement policy is adjusted.

[0064] In an optional embodiment, during the temporal locality optimization process of the processor, the processor may check whether the second instruction is a cache management operation instruction, such as an instruction to move data to the memory. If the second instruction is a cache management operation instruction, it may indicate that the target data is actively refreshed to the downstream cache, and a copy may be saved locally. At this time, there is no need to adjust the cache replacement policy. If it is determined that the second instruction is not a cache management operation instruction, the cache replacement policy may be adjusted. If the second instruction is not a cache management operation instruction, it indicates that the target data may be frequently replaced. In order to improve the cache hit rate and temporal locality, the cache replacement policy may be adjusted, and a suitable cache replacement policy may be selected according to the specific situation. The processor may also monitor the access frequency and mode of the target data in real time, and continuously adjust the cache replacement policy to adapt to the real-time data access mode. By continuously optimizing the cache replacement policy, the cache hit rate can be improved, cache failures can be reduced, and the performance and efficiency of the program can be improved. Through the above steps, the processor can effectively optimize the temporal locality and improve the performance and efficiency of the program.

[0065] In the above steps, by adjusting the cache replacement strategy, the data blocks on the critical path are retained in the cache, which reduces the number of cache misses, improves the cache hit rate, speeds up the execution of the program, reduces the number of memory accesses, reduces the latency of memory access, improves the overall performance of the program, effectively improves the overall performance of the processor, improves the execution efficiency and response speed of the program, and improves the user experience.

[0066] In the above embodiments of the present application, the cache replacement strategy is adjusted, including at least one of the following: marking the target data according to preset marking information; adjusting the priority of the target data; pre-extracting the target data from the memory and storing the target data in the cache.

[0067] In an optional embodiment, the adjustment of the cache replacement strategy can be implemented in the following manner: the target data can be marked according to the preset marking information. In the cache replacement strategy, a marking information can be added to each data block to indicate the importance of the data block or the degree of frequent access. When the data in the cache needs to be replaced, the less frequently accessed data can be replaced first according to the marking information, thereby improving the temporal locality. The priority of the target data can also be adjusted. According to the frequency of use or importance of the data, the priority of the data in the cache can be adjusted. For example, the frequently accessed data can be promoted to a high priority, so that the data will be retained first when the cache data is replaced, thereby improving the temporal locality. The target data can also be extracted in advance and stored in the cache. In order to avoid performance loss during cache replacement, the target data can be pre-loaded into the cache before the program is executed, so that the target data can be quickly accessed when needed, thereby improving the temporal locality. By adjusting the cache replacement strategy in the above manner, the temporal locality of the processor can be effectively improved, the situation of cache misses can be reduced, and the execution efficiency of the program can be improved.

[0068] In the above steps, by adjusting the cache replacement strategy, adjusting the priority of the target data, it is possible to determine which data is retained in the cache according to the importance and access frequency of the data, which can help improve the cache hit rate, thereby reducing the performance loss caused by cache misses. Specifically, by marking the target data according to the preset tag information, it can be classified according to the characteristics and access patterns of the data, so as to better decide whether to store the data in the cache, which can improve the cache hit rate, reduce cache misses, and improve the matching degree between the data stored in the cache and the data actually accessed, further improving the cache hit rate, and loading the data into the cache before the actual access, thereby reducing the time overhead of cache misses. This can accelerate the access speed to the target data and improve the execution efficiency of the program.

[0069] In the above embodiment of the present application, after adjusting the cache replacement policy of the target data, the method further includes: in the event that an exception occurs during the execution of the second instruction, restoring the cache replacement policy of the target data.

[0070] In an optional embodiment, after adjusting the cache replacement policy, if an exception occurs during the execution of the second instruction, the cache replacement policy of the target data can be restored to ensure the normal operation of the program. Specifically, before adjusting the cache replacement policy, the current cache replacement policy state can be saved first, and a mark bit can be added in the cache controller to indicate the current cache replacement policy state. When it is necessary to adjust the cache replacement policy, the current cache replacement policy state is first saved in the mark bit, and then the replacement policy is adjusted. During the execution of the second instruction, if an exception occurs, the cache replacement policy of the target data needs to be restored. At this time, the cache replacement policy state can be restored by reading the previously saved mark bit. Then, according to the restored cache replacement policy state, the replacement policy parameters in the cache controller can be reset to ensure that the subsequent program execution can be carried out according to the restored replacement policy. Through the above steps, the cache replacement policy of the target data can be restored when an exception occurs to ensure the normal operation of the program, and the cache replacement policy adjustment under abnormal conditions can be handled while ensuring the efficient operation of the program.

[0071] In the above embodiment of the present application, after adjusting the cache replacement strategy of the target data, the method also includes: when an interruption occurs during the execution process between the first instruction and the second instruction, executing an interrupt handler; when the interrupt handler is executed, re-executing the second instruction.

[0072] In an optional embodiment, in the optimization of the temporal locality of the processor, the cache replacement strategy of the target data can be adjusted, and when an interruption occurs, the interruption handler can be executed, and the second instruction can be re-executed after the interruption handler is executed. Specifically, when an interruption occurs between the first instruction and the second instruction, the processor can save the state of the current instruction and jump to the entry point of the interruption handler. Then, the interruption handler can process the interruption, which may include saving the scene, executing the corresponding processing logic, etc. After the interruption handler is executed, the processor can re-execute the second instruction according to the saved state information, and this process may include operations such as restoring the scene and reloading related data. Finally, when the second instruction is re-executed, since the instruction has been executed before, the previously loaded data may be obtained from the cache, thereby reducing the number of accesses to the main memory and improving the execution efficiency of the program. In this way, in the optimization of the temporal locality of the processor, the interruption event can be effectively handled, the execution fluency of the program is guaranteed, and the execution efficiency of the program is improved by adjusting the cache replacement strategy.

[0073] In the above embodiment, after the cache replacement strategy of the target data is adjusted, the interrupt handler is executed and the second instruction is re-executed, so that the second instruction can be re-loaded in the cache, thereby improving the cache hit rate of the instruction, because the second instruction has been loaded into the cache when it is first executed, and it is more likely to hit the cache when it is executed again. When an interruption occurs, the data originally in the cache may be replaced, resulting in a miss when accessed next time. By re-executing the second instruction, the cost of cache misses caused by interruptions can be effectively reduced, the access efficiency of data can be improved, the interruption of program execution caused by interruptions can be avoided, the pause time of program execution is reduced, and the execution efficiency of the overall program is improved.

[0074] In the above embodiment of the present application, when the interrupt handling program is executed, the method further includes: when the first instruction and the second instruction are merged, re-executing the first instruction.

[0075] In an optional embodiment, after the execution of the interrupt handler is completed, the processor can continue to execute the originally interrupted program. If during the execution of the interrupt handler, there is a situation where the first instruction and the second instruction are merged, that is, the execution of the first instruction is interrupted by the second instruction. After the execution of the interrupt handler is completed, the processor can recheck the execution of the first instruction. If the result of the execution of the first instruction needs to be recalculated or updated, the processor will re-execute the first instruction. The process of re-executing the first instruction may include reloading instructions and data, recalculating the result of the instruction, and updating related registers and memories, so as to ensure that the execution result of the first instruction is accurate and will not be affected by the interrupt handler. The process of re-executing the first instruction can help improve the temporal locality of the processor, reduce the impact of interrupts on program execution, and improve the execution efficiency and performance of the program. The above-mentioned process of re-executing the first instruction is an optimization strategy for the processor after the execution of the interrupt handler is completed, which can help the processor improve the temporal locality and improve the efficiency and performance of program execution.

[0076] In the above embodiment, when the first instruction and the second instruction are merged, re-executing the first instruction can reduce the number of execution times of the instruction, thereby improving the efficiency of instruction execution, reducing the number of processor clock cycles, and speeding up the execution speed of the instruction. It can avoid the interruption and rescheduling of instruction execution caused by the interrupt handler, thereby reducing the execution time and delay of the program, reducing the impact on other instructions, improving the overall performance of the system, reducing the waste of resources, and improving the concurrency and throughput of the system.

[0077] The technical solution proposed in the present application is explained below in combination with an optional application scenario. The present application marks memory accesses with temporal locality hints, so that data exhibits critical locality in the cache, optimizes the access delay of the software critical path, and improves the overall performance. In order to solve the above problems with less hardware, the present application proposes a temporal locality hint extension (Temporal Locality Hint, referred to as TL Hint). TL Hint can be used in the critical path of the software code so that the cached data will not be immediately replaced by the cache replacement strategy, thereby exhibiting critical temporal locality. The present application defines a temporal locality hint to indicate that the data is critical in the cache. The difference from the traditional prefetch instruction is that the hint can be inserted in a more free position without worrying about the data being replaced quickly by the cache replacement strategy.

[0078] TL Hint is also known as temporal locality hint, and its definition can be as follows: it indicates the instruction that follows it, hereinafter referred to as the target instruction. The explicit memory access of the target instruction exhibits critical reference temporal locality. The explicit memory access can be directly loading or storing data through instructions (load / store); this hint indicates that the target instruction will exhibit critical temporal locality within the private cache in the memory hierarchy, and the data will not be immediately replaced by the cache replacement policy. The range of the private cache may depend on the microarchitecture; this TL Hint can be encoded as SLTI x0,x0,0, SLTI (SetLess Than Immediate, signed immediate less than instruction) is encoded as the part of the Hint instruction used for custom extensions based on the 64-bit integer basic instruction set (RV64I) of the RISC-V instruction set architecture. If the C extension is implemented, the C-expanded version of this TLHint is C.SLTI x0,0, where x0 is integer register No. 0 defined in the architecture (RISC-V), the first x0 in front of SLTIx0,x0,0 is the target register, the second x0 is the source register, and 0 is the immediate value 0; TL Hint will neither change the architectural state nor the architecturally visible effects of the target instruction.

[0079] The reference time locality in this application may mean that used data may be used again after a period of time. Through this feature, the data can be kept in a frequently used state to prevent it from being replaced immediately; the memory hierarchy structure is divided into private and shared, and data may be replaced in both, but for security reasons, the prompt can act on the private cache; the length of the stay time may depend on the specific microarchitecture implementation, and there will be different cache replacement strategy algorithms to determine which ones will be replaced.

[0080] The impact of the programming model on cache management operations (CMO). TL Hint affects other memory access instructions besides cache block operations in the "CMO" extension. The meaning of the impact here can be said that TLHint will change the behavior of subsequent memory access instructions. The "CMO" instruction evicts data from the cache to the memory, while TL Hint keeps the data in the cache for critical time locality. The two have opposite meanings.

[0081] In terms of exceptions, if a trap occurs on the target instruction, the instruction trap means that the subsequent target instruction is a memory access instruction, and a page fault or access permission exception may occur when parsing the address. Whether Hint can be ignored depends on the specific microarchitecture implementation. It can be ignored when taking values ​​or in the pipeline. It is not recommended to apply TL Hint to the first instruction in the trap handler. On the contrary, it is recommended to ignore Hint in this case.

[0082] If an interruption occurs between the execution of a TL Hint and its target instruction, execution will usually resume at the target instruction. After the interruption occurs, the program will enter the interrupt handler. When the interrupt handler is completed, it is necessary to return to the original instruction sequence. The recovery here means that after the interrupt handler is executed, the target memory access instruction needs to be re-instructed. If the TL Hint is not re-executed, the semantics of the program will not be changed.

[0083] If no instructions are inserted between the TL Hint and its target instruction, the absence of any instructions can allow the microarchitecture implementation to fuse the TL Hint and the target instruction and execute them as one instruction in subsequent processing; then the TL Hint can be fused with the memory access. Such an implementation can accept interrupts before the TL Hint rather than between the TL Hint and the memory access. After the fusion occurs at the microarchitecture level, the interrupt handler will not force the fused instructions to be split.

[0084] Impact on Load-Reserved / Store-Conditional (LR / SC) loops: Since TL Hint is encoded as SLTI, it can be used in LR / SC loops without invalidating the forward progress guarantee. The forward progress guarantee means that the LR / SC instruction pair itself needs to be used in pairs to achieve the atomic effect. The LR will set the mark bit. If the mark bit is not cleared when the SC instruction is executed, the SC execution succeeds. If the TL Hint is inserted before the SC, it will not destroy the atomicity of the LR / SC. There is basically no difference between using TL Hint in an LR / SC loop and using it normally. However, since using other loads and stores in an LR / SC loop does invalidate the forward progress guarantee, the reason for using TL Hint in such loops can be to modify the LR or SC.

[0085] This application defines a new hint instruction (TL Hint) to indicate that the data accessed by subsequent memory has critical time locality and is not easily replaced in the cache, ensuring that the delay is reduced in subsequent software access and improving the overall performance. Innovatively propose data time locality hint. Used to mark the time locality of memory access data. Compared with prefetch instructions, time locality hints can be more flexibly inserted into application software to improve the access delay of critical paths.

[0086] According to an embodiment of the present application, a data processing device for implementing the above data processing method is also provided. Figure 4 is a schematic diagram of a data processing device according to an embodiment of the present application, such as Figure 4 As shown, the device includes: a first acquisition module 402 , a determination module 404 , a second acquisition module 406 and an adjustment module 408 .

[0087] Among them, the first acquisition module is used to acquire the first instruction to be executed; the determination module is used to identify the first instruction and determine whether the first instruction is a preset prompt instruction; the second acquisition module is used to acquire the second instruction located after the first instruction when it is determined that the first instruction is the preset prompt instruction, wherein the second instruction is used to access the target data stored in the memory; the adjustment module is used to adjust the cache replacement policy of the target data, wherein the adjusted cache replacement policy is used to ensure that the target data is prohibited from being replaced into the cache within a preset time period.

[0088] Among them, the adjustment module is also used to decode the first instruction to obtain the operation code, register and immediate number contained in the first instruction; match the operation code with the preset operation code corresponding to the preset prompt instruction, match the register with the preset register corresponding to the preset prompt instruction, and match the immediate number with the preset immediate number corresponding to the preset prompt instruction; when the operation code matches the preset operation code successfully, the register matches the preset register successfully, and the immediate number matches the preset immediate number successfully, it is determined that the first instruction is the preset prompt instruction.

[0089] Among them, the adjustment module is also used to determine the target storage area corresponding to the target data based on the second instruction, wherein the target storage area is used to represent the storage area in the processor's cache for storing the target data; when the target storage area belongs to a private cache, the cache replacement strategy is adjusted.

[0090] Among them, the adjustment module is also used to determine whether the second instruction is a cache management operation instruction, wherein the cache management operation instruction is used to move data stored in the processor's cache to the memory; when it is determined that the second instruction is not a cache management operation instruction, the cache replacement strategy is adjusted.

[0091] Among them, the adjustment module is also used to adjust the cache replacement strategy, including at least one of the following: marking the target data according to preset marking information; adjusting the priority of the target data; pre-extracting the target data from the memory and storing the target data in the cache.

[0092] The adjustment module is further used to restore the cache replacement policy of the target data after the cache replacement policy of the target data is adjusted if an exception occurs during the execution of the second instruction.

[0093] The adjustment module is further used to execute an interruption handler when an interruption occurs during the execution of the first instruction and the second instruction after adjusting the cache replacement strategy of the target data; and to re-execute the second instruction when the interruption handler is completed.

[0094] The adjustment module is further used to re-execute the first instruction when the interrupt processing program is executed and the first instruction and the second instruction are merged.

[0095] According to another aspect of the embodiments of the present application, a processor is provided for running a program, wherein the method in each embodiment of the present application is executed when the program is running.

[0096] In the above embodiments of the present application, the processor adopts a reduced instruction set architecture.

[0097] The above-mentioned Reduced Instruction Set Computing (RISC) may be a processor architecture design concept, which is characterized in that the instruction set only contains instructions for performing basic operations, thereby improving the performance and efficiency of the processor by reducing the types and complexity of instructions.

[0098] In an optional embodiment, during the temporal locality prompting process of the processor, the processor may adopt a reduced instruction set architecture. The RISC architecture can reduce the execution time of each instruction by simplifying the instruction set and improving the efficiency of instruction execution, and can increase the running speed of the processor, thereby speeding up the execution speed of the program. The design of the RISC architecture makes it easier for the processor to reuse instructions, that is, the same instruction is executed multiple times in a short period of time. This can improve the processor's utilization of temporal locality, thereby reducing the number of memory accesses for instructions and improving program performance. In addition, the instruction set of the RISC architecture is simpler, and conflicts between instructions are reduced, which can reduce the execution delay of instructions and improve the parallelism and performance of the processor.

[0099] According to another aspect of the embodiments of the present application, a system on chip is also provided, including the processor in each embodiment of the present application.

[0100] Optionally, Figure 5 is a structural block diagram of a computing device according to an embodiment of the present application. Figure 5 As shown, the computing device A may include: one or more (only one is shown in the figure) processors 102 , a memory 104 , and a peripheral interface 106 , wherein the processor 102 , the memory 104 , and the peripheral interface 106 are interconnected via a bus 108 .

[0101] Among them, the memory can be used to store software programs and modules, such as program instructions / modules corresponding to the methods and devices in the embodiments of the present application. The processor executes various functional applications and data processing by running the software programs and modules stored in the memory, that is, implementing the methods in the above embodiments. The memory may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory may further include a memory remotely arranged relative to the processor, and these remote memories may be connected to the terminal A via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0102] The processor may call the information and application programs stored in the memory through the transmission device to execute the steps in each embodiment.

[0103] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of the relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0104] It should be noted that, for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described order of actions, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0105] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on such an understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, a disk, or an optical disk), and includes a number of instructions for the processing unit to execute the method in each embodiment of the present application.

[0106] The embodiment of the present application further provides a computer-readable storage medium. Optionally, in this embodiment, the computer-readable storage medium can be used to store the program code executed by the method provided in the above embodiment.

[0107] Optionally, in this embodiment, the above storage medium may be located in any computing device in the computing device group.

[0108] Optionally, in this embodiment, the computer-readable storage medium is configured to store program codes for executing the following.

[0109] Obtain a first instruction to be executed; identify the first instruction and determine whether the first instruction is a preset prompt instruction; if it is determined that the first instruction is the preset prompt instruction, obtain a second instruction that follows the first instruction, wherein the second instruction is used to access target data stored in a memory; adjust a cache replacement policy for the target data, wherein the adjusted cache replacement policy is used to ensure that the target data is prevented from being replaced or refreshed to a downstream cache within a preset time period.

[0110] Optionally, the first instruction is identified to determine whether the first instruction is a preset prompt instruction, including: decoding the first instruction to obtain the operation code, register and immediate number contained in the first instruction; matching the operation code with the preset operation code corresponding to the preset prompt instruction, matching the register with the preset register corresponding to the preset prompt instruction, and matching the immediate number with the preset immediate number corresponding to the preset prompt instruction; when the operation code successfully matches the preset operation code, the register successfully matches the preset register, and the immediate number successfully matches the preset immediate number, determining that the first instruction is the preset prompt instruction.

[0111] Optionally, the cache replacement policy of the target data is adjusted, including: based on the second instruction, determining the target storage area corresponding to the target data, wherein the target storage area is used to represent the storage area in the processor's cache for storing the target data; when the target storage area belongs to a private cache, adjusting the cache replacement policy.

[0112] Optionally, the cache replacement policy of the target data is adjusted, including: determining whether the second instruction is a cache management operation instruction, wherein the cache management operation instruction is used to move data stored in the processor's cache to the memory; if it is determined that the second instruction is not a cache management operation instruction, adjusting the cache replacement policy.

[0113] Optionally, the cache replacement strategy is adjusted, including at least one of the following: marking the target data according to preset marking information; adjusting the priority of the target data; pre-extracting the target data from the memory and storing the target data in the cache.

[0114] Optionally, after adjusting the cache replacement policy of the target data, the method further includes: restoring the cache replacement policy of the target data when an exception occurs during the execution of the second instruction.

[0115] Optionally, after adjusting the cache replacement policy of the target data, the method further includes: executing an interruption handler when an interruption occurs during the execution of the first instruction and the second instruction; and re-executing the second instruction when the interruption handler is completed.

[0116] Optionally, when the interrupt handling program is executed, the method further includes: when the first instruction and the second instruction are merged, re-executing the first instruction.

[0117] The embodiment of the present application further provides a computer program product. Optionally, in this embodiment, the computer program product may include computer instructions, and the computer instructions implement the method provided by the above embodiment when executed by a processor.

[0118] The above-mentioned computer program product may refer to software instructions that have been written, tested and released, and can be run on a computer or other device. The computer program product may include application programs, operating systems, tool software, etc., which are used to implement specific functions or solve specific problems.

[0119] The embodiments of the present application also provide a computer program product. Optionally, the computer program product may include a non-volatile computer-readable storage medium, which may be used to store computer instructions, and the computer instructions implement the method provided in the embodiments when executed by a processor.

[0120] The above-mentioned non-volatile computer-readable storage medium may refer to a medium for storing data. The non-volatile computer-readable storage medium can keep the data from being lost when the power is off, and can be used to store long-term data, such as operating systems, applications, and user files. The non-volatile storage medium may include hard disk drives, solid-state drives, optical disks, and flash memory storage devices, etc.

[0121] The embodiment of the present application also provides a computer program. Optionally, in this embodiment, when the above computer instructions are executed by a processor, the method provided in the above embodiment is implemented.

[0122] The above-mentioned computer instructions may refer to a collection of instructions used to tell a computer to perform a specific task or operation. Computer instructions may be written by a programmer using a specific programming language and may include algorithms, data structures, logic, and control flows. Computer instructions may be used for a variety of purposes, including application software, operating systems, and the like.

[0123] In the above embodiments of the present application, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant description of other embodiments.

[0124] It should be noted that the preferred implementation scheme involved in the above embodiments of the present application is the same as the scheme provided in the above embodiments, as well as the application scenario and implementation process, but is not limited to the scheme provided in the above embodiments.

[0125] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0126] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0127] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0128] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, in essence, or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, a server or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, disk or optical disk and other media that can store program codes.

[0129] The above is only a preferred implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

[0130] The above is only a preferred implementation of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A data processing method, characterized in that: Applicable to processors, including: Get the first instruction to be executed; Identify the first instruction and determine whether the first instruction is a preset prompt instruction; In the case where it is determined that the first instruction is the preset prompt instruction, obtaining a second instruction located after the first instruction, wherein the second instruction is used to access target data stored in the memory; The cache replacement policy of the target data is adjusted, wherein the adjusted cache replacement policy is used to ensure that the target data is prohibited from being replaced into the cache within a preset time period.

2. The method according to claim 1, characterized in that The identifying the first instruction to determine whether the first instruction is a preset prompt instruction includes: Decoding the first instruction to obtain an operation code, a register, and an immediate value included in the first instruction; Matching the operation code with a preset operation code corresponding to the preset prompt instruction, matching the register with a preset register corresponding to the preset prompt instruction, and matching the immediate value with a preset immediate value corresponding to the preset prompt instruction; When the operation code successfully matches the preset operation code, the register successfully matches the preset register, and the immediate value successfully matches the preset immediate value, it is determined that the first instruction is the preset prompt instruction.

3. The method according to claim 1, characterized in that The adjusting the cache replacement strategy of the target data includes: Based on the second instruction, determining a target storage area corresponding to the target data, wherein the target storage area is used to represent a storage area in the cache of the processor for storing the target data; In the case where the target storage area belongs to a private cache, the cache replacement strategy is adjusted.

4. The method according to claim 1, characterized in that The adjusting the cache replacement strategy of the target data includes: determining whether the second instruction is a cache management operation instruction, wherein the cache management operation instruction is used to move data stored in the cache of the processor to the memory; When it is determined that the second instruction is not the cache management operation instruction, the cache replacement policy is adjusted.

5. The method according to claim 3 or 4, characterized in that: The adjusting of the cache replacement strategy includes at least one of the following: Marking the target data according to preset marking information; Adjusting the priority of the target data; The target data is pre-extracted from the memory and stored in the cache.

6. The method according to claim 1, characterized in that After adjusting the cache replacement strategy of the target data, the method further includes: When an exception occurs during the execution of the second instruction, the cache replacement policy of the target data is restored.

7. The method according to claim 1, characterized in that After adjusting the cache replacement strategy of the target data, the method further includes: In the event of an interruption occurring during the execution of the first instruction and the second instruction, executing an interruption handling program; When the interrupt processing program is executed completely, the second instruction is re-executed.

8. The method according to claim 7, characterized in that When the interrupt processing program is executed, the method further includes: When the first instruction and the second instruction are merged, the first instruction is re-executed.

9. A processor, characterized in that: Used to run a program, wherein the program executes the method according to any one of claims 1 to 8 when running.

10. The processor according to claim 9, characterized in that The processor adopts a reduced instruction set architecture.

11. A system on chip, characterized in that: include: A processor as claimed in claim 9 or 10.

12. A computing device, characterized in that: include: A memory storing an executable program; A processor, configured to run the program, wherein the program executes the method according to any one of claims 1 to 8 when running.

13. A computer-readable storage medium, characterized in that: The computer-readable storage medium comprises a stored executable program, wherein when the executable program is executed by a processor, the method according to any one of claims 1 to 8 is implemented.

14. A computer program product, characterized in that The method comprises computer instructions which, when executed by a processor, implement the method according to any one of claims 1 to 8.

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