Memory controller including walking hammer tracking device

Abstract

The invention relates to a memory controller including a hammer tracking device. A memory controller includes: a command / address generation module; and a row hammer tracking module configured to track a row hammer address based on an activity command and addresses of a target library and a target row indicated by the activity command, the activity command and the address received from the command / address generation module, a plurality of storage devices each including a field corresponding to the library, each of the fields storing a candidate address and an access count value for the candidate address; and at least one search controller configured to sequentially search fields of the plurality of storage devices corresponding to a target library according to a clock when an activity command is input, and search fields of the plurality of storage devices corresponding to different libraries during one clock based on an activity command indicating the different libraries.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2023-0116201, filed on September 1, 2023, which is hereby incorporated by reference in its entirety. Technical Field

[0003] Various embodiments of the present disclosure relate to semiconductor design technology, and more particularly, to a memory system and a memory controller including a hammer tracking device. Background Art

[0004] Recently, in a memory system, in addition to a normal refresh operation, an additional refresh operation may be performed. The normal refresh operation may be an operation for sequentially refreshing a plurality of word lines. An additional refresh operation may be performed on a specific word line that may lose data due to row hammering, which will be referred to as a "target refresh operation" hereinafter. The row hammering phenomenon refers to a phenomenon in which data of memory cells coupled to a specific word line or a neighboring word line disposed adjacent to the specific word line is damaged due to a large number of activations of a specific word line. In order to prevent the row hammering phenomenon, a target refresh operation is performed on a word line disposed adjacent to a word line that is activated more than a predetermined number of times (which will be referred to as a "target word line" hereinafter).

[0005] During a targeted refresh operation, in order to detect an attacking word line and select an address to be refreshed (hereinafter referred to as a "row hammer address"), a memory device or a memory controller needs to detect a word line that has been activated more than a preset number of times. Recently, various methods for detecting a row hammer address by tracking a row address input together with an active command have been studied. Summary of the invention

[0006] Embodiments of the present disclosure relate to a memory controller including a row hammer tracking device capable of efficiently detecting a row hammer address.

[0007] According to one embodiment of the present disclosure, a memory controller includes: a command / address generation module; and a row hammer tracking module, which is configured to track a row hammer address based on an active command and an address of a target bank and a target row indicated by the active command, the active command and the address being received from the command / address generation module, wherein the row hammer tracking module includes: a plurality of storage devices, each of the plurality of storage devices including a field corresponding to a bank, each of the fields storing a candidate address and an access count value for the candidate address; and at least one search controller, which is configured to sequentially search the fields of the plurality of storage devices corresponding to the target bank according to a clock when an active command is input, and to search the fields of the plurality of storage devices corresponding to different banks during one clock based on active commands indicating different banks.

[0008] According to one embodiment of the present disclosure, a row hammer tracking device includes: an overflow counter, which is configured to store a leak count value; a plurality of storage devices, each of which includes a field corresponding to a library, each field in the field storing a candidate address and an access count value for the candidate address; a plurality of search controllers cascaded to each other and corresponding to the plurality of storage devices, which are configured to generate an address hit signal, a count hit signal, and field information by comparing the candidate address and the access count value read from the field corresponding to the library address with the row address and the leak count value, respectively; and an update controller, which is configured to update the leak count value or the access count value of the target field specified by the field information according to the address hit signal and the count hit signal.

[0009] According to an embodiment of the present disclosure, a memory system can implement a row hammer tracking device by using a static random access memory (SRAM) instead of a previously known content addressable memory (CAM) as a storage device, minimizing the area occupied by the row hammer tracking device. In addition, the memory system can detect a row hammer address in a short time by reading data from the storage device in a pipeline manner, thereby efficiently mitigating the row hammer risk. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1A and Figure 1B is a block diagram illustrating a known memory system.

[0011] Figure 2 is a block diagram illustrating a memory system according to one embodiment of the present disclosure.

[0012] Figure 3 is a diagram illustrating a detailed configuration of a memory controller according to one embodiment of the present disclosure.

[0013] Figure 4 FIG. 4 is a diagram illustrating a detailed configuration of a hammer tracking module according to an embodiment of the present disclosure.

[0014] Figure 5 It is a graphic Figure 4 Detailed configuration diagram of the overflow counter.

[0015] Figure 6 is a timing diagram for describing a known first activity interval (tRC) and a known second activity interval (tRRD).

[0016] Figure 7 is a diagram illustrating a detailed configuration of a storage device group according to the first embodiment of the present disclosure.

[0017] FIG. 8A to FIG. 8C describe Figure 7 Read operations on storage device groups.

[0018] 9A to 9D describe Figure 7 Another read operation for the storage device group.

[0019] Fig.10 is a diagram illustrating a detailed configuration of a storage device group according to a second embodiment of the present disclosure.

[0020] Fig.11A and Fig. 11B describe Fig.10 Read operations on storage device groups.

[0021] FIG. 12A to FIG. 12C describe Fig.10 Another read operation for the storage device group.

[0022] Fig.13A and Fig. 13B is a block diagram and a flow chart illustrating the operation of a search controller according to one embodiment of the present disclosure.

[0023] Fig.14 is a flowchart for describing the operation of an update controller according to one embodiment of the present disclosure.

[0024] FIG. 15A to FIG. 15M A hammer tracking method according to an embodiment of the present disclosure is described. DETAILED DESCRIPTION

[0025] Various embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. The present disclosure may have embodiments of different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the present disclosure, similar reference numerals throughout the various figures and embodiments of the present disclosure refer to similar parts.

[0026] It will be understood that when an element is referred to as being "coupled" or "connected" to another element, this may mean that the two are directly coupled, or that the two are electrically connected to each other with another circuit interposed between them. It will be further understood that the terms "comprise, include", "having", etc., when used in this specification, indicate the presence of stated features, numbers, steps, operations, elements, components, and / or combinations thereof, but do not exclude the presence or addition of one or more other features, numbers, steps, operations, elements, components, and / or combinations thereof. In the present disclosure, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form.

[0027] Figure 1A and Figure 1B is a block diagram illustrating the memory system 1 .

[0028] refer to Figure 1A and Figure 1B , a memory system 1 includes a memory controller 2 and a memory module 3 .

[0029] The memory controller 2 may control the overall operation of the memory module 3 according to the request of the host 5. The memory module 3 may include a plurality of memory devices 4. The memory devices 4 may collectively receive commands and addresses from the memory controller 2 and exchange data with the memory controller 2 respectively.

[0030] The memory device 4 may include a plurality of memory cells coupled between a plurality of word lines (hereinafter referred to as "rows") and a plurality of bit lines (hereinafter referred to as "columns"). The memory controller 2 may select a preset number of memory cells by providing a row address for specifying a row of the memory device 4 and a column address for specifying a column of the memory device 4. The rows of the memory devices 4 included in one memory module 3 may be selected by the same row address.

[0031] refer to Figure 1A , each memory device 4 in the memory device 4 may include a counting circuit 4A, which is used to count the number of activations (or the number of accesses, hereinafter referred to as the "number of accesses") of each row. The counting circuit 4A of each memory device 4 in the memory device 4 may have substantially the same configuration, and may be implemented using a plurality of row counters corresponding to a plurality of rows, respectively. Each of the row counters may generate a count value by counting the number of inputs of the row address specifying the corresponding row. The memory controller 2 may select a row address having a maximum value among the count values ​​provided from the memory device 4 as a row hammer address. The memory controller 2 may provide a refresh command (e.g., a refresh management command) together with the row hammer address to the memory device 4, so that the memory device 4 may perform a target refresh operation on an adjacent row of the row corresponding to the row hammer address.

[0032] like Figure 1A As shown, when the count circuit 4A is placed in each of the memory devices 4, since the count circuit 4A performs the same count operation, the unnecessary area of ​​the memory device (or module) increases.

[0033] refer to Figure 1B, the memory controller 2 may include a counting circuit 2A for counting the number of accesses to each row. The counting circuit 2A may be implemented using a plurality of row counters corresponding to a plurality of rows, respectively. Each row counter in the row counters may generate a count value by counting the number of inputs of the row address specifying the corresponding row. The memory controller 2 may calculate a row hammer address based on the count value of the counting circuit 2A. For example, the memory controller 2 may select a row address having a maximum value among the count values ​​as the row hammer address. That is, the row hammer address may indicate a row address among the rows of the memory device 4 that is frequently accessed or called by the memory controller 2. The memory controller 2 may provide a refresh command (e.g., a refresh management command) together with the row hammer address to the memory device 4, so that the memory device 4 may perform a target refresh operation on an adjacent row of the row corresponding to the row hammer address.

[0034] like Figure 1B As shown, when the counting circuit 2A is placed on the memory controller 2, the counting capability required by the memory controller 2 is (number of rows)*(number of bits of each row counter). For example, if 512 rows are deployed and each row requires a 16-bit row counter to count, a counting capability of 8192 bits is required, otherwise, the performance of the memory controller 2 may be degraded.

[0035] In order to solve this problem, without counting the number of accesses to all rows, a method of storing candidate addresses and the number of inputs of the candidate addresses in entries of a content addressable memory (CAM) and using the data stored in the entries of the CAM to track the row hammer addresses has been proposed. However, as the chip area decreases due to process refinement, the minimum number of activations that can cause the row hammer phenomenon (hereinafter referred to as a "row hammer threshold") also decreases, and as a result, the number of entries in the CAM to be tracked increases, making it difficult to actually perform row hammer tracking using the CAM.

[0036] Therefore, an embodiment of the present disclosure provides a method for preventing performance degradation of a memory controller and reducing the risk of row hammer by implementing a row hammer tracking device using a static random access memory (SRAM) instead of a previously known CAM.

[0037] Figure 2 is a block diagram illustrating a memory system 10 according to one embodiment of the present disclosure.

[0038] refer to Figure 2, the memory system 10 may store data or read stored data in response to a request provided from the host 20. The memory system 10 may be used as a main storage device or an auxiliary storage device of the host 20. The memory system 10 may be used as a device for storing data under the control of the host 20, such as a mobile phone, a smart phone, an MP3 player, a laptop computer, a desktop computer, a game console, a TV, a tablet PC, or an in-vehicle infotainment system.

[0039] The memory system 10 may include a memory controller 100 and at least one memory module 200 .

[0040] The memory controller 100 may control the overall operation of the memory module 200 by generating a command / address signal C / A according to a request REQ of the host 20 and providing the command / address signal C / A to the memory module 200. The memory controller 100 may provide a clock together with the command / address signal C / A to the memory module 200. For example, the memory controller 100 may provide the memory module 200 with data provided from the host 20 during a write operation. The memory controller 100 may provide the host 20 with data read from the memory module 200 during a read operation.

[0041] The memory module 200 may operate as a buffer memory, a working memory, and a main memory of the host 20 and the memory controller 100. The memory module 200 may operate according to a command / address signal C / A issued by the memory controller 100. The memory module 200 may store data transmitted from the memory controller 100 or transmit data to the memory controller 100. In some embodiments, the memory module 200 may further include a module controller or a register clock driver, and a data buffer. In other embodiments, the memory controller 100 may include a module controller or a register clock driver, and a configuration corresponding to the data buffer.

[0042] The memory module 200 may include one or more memory devices 200A. The memory device 200A may include a plurality of memory cells coupled between a plurality of rows and a plurality of columns. The memory controller 100 may select a preset number of memory cells by providing a row address for specifying a row of the memory device 200A and a column address for specifying a column of the memory device 200A.

[0043] According to the command / address signal C / A and / or data provided from the memory controller 100, each memory device 200A in the memory device 200A can perform an active operation, a precharge operation, a refresh operation, a read operation or a write operation on the memory cell. Each memory device 200A in the memory device 200A can also be referred to as a memory chip. The memory devices 200A included in the same memory module 200 can have different data input / output paths when receiving the command / address signal C / A together. Depending on the embodiment, each memory device 200A in the memory device 200A can be a DRAM (dynamic random access memory), such as DDR SDRAM (double data rate synchronous dynamic random access memory), LPDDR (low power double data rate) SDRAM, GDDR (graphic double data rate) SDRAM, RDRAM (Rambus dynamic random access memory), etc. According to one embodiment, the memory device 200A can be configured with different types of memory. In the following, it is described that the memory device 200A is a DRAM device supporting a double data rate (DDR) interface.

[0044] Figure 3 is a diagram illustrating a detailed configuration of a memory controller 100 according to one embodiment of the present disclosure.

[0045] refer to Figure 3 , the memory controller 100 may include a data transmission module 110 , a command / address generation module 130 , and a hammer tracking module 150 .

[0046] The data transfer module 110 may transfer data DQ corresponding to a request REQ from the host 20 to the memory module 200 during a write operation, or transfer data DQ read from the memory module 200 to the host 20 during a read operation.

[0047] The command / address generation module 130 may generate a command / address signal C / A corresponding to the request REQ from the host 20 and provide the command / address signal C / A to the memory module 200 .

[0048] The command / address generation module 130 may provide the bank address BKADD, the row address RADD, and the column address for respectively specifying the bank, row, and column together with the read command for the read operation as the command / address signal C / A. The command / address generation module 130 may provide the bank address BKADD, the row address RADD, and the column address for respectively specifying the bank, row, and column together with the write command for the write operation as the command / address signal C / A. For the refresh time (tREF) interval defined in the specification as the time when all rows are normally refreshed, the command / address generation module 130 may provide a preset number of normal refresh commands as the command / address signal C / A.

[0049] The command / address generation module 130 may provide a bank address BKADD and a row address RADD for respectively specifying a bank and a row to be active together with an active command ACT for an active operation as a command / address signal C / A. In one embodiment of the present disclosure, when generating the active command ACT, the command / address generation module 130 may provide the active command ACT, the bank address BKADD, and the row address RADD to the row hammer tracking module 150. When the row hammer address RH_ADD and the alarm signal ALERT_S are transmitted from the row hammer tracking module 150, the command / address generation module 130 may provide the row hammer address RH_ADD for specifying a bank and a row to be refreshed together with the refresh management command as the command / address signal C / A. In the following embodiment, it will be described that the row hammer address RH_ADD provided from the row hammer tracking module 150 includes information on both the bank address and the row address.

[0050] The row hammer tracking module 150 may collect information about the bank and row attacked by the row hammer in the memory device 200A based on the active command ACT, the bank address BKADD, and the row address RADD. Based on the collected information (i.e., the bank address BKADD and the row address RADD), the row hammer tracking module 150 may generate an alarm signal ALERT_S and a row hammer address RH_ADD, and transmit the alarm signal ALERT_S and the row hammer address RH_ADD to the command / address generation module 130.

[0051] Figure 4 FIG. 1 is a diagram illustrating a detailed configuration of the hammer tracking module 150 according to one embodiment of the present disclosure. Figure 5 It is a graphic Figure 4 Detailed configuration diagram of the overflow counter 410.

[0052] refer to Figure 4, the hammer tracking module 150 may include an overflow counter 410, a storage device group 420 including a plurality of storage devices 421 to 424, a plurality of search controllers 431 to 434, an update controller 440, and a reset circuit 450. The plurality of storage devices 421 to 424 and the plurality of search controllers 431 to 434 may correspond one to one. Hereinafter, as an example, a case in which the first storage device 421 to the fourth storage device 424 and the first search controller 431 to the fourth search controller 434 are arranged will be described.

[0053] Overflow counter 410 may include a plurality of fields corresponding to a plurality of banks respectively. In each field, a leak count value SP_CNT of a corresponding bank may be stored. Figure 5 As shown, when the first to fourth banks BK0 to BK3 are arranged in the memory device, the overflow counter 410 may include first to fourth fields storing leak count values ​​1, 4, 3, and 6 of the first to fourth banks BK0 to BK3, respectively.

[0054] The first storage device 421 to the fourth storage device 424 may include a plurality of fields corresponding to a plurality of libraries, respectively. For example, the first storage device 421 to the fourth storage device 424 may include a first field F1 corresponding to the first library BK0. Similarly, the first storage device 421 to the fourth storage device 424 may include a second field corresponding to the second library BK1, a third field corresponding to the third library BK2, and a fourth field corresponding to the fourth library BK3. In each field, a candidate address ( Figure 7 and Fig.10 A_ADD in ) and the access count value for the candidate address ( Figure 7 and Fig.10 A candidate address and its access count value may constitute an entry, and a field may include multiple entries. Fields of the same level (e.g., k, where k is a positive integer) of the first storage device 421 to the fourth storage device 424 may store candidate addresses A_ADD and access count values ​​A_CNT for the same bank. Each of the first storage device 421 to the fourth storage device 424 may be configured as a static random access memory (SRAM). Figures 7 to 11B The detailed configurations of the first to fourth storage devices 421 to 424 are described in detail.

[0055] The first to fourth search controllers 431 to 434 may be cascaded with each other. That is, each of the first to fourth search controllers 431 to 434 may have an input terminal coupled to an output terminal of a search controller in a previous stage, and an output terminal coupled to an input terminal of a search controller in a next stage. The output of the fourth search controller 434 disposed at the last stage among the first to fourth search controllers 431 to 434 may be provided to the update controller 440. The first to fourth search controllers 431 to 434 may sequentially read the candidate addresses and access count values ​​stored in the fields of the same level according to the clock CK. In one embodiment, the first to fourth search controllers 431 to 434 may be operated in a pipeline manner, wherein the candidate addresses and access count values ​​stored in the fields of different levels are read simultaneously.

[0056] The first to fourth search controllers 431 to 434 may receive the bank address BKADD and the row address RADD and the active command ACT from the command / address generation module 130. The first to fourth search controllers 431 to 434 may read the candidate address and the access count value from the field selected according to the bank address BKADD among the fields of the first to fourth storage devices 421 to 424, and read the leakage count value SP_CNT from the field selected according to the bank address BKADD among the fields of the overflow counter 410. The first to fourth search controllers 431 to 434 may compare the read candidate address with the row address RADD, and compare the read access count value with the read leakage count value SP_CNT to generate an address hit signal R_HIT, a count hit signal C_HIT, and field information S_LINE and S_PTR. Each of the first to fourth search controllers 431 to 434 may transmit an active command ACT, a bank address BKADD, a row address RADD, an address hit signal R_HIT, a count hit signal C_HIT, and field information S_LINE and S_PTR to a search controller in a next stage. In particular, the address hit signal R_HIT, the count hit signal C_HIT, and the field information S_LINE and S_PTR generated from the fourth search controller 434 may be provided to the update controller 440.

[0057] For example, the first to fourth search controllers 431 to 434 may compare the read candidate addresses with the row address RADD. When one of the read candidate addresses matches the row address RADD, the first to fourth search controllers 431 to 434 may activate the address hit signal R_HIT. When all the read candidate addresses do not match the row address RADD, the first to fourth search controllers 431 to 434 may compare the read access count value with the read drain count value SP_CNT. When one of the read access count values ​​matches the read drain count value SP_CNT, the first to fourth search controllers 431 to 434 may activate the count hit signal C_HIT. When the address hit signal R_HIT or the count hit signal C_HIT is activated, the first to fourth search controllers 431 to 434 may generate field information S_LINE and S_PTR for a field having a hit candidate address or a hit access count value (hereinafter referred to as a "target field"). The field information S_LINE and S_PTR may include: a position pointer S_PTR for specifying a level (or position) of a storage device including a target field and a hit entry of the target field, and shift line data S_LINE in which field data of the target field is stored. Fig.13A and Fig. 13B Detailed configurations and operations of the first to fourth search controllers 431 to 434 are described in detail in FIG.

[0058] The update controller 440 may receive an active command ACT, a bank address BKADD, a row address RADD, an address hit signal R_HIT, a count hit signal C_HIT, and field information S_LINE and S_PTR from the fourth search controller 434. According to one embodiment, the update controller 440 may receive a bank address BKADD and a row address RADD and an active command ACT from the command / address generation module 130.

[0059] When the address hit signal R_HIT is activated, the update controller 440 may increase the access count value of the hit entry of the target field based on the field information S_LINE and S_PTR, or generate a row hammer address RH_ADD and an alarm signal ALERT_S. For example, the update controller 440 may compare the access count value of the hit entry in the shift line data S_LINE with a preset row hammer threshold. If the access count value is less than the row hammer threshold, the update controller 440 may increase the access count value of the hit entry of the target field according to the position pointer S_PTR. If the access count value is greater than or equal to the row hammer threshold, the update controller 440 may generate a row hammer address RH_ADD using the candidate address and the library address of the shift line data S_LINE, and provide the row hammer address RH_ADD together with the alarm signal ALERT_S to the command / address generation module 130. In addition, the update controller 440 may initialize the access count value of the hit entry of the target field.

[0060] When the address hit signal R_HIT is deactivated and the count hit signal C_HIT is activated, the update controller 440 may replace the candidate address of the hit entry of the target field with the row address RADD and increase the access count value of the hit entry. When both the address hit signal R_HIT and the count hit signal C_HIT are deactivated, the update controller 440 may increase the leak count value SP_CNT of the field selected according to the bank address BKADD among the fields of the overflow counter 410.

[0061] In one embodiment, the update controller 440 may initialize all fields of the first to fourth storage devices 421 to 424 in response to the reset signal RST. The update controller 440 may initialize all leak count values ​​of the overflow counter 410 in response to the reset signal RST. Fig.14 The detailed operation of the update controller 440 is described in detail.

[0062] The reset circuit 450 may generate the reset signal RST at intervals of the refresh time (tREF) defined in the specification as the time when all rows are normally refreshed. For example, when the refresh time (tREF) is set to 64ms, the reset circuit 450 may activate the reset signal RST every 64ms.

[0063] Hereinafter, a configuration of a storage device according to an embodiment of the present disclosure will be described with reference to the accompanying drawings.

[0064] Figure 6 is a timing diagram for describing a known first active interval tRC and a known second active interval tRRD.

[0065] refer to Figure 6, the minimum interval between consecutive active commands for the same bank is defined as a first active interval (RAS cycle time) tRC, and the minimum interval between consecutive active commands for different banks is defined as a second active interval tRRD. For example, the first active interval tRC may be set to tens of ns, and the second active interval tRRD may be set to several ns.

[0066] In the following embodiment, the first activity interval tRC and the second activity interval tRRD will be described by converting the interval from time to clock. For this purpose, the values ​​obtained by dividing the first activity interval and the second activity interval defined based on the actual time by the unit clock tCK and performing the floor rounding function "FLOOR" on the divided result will be described as the first activity interval tRC and the second activity interval tRRD. That is, Figure 6 As shown, after the second active interval tRRD of 2CK from the input of the active command ACT for the first bank BK0, the active command ACT for the second bank BK1 may be input. In addition, after the first active interval tRC of 8CK from the input of the active command ACT for the first bank BK0, the active command ACT for the first bank BK0 may be input again.

[0067] Figure 7 is a diagram illustrating a detailed configuration of the storage device group 420 according to the first embodiment of the present disclosure.

[0068] refer to Figure 7 , the number of storage devices in the storage device group 420 can be set according to the first active interval tRC. For example, when the first active interval tRC is set to 8CK, eight storage devices can be provided. In this case, the depth of each storage device can be set according to the number of banks. For example, when four banks BK0 to BK3 are set in each memory device, the depth of each storage device can be set to 4, and each storage device can include four fields.

[0069] As described above, one field may include multiple entries, and each entry may store a candidate address A_ADD and its access count value A_CNT. The number of entries included in one field may be set to a value obtained by dividing the number of candidate addresses to be tracked by the number of storage devices. For example, if the number of candidate addresses to be tracked is 5000 and the number of storage devices is 8, the number of entries included in one field may be set to 5000 / 8=625.

[0070] FIG. 8A to FIG. 8C describe Figure 7 The read operation of the storage device group 420. FIG. 8A to FIG. 8CIn the example, the first bank BK0 to the fourth bank BK3 are arranged, the first active interval tRC is set to 8CK, and the second active interval tRRD is set to 1CK. In this case, the first storage device 810 to the eighth storage device 880 are arranged, and each storage device may be composed of the first field to the fourth field. Although there is no FIG. 8A to FIG. 8C Although not shown in the figure, first to eighth search controllers corresponding to the first to eighth storage devices 810 to 880 may be respectively provided.

[0071] refer to Fig. 8A (A), an active command ACT for the first bank BK0 is input during the first clock cycle 1CK. The first search controller may read field data including a candidate address and an access count value stored in a first field of the first memory device 810.

[0072] refer to Fig. 8A (B), an active command ACT for the second bank BK1 is input at a second active interval tRRD during the second clock cycle 2CK. The first search controller may read field data stored in the second field of the first storage device 810, and the second search controller may read field data stored in the first field of the second storage device 820.

[0073] refer to Fig. 8A (C), an active command ACT for the third bank BK2 is input at a second active interval tRRD during a third clock cycle 3CK. The first search controller may read field data stored in a third field of the first storage device 810, the second search controller may read field data stored in a second field of the second storage device 820, and the third search controller may read field data stored in a first field of the third storage device 830.

[0074] refer to Fig. 8A (D), an active command ACT for the fourth bank BK3 is input at the second active interval tRRD during the fourth clock cycle 4CK. The first search controller may read field data stored in the fourth field of the first storage device 810, the second search controller may read field data stored in the third field of the second storage device 820, the third search controller may read field data stored in the second field of the third storage device 830, and the fourth search controller may read field data stored in the first field of the fourth storage device 840. That is, the search controllers may read the field data of the storage devices 810 to 880 in a pipeline manner.

[0075] refer to Figure 8B(E), (F), (G) and (H), during the fifth clock cycle 5CK to the eighth clock cycle 8CK, the first search controller to the eighth search controller can read the field data of the first storage device 810 to the eighth storage device 880 in the above-mentioned pipeline manner.

[0076] refer to Figure 8C (I), after the first active interval tRC of 8CK, all fields for the first bank BK0 have been read, so even if an active command ACT is input to the first bank BK0, the next read operation can be performed normally. Figure 8C (I), (J) and (K), the first to eighth search controllers can read all field data of the first to eighth storage devices 810 to 880 in the above-mentioned pipeline manner during the ninth clock cycle 9CK to the eleventh clock cycle 11CK.

[0077] 9A to 9D describe Figure 7 Another read operation of the storage device group 420. 9A to 9D In the example, the first bank BK0 to the fourth bank BK3 are arranged, the first active interval tRC is set to 8CK, and the second active interval tRRD is set to 2CK. In this case, the first storage device 910 to the eighth storage device 980 are arranged, and each storage device may be composed of the first field to the fourth field. Although there is no 9A to 9D Although not shown in the figure, first to eighth search controllers corresponding to the first to eighth storage devices 910 to 980 may be respectively provided.

[0078] refer to Fig. 9A (A), an active command ACT for the first bank BK0 is input during the first clock cycle 1CK. The first search controller may read field data stored in the first field of the first storage device 910. Fig. 9A (B), the second search controller may read the field data stored in the first field of the second storage device 920 during the second clock cycle 2CK.

[0079] refer to Fig. 9A (C), an active command ACT for the second bank BK1 is input at a second active interval tRRD during the third clock cycle 3CK. The first search controller may read field data stored in the second field of the first storage device 910, and the third search controller may read field data stored in the first field of the third storage device 930. Fig. 9A(D), during the fourth clock cycle 4CK, the second search controller may read the field data stored in the second field of the second storage device 920, and the fourth search controller may read the field data stored in the first field of the fourth storage device 940.

[0080] refer to Fig. 9B (E), an active command ACT for the third bank BK2 is input at the second active interval tRRD during the fifth clock cycle 5CK. The first search controller may read field data stored in the third field of the first storage device 910, the third search controller may read field data stored in the second field of the third storage device 930, and the fifth search controller may read field data stored in the first field of the fifth storage device 950. Fig. 9B (F), during the sixth clock cycle 6CK, the second search controller can read the field data stored in the third field of the second storage device 920, the fourth search controller can read the field data stored in the second field of the fourth storage device 940, and the sixth search controller can read the field data stored in the first field of the sixth storage device 960.

[0081] refer to Fig. 9B (G), an active command ACT for the fourth bank BK3 is input at the second active interval tRRD during the seventh clock cycle 7CK. The first search controller may read field data stored in the fourth field of the first storage device 910, the third search controller may read field data stored in the third field of the third storage device 930, the fifth search controller may read field data stored in the second field of the fifth storage device 950, and the seventh search controller may read field data stored in the first field of the seventh storage device 970. Reference Fig. 9B (H), during the eighth clock cycle 8CK, the second search controller reads the field data stored in the fourth field of the second storage device 920, the fourth search controller reads the field data stored in the third field of the fourth storage device 940, the sixth search controller reads the field data stored in the second field of the sixth storage device 960, and the eighth search controller reads the field data stored in the first field of the eighth storage device 980. That is, the search controllers can read the field data of the storage devices 910 to 980 in a pipeline manner.

[0082] refer to Fig. 9C (I), after the first active interval tRC of 8CK, all fields for the first bank BK0 have been read. Therefore, even if the active command ACT is input to the first bank BK0, the next read operation can be performed normally. Fig. 9C and Fig.9D (I), (J), (K), (L), (M) and (N), the first search controller to the eighth search controller can read all field data of the first storage device 910 to the eighth storage device 980 in the above-mentioned pipeline manner during the ninth clock cycle 9CK to the fourteenth clock cycle 14CK.

[0083] like 8A to 9D As shown, the search controller of the first embodiment can read the candidate address and access count value stored in the kth field of the xth storage device, and simultaneously read the candidate address and access count value stored in the mth field of the (x+y)th storage device, where k is a positive integer, x is a positive integer, and m is a positive integer different from k. At this time, y can be set based on the second activity interval tRRD. For reference, in 8A to 9D In the example described in , if it is determined that one of the read candidate addresses matches the row address RADD, the subsequent search controller can stop further read operations for the same bank.

[0084] exist 8A to 9D In the embodiment described in, as an example, a case has been described in which the activity command ACT is sequentially input to the first bank BK0 to the fourth bank BK3, but the embodiment is not limited thereto. The activity command ACT may be input regardless of the order of the banks. For example, the activity command ACT may be first input to the second bank BK1, and the activity command ACT may be input to the fourth bank BK3 after the second activity interval tRRD.

[0085] Fig.10 is a diagram illustrating a detailed configuration of a storage device group 420 according to the second embodiment of the present disclosure.

[0086] refer to Fig.10 , the number of storage devices in the storage device group 420 can be set according to the ratio of the first active interval tRC to the second active interval tRRD. For example, when the first active interval tRC is set to 8CK and the second active interval tRRD is set to 2CK, four storage devices can be provided. In this case, the depth of each storage device can be set according to the product of the number of libraries and the second active interval tRRD. For example, when four libraries BK0 to BK3 are arranged in each memory device, the depth of each storage device is set to 4*2=8, that is, each storage device can include eight fields, that is, two fields for each library.

[0087] Fig.11A and Fig. 11B describe Fig.10 The storage device reads the data. Fig.11A and Fig. 11B, the first bank BK0 to the fourth bank BK3 are arranged, the first active interval tRC is set to 8CK, and the second active interval tRRD is set to 2CK. In this case, the first storage device 1110 to the fourth storage device 1140 are arranged, and each storage device can be configured by the first field to the eighth field. Although not shown in the drawings, the first search controller to the fourth search controller corresponding to the first storage device 1110 to the fourth storage device 1140 can be respectively set.

[0088] refer to Fig.11A (A), an active command ACT for the first bank BK0 is input during the first clock cycle 1CK. The first search controller may read field data stored in the first field of the first storage device 1110. Fig.11A (B), the first search controller may read the field data stored in the second field of the first storage device 1110 during the second clock cycle 2CK.

[0089] refer to Fig.11A (C), an active command ACT for the second bank BK1 is input at a second active interval tRRD during the third clock cycle 3CK. The first search controller may read field data stored in the third field of the first storage device 1110, and the second search controller may read field data stored in the first field of the second storage device 1120. Fig.11A (D), during the fourth clock cycle 4CK, the first search controller may read field data stored in the fourth field of the first storage device 1110, and the second search controller may read field data stored in the second field of the second storage device 1120.

[0090] refer to Fig.11A (E), an active command ACT for the third bank BK2 is input at the second active interval tRRD during the fifth clock cycle 5CK. The first search controller may read field data stored in the fifth field of the first storage device 1110, the second search controller may read field data stored in the third field of the second storage device 1120, and the third search controller may read field data stored in the first field of the third storage device 1130. Reference Fig.11A (F), during the sixth clock cycle 6CK, the first search controller can read the field data stored in the sixth field of the first storage device 1110, the second search controller can read the field data stored in the fourth field of the second storage device 1120, and the third search controller can read the field data stored in the second field of the third storage device 1130.

[0091] refer to Fig. 11B(G), an active command ACT for the fourth bank BK3 is input at the second active interval tRRD during the seventh clock cycle 7CK. The first search controller may read field data stored in the seventh field of the first storage device 1110, the second search controller may read field data stored in the fifth field of the second storage device 1120, the third search controller may read field data stored in the third field of the third storage device 1130, and the fourth search controller may read field data stored in the first field of the fourth storage device 1140. Reference Fig. 11B (H), during the eighth clock cycle 8CK, the first search controller reads the field data stored in the eighth field of the first storage device 1110, the second search controller reads the field data stored in the sixth field of the second storage device 1120, the third search controller reads the field data stored in the fourth field of the third storage device 1130, and the fourth search controller reads the field data stored in the second field of the fourth storage device 1140. That is, the search controllers may read the field data of the storage devices 1110 to 1140 in a pipeline manner.

[0092] refer to Fig. 11B (I), after the first active interval tRC of 8CK, all fields for the first bank BK0 have been read. Therefore, even if the active command ACT is input to the first bank BK0, the next read operation can be performed normally. Fig. 11B (I), (J) and (K), the first to fourth search controllers can read all field data of the first to fourth storage devices 1110 to 1140 in the above-mentioned pipeline manner during the ninth clock cycle 9CK to the fourteenth clock cycle 14CK.

[0093] FIG. 12A to FIG. 12C describe Fig.10 Another read operation of storage device group 420. FIG. 12A to FIG. 12C The following figure shows the situation: When connecting with 11A and Fig. 11B Under the same conditions, the active command ACT is input regardless of the order of the first bank BK0 to the fourth bank BK3.

[0094] refer to Fig. 12A (A), an active command ACT for the third bank BK2 is input during the first clock cycle 1CK. The first search controller may read field data stored in the fifth field of the first storage device 1210. Fig. 12A (B), during the second clock cycle 2CK, the first search controller may read the field data stored in the sixth field of the first storage device 1210. Fig. 12A(C), since the second activity interval tRRD has passed but the additional activity command ACT has not been input, the second search controller may read the field data stored in the fifth field of the second storage device 1220 during the third clock cycle 3CK.

[0095] refer to Fig. 12A (D), an active command ACT for the first bank BK0 is input during the fourth clock cycle 4CK. The first search controller may read field data stored in the first field of the first storage device 1210, and the second search controller may read field data stored in the sixth field of the second storage device 1220. Fig. 12A (E), during the fifth clock cycle 5CK, the first search controller may read the field data stored in the second field of the first storage device 1210, and the third search controller may read the field data stored in the fifth field of the third storage device 1230. Fig. 12A (F), during the sixth clock cycle 6CK, the second search controller may read the field data stored in the first field of the second storage device 1220, and the third search controller may read the field data stored in the sixth field of the third storage device 1230. Fig. 12B (G), the second search controller may read field data stored in the second field of the second storage device 1220 , and the fourth search controller may read field data stored in the fifth field of the fourth storage device 1240 .

[0096] refer to Fig. 12B (H), an active command ACT for the second bank BK1 is input during the eighth clock cycle 8CK. The first search controller may read field data stored in the third field of the first storage device 1210, the third search controller may read field data stored in the first field of the third storage device 1230, and the fourth search controller may read field data stored in the sixth field of the fourth storage device 1240. Fig. 12B (I), during the ninth clock cycle 9CK, the first search controller may read the field data stored in the fourth field of the first storage device 1210, and the third search controller may read the field data stored in the second field of the third storage device 1230.

[0097] refer to Fig. 12B(J), an active command ACT for the fourth bank BK3 is input during the tenth clock cycle 10CK. The first search controller may read field data stored in the seventh field of the first storage device 1210, the second search controller may read field data stored in the third field of the second storage device 1220, and the fourth search controller may read field data stored in the first field of the fourth storage device 1240. In this manner, referring to Fig. 12B and Fig. 12C (K), (L), (M), (N), (O) and (P), the first search controller to the fourth search controller can read all field data of the first storage device 1210 to the fourth storage device 1210 to 1240 in the above-mentioned pipeline manner during the eleventh clock cycle 11CK to the seventeenth clock cycle 17CK.

[0098] like FIG. 11A to FIG. 12C As shown, the search controller of the second embodiment can read the candidate address and access count value stored in the kth field of the xth storage device, and at the same time read the candidate address and access count value stored in the (ky)th field of the zth storage device, where k is a positive integer, x is a positive integer, and z is a positive integer different from x. At this time, y can be set based on the second activity interval tRRD and the order of the library into which the activity command is input. For reference, in FIG. 11A to FIG. 12C In the example described in , if it is determined that one of the read candidate addresses matches the row address RADD, the subsequent search controller can stop further read operations for the same bank.

[0099] In the specification of the memory device, the time window to which four active commands can be applied is defined as the third active interval (four active windows) tFAW. In one embodiment, Figure 3 The row hammer tracking module 150 may arrange a buffer for storing four consecutive active commands in front of the storage device group 420. The storage device group 420 may receive the output of the buffer. In this case, the number of storage devices in the storage device group 420 may be set according to a number obtained by multiplying the ratio of the first active interval tRC to the third active interval tFAW by a specific number (e.g., 4). For example, when the first active interval tRC is set to 8CK and the third active interval tFAW is set to 8CK, (8 / 8)*4=4 storage devices may be provided. In addition, the depth of each storage device may be set according to a value obtained by dividing the product of the third active interval tFAW and the number of libraries by a specific number (e.g., 4). For example, when four libraries BK0 to BK3 are arranged for each memory device, the depth of each storage device is set to (4*8) / 4=8, and each storage device may include eight fields, i.e., two fields for each library.

[0100] Fig.13A and Fig. 13B 2 are a block diagram and a flow chart respectively illustrating the operation of a search controller according to one embodiment of the present disclosure.

[0101] refer to Fig.13A , showing Figure 4 Input / output signals of the search controller 1300 among the first to fourth search controllers 431 to 434 are shown in FIG.

[0102] The search controller 1300 may read the candidate address A_ADD and the access count value A_CNT from the field of the storage device according to the bank address BKADD, and read the leak count value SP_CNT from the field of the overflow counter 410. The search controller 1300 may compare the read candidate address A_ADD and the read access count value A_CNT with the row address RADD and the read leak count value SP_CNT, respectively, to generate an address hit signal R_HIT, a count hit signal C_HIT, and field information S_LINE and S_PTR. The search controller 1300 may transmit an active command ACT, a bank address BKADD, a row address RADD, an address hit signal R_HIT, a count hit signal C_HIT, and field information S_LINE and S_PTR to the next search controller.

[0103] For reference, among the search controllers connected in cascade, the search controller disposed at the first stage may receive a bank address BKADD and a row address RADD and an active command ACT from the command / address generation module 130. The search controller disposed at the first stage may receive: an address hit signal R_HIT, a count hit signal C_HIT, and field information S_LINE and S_PTR, which are set to an initial value (e.g., 0).

[0104] refer to Fig. 13B , illustrating the operation of the search controller 1300.

[0105] The bank address BKADD and the row address RADD are input together with the active command ACT (at S110 ).

[0106] When the address hit signal R_HIT transmitted from the previous search controller has been activated ("Yes" in S120), the search controller 1300 may transmit the signal received from the previous search controller as is to the next search controller (at S180). On the other hand, when the address hit signal R_HIT is deactivated ("No" in S120), the search controller 1300 may select one of the fields of the storage device and one of the fields of the overflow counter 410 according to the library address BKADD. Therefore, the candidate address A_ADD and the access count value A_CNT may be read from the storage device, and the leak count value SP_CNT may be read from the overflow counter 410 (at S130).

[0107] The search controller 1300 may compare the row address RADD with the candidate address A_ADD (at S140). When one of the candidate addresses A_ADD matches the row address RADD ("Yes" of S140), the search controller 1300 may activate the address hit signal R_HIT and generate (or update) field information S_LINE and S_PTR for the field (i.e., the target field) of the storage device (at S150). In this case, the field information S_LINE and S_PTR may include: a position pointer S_PTR for specifying the level of the storage device including the target field and the hit entry of the target field, and shift line data S_LINE in which the field data of the target field is stored. Thereafter, the search controller 1300 may transmit the address hit signal R_HIT, the count hit signal C_HIT, and the field information S_LINE and S_PTR together with the active command ACT, the bank address BKADD, and the row address RADD to the next search controller (at S180).

[0108] When all candidate addresses A_ADD do not match the row address RADD ("No" in S140), the search controller 1300 may compare the drain count value SP_CNT with the access count value A_CNT (at S160). When one of the access count values ​​A_CNT matches the drain count value SP_CNT ("Yes" in S160), the search controller 1300 may activate the count hit signal C_HIT and generate (or update) the field information S_LINE and S_PTR of the target field (at S170). Thereafter, the search controller 1300 may transmit the address hit signal R_HIT, the count hit signal C_HIT, and the field information S_LINE and S_PTR together with the active command ACT, the bank address BKADD, and the row address RADD to the next search controller (at S180).

[0109] In the configuration of the storage device arranged as described in the second embodiment, Fig. 13BThe operations described in may be repeatedly performed a number of times corresponding to the second activity interval tRRD.

[0110] Fig.14 is a flowchart for describing the operation of the update controller 440 according to one embodiment of the present disclosure.

[0111] refer to Fig.14 , when the reset signal RST is activated ("Yes" in S210), the update controller 440 may initialize all field data of the storage devices 421 to 424 and the leak count value of the overflow counter 410 (at S220). For example, since the reset signal RST is activated at a constant period, the storage devices 421 to 424 and the overflow counter 410 may be initialized at a constant period. For reference, in order to initialize all field data of the storage devices 421 to 424, a clock cycle corresponding to the number of fields of each storage device may be required. For example, if each storage device has four fields, at least four clock cycles are required.

[0112] When the bank address BKADD and the row address RADD are input together with the active command ACT ( S230 ), the update controller 440 may receive the active command ACT, the bank address BKADD, the row address RADD, the address hit signal R_HIT, the count hit signal C_HIT, and the field information S_LINE and S_PTR from the fourth search controller 434 .

[0113] When the address hit signal R_HIT is activated ("Yes" in S240), the update controller 440 may compare the access count value A_CNT of the shift line data S_LINE with the preset row hammer threshold value RH_T (at S250). In this case, the hit entry is selected by the position pointer S_PTR, and the access count value A_CNT of the hit entry may be compared with the row hammer threshold value RH_T. If the access count value A_CNT of the hit entry is less than the row hammer threshold value RH_T ("No" in S250), the update controller 440 may increase the access count value A_CNT of the hit entry by a specific value, such as "+1" (at S252). Thereafter, the update controller 440 may write (or update) the shift line data S_LINE into the target field according to the position pointer S_PTR and the library address BKADD (at S258). Therefore, the access count value of the hit entry of the target field may be increased.

[0114] On the other hand, if the access count value A_CNT of the hit entry is greater than or equal to the row hammer threshold value RH_T ("Yes" of S250), the update controller 440 may generate a row hammer address RH_ADD using the candidate address A_ADD of the hit entry of the shift line data S_LINE and the library address BKADD, and output the row hammer address RH_ADD and an alarm signal ALERT_S indicating that a row hammer situation has occurred (at S254). In addition, the update controller 440 may set the access count value A_CNT of the hit entry to a specific value (e.g., 0) (at S256). Thereafter, the update controller 440 may write (or update) the shift line data S_LINE into the target field according to the position pointer S_PTR and the library address BKADD (at S258).

[0115] When the address hit signal R_HIT is deactivated ("No" in S240) and the count hit signal C_HIT is activated ("Yes" in S260), the update controller 440 may replace the candidate address A_ADD of the hit entry of the shift line data S_LINE with the row address RADD, and increase the access count value A_CNT of the hit entry of the shift line data S_LINE by a specific value, such as "+1" (at S264). Thereafter, the update controller 440 may write (or update) the shift line data S_LINE into the target field according to the location pointer S_PTR and the library address BKADD (at S258). Therefore, both the candidate address and the access count value of the hit entry of the target field may be updated.

[0116] When the count hit signal C_HIT is deactivated (No in S260 ), the update controller 440 may increase the leak count value SP_CNT of the field selected according to the bank address BKADD among the fields of the overflow counter 410 (at S262 ).

[0117] Hereinafter, as a specific example, a hammer tracking method according to an embodiment of the present disclosure will be described.

[0118] FIG. 15A to FIG. 15M A hammer tracking method according to an embodiment of the present disclosure is described.

[0119] refer to Fig.15A , the first bank BK0 to the fifth bank BK4 are arranged, the first active interval tRC is set to 4CK, and the second active interval tRRD is set to 1CK. In this case, the first storage device to the fourth storage device are set, and each storage device may include the first field to the fifth field corresponding to the first bank BK0 to the fifth bank BK4, respectively. Fig.15A, the first to fifth entries are arranged in each field, and the row hammer threshold RH_T is set to 5000-1=4999.

[0120] refer to Fig. 15B , together with the active command ACT for the first clock cycle 1CK, the bank address BKADD for specifying the first bank BK0 and the row address RADD for specifying the sixteenth row, that is, (BKADD:0, RADD:16). The first search controller can read field data (that is, candidate addresses and access count values) (1,3), (2,2), (3,4000), (4,2000), (5,30) from the first field corresponding to the first bank BK0 among the fields of the first storage device, and read the leakage count value 2 from the overflow counter. Since all candidate addresses are different from the row address RADD 16, and the access count value 2 of the second entry is the same as the leakage count value 2, the first search controller can activate the count hit signal C_HIT, generate field information S_LINE and S_PTR for the first field, and transmit the signal to the second search controller. In this case, the shift line data S_LINE of the field information S_LINE and S_PTR are updated using the field data (1, 3), (2, 2), (3, 4000), (4, 2000), (5, 30) read from the first field, and the location pointer S_PTR can be set to a value (stage 1, entry 2) specifying the stage of the first storage device and the hit second entry.

[0121] refer to Fig. 15C , together with the active command ACT for the second clock cycle 2CK, the bank address BKADD for specifying the second bank BK1 and the row address RADD for specifying the thirteenth row are input, that is, (BKADD:1, RADD:13). The first search controller can read the field data (0,0), (0,0), (0,0), (0,0), (0,0) from the second field corresponding to the second bank BK1, and read the leakage count value 0 from the overflow counter. Since the access count value 0 of the first entry is the same as the leakage count value 0, the first search controller can generate field information S_LINE and S_PTR for the second field and transmit a signal to the second search controller. In this case, the shift line data S_LINE is updated with the field data (0,0), (0,0), (0,0), (0,0), (0,0) read from the second field, and the position pointer S_PTR can be set to the value (stage 1, entry 1) specifying the stage of the first storage device and the first entry hit.

[0122] In addition, the second search controller may read field data (6, 2), (7, 3), (8, 4000), (9, 2000), (10, 30) from the first field corresponding to the first bank BK0 according to the bank address BKADD received from the first search controller, and read the leak count value 2 from the overflow counter. Since the access count value 2 of the first entry is the same as the leak count value 2, the second search controller may update the shift line data S_LINE to the field data (6, 2), (7, 3), (8, 4000), (9, 2000), (10, 30) read from the first field, and set the position pointer S_PTR to the value (stage2, entry 1).

[0123] refer to Fig.15D , together with the active command ACT for the third clock cycle 3CK, the bank address BKADD for specifying the third bank BK2 and the row address RADD for specifying the 23rd row are input, that is, (BKADD:2, RADD:23). Since the access count value 5 of the first entry of the third field is first the same as the leakage count value 5, the first search controller can update the shift line data S_LINE to the field data (1,5), (2,5), (3,4000), (4,2000), (5,30) read from the third field, and set the position pointer S_PTR to the value (stage 1, entry1). Because the access count value 0 of the first entry of the second field is the same as the leakage count value 0, the second search controller can update the shift line data S_LINE to the field data (0,0), (0,0), (0,0), (0,0), (0,0) read from the second field, and set the position pointer S_PTR to the value (stage 2, entry 1). Furthermore, since the comparison results are all inconsistent, the third search controller may transmit the signal received from the second search controller to the fourth search controller as it is.

[0124] refer to Fig.15E, together with the active command ACT for the fourth clock cycle 4CK, the bank address BKADD for specifying the fourth bank BK3 and the row address RADD for specifying the ninth row are input, that is, (BKADD:3, RADD:9). Since the access count value 6 of the first entry of the fourth field is the same as the leakage count value 6, the first search controller can update the shift line data S_LINE to the field data (1,6), (2,6), (3,6), (4,6), (5,6) read from the fourth field, and set the position pointer S_PTR to the value (stage 1, entry 1). Since all comparison results are inconsistent, the second search controller can transmit the signal received from the first search controller to the third search controller as is. Since the access count value 0 of the first entry of the second field is the same as the leak count value 0, the third search controller can update the shift line data S_LINE to the field data (0,0), (0,0), (0,0), (0,0), (0,0) read from the second field, and set the position pointer S_PTR to the value (stage 3, entry 1). Since the candidate address 16 of the first entry of the first field is the same as the row address RADD 16, the fourth search controller can activate the address hit signal R_HIT, update the shift line data S_LINE to the field data (16,7), (17,3), (18,4000), (19,20), (20,30) read from the first field, and set the position pointer S_PTR to the value (stage 4, entry 1).

[0125] Thereafter, for the fifth clock cycle 5CK, the update controller may check the signal transmitted from the fourth search controller. Since the address hit signal R_HIT is activated and the access count value 7 of the first entry of the shift line data S_LINE specified by the position pointer S_PTR is less than the row hammer threshold RH_T, the update controller may increase the access count value 7 of the first entry of the shift line data S_LINE by a specific value, such as "+1". Fig.15F As shown, the update controller can write the shift line data S_LINE to the first field of the fourth storage device specified by the position pointer S_PTR. Therefore, the first entry of the first field can be updated to the value (16, 8). Since the update controller knows the bank address BKADD, the update controller can select the first field.

[0126] During the fifth clock cycle 5CK, the library address BKADD for specifying the fifth library BK4 and the row address RADD for specifying the 30th row are input together with the active command ACT, that is, (BKADD:4, RADD:30). The first search controller can transmit the signal set to the initial value to the second search controller as is. Since the candidate address 9 of the fourth entry of the fourth field is the same as the row address RADD 9, the second search controller can activate the address hit signal R_HIT, update the shift line data S_LINE to the field data (6,6), (7,6), (8,6), (9,4999), (10,6) read from the fourth field, and set the position pointer S_PTR to the value (stage 2, entry 4). The third search controller can transmit the signal received from the second search controller to the fourth search controller as is. Since the access count value 0 of the first entry of the second field is the same as the leak count value 0, the fourth search controller can update the shift line data S_LINE to the field data (0,0), (0,0), (0,0), (0,0), (0,0) read from the second field, and set the position pointer S_PTR to the value (stage 4, entry 1).

[0127] Thereafter, for the sixth clock cycle 6CK, the update controller may check the signal transmitted from the fourth search controller. Since the count hit signal C_HIT is activated, the update controller may replace the candidate address of the first entry of the shift line data S_LINE with the row address RADD 13 and increase the access count value 0 of the first entry of the shift line data S_LINE by a specific value, such as “+1”. Figure 15G , the update controller may write the shift line data S_LINE to the second field of the fourth storage device specified by the position pointer S_PTR. Therefore, the first entry of the second field may be updated to the value (13, 1). During the sixth clock cycle 6CK, the bank address BKADD for specifying the first bank BK0 and the row address RADD for specifying the fourth row are input together with the active command ACT, that is, (BKADD:0, RADD:4). As described above, each search controller may generate an address hit signal R_HIT, a count hit signal C_HIT, and field information S_LINE and S_PTR.

[0128] Thereafter, for the seventh clock cycle 7CK, the update controller may replace the candidate address of the first entry of the shift line data S_LINE with the row address RADD 23 according to the count hit signal C_HIT, and increase the access count value 5 of the first entry of the shift line data S_LINE by a specific value, such as “+1”. Fig.15H, the update controller may write the shift line data S_LINE to the third field of the first storage device specified by the position pointer S_PTR. Therefore, the first entry of the third field may be updated to the value (23,6). During the seventh clock cycle 7CK, the bank address BKADD for specifying the third bank BK2 and the row address RADD for specifying the 23rd row are input together with the active command ACT, that is, (BKADD:2, RADD:23). As described above, each search controller may generate an address hit signal R_HIT, a count hit signal C_HIT, and field information S_LINE and S_PTR.

[0129] According to one embodiment, when a write operation of an update controller and a read operation of a search controller are simultaneously requested for the same field, an additional circuit for preventing conflicts may be arranged. Fig.15I , a comparator 1510 and a multiplexer 1520 may be provided at the front end of each search controller. For each clock, the comparator 1510 may generate a match signal HIT by comparing the bank address BKADD input to the search controller with the bank address BKADD provided from the update controller. According to the match signal HIT, the multiplexer 1520 may select one of the field data read from the field corresponding to the bank address BKADD of the storage device and the shift line data S_LINE provided from the update controller, and provide the selected one to the search controller. For example, referring to Fig.15I During the seventh clock cycle 7CK, when the library address BKADD input to the search controller is the same as the library address BKADD provided from the update controller (as the library address of the third library BK2), the comparator 1510 may generate a match signal HIT as a logic high level "H". The multiplexer 1520 may select the shift line data S_LINE provided from the update controller in response to the logic high level match signal HIT, and provide the shift line data S_LINE to the search controller. Finally, the search controller may generate an address hit signal R_HIT, a count hit signal C_HIT, and field information S_LINE and S_PTR using the library address BKADD, the row address RADD, the selected data provided from the multiplexer 1520, and the leak count value provided from the overflow counter. The update controller may perform a write operation. Fig.15I In the embodiment, the comparator 1510 and the multiplexer 1520 are provided at the front end of the search controller, but the embodiment is not limited thereto. Depending on the embodiment, the comparator 1510 and the multiplexer 1520 may be included in each search controller.

[0130] For the eighth clock cycle 8CK, the update controller may confirm that the address hit signal R_HIT is activated and the access count value of the fourth entry of the shift line data S_LINE specified by the position pointer S_PTR is greater than or equal to the row hammer threshold RH_T. Therefore, the update controller may generate a row hammer address RH_ADD including a candidate address (or row address RADD) of the fourth entry of the shift line data S_LINE and a bank address BKADD, and set the access count value of the fourth entry of the shift line data S_LINE to 0. Reference Fig.15J , the update controller may output the row hammer address RH_ADD and the alarm signal ALERT_S. In addition, the update controller may write the shift line data S_LINE to the fourth field of the second storage device specified by the position pointer S_PTR. Therefore, the fourth entry of the fourth field is updated to the value (9, 0), so that the access count value can be initialized.

[0131] refer to Figure 15K For the ninth clock cycle 9CK, since both the address hit signal R_HIT and the count hit signal C_HIT have been deactivated, the update controller may increase the leak count value 3 of the fifth field of the overflow counter by “+1” according to the bank address BKADD.

[0132] For the tenth clock cycle 10CK, since the address hit signal R_HIT is activated and the access count value 2000 of the fourth entry of the shift line data S_LINE specified by the position pointer S_PTR is less than the row hammer threshold RH_T, the update controller may increase the access count value 2000 of the fourth entry of the shift line data S_LINE by “+1”. Figure 15L , the update controller may write the shift line data S_LINE to the first field of the first storage device specified by the location pointer S_PTR. Therefore, the fourth entry of the first field may be updated to a value (4,2001).

[0133] For the eleventh clock cycle 11CK, since the address hit signal R_HIT is activated and the access count value 6 of the first entry of the shift line data S_LINE specified by the position pointer S_PTR is less than the row hammer threshold RH_T, the update controller can increase the access count value 6 of the first entry of the shift line data S_LINE by "+1". Figure 15M , the update controller may write the shift line data S_LINE to the third field of the first storage device specified by the position pointer S_PTR. Therefore, the first entry of the third field may be updated to the value (23, 7).

[0134] For reference, a content addressable memory (CAM) is a memory with a relatively complex structure that can search the memory according to the content of the data. When a data pattern is input, the CAM can search for data that matches the data pattern. For this reason, CAM is used very efficiently in database searches, but due to its complex structure, it occupies a large capacity and is difficult to implement as the number of targets to be searched increases. A static random access memory (SRAM) is a memory with a relatively simple structure, and data can be directly accessed or written depending on the address. For this reason, SRAM is characterized by high speed and low access latency, which can increase the operating speed of the processor.

[0135] As described above, the memory controller 100 according to an embodiment of the present disclosure can use SRAM instead of the previously known CAM as a storage device to store candidate addresses and their access count values. When a row hammer tracking device is implemented using CAM, a number of CAMs corresponding to the library must be provided, and the lower the row hammer threshold, the more targets to be searched, making it difficult to implement in practice. In an embodiment of the present disclosure, by using SRAM as a storage device to store candidate addresses and their access count values, the area occupied by the row hammer tracking device can be minimized. In addition, a plurality of SRAMs and their corresponding search controllers are arranged one to one, and the search controller reads the data stored in the SRAM in a pipeline manner to detect the row hammer address in a short time, thereby efficiently reducing the row hammer risk.

[0136] In the above embodiment, it has been described that the row hammer tracking module 150 is placed inside the memory controller 100, but the embodiment is not limited thereto. According to one embodiment, the row hammer tracking module 150 may be provided in a module controller or a register clock driver of the memory module 200, and may be provided in each memory device 200A.

[0137] Various embodiments of the present disclosure have been described in the drawings and the specification. Although specific terms are used herein, these terms are only used to describe embodiments of the present disclosure. Therefore, the present disclosure is not bound by the above-described embodiments, and many changes are possible within the spirit and scope of the present disclosure. It should be apparent to those skilled in the art that, in addition to the embodiments disclosed herein, various modifications may also be made based on the technical scope of the present disclosure. The embodiments may be combined to form additional embodiments.

[0138] It should be noted that although the technical spirit of the present disclosure has been described in conjunction with its embodiments, this is only for descriptive purposes and should not be interpreted as limiting. It should be recognized by those skilled in the art that various changes can be made to it without departing from the technical spirit of the present disclosure and the appended claims.

[0139] For example, for the logic gates and transistors provided as examples in the above-described embodiments, different positions and types may be implemented depending on the polarity of an input signal.

Claims

1. A memory controller, comprising: Command / address generation module; as well as a row hammer tracking module configured to track row hammer addresses based on active commands and addresses of target banks and target rows indicated by the active commands, the active commands and the addresses being received from the command / address generation module, The hammer tracking module includes: a plurality of storage devices, each of the plurality of storage devices comprising fields corresponding to a library, each of the fields storing a candidate address and an access count value for the candidate address; as well as At least one search controller is configured to sequentially search the fields of the plurality of storage devices corresponding to the target library according to a clock when the active command is input, and search the fields of the plurality of storage devices corresponding to the different libraries during one clock based on the active command indicating the different libraries. 2 . The memory controller according to claim 1 , wherein fields at a same level among the fields of the plurality of storage devices store candidate addresses and access count values ​​for a same bank. 3 . The memory controller of claim 1 , wherein the number of the plurality of storage devices is set according to a first activity interval, the first activity interval being a minimum interval between consecutive active commands for the same bank. 4 . The memory controller according to claim 3 , wherein each of the plurality of memory devices has a depth set according to the number of banks.

5. The memory controller of claim 3 , wherein the hammer tracking module is configured to: For one clock, read the candidate address and access count value stored in the kth field of the xth storage device, and read the candidate address and access count value stored in the mth field of the (x+y)th storage device at the same time, wherein k is a positive integer, x is a positive integer, m is a positive integer different from k, and y is set based on a second activity interval, which is a minimum interval between consecutive active commands for different banks.

6. The memory controller of claim 1 , wherein the number of the plurality of storage devices is set according to a ratio of a first activity interval to a second activity interval, wherein the first activity interval is a minimum interval between consecutive activity commands for the same bank, and the second activity interval is a minimum interval between consecutive activity commands for different banks. 7 . The memory controller of claim 6 , wherein each of the plurality of memory devices has a depth set according to a product of the number of banks and the second activity interval.

8. The memory controller of claim 6, wherein the hammer tracking module is configured to: read the candidate address and access count value stored in the kth field of the xth storage device, and read the candidate address and access count value stored in the (ky)th field of the zth storage device, wherein k is a positive integer, x is a positive integer, z is a positive integer different from x, and y is set based on the second activity interval and the order of the library in which the activity command is input.

9. A hammer tracking device comprising: an overflow counter configured to store a leak count value; a plurality of storage devices, each of the plurality of storage devices comprising fields corresponding to a library, each of the fields storing a candidate address and an access count value for the candidate address; a plurality of search controllers cascaded to each other and corresponding to the plurality of storage devices, configured to generate an address hit signal, a count hit signal, and field information by comparing a candidate address and an access count value read from a field corresponding to a bank address with a row address and the leak count value, respectively; as well as An update controller is configured to update the leak count value or an access count value of a target field specified by the field information according to the address hit signal and the count hit signal.

10. The hammer tracking device of claim 9, wherein each of the plurality of memory devices comprises a static random access memory (SRAM). 11 . The hammer tracking device of claim 9 , wherein a k-th field of the plurality of storage devices stores candidate addresses and access count values ​​for the same bank, wherein k is a positive integer. 12 . The hammer tracking device of claim 9 , wherein the plurality of search controllers sequentially read candidate addresses and access count values ​​stored in fields at the same level among the fields of the plurality of storage devices based on a clock. 13 . The hammer tracking device of claim 12 , wherein the plurality of search controllers simultaneously read candidate addresses and access count values ​​stored in fields at different levels among the fields of the plurality of storage devices. 14 . The hammer tracking device of claim 9 , wherein the number of the plurality of storage devices is set according to a first activity interval, the first activity interval being a minimum interval between consecutive activity commands for the same bank.

15. The hammer tracking device of claim 14, wherein each of the plurality of storage devices has a depth set according to the number of libraries.

16. The hammer tracking device of claim 9, wherein the number of the plurality of storage devices is set according to a ratio of a first activity interval to a second activity interval, wherein the first activity interval is a minimum interval between consecutive activity commands for the same library, and the second activity interval is a minimum interval between consecutive activity commands for different libraries.

17. The hammer tracking device of claim 16, wherein each storage device of the plurality of storage devices has a depth set according to a product of the number of libraries and the second activity interval.

18. The hammer tracking device of claim 9, wherein the update controller is configured to: When the address hit signal is activated, When the access count value of the target field is less than a row hammer threshold, increasing the access count value of the target field, and A row hammer address is generated using the candidate address of the target field, and the access count value of the target field is initialized.

19. The hammer tracking device of claim 9, wherein the update controller is configured to: When the count hit signal is activated, replacing the candidate address of the target field with the row address and increasing the access count value of the target field, and When the count hit signal is deactivated, the leak count value of the overflow counter is increased.

20. The hammer tracking device according to claim 9, wherein the overflow counter stores a plurality of leak count values ​​corresponding to the banks respectively, and The update controller reads a leak count value corresponding to the bank address from the overflow counter.

21. The hammer tracking device of claim 9, further comprising: a reset circuit configured to generate a reset signal at refresh time intervals; The update controller initializes all fields of the storage device and the leak count value of the overflow counter in response to the reset signal.

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