In-memory computing system employing segmented memory architecture with local memory array selection for simultaneous execution of multiple independent operations

Abstract

The disclosure relates to an in-memory computing system employing a segmented memory architecture with local memory array selection for performing multiple independent operations simultaneously. A memory array includes memory cells arranged in a matrix, wherein cell rows are coupled to word lines and cell columns are coupled to output bit lines. The control circuit maps a first set of memory cells to a first in-memory computation operation that produces a computation output signal on a first output bit line according to a first matrix vector multiplication of a first input vector with a first set of computation weights stored in the first set of memory cells, and mapping the second group of memory cells into a second memory for computing operations, the second in-memory compute operation produces a compute output signal on a second output bit line different from the first output bit line according to a second matrix vector multiplication of a second input vector different from the first input vector with a second set of compute weights stored in a second set of memory cells. The first in-memory computing operation and the second in-memory computing operation are performed substantially simultaneously.

Description

Technical Field

[0001] Embodiments relate to in-memory computing circuits and, more particularly, to using a segmented memory architecture including a matrix of local memory arrays with selection of the local memory arrays to support simultaneous execution of multiple independent in-memory computing operations. Background Art

[0002] In-memory computing (IMC) systems store information in bit cells of a memory array and perform computations at the bit cell level. Examples of computations performed by IMC systems are multiply and accumulate (MAC) operations or matrix-vector multiplication (MVM) operations, where an input array (or vector) of numbers (X values, also called feature or coefficient data) is multiplied by an array of computation weights (g values) stored in memory, and the products are then added to produce an output array of numbers (Y values).

[0003]

[0004] By performing these calculations at the bit cell level in memory, the IMC system does not need to move data back and forth between the memory device and the computing device. Therefore, the limitations associated with the data transfer bandwidth between devices are eliminated, and the calculations can be performed with lower power consumption.

[0005] refer to Figure 1 , which shows a schematic diagram of an in-memory computing circuit 10. The circuit 10 utilizes a plurality of memory cells 14 AB The memory array 12 is formed such that the memory cells are arranged in a matrix having m columns and n rows. Each memory cell 14 AB is programmed to store the computation weights g for in-memory computation operations AB , where A is an integer from 1 to m and B is an integer from 1 to n, such computational weights are also referred to as kernel data. Each computational weight may be represented in a binary format (where the weight has a logical "1" value or a logical "0" value) or in a multivariate format (where the weight has three or more possible values). The value of the computational weight is represented, for example, by a programmable conductance in the memory cell 14.

[0006] In one embodiment of the memory array 12, each memory cell 14 ABA phase change memory (PCM) cell is formed by a selection circuit (MOSFET transistor, BJT transistor, diode device, etc.) 14t operating as a switching element and a variable resistive element 14r providing programmable conductance. In the case of a MOSFET transistor for the selection circuit 14t, the control node (gate) of the MOSFET transistor is connected to the word line WL. The source-drain path of the MOSFET transistor is connected in series with the variable resistive element 14r between the bit line BL and a reference node (e.g., source line or ground). More specifically, the drain of the MOSFET transistor is connected to a first terminal of the variable resistive element 14r, the source of the MOSFET transistor is connected to the reference node, and the second terminal of the variable resistive element 14r is connected to the bit line BL.

[0007] As is well known to those skilled in the art, the PCM type memory cell 14 is configured to store data using a phase change material (such as chalcogenide) that can stably transform between an amorphous phase and a crystalline phase according to the heat transferred thereto. The amorphous phase and the crystalline phase exhibit two (binary configuration) or more (multi-configuration) different resistances corresponding to the variable resistive element 14r, in other words, two or more different conductances, which are used to distinguish two or more different logical values ​​or states that can be programmed into the memory cell. The amorphous phase exhibits a relatively high resistance (i.e., a low conductance), so when selected by the assertion of the word line signal at the gate of the selection circuit 14t, the current absorbed from the bit line BL by the memory cell programmed in this state is relatively small. In contrast, the crystalline phase exhibits a relatively low resistance (i.e., a high conductance), so when selected by the assertion of the word line signal at the gate of the selection circuit 14t, the current absorbed from the bit line BL by the memory cell programmed in this state is relatively large.

[0008] In an embodiment, for a specific but non-limiting example of two different logical values ​​in a binary configuration: the amorphous phase can represent programming the memory cell to a logical "0" (or reset state) for the associated coefficient weight, and the crystalline phase can represent programming the memory cell to a logical "1" (or set state) for the associated coefficient weight.

[0009] It will be appreciated that other types of memory cells may also be used in the array 12. For example, magnetoresistive random access memory (MRAM) cells or resistive random access memory (RRAM) cells may be used.

[0010] Each memory cell 14 AB Including word line WL and bit line BL The memory cells 14 in the same row of the matrix are connected by a common word line WL The memory cells 14 in the same column of the matrix are connected to each other through a common bit line BL. Connect with each other.

[0011] Each word line WL Driven by word line driver circuit 16 using a pulsating word line signal generated by row controller circuit 18. Word line driver circuit 16 may be implemented as a CMOS driver circuit (eg, a series connected pair of p-channel and n-channel MOSFET transistors forming a logic inverter circuit).

[0012] The row controller circuit 18 receives an address signal (Address) for an in-memory computing operation and, in response thereto, performs selection to simultaneously access (or actuate) word lines WL in parallel during the emulated in-memory computing operation. <1> To WL <n>The row controller circuit 18 also receives characteristic or coefficient data X for in-memory computation operations. B , and in response thereto, for each corresponding actuated word line WL Control the width of the generated pulsating word line signal (ie, the turn-on time T ON ). This functionality is a form of pulse width modulation (PWM) control of the applied word line signal depending on the digital value of the received characteristic or coefficient data X.

[0013] < / n> Figure 1 It is only illustrated by way of example that in response to the received Address, all word lines WL are activated simultaneously. <1> ,…,WL <n>, where the pulsating word line signal has corresponding coefficient data X1, ..., X n Of course, it will be appreciated that analog in-memory computation operations may instead use simultaneous actuation of fewer than all rows of the memory array (selected by the Address signal or by actuating the same number of rows for a given coefficient data X). B of zero).

[0014] On the bit line BL The analog signal Y generated on A Depending on the memory cell 14 stored in the column B=1 to n AB The calculation weight g in AB and the word lines WL applied to those memory cells 14. <1> ,…,WL <n>More specifically, it will be understood that each memory cell 14 AB Contribution and X B ×g AB is proportional to the bit line BL discharge current.< / n> Figure 1 In the example shown in FIG. 1 , word line signals are simultaneously applied to word lines WL <1> ,…,WL <n>, on the bit line BL <1> The analog signal Y1 generated by 11 , X2×g 12 , …, and X n ×g 1n is proportional to the sum of the discharge currents caused.

[0015] The column processing circuit 20 senses and samples the bit line BL of each of the m columns. The analog signal Y A , and use the analog-to-digital converter circuit system to convert the analog signal into the corresponding digital signal dY A .Although Figure 1 An analog-to-digital converter (ADC) is illustrated as being provided for each column, but it will be appreciated that the ADC resources in the column processing circuit 20 may instead be shared by multiple columns using time division multiplexing. The column processing circuit 20 may also include a digital signal processing circuit system for processing the digital signal dY A Perform digital calculations and operations to generate decision outputs for in-memory computing operations.

[0016] Although Figure 1 1, but it will be understood that the circuit 10 also includes conventional row decoding, column decoding, and read-write circuits known to those skilled in the art for use in conjunction with writing the computation weights to, and reading data from, the memory cells 14 of the memory array 12. This operation is referred to as a conventional memory access mode and is distinct from the analog in-memory computation operation discussed above. Summary of the invention

[0017] In an embodiment, an in-memory computing circuit comprises: a memory including a plurality of memory cells arranged in a matrix having a plurality of cell rows and a plurality of cell columns, wherein each cell row is associated with a word line connected to the memory cells in the cell row, and wherein each cell column is associated with a global bit line; wherein the memory is segmented into a plurality of local memory arrays, the plurality of local memory arrays being arranged in a matrix having a plurality of array rows and a plurality of array columns; a word line driver for each array row, the word line driver being selectively enabled to drive the word line of the array row in response to a row select signal; wherein each local memory array comprises a plurality of local bit lines connected to the memory cells in the cell columns, and a column decoder circuit being configured to selectively connect local bit lines to global bit lines of array columns in response to column select signals; and control circuitry configured to generate row select signals for word line drivers and column select signals for column decoder circuits to map a first set of one or more local memory arrays to participate in a first in-memory computational operation that produces computational output signals on a first one of the global bit lines, and to map a second set of one or more local memory arrays (different from the first set of one or more local memory arrays) to participate in a second in-memory computational operation that produces computational output signals on a second one of the global bit lines (different from the first one of the global bit lines); and wherein the first in-memory computational operation and the second in-memory computational operation are performed substantially simultaneously.

[0018] In an embodiment, an in-memory computing circuit includes: a memory array including a plurality of memory cells arranged in a matrix having a plurality of cell rows and a plurality of cell columns, wherein each cell row is associated with a word line coupled to the memory cells in the cell row, and wherein each cell column is associated with an output bit line coupled to the memory cells in the cell column; a control circuit configured to map a first group of memory cells to participate in a first in-memory computing operation to generate a computing output signal on a first output bit line in output bit lines according to a first matrix-vector multiplication of a first input vector and a first set of computing weights stored in the first group of memory cells, and to map a second group of memory cells to participate in a second in-memory computing operation to generate a computing output signal on a second output bit line in output bit lines different from the first output bit line in output bit lines according to a second matrix-vector multiplication of a second input vector different from the first input vector and a second set of computing weights stored in the second group of memory cells; and wherein the first in-memory computing operation and the second in-memory computing operation are performed substantially simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] For a better understanding of the embodiments, reference will now be made, by way of example only, to the accompanying drawings, in which:

[0020] Figure 1 is a schematic diagram of an embodiment of a computing circuit in memory;

[0021] Figure 2 is a schematic diagram of an embodiment of a computing circuit in memory;

[0022] Figure 3 yes Figure 2 A schematic diagram of a local memory array used in a circuit of;

[0023] Figure 4A-4D Examples are illustrated for configuring in-memory computing circuitry to support the execution of substantially simultaneous and independent in-memory computing operations;

[0024] Figure 5A-5D Shown with Figure 2 A diagram of a control circuit used in conjunction with the circuit;

[0025] Fig. 6A and Fig. 7A A circuit is shown for solving the problem of input analog-to-digital converter dynamic range when performing in-memory computation operations with reduced matrix dimensions;

[0026] Figure 6B and Figure 7B A circuit is shown for solving the problem of input analog-to-digital converter dynamic range when performing in-memory computation operations with reduced matrix dimensions; and

[0027] Figure 6C and Figure 7C A circuit is shown for solving the problem of input analog-to-digital converter dynamic range when performing in-memory computation operations with reduced matrix dimensions. DETAILED DESCRIPTION

[0028] Reference now Figure 2 , which shows a schematic diagram of an analog in-memory computing circuit 100 including a memory 110 formed by a plurality of memory cells 114 arranged in a matrix having m cell columns and n cell rows. Thus, the memory 110 may have Figure 1 The memory 110 is the same size as the memory 10, but the memory 110 has a different architectural configuration. The memory 110 is segmented to form a plurality of local memory arrays 112 arranged in a matrix form having j array columns and k array rows. cd (Local memory array 112 cd Each array row forms a memory row partition and the local memory array 112 cd Each array column of forms a memory column partition), where c is an integer from 1 to j and d is an integer from 1 to k. Figure 2 One implementation is shown (by way of example only and not limitation) for a total of sixteen local memory arrays 112 in a 4x4 matrix, where j=4 and k=4, with four memory row partitions and four memory column partitions.

[0029] like Figure 3 As shown in FIG. 1 , each local memory array 112 cd The memory cell 114 is composed of a plurality of memory cells 114 arranged in a matrix form having M cell columns and N cell rows. ab , where a is an integer from 1 to M (M=m / j) and b is an integer from 1 to N (N=n / k). Memory cells 114 in the same cell row b of the matrix for local memory array 112 are formed. ab Through the word line WL Memory cells 114 in the same cell column a of the matrix for the local memory array 112 are connected to each other. ab Through the local bit line LBL Connect with each other.

[0030] Each memory cell 114 includes a phase change memory (PCM) cell formed by a selection circuit (MOSFET transistor, BJT transistor, diode device, etc.) 114t operating as a switching element and a variable resistive element 114r providing programmable conductance. In the case of a MOSFET transistor for the selection circuit 114t, the control node (gate) of the MOSFET transistor is connected to the word line WL. The source-drain path of the MOSFET transistor is connected in series with the variable resistive element 114r between the local bit line LBL and a reference node (e.g., source line or ground). More specifically, the drain of the MOSFET transistor is connected to the first terminal of the variable resistive element 114r, the source of the MOSFET transistor is connected to the reference node, and the second terminal of the variable resistive element 114r is connected to the local bit line LBL.

[0031] It will be appreciated that other types of memory cells may be used instead for each local memory array 112. For example, magnetoresistive random access memory (MRAM) cells or resistive random access memory (RRAM) cells may be used.

[0032] Each memory cell 114ab is programmed to store a corresponding computation weight g for (one or more) in-memory computation operations. ab , such computational weights are also referred to as kernel data. Each computational weight may be expressed in a binary format (where the weight has a logical "1" value or a logical "0" value) or in a multivariate format (where the weight has three or more possible values). The value of the computational weight is represented, for example, by a programmable conductance in memory cell 114. The memory cell 114 may be stored in each local memory array 112. cd The calculation weight data in may be different, but in some cases can be the same or some data can be shared between multiple local memory arrays.

[0033] Each local memory array 112 participates in an in-memory computation operation similar to Figure 1 The operation of the memory array 12 is similar to that shown in FIG. 1 , but on a reduced scale. During the simulation of in-memory computing operations, the word lines WL are simultaneously accessed (or actuated) in parallel. <1> To WL <n>The width of the generated pulsating word line signal (i.e., the opening time T ON ) The characteristic or coefficient data X of the computation operation in the memory b For example, with the corresponding coefficient data X1, ..., X N The digital value sets the pulse width of the pulsating word line signal to activate all word lines WL at the same time <1> ,…,WL <n>On a given local bit line LBL The analog signal y generated on a Depending on the calculated weight g stored in the memory cells 114 of cell column a with b=1 to N ab and the word lines WL applied to those memory cells 114 at the b cell rows. <1> ,…,WL <n>More specifically, it will be appreciated that each memory cell 114 contributes to the width of the pulsating word line signal X. b ×g ab Therefore, when the word line signal is simultaneously applied to the word line WL <1> ,…,WL <n>In the example, the local bit line LBL <1> The analog signal y1 generated by X1×g 11 , X2×g 12 , …, and X n ×g 1N The sum of the discharge currents caused by each local bit line LBL of the corresponding cell column is proportional to< / n> < / n> The analog signal y a It can then be sensed, sampled, and converted into a corresponding digital signal using analog-to-digital converter circuitry. Digital calculations and operations can then be performed on the digital signal to generate a decision output for the in-memory computing operation.

[0034] Again additional reference Figure 2 , the word line WL of each local memory array 112 of array row d (corresponding to the memory row partition) Shared by all local memory arrays 112 in that array row of memory 110. Each array row is provided with a corresponding word line driver WLD d circuit, and this WLD circuit is connected to the word line WL <1> ,…,WL <n>and is configured to apply a feature or coefficient data X b A pulse width of pulsating word line signal is used for in-memory computing operations. Figure 1 As shown in FIG. 1 , each WLD circuit includes a word line driving circuit (CMOS driver, reference numeral 16 ) for each word line WL. d The activation of the circuit is in response to the array row selection signal RSel d For example, if the row selection signal RSel d In the first logic state, indicating connection to WLD d At least one local memory array 112 in array row d of the circuit cd Is participating in a given in-memory compute operation, then enable that WLD d The circuit is used to drive the local memory array 112 in that row through the driver circuit 16 using the word line signal for a given in-memory computing operation. cd On the contrary, if the row select signal RSel d In the second logic state, indicating connection to WLD d There is no local memory array 112 in array row d of the circuit cd is participating in a given in-memory compute operation, then disable that WLD d The circuit does not apply a word line signal to the word line WL of that row.

[0035] For the local memory array 112 cd The memory 110 is formed of a matrix having m columns of memory cells 114 and n rows of memory cells 114, where m=j*M and n=k*N. The m memory cells 114 in a cell row of the memory 110 share a common word line WL. Each of the m columns of memory cells 114 in a cell column of the memory 110 is connected to a global bit line GBL. <m>For each local memory array 112 cd A column decoding circuit 200 is provided to respond to an array column selection signal CSel. cd Each local bit line LBL of the local memory array 112 is selectively coupled (e.g., electrically connected through a transistor switch) to one of the global bit lines GBL of the memory 110 that corresponds to the cell column. cd is in a first logic state, indicating that the local memory array 112 cd is participating in a given in-memory computation operation, then that local memory array 112 cd The local bit line LBL in the array is connected to the corresponding global bit line GBL provided for the array column. cd is in the second logic state, indicating that the local memory array 112 cd If the local memory array 112 is not involved in a given in-memory computation operation, cd The local bit line LBL in is disconnected from the corresponding global bit line GBL.

[0036] The granularity of control discussed above is at the local memory array level, which means that for a local memory array partitioned by a memory column, the connection / disconnection between the local bit line LBL and the global bit line GBL is all or nothing. As discussed elsewhere herein, in another embodiment, the connection / disconnection between the local bit line LBL and the global bit line GBL is all or nothing. cd , finer granularity control over the connection / disconnection between each local bit line LBL and the global bit line GBL within each local memory array is also possible.

[0037] The pulsating wordline signals for the (one or more) in-memory computation operations are generated by the row controller circuit 118 and are responsive to the row select signal RSel. d Through WLD d circuit selectively applied to the local memory array 112 cd Each local bit line LBL The analog signal y a The column decoder circuit 200 selectively applies the bit line GBL to the global bit line GBL. <m>Each global bit line GBL <m>The analog signal Y generated on m Depending on the local bit line LBL selected by the column decoding circuit 200< / m> < / m> The analog signal y a For example, the global bit line GBL <1> The analog signal Y1 generated by the column select signal CSel 1d Selected local memory array 112 1d One or more local bit lines LBL in <1> The analog signal y1 is proportional to the sum of the discharge currents obtained.

[0038] The column processing circuitry senses and samples each global bit line GBL <m>The analog signal Y m , and use the analog-to-digital converter circuit system to convert the analog signal into the corresponding digital signal dY m .Although< / m> Figure 2 An analog-to-digital converter (ADC) is illustrated as being provided for each global bit line GBL column, but it will be appreciated that the ADC resources in the column processing circuit may instead be shared by multiple global bit line columns using time division multiplexing. The column processing circuit may also include a digital signal processing circuit system for processing the digital signal dY m Digital calculations and operations are performed to generate decision outputs for in-memory computing operation(s).

[0039] The local memory array 112 cd The architecture of the in-memory computing circuit 100 of the memory 110 formed by the matrix of enables two or more independent in-memory computing operations to be performed simultaneously. This is achieved by generating a column select signal CSel cd and row select signal RSel d To achieve this, these signals will be local memory array 112 cd By controlling the mapping operation, each in-memory computing operation uses a different set of global bit lines GBL. <m>To calculate the analog signal Y generated by matrix-vector multiplication m , two or more in-memory computing operations can be performed substantially simultaneously and independently of each other. In this context, substantially simultaneously means that the timing of the execution of the two or more in-memory computing operations occurs simultaneously or at least partially overlaps in time. In addition, in this context, independent means that the two or more in-memory computing operations produce separate outputs from the computing inputs. This can be better understood by referring to several examples.

[0040] Example A: Generate column select signal CSel cd and row select signal RSel d The local memory array 112 11 , 112 21 , 112 12 and 112 22 Mapped to the first in-memory computation operation (IMC-OP1), and local memory array 112 33 , 112 43 , 112 34 and 112 44 Mapped to the second in-memory computation operation (IMC-OP2). This can be achieved by, for example, the following operations: a) asserting row select signals RSel1, RSel2, RSel3, and RSel4, which will enable WLD1, WLD2, WLD3, and WLD4 circuits; b) asserting column select signal CSel 11 ,CSel 21 ,CSel 12 and CSel 22 , which will enable the local memory array 112 to participate in the first in-memory computing operation (IMC-OP1) 11 , 112 21 , 112 12 and 112 22 The column decoding circuit 200 and asserts the column selection signal CSel 33 ,CSel 43 ,CSel 34 and CSel 44 , which will enable the local memory array 112 to participate in the second in-memory computing operation (IMC-OP2) 33 , 112 43 , 112 34 and 112 44 and c) de-asserting the column select signal CSel 13 ,CSel 23 ,CSel 14 ,CSel 24 ,CSel 31 ,CSel 41 ,CSel 32 and CSel 42 , which will disable the local memory array 112 that is not involved in any of the first in-memory computing operation and the second in-memory computing operation. 13 , 112 23 , 112 14 , 112 24 , 112 31 , 112 41 , 112 32 and 112 42 The column decoding circuit 200 is provided. Figure 4A Such a mapping is illustrated with an "X" indicated on the local memory arrays 112 that are not enabled, and dashed boxes labeled IMC-OP1 and IMC-OP2 enclosing the local memory arrays 112 that are participating in two independent and substantially simultaneous in-memory computation operations.

[0041] In this example A, a pulsating wordline signal for a first in-memory computation operation (IMC-OP1) is generated by row controller circuit 118 based on characteristic or coefficient data X and selectively applied to local memory array 112 in a first array row (memory row partition) through WLD1 circuit in response to row select signal RSel1. 11 and 112 21 In addition, a pulsating word line signal for a first in-memory computation operation (IMC-OP1) is generated by the row controller circuit 118 and selectively applied to the local memory array 112 in the second array row (memory row partition) through the WLD2 circuit in response to the row select signal RSel2. 12 and 112 22 The local memory array 112 in the first array column (first memory column partition) 11 and 112 12 Each local bit line LBL The analog signal y a In response to the column selection signal CSel 11 and CSel 12 The column decoding circuit 200 selectively applies the signal to the global bit line GBL. <1> to GBL <f>To generate analog signals Y1 to Y f The local memory array 112 in the second array column (second memory column partition) 21 and 112 22 Each local bit line LBL< / f> The analog signal y a In response to the column selection signal CSel 21 and CSel 22 The column decoding circuit 200 selectively applies the signal to the global bit line GBL. <g>to GBL <h>To generate an analog signal Y g To Y h . Analog signals Y1 to Y h Indicates the result of the matrix-vector multiplication of the first in-memory compute operation (IMC-OP1).

[0042] The column processing circuitry senses and samples the global bit line GBL <1> to GBL <h>The analog signal Y1 to Y h To perform matrix-vector multiplication and use an analog-to-digital converter circuit system to convert the analog signal into the corresponding digital signal dY1 to dY h . The digital signals dY1 to dY h Digital calculations and operations are performed to generate a decision output of a first in-memory computation operation (IMC-OP1).

[0043] In addition, a pulsating word line signal for a second in-memory computation operation (IMC-OP2) is generated by the row controller circuit 118 based on the characteristic or coefficient data X and is selectively applied to the local memory array 112 in the third array row (memory row partition) through the WLD3 circuit in response to the row select signal RSel3. 33 and 112 43 In addition, a pulsating word line signal for a second in-memory computation operation (IMC-OP2) is generated by the row controller circuit 118 and selectively applied to the local memory array 112 in the fourth array row (memory row partition) through the WLD4 circuit in response to the row select signal RSel4. 34 and 112 44 The local memory array 112 in the third array column (third memory column partition) 33 and 112 34 Each local bit line LBL< / h> < / h> < / g> The analog signal y a In response to the column selection signal CSel 33 and CSel 34 The column decoding circuit 200 selectively applies the signal to the global bit line GBL. <s>to GBL <t>To generate an analog signal Y s To Y t The local memory array 112 in the fourth array column (fourth memory column partition) 43 and 112 44 Each local bit line LBL< / t> < / s> <s> The analog signal y a In response to the column selection signal CSel 43 and CSel 44 The column decoding circuit 200 selectively applies the signal to the global bit line GBL. to GBL <m>To generate an analog signal Y u To Y m . Analog signal Y u To Y m Indicates the result of the matrix-vector multiplication of the second in-memory compute operation (IMC-OP2).

[0044] The column processing circuitry senses and samples the global bit line GBL <s>to GBL <m>The analog signal Y s To Y m To perform matrix-vector multiplication and use an analog-to-digital converter circuit system to convert the analog signal into the corresponding digital signal dY s To dY m . The digital signal dY can be s To dY m Digital calculations and operations are performed to generate a decision output of a second in-memory computation operation (IMC-OP2).

[0045] It is worth noting that the pulsating word line signal applied by the WLD1 and WLD2 circuits for the first in-memory computing operation (IMC-OP1) can be performed at least partially overlapping, and preferably completely simultaneously, with the pulsating word line signal applied by the WLD3 and WLD4 circuits for the second in-memory computing operation (IMC-OP2). Thus, the two in-memory computing operations are substantially performed simultaneously, and the results of those two in-memory computing operations are respectively transmitted through the global bit lines GBL <1> to GBL <h>The analog signal Y1 to Y h and global bit line GBL <s>to GBL <m>The analog signal Y s To Y m Independent output.

[0046] Example B: Generate column select signal CSel cd and row select signal RSel d , so that the local memory array 112 11 and 112 21 Mapped to the first in-memory computation operation (IMC-OP1), and local memory array 112 33 , 112 43 , 112 34 and 112 44 Mapped to the second in-memory computation operation (IMC-OP2). This can be achieved, for example, by the following operations: a) asserting row select signals RSel1, RSel3, and RSel4, which will enable WLD1, WLD3, and WLD4 circuits, and deasserting row select signal RSel2, which will disable WLD2 circuit; b) asserting column select signal CSel 11 and CSel 21 , which will enable the local memory array 112 to participate in the first in-memory computing operation (IMC-OP1) 11 and 112 21 The column decoding circuit 200 and asserts the column selection signal CSel 33 ,CSel 43 ,CSel 34 and CSel 44 , which will enable the local memory array 112 to participate in the second in-memory computing operation (IMC-OP2) 33 , 112 43 , 112 34 and 112 44 and c) de-asserting the column select signal CSel 12 ,CSel 22 ,CSel 13 ,CSel 23 ,CSel 14 ,CSel 24 ,CSel 31 ,CSel 41 ,CSel 32 and CSel 42 , which will disable the local memory array 112 that is not involved in either of the first in-memory computing operation and the second in-memory computing operation 12 , 112 22 , 112 13 , 112 23 , 112 14 , 112 24 , 112 31 , 112 41 , 112 32 and 112 42 The column decoding circuit 200 is provided.< / m> < / s> < / h> < / m> < / s> < / m> <s> <s> Figure 4B Such a mapping is illustrated with inactive local memory arrays 112 indicated with an "X" and dashed boxes labeled IMC-OP1 and IMC-OP2 enclosing local memory arrays 112 that are substantially simultaneously participating in two independent in-memory computation operations.

[0047] In this example B, a pulsating wordline signal for a first in-memory computation operation (IMC-OP1) is generated by row controller circuit 118 based on characteristic or coefficient data X and selectively applied to local memory array 112 in a first array row (memory row partition) through WLD1 circuit in response to row select signal RSel1. 11 and 112 21 The local memory array 112 in the first array column (first memory column partition) 11 Each local bit line LBL The analog signal y a In response to the column selection signal CSel 11 The column decoding circuit 200 selectively applies the signal to the global bit line GBL. <1> to GBL <f>To generate analog signals Y1 to Y f The local memory array 112 in the second array column (second memory column partition) 21 Each local bit line LBL< / f> The analog signal y a In response to the column selection signal CSel 21 The column decoding circuit 200 selectively applies the signal to the global bit line GBL. <g>to GBL <h>To generate an analog signal Y g To Y h . Analog signals Y1 to Y h Indicates the result of the matrix-vector multiplication of the first in-memory compute operation (IMC-OP1).

[0048] The column processing circuitry senses and samples the global bit line GBL <1> to GBL <h>The analog signal Y1 to Y h To perform matrix-vector multiplication and use an analog-to-digital converter circuit system to convert the analog signal into corresponding digital signals dY1 to dY h . The digital signals dY1 to dY h Digital calculations and operations are performed to generate a decision output of a first in-memory computation operation (IMC-OP1).

[0049] In addition, a pulsating word line signal for a second in-memory computation operation (IMC-OP2) is generated by the row controller circuit 118 based on the characteristic or coefficient data X and is selectively applied to the local memory array 112 in the third array row (memory row partition) through the WLD3 circuit in response to the row select signal RSel3. 33 and 112 43 In addition, a pulsating word line signal for a second in-memory computation operation (IMC-OP2) is generated by the row controller circuit 118 and selectively applied to the local memory array 112 in the fourth array row (memory row partition) through the WLD4 circuit in response to the row select signal RSel4. 34 and 112 44 The local memory array 112 in the third array column (third memory column partition) 33 and 112 34 Each local bit line LBL< / h> < / h> < / g> The analog signal y a In response to the column selection signal CSel 33 and CSel 34 The column decoding circuit 200 selectively applies the signal to the global bit line GBL. <s>to GBL <t>To generate analog signal Y s To Y t The local memory array 112 in the fourth array column (fourth memory column partition) 43 and 112 44 Each local bit line LBL< / t> < / s> <s> The analog signal y a In response to the column selection signal CSel 43 and CSel 44 The column decoding circuit 200 selectively applies the signal to the global bit line GBL. to GBL <m>To generate an analog signal Y u To Y m . Analog signal Y s To Y m Indicates the result of the matrix-vector multiplication of the second in-memory compute operation (IMC-OP2).

[0050] The column processing circuitry senses and samples the global bit line GBL <s>to GBL <m>The analog signal Y s To Y m To perform matrix-vector multiplication and use an analog-to-digital converter circuit system to convert the analog signal into the corresponding digital signal dY s To dY m . The digital signal dY can be s To dY m Digital calculations and operations are performed to generate a decision output of a second in-memory computation operation (IMC-OP2).

[0051] It is noteworthy that the pulsating word line signal applied by the WLD1 circuit for the first in-memory computing operation (IMC-OP1) can be performed at least partially overlapping, and preferably simultaneously with, the pulsating word line signal applied by the WLD3 and WLD4 circuits for the second in-memory computing operation (IMC-OP2). Thus, the two in-memory computing operations are substantially performed simultaneously, and the results of those two in-memory computing operations are respectively transmitted through the global bit lines GBL <1> to GBL <h>The analog signal Y1 to Y h and global bit line GBL <s>to GBL <m>The analog signal Y s To Y m are output independently.

[0052] Example C: Generate column select signal CSel cd and row select signal RSel d The local memory array 112 11 and 112 21 Mapped to the first in-memory computing operation (IMC-OP1), the local memory array 112 33 and 112 34 Mapped to the second in-memory computation operation (IMC-OP2), and the local memory array 112 43 and 112 44 Mapped to the third in-memory computation operation (IMC-OP3). This can be achieved, for example, by the following operations: a) asserting row select signals RSel1, RSel3, and RSel4, which will enable WLD1, WLD3, and WLD4 circuits, and deasserting row select signal RSel2, which will disable WLD2 circuit; b) asserting column select signal CSel 11 and CSel 21 , which will enable the local memory array 112 to participate in the first in-memory computing operation (IMC-OP1) 11 and 112 21 The column decoding circuit 200 asserts the column selection signal CSel 33 and CSel 34 , which will enable the local memory array 112 to participate in the second in-memory computing operation (IMC-OP2) 33 and 112 34 The column decoding circuit 200 and asserts the column selection signal CSel 43 and CSel 44 , which will enable the local memory array 112 to participate in the third in-memory computing operation (IMC-OP3) 43 and 112 44 and c) de-asserting the column select signal CSel 12 ,CSel 22 ,CSel 13 ,CSel 23 ,CSel 14 ,CSel 24 ,CSel 31 ,CSel 41 ,CSel 32 and CSel 42 , which will disable the local memory array 112 that is not involved in any of the first in-memory computing operation, the second in-memory computing operation, and the third in-memory computing operation. 12 , 112 22 , 112 13 , 112 23 , 112 14 , 112 24 , 112 31 , 112 41 , 112 32 and 112 42 The column decoding circuit 200 is provided.< / m> < / s> < / h> < / m> < / s> < / m> <s> <s> Figure 4C Such a mapping is illustrated with inactive local memory arrays 112 indicated with an "X" and dashed boxes labeled IMC-OP1, IMC-OP2, and IMC-OP3 enclosing local memory arrays 112 that participate in three independent in-memory computation operations substantially simultaneously.

[0053] In this example C, a pulsating wordline signal for a first in-memory computation operation (IMC-OP1) is generated by row controller circuit 118 based on characteristic or coefficient data X and selectively applied to local memory array 112 in a first array row (memory row partition) through WLD1 circuit in response to row select signal RSel1. 11 and 112 21 The local memory array 112 in the first array column (first memory column partition) 11 Each local bit line LBL The analog signal y a In response to the column selection signal CSel 11 The column decoding circuit 200 selectively applies the signal to the global bit line GBL. <1> to GBL <f>To generate analog signals Y1 to Y f The local memory array 112 in the second array column (second memory column partition) 21 Each local bit line LBL< / f> The analog signal y a In response to the column selection signal CSel 21 The column decoding circuit 200 selectively applies the signal to the global bit line GBL. <g>to GBL <h>To generate an analog signal Y g To Y h . Analog signal Y1 to Y h Indicates the result of the matrix-vector multiplication of the first in-memory compute operation (IMC-OP1).

[0054] The column processing circuitry senses and samples the global bit line GBL <1> to GBL <h>The analog signal Y1 to Y h To perform matrix-vector multiplication and use an analog-to-digital converter circuit system to convert the analog signal into the corresponding digital signal dY1 to dY h . The digital signals dY1 to dY h Digital calculations and operations are performed to generate a decision output of a first in-memory computation operation (IMC-OP1).

[0055] In addition, pulsating word line signals for the second in-memory computation operation and the third in-memory computation operation (IMC-OP2 and IMC-OP3) are generated by the row controller circuit 118 based on the characteristic or coefficient data X and selectively applied to the local memory array 112 in the third array row (memory row partition) through the WLD3 circuit in response to the row select signal RSel3. 33 and 112 43 In addition, pulsating word line signals for the second in-memory computing operation and the third in-memory computing operation (IMC-OP2 and IMC-OP3) are generated by the row controller circuit 118 and selectively applied to the local memory array 112 in the fourth array row (memory row partition) through the WLD4 circuit in response to the row select signal RSel4. 34 and 112 44 The local memory array 112 in the third array column (third memory column partition) 33 and 112 34 Each local bit line LBL< / h> < / h> < / g> The analog signal y a In response to the column selection signal CSel 33 and CSel 34 The column decoding circuit 200 selectively applies the signal to the global bit line GBL. <s>to GBL <t>To generate an analog signal Y s To Y t . Analog signal Y s To Y t Indicates the result of the matrix-vector multiplication of the second in-memory computation operation (IMC-OP2). Local memory array 112 in the fourth array column (fourth memory column partition) 43 and 112 44 Each local bit line LBL< / t> < / s> <s> The analog signal y a In response to the column selection signal CSel 43 and CSel 44 The column decoding circuit 200 selectively applies the signal to the global bit line GBL. to GBL <m>To generate an analog signal Y u To Y m . Analog signal Y u To Y m Indicates the result of the matrix-vector multiplication of the third in-memory compute operation (IMC-OP3).

[0056] The column processing circuitry senses and samples the global bit line GBL <s>to GBL <t>The analog signal Y s To Y t To perform matrix-vector multiplication and use an analog-to-digital converter circuit system to convert the analog signal into the corresponding digital signal dY s To dY t . The digital signal dY can be s To dY t Digital calculations and operations are performed to generate a decision output of the second in-memory computation operation (IMC-OP2). Similarly, the column processing circuitry senses and samples the global bit line GBL to GBL <m>The analog signal Y u To Y m To perform matrix-vector multiplication and use an analog-to-digital converter circuit system to convert the analog signal into the corresponding digital signal dY u To dY m . The digital signal dY can be u To dY m Digital calculations and operations are performed to generate a decision output of a third in-memory computation operation (IMC-OP3).

[0057] It is noteworthy that the pulsating word line signal applied for the first in-memory computing operation (IMC-OP1) by the WLD1 and WLD2 circuits can be applied at least partially overlapping, and preferably simultaneously, with the pulsating word line signal applied for the second in-memory computing operation and the third in-memory computing operation (IMC-OP2 and IMC-OP3) by the WLD3 and WLD4 circuits. Thus, the three in-memory computing operations are substantially performed simultaneously, and the results of those three in-memory computing operations are respectively transmitted through the global bit lines GBL. <1> to GBL <h>The analog signal Y1 to Y h , Global Bit Line GBL <s>to GBL <t>The analog signal Y s To Y t and global bit line GBL to GBL <m>The analog signal Y u To Y m are output independently.

[0058] Example D: Generate column select signal CSel cd and row select signal RSel d The local memory array 112 11 Mapped to the first in-memory computing operation (IMC-OP1), the local memory array 112 22 Mapped to the second in-memory computing operation (IMC-OP2), the local memory array 112 33 Mapped to the third in-memory computation operation (IMC-OP3), and local memory array 112 44 Mapped to the fourth in-memory computation operation (IMC-OP4). This can be achieved by, for example, the following operations: a) asserting row select signals RSel1, RSel2, RSel3, and RSel4, which will enable WLD1, WLD2, WLD3, and WLD4 circuits; b) asserting column select signal CSel 11 , which will enable the local memory array 112 to participate in the first in-memory computing operation (IMC-OP1) 11 The column decoding circuit 200 asserts the column selection signal CSel 22 , which will enable the local memory array 112 to participate in the second in-memory computing operation (IMC-OP2) 22 The column decoding circuit 200 asserts the column selection signal CSel 33 , which will enable the local memory array 112 to participate in the third in-memory computing operation (IMC-OP3) 33 The column decoding circuit 200 and asserts the column selection signal CSel 44 , which will enable the local memory array 112 to participate in the fourth in-memory computation operation (IMC-OP4) 44 and c) de-asserting the column select signal CSel 21 ,CSel 31 ,CSel 41 ,CSel 12 ,CSel 32 、CSe1 42 ,CSel 13 ,CSel 23 ,CSel 43 ,CSel 14 ,CSel 24 and CSel 34 , which will disable the local memory array 112 that does not participate in any of the first in-memory computing operation, the second in-memory computing operation, the third in-memory computing operation, and the fourth in-memory computing operation. 21 , 112 31 , 112 41 , 112 12 , 112 32 , 112 42 , 112 13 , 112 23 , 112 43 , 112 14 , 112 24 and 112 34 The column decoding circuit 200 is provided.< / m> < / t> < / s> < / h> < / m> < / t> < / s> < / m> <s> <s> Figure 4D Such a mapping is illustrated with inactive local memory arrays 112 indicated with an "X" and dashed boxes labeled IMC-OP1, IMC-OP2, IMC-OP3, and IMC-OP4 surrounding local memory arrays 112 that participate in four independent in-memory computation operations substantially simultaneously.

[0059] In this example D, a pulsating wordline signal for a first in-memory computation operation (IMC-OP1) is generated by row controller circuit 118 based on characteristic or coefficient data X and selectively applied to local memory array 112 in a first array row (memory row partition) through WLD1 circuit in response to row select signal RSel1. 11 The local memory array 112 in the first array column (first memory column partition) 11 Each local bit line LBL The analog signal y a In response to the column selection signal CSel 11 The column decoding circuit 200 selectively applies the signal to the global bit line GBL. <1> to GBL <f>To generate analog signals Y1 to Y f . Analog signals Y1 to Y f Indicates the result of the matrix-vector multiplication of the first in-memory compute operation (IMC-OP1).

[0060] The column processing circuitry senses and samples the global bit line GBL <1> to GBL <f>The analog signal Y1 to Y f To perform matrix-vector multiplication and use an analog-to-digital converter circuit system to convert the analog signal into corresponding digital signals dY1 to dY f . The digital signals dY1 to dY f Digital calculations and operations are performed to generate a decision output of a first in-memory computation operation (IMC-OP1).

[0061] In addition, a pulsating word line signal for a second in-memory computation operation (IMC-OP2) is generated by the row controller circuit 118 based on the characteristic or coefficient data X and is selectively applied to the local memory array 112 in the second array row (memory row partition) through the WLD2 circuit in response to the row select signal RSel2. 22 The local memory array 112 in the second array column (second memory column partition) 22 Each local bit line LBL< / f> < / f> The analog signal y a In response to the column selection signal CSel 22 The column decoding circuit 200 selectively applies the signal to the global bit line GBL. <g>to GBL <h>To generate an analog signal Y g To Y h . Analog signal Y g To Y h Indicates the result of the matrix-vector multiplication of the second in-memory compute operation (IMC-OP2).

[0062] The column processing circuitry senses and samples the global bit line GBL <g>to GBL <h>The analog signal Y g To Y h To perform matrix-vector multiplication and use an analog-to-digital converter circuit system to convert the analog signal into the corresponding digital signal dY g To dY h . The digital signal dY can be g To dY h Digital calculations and operations are performed to generate a decision output of a second in-memory computation operation (IMC-OP2).

[0063] Also, a pulsating word line signal for a third in-memory computation operation (IMC-OP3) is generated by the row controller circuit 118 based on the characteristic or coefficient data X and selectively applied to the local memory array 112 in the third array row (memory row partition) through the WLD3 circuit in response to the row select signal RSel3. 33 The local memory array 112 in the third array column (third memory column partition) 33 Each local bit line LBL< / h> < / g> < / h> < / g> The analog signal y a In response to the column selection signal CSel 33 The column decoding circuit 200 selectively applies the signal to the global bit line GBL. <s>to GBL <t>To generate an analog signal Y s To Y t . Analog signal Y s To Y t Indicates the result of the matrix-vector multiplication of the third in-memory compute operation (IMC-OP3).

[0064] The column processing circuitry senses and samples the global bit line GBL <s>to GBL <t>The analog signal Y s To Y t To perform matrix-vector multiplication and use an analog-to-digital converter circuit system to convert the analog signal into the corresponding digital signal dY s To dY t . The digital signal dY can be s To dY t Digital calculations and operations are performed to generate a decision output of a third in-memory computation operation (IMC-OP3).

[0065] Finally, a pulsating wordline signal for a fourth in-memory computation operation (IMC-OP4) is generated by row controller circuit 118 based on the characteristic or coefficient data X and selectively applied to the local memory array 112 in the fourth array row (memory row partition) through WLD4 circuit in response to row select signal RSel4. 44 The local memory array 112 in the fourth array column (fourth memory column partition) 44 Each local bit line LBL< / t> < / s> < / t> < / s> <s> <s> The analog signal y a In response to the column selection signal CSel 44 The column decoding circuit 200 selectively applies the signal to the global bit line GBL. to GBL <m>To generate an analog signal Y u To Y m . Analog signal Y u To Y m Indicates the result of the matrix-vector multiplication of the fourth in-memory compute operation (IMC-OP4).

[0066] The column processing circuitry senses and samples the global bit line GBL to GBL <m>The analog signal Y u To Y m To perform matrix-vector multiplication and use an analog-to-digital converter circuit system to convert the analog signal into the corresponding digital signal dY u To dY m . The digital signal dY can be u To dY m Digital calculations and operations are performed to generate a decision output of a fourth in-memory computation operation (IMC-OP4).

[0067] It is noteworthy that the pulsating word line signal applied by the WLD1 circuit for the first in-memory computing operation (IMC-OP1), the pulsating word line signal applied by the WLD2 circuit for the second in-memory computing operation (IMC-OP2), the pulsating word line signal applied by the WLD3 circuit for the third in-memory computing operation (IMC-OP3), and the pulsating word line signal applied by the WLD4 circuit for the fourth in-memory computing operation (IMC-OP4) are at least partially overlapping, preferably simultaneous. Thus, the four in-memory computing operations are substantially performed simultaneously, and the results of those four in-memory computing operations are respectively transmitted through the global bit lines GBL. <1> to GBL <f>The analog signal Y1 to Y f , Global Bit Line GBL <g>to GBL <h>The analog signal Y g To Y h , Global Bit Line GBL <s>to GBL <t>The analog signal Y s To Y t and global bit line GBL to GBL <m>The analog signal Y u To Y m are output independently.

[0068] pass< / m> < / t> < / s> < / h> < / g> < / f> < / m> < / m> <s> Figure 4A-4D The example of well illustrates the flexibility of the system to handle multiple in-memory computing operations of selected sizes (using different numbers of local memory arrays 112) substantially simultaneously. Figure 4A-4D The example shown should not be considered as limiting. In practice, the user can select the column through the column selection signal CSel cd and row select signal RSel d The selective assertion / deassertion of memory blocks can be used to configure a variety of different arrangements to efficiently handle multiple simultaneous and independent in-memory computation operations.

[0069] Reference again Figure 2 and Figure 3 By splitting the wordline drive control within each array row (memory row partitioning), an even smaller mapping of independent in-memory computation operations can be achieved. Figure 3 Divide each WLD d The circuit is represented by a dotted line that distinguishes the upper half of the circuit from the lower half of the circuit. d It can be implemented using, for example, two bits to control whether all word lines WL of an array row (partition) are enabled through both the upper and lower half circuits, and only the word lines WL and WLD are enabled. d The upper word line WL associated with the upper half of the circuit, or only enable the WLD d The lower half of the circuit is associated with the lower half word line WL.

[0070] Reference now Figure 5A-Figure 5B , showing the control circuit system generating the row selection signal RSel d and column select signal CSel cd . Figure 5A and Figure 5B As an example only, we assume that Figure 2 and Figure 4A-4D 1, wherein the matrix of the local memory array 112 has four array rows, with corresponding four WLD1, WLD2, WLD3 and WLD4 circuits, four array rows (memory row partitions), four array columns (memory column partitions) and sixteen local memory arrays 112. 11 , …, 112 44 .

[0071] The data register 302 stores the data bits of the local array select signal (Local_Array_Select<15:0>). In this example, there are sixteen bits in the signal, and the logic state of each bit indicates whether the local memory array 112 corresponding to that bit is participating in any in-memory computing operation. For example, if the bit is a logic "1", then the corresponding local memory array 112 is participating. The enable input of each WLD circuit is coupled to receive a row select signal RSel, which is generated by logically combining certain bits of the local array select signal.

[0072] The first logic OR gate 3041 has a local memory array 112 coupled to receive the first array rows respectively assigned to the memory 110. 11 , 112 21 , 112 31 and 112 41 Position <0> , <1> , <2> and <3> The output terminal of gate 3041 generates row selection signal RSel1. 11 , 112 21 , 112 31 and 112 41 Any of the <0> , <1> , <2> and <3> If any one of the two is logic “1”, the row select signal RSel1 is asserted and the WLD1 circuit is enabled.

[0073] The second logic OR gate 3042 has a local memory array 112 coupled to receive the second array rows respectively assigned to the memory 110. 12 , 112 22 , 112 32 and 112 42 Position <4> , <5> , <6> and <7> The output terminal of gate 3042 generates row selection signal RSel2. 12 , 112 22 , 112 32 and 112 42 Any of the <4> , <5> , <6> and <7> is logic “1”, then the row select signal RSel2 is asserted and the WLD2 circuit is enabled.

[0074] The third logic OR gate 3043 has a local memory array 112 coupled to receive the third array rows respectively assigned to the memory 110. 13 , 112 23 , 112 33 and 112 43 Position <8> , <9> , <10> and <11> The output terminal of gate 3043 generates row selection signal RSel3. 13 , 112 23 , 112 33 and 112 43 Any of the <8> , <9> , <10> and <11> is logic “1”, then row select signal RSel3 is asserted and the WLD3 circuit is enabled.

[0075] The fourth logical OR gate 3044 has a local memory array 112 coupled to receive the fourth array row assigned to the memory 110. 14 , 112 24 , 112 34 and 112 44 Position <12> , <13> , <14> and <15> The output terminal of gate 3044 generates row selection signal RSel4. 14 , 112 24 , 112 34 and 112 44 Any of the <12> , <13> , <14> and <15> is logic “1”, then row select signal RSel4 is asserted and WLD4 circuit is enabled.

[0076] The data register 310 stores data bits of an array column select signal (Array_Column_Select<3:0>). In this example, there are three bits in the signal, and the logic state of each bit indicates whether the array column (memory column partition) corresponding to that bit has a local memory array 112 participating in any in-memory computation operation. For example, if the bit is a logic "1", then the corresponding array column has one or more participating local memory arrays 112. The enable input of each column decoder circuit 200 of the local memory array is coupled to receive a column select signal CSel, which is generated by logically combining certain bits of the array column select signal and the local array select signal.

[0077] For the local memory array 112 in the first column of the memory 110 11 , 112 12 , 112 13 and 112 14 The associated column decoder 200 11 , 200 12 , 200 13 and 200 14 , the logical AND gate converts the bit of the array column select signal <0> The local array select signal bit <0> , <4> , <8> and <12> The logical AND gate generates the column select signal CSel. 11 ,CSel 12 ,CSel 13 and CSel 14 , to selectively enable the column decoder 200 11 , 200 12 , 200 13 and 200 14 . The array column select signal bit <0> The logic "1" state indicates that the local memory array 112 11 , 112 12 , 112 13 and 112 14 At least one of them is participating in the in-memory computation operation, and the bit of the local array select signal <0> , <4> , <8> and <12> A logic "1" state of any one of the local memory array 112 specifies 11 , 112 12 , 112 13 and 112 14 If both bits input to the AND gate are logic "1", the corresponding column decoder 200 is enabled to connect the local bit line LBL of the local memory array 112 to the corresponding global bit line GBL. <1> to GBL <f>.

[0078] For the local memory array 112 in the second column of the memory 110 21 , 112 22 , 112 23 and 112 24 Associated column decoder 200 21 , 200 22 , 200 23 and 200 24 , the logical AND gate array column select signal bit <1> The local array select signal bit <1> , <5> , <9> and <13> The logical AND gate generates the column select signal CSel. 21 ,CSel 22 ,CSel 23 and CSel 24 , to selectively enable the column decoder 200 21 , 200 22 , 200 23 and 200 24 . The array column select signal bit <1> The logic "1" state indicates that the local memory array 112 21 , 112 22 , 112 23 and 112 24 At least one of them is participating in the in-memory computation operation, and the bit of the local array select signal <1> , <5> , <9> and <13> A logic "1" state of any one of the local memory array 112 specifies 21 , 112 22 , 112 23 and 112 24 If both bits input to the AND gate are logic "1", the corresponding column decoder 200 is enabled to connect the local bit line LBL of the local memory array 112 to the corresponding global bit line GBL. <g>to GBL <h>.

[0079] For the local memory array 112 in the third column of the memory 110 31 , 112 32 , 112 33 and 112 34 Associated column decoder 200 31 , 200 32 , 200 33 and 200 34 , the logical AND gate array column select signal bit <2> The local array select signal bit <2> , <6> , <10> and <14> The logical AND gate generates the column select signal CSel. 31 ,CSel 32 ,CSel 33 and CSel 34 , to selectively enable the column decoder 200 31 , 200 32 , 200 33 and 200 34 . The array column select signal bit <2> The logic "1" state indicates that the local memory array 112 31 , 112 32 , 112 33 and 112 34 At least one of them is participating in the in-memory computation operation, and the bit of the local array select signal <2> , <6> , <10> and <14> A logic "1" state of any one of the local memory array 112 specifies 31 , 112 32 , 112 33 and 112 34 If both bits input to the AND gate are logic "1", the corresponding column decoder 200 is enabled to connect the local bit line LBL of the local memory array 112 to the corresponding global bit line GBL. <s>to GBL <t>.

[0080] For the local memory array 112 in the fourth column of the AND memory 110 41 , 112 42 , 112 43 and 112 44 Associated column decoder 200 41 , 200 42 , 200 43 and 200 44 , the logical AND gate array column select signal bit <3> The local array select signal bit <3> , <7> , <11> and <15> The logical AND gate generates the column select signal CSel. 41 ,CSel 42 ,CSel 43 and CSel 44 , to selectively enable the column decoder 200 41 , 200 42 , 200 43 and 200 44 . The array column select signal bit <3> The logic "1" state indicates that the local memory array 112 41 , 112 42 , 112 43 and 112 44 At least one of them is participating in the in-memory computation operation, and the bit of the local array select signal <3> , <7> , <11> and <15> A logic "1" state of any one of the local memory array 112 specifies 41 , 112 42 , 112 43 and 112 44 If both bits input to the AND gate are logic "1", the corresponding column decoder 200 is enabled to connect the local bit line LBL of the local memory array 112 to the corresponding global bit line GBL. to GBL <m>.

[0081] A higher degree of selectivity (granularity) may also be employed in the column decoder 200 to connect the local bit lines LBL to the global bit lines GBL. Instead of the column select signal CSel being a single bit that controls the column decoder 200 to connect all local bit lines LBL to corresponding global bit lines GBL, the column select signal CSel may instead be implemented as a multi-bit signal, where each individual bit of the column select signal CSel controls the column decoder 200 to connect one local bit line LBL to its corresponding global bit line. Figure 5C Regarding a single local memory array 112 11 An embodiment of a control circuit 300 is shown for supporting this operation, it being understood that this circuit will be replicated in relation to each local memory array.

[0082] Consider here an example where the local memory array 112 11 Includes eight local bit lines LBL <0> To LBL <7> The column decoder 200 can be driven by a multi-bit column select signal CSel. 11 <f:0>Control to individually (and selectively) connect each local bit line to the corresponding global bit line GBL <0> to GBL <f>For example, the selective connection between a local bit line and its associated global bit line may be made by using a transistor switch (S) actuated by a corresponding bit of a column select signal CSel.

[0083] Data register 310_c stores data bits of an array column select signal (Array_Column_Select_c<7:0>), where the value of c indicates an array column of memory 110. In this example, there are eight bits in the signal, and the logic state of each bit indicates whether the corresponding local bit line LBL in the local memory array 112 is participating in any in-memory computing operation and is to be connected to the corresponding global bit line GBL. For example, if the local memory array 112 11 The array column select signal bits <0> is logic "1", then the local bit line LBL <0> will be connected to the corresponding global bit line GBL <0> To perform in-memory computations. <0> Select local memory array 112 11 When performing in-memory calculation operations, which bit is related to the array column select signal bit? <0> The logical combination of the column select signal CSel 11 <0> assertion to actuate the switch (S) and place the local bit line LBL <0> Connected to the corresponding global bit line GBL <0> .

[0084] For each local memory array 112 cd The control circuit 300 includes a plurality of logic AND gates, one logic AND gate for each local bit line LBL of the local memory array 112, wherein the AND gate logically combines a bit of a local array selection signal for the local memory array 112 with a bit of an array column selection signal to generate a corresponding bit of a column selection signal CSel, which is used to individually control a switch (S) to selectively connect the local bit line LBL to the corresponding global bit line GBL.

[0085] Figure 5C The logic circuit shown in FIG. 1 is used in the control circuit 300 for each local memory array 112. cd However, for the local memory array 112 cd For each array column (memory column partition), there will be a different data register 310_c storing the data bits of the array column select signal (Array_Column_Select_c<7:0>).

[0086] For example purposes, Figure 5D Control circuit 300 is shown for controlling the connection of each local bit line LBL of the first array column (c=1) to the global bit line GBL using the bits of the array column select signal (Array_Column_Select_1<7:0>). This circuit configuration will be repeated in control circuit 200 for each array column of memory 110.

[0087] Again, refer to Example A and Figure 4A , the bits of the local array select signal (Local_Array_Select<15:0>) will be <1,1,0,0,1,1,0,0,0,0,1,1,0,0,1,1>. In response to these bits, the logic OR gate of the control circuit 300 will assert the row select signals RSel1, RSel2, RSel3 and RSel4 and activate the WLD1, WLD2, WLD3 and WLD4 circuits. The logic AND gate of the control circuit 300 will assert the column select signal CSel 11 ,CSel 21 ,CSel 12 ,CSel 22 ,CSel 33 ,CSel 43 ,CSel 34 and CSel 44 , and the local memory array 112 11 , 112 21 , 112 12 , 112 22 , 112 33 , 112 43 , 112 34 and 112 44 The local bit lines LBL of the memory 110 are connected to the corresponding global bit lines. By using the array column select signal (Array_Column_Select_c<7:0>), more refined control can be exercised over the connection of each local bit line LBL in each array column to the global bit line GBL. For example, if the bits of the array column select signal (Array_Column_Select_1<15:0>) for the first array column of the memory 110 are <1,1,0,0,0,0,1,1>, then only the first local bit line, the second local bit line, the seventh local bit line, and the eighth local bit line LBL will be connected to the corresponding global bit line GBL. In either case, one or more bits of the column select signal CSel actuate the selected switch S of the column decoder circuit 200 to achieve the desired LBL to GBL connection.

[0088] It will be noted that changing the dimension of the matrix of the computational operation in the memory results in the analog signal Y input to the analog-to-digital converter circuit being a For example, consider using Figure 1 The in-memory computation operation and use of the circuit shown in Figure 4A The configuration shown in Figure 2 The first in-memory computation operation (IMC-OP1) performed by the circuit is: Figure 4A Generate analog signal Y a The global bit line GBL current will be Figure 1 Generate analog signal Y a Half of the bit line BL current.

[0089] There are many solutions suitable for solving the above problems.

[0090] First solution: Reference Fig. 6A and Fig. 7A The dynamic bias voltage control circuit 400 is connected to each global bit line GBL. The dynamic bias voltage control circuit 400 controls the bias voltage BV on each global bit line GBL according to the matrix dimension information used for each in-memory computing operation. m Information about the matrix dimensions is provided by the bits of the local array select signal (Local_Array_Select<15:0>) that indicates which local memory arrays 112 have been selected to participate in one or more in-memory computation operations. Based on the number of local memory arrays 112 selected in a given array column (memory column partition), the dynamic bias voltage control circuit 400 will scale the bias voltage BV on each global bit line GBL of that array column. m , to take into account the matrix dimensions. Figure 4A As an example, the first array column (including the local memory array 112 11 , 112 12 , 112 13 and 112 14 ) uses only two local memory arrays 112 11 and 112 12 The first in-memory computing operation (IMC-OP1) is performed. To take into account the reduced global bit line GBL current in the first array column, the dynamic bias voltage control circuit 400 will make the global bit line GBL <1> to GBL <f>The bias voltage BV on each global bit line in m Double (2X). For example, if only one of the four local memory arrays is used (see Figure 5B ), the dynamic bias voltage control circuit 400 will be on the global bit line GBL <1> to GBL <f>A 4X bias voltage BV is provided on each global bit line in m When three of the four are used, circuit 400 will provide a bias voltage scaling of 4X / 3.

[0091] To support dynamic control of the bias voltage BV applied to each global bit line GBL, the dynamic bias voltage control circuit 400 may include a plurality of bias voltage generator (BVG) circuits, each of which is configured to generate a different bias voltage level (BV_1, BV_2, ..., BV_x), and a switching (e.g., multiplexing) circuit 406 at each global bit line GBL, the switching circuit 406 being controlled by a selection signal 402 in response to processing 404 of a bit of a local array select signal (Local_Array_Select<15:0>) to select an appropriate one of the generated bias voltage levels to be applied to the global bit line GBL.

[0092] Second solution: Reference Figure 6B and Figure 7B The dynamic current mirror control circuit 420 is connected between the global bit line GBL and the input of the ADC circuit. The dynamic current mirror control circuit 420 controls the mirror ratio R applied between the input current received on the global bit line GBL and the output current applied to the input of the ADC circuit depending on the matrix dimension of each in-memory calculation operation. m Information about the matrix dimensions is provided by bits of the local array select signal (Local_Array_Select<15:0>) that indicates which local memory arrays 112 have been selected to participate in one or more in-memory computation operations. Based on the number of local memory arrays 112 selected in a given array column, the dynamic current mirror control circuit 420 will scale the current mirror ratio R of the current on each global bit line GBL of that array column. m , to take into account the matrix dimensions. Figure 4A As an example, the first array column (including the local memory array 112 11 , 112 12 , 112 13 and 112 14 ) uses only two local memory arrays 112 11 and 112 12 The first in-memory computing operation (IMC-OP1) is performed. To take into account the reduced global bit line GBL current in the first array column, the dynamic current mirror control circuit 420 will make the current applied to the global bit line GBL <1> to GBL <f>The mirror ratio R of the current on each global bit line m Likewise, if only one of the four local memory arrays is used, then 4X scaling is provided, and if three of the four are used, then 4X / 3 scaling is provided.

[0093] In order to support dynamic control of the current mirror ratio R of the current applied to each global bit line GBL, the dynamic current mirror control circuit 420 may include a controllable mirror ratio R at each global bit line GBL. m =1:k current mirror circuit 422, wherein k can be set equal to a selected mirror ratio R by control signal 424 in response to processing 426 of the bits of the local array select signal (Local_Array_Select<15:0>) to select an appropriate current mirror ratio for scaling the current on the global bit line GBL before analog-to-digital conversion.

[0094] The third solution: Reference Figure 6C and Figure 7C Each ADC circuit includes an integration circuit 442 and a counter circuit 444. The integration circuit 442 integrates the current on the global bit line GBL, for example, in combination with the above Figure 6B and Figure 7B After selective scaling as discussed above, a clock signal 446 is generated whose frequency is a function of the global bit line current. Counter circuit 444 is implemented as a ripple counter and operates to count the number of pulses in clock signal 446 during a particular time period. The count value of counter circuit 444 at the end of that particular time period is a digital signal dY converted from analog signal Y.

[0095] A dynamic ADC multiplication circuit 440 is provided for the ADC circuit. The dynamic ADC multiplication circuit 440 controls the multiplication factor Mult applied to the counting of the number of pulses in the clock signal 446 by the counter circuit 444. m , where the multiplication depends on the matrix dimensions of each in-memory computation operation. Information about the matrix dimensions is provided by bits of the local array select signal (Local_Array_Select<15:0>) that indicates which local memory arrays 112 have been selected to participate in one or more in-memory computation operations. Based on the number of local memory arrays 112 selected in a given array column, the dynamic ADC multiplication circuit 440 will select a multiplication factor Mult for the pulse count at each ADC circuit. m to take into account the matrix dimensions. Figure 4A As an example, the first array column (including the local memory array 112 11 , 112 12 , 112 13 and 112 14 ) uses only two local memory arrays 112 11 and 112 12 The first in-memory calculation operation (IMC-OP1) is performed. To account for the reduced global bit line GBL current in the first array column, the dynamic ADC multiplication circuit 440 will choose to apply a 2X (or twice) multiplication factor Mult when counting pulses. m (That is, each pulse in clock signal 446 will increase the count value by 2). Similarly, for Figure 4B The configuration shown in will apply a multiplication factor of 4X when counting pulses (each pulse will increase the count value by 4).

[0096] In order to support dynamic control of the multiplication factor Mult applied when counting the pulses of the clock signal 446 m The dynamic ADC multiplication circuit 440 may include a switch circuit 448 (e.g., a demultiplexer) at each ADC circuit that receives a clock signal 446 and passes the clock signal 446 to a control signal 452 that selects one output from a plurality of outputs in response to processing 450 of bits of a local array select signal (Local_Array_Select<15:0>) to select an appropriate multiplication factor Mult m The output of the switch circuit 448 is connected to different latch inputs of the counter circuit 444. For example, for the multiplication factor Mult m =1, the clock signal 446 is applied from the output terminal of the switch circuit 448 to the clock input terminal of the first latch circuit in the plurality of latch circuits connected in series to form the ripple counter. m =2, the clock signal 446 is applied from the output terminal of the switch circuit 448 to the clock input terminal of the second latch circuit among the multiple latch circuits connected in series to form a ripple counter.

[0097] It is to be noted that two or more of the above solutions may be used concurrently.

[0098] The above description has provided by way of exemplary and non-limiting examples a complete and informative description of exemplary embodiments of the present invention. However, various modifications and adaptations may become apparent to those skilled in the relevant arts in view of the above description when read in conjunction with the accompanying drawings and the appended claims. However, all such and similar modifications of the teachings of the present invention will still fall within the scope of the present invention as defined by the appended claims.< / f> < / f> < / f> < / f> < / m> < / t> < / s> < / h> < / g> < / f> < / s> < / s> < / s> < / s> < / s> < / s> < / s> < / s> < / s> < / s> < / s> < / s> < / m> < / m> < / n> < / n> < / n> < / n> < / n>

Claims

1. A memory computing circuit, comprising: A memory comprising a plurality of memory cells arranged in a matrix having a plurality of cell rows and a plurality of cell columns, wherein each cell row is associated with a word line connected to the memory cells in the cell row, and wherein each cell column is associated with a global bit line; wherein the memory is segmented into a plurality of local memory arrays, the plurality of local memory arrays being arranged in a matrix having a plurality of array rows and a plurality of array columns; a word line driver for each array row, the word line driver being selectively enabled in response to a row select signal to drive a word line of the array row; wherein each local memory array includes a plurality of local bit lines connected to memory cells in a column of cells and a column decoder circuit configured to selectively connect the local bit lines to a global bit line of the array column in response to a column select signal; as well as a control circuit configured to generate row select signals for a word line driver and column select signals for a column decoder circuit to map a first set of one or more local memory arrays to participate in a first in-memory computation operation that produces computation output signals on a first one of the global bit lines, and to map a second set of one or more local memory arrays different from the first set of one or more local memory arrays to participate in a second in-memory computation operation that produces computation output signals on a second one of the global bit lines different from the first one of the global bit lines; and The first in-memory computing operation and the second in-memory computing operation are performed substantially simultaneously.

2. The in-memory computing circuit of claim 1, wherein the column decoder circuit connects all local bit lines to the global bit lines of the array column in response to assertion of the column select signal.

3. The in-memory computing circuit of claim 2, wherein the control circuit comprises: a local array select register storing first bits, each first bit corresponding to one of the local memory arrays and indicating whether the one local memory array is participating in one of the first in-memory computing operation and the second in-memory computing operation; an array column select register storing second bits, each second bit corresponding to one of the array columns and indicating whether any local memory array in the array column is participating in one of the first in-memory computation operation and the second in-memory computation operation; as well as A logic circuit is configured to logically combine a first bit for a local memory array in an array column with a second bit for the array column to generate a column selection signal for the local memory array in the array column.

4. The in-memory computing circuit of claim 1, wherein the column decoder circuit selectively connects corresponding respective local bit lines to corresponding global bit lines of the array column in response to assertion of respective bits of the column select signal.

5. The in-memory computing circuit of claim 4, wherein the control circuit comprises: a local array select register storing first bits, each first bit corresponding to one of the local memory arrays and indicating whether the one local memory array is participating in one of the first in-memory computing operation and the second in-memory computing operation; an array column select register for each array column storing second bits, each second bit corresponding to one of the cell columns and indicating whether the cell column is participating in one of the first in-memory computation operation and the second in-memory computation operation; as well as The logic circuit is configured to logically combine a first bit for a local memory array with a second bit for a cell column to generate a column selection signal for the local memory array to control the selective connection of a local bit line with a global bit line.

6. The in-memory computing circuit of claim 1, wherein the word line driver drives all word lines of an array row in response to assertion of a row select signal.

7. The in-memory computing circuit of claim 1, wherein the word line driver selectively drives certain word lines of the array rows in response to assertion of respective bits of the row select signal.

8. The in-memory computing circuit of claim 1, wherein the control circuit comprises: a local array select register storing bits, each bit corresponding to one of the local memory arrays and indicating whether the one local memory array is participating in one of the first in-memory computation operation and the second in-memory computation operation; as well as The logic circuit is configured to logically combine the bits of the row selection signal corresponding to the local memory array in the array column to generate a row selection signal for the word line drive of the array column.

9. The in-memory computing circuit as described in claim 1 also includes a dynamic bias voltage control circuit, which is configured to control the voltage level of the bias voltage applied to the first global bit line in the global bit line according to the matrix dimension of the first in-memory computing operation, and to control the voltage level of the bias voltage applied to the second global bit line in the global bit line according to the matrix dimension of the second in-memory computing operation.

10. The in-memory computing circuit of claim 9, further comprising: a local array select register storing bits, each bit corresponding to one of the local memory arrays and indicating whether the one local memory array is participating in one of the first in-memory computing operation and the second in-memory computing operation; and The dynamic bias voltage control circuit includes a processing circuit configured to process bits of a local array selection register to determine matrix dimensions of a first in-memory computing operation and a second in-memory computing operation, and to select voltage levels of bias voltages applied to a first global bit line and a second global bit line in the global bit lines respectively based on the determined matrix dimensions.

11. The in-memory computing circuit of claim 1 , wherein a current is derived from each computing output signal, and the in-memory computing circuit further comprises a dynamic current mirror control circuit configured to control a ratio of currents derived from the computing output signals mirrored at a first global bit line among the global bit lines according to a matrix dimension of a first in-memory computing operation, and to control a ratio of currents derived from the computing output signals mirrored at a second global bit line among the global bit lines according to a matrix dimension of a second in-memory computing operation.

12. The in-memory computing circuit of claim 10 , further comprising: a local array select register storing bits, each bit corresponding to one of the local memory arrays and indicating whether the one local memory array is participating in one of the first in-memory computing operation and the second in-memory computing operation; and The dynamic current mirror control circuit includes a processing circuit configured to process bits of a local array select register to determine matrix dimensions of a first in-memory computation operation and a second in-memory computation operation, and to select a ratio for mirroring a current derived from a computation output signal at a first global bit line and a second global bit line in the global bit lines, respectively, based on the determined matrix dimensions.

13. The in-memory computing circuit of claim 1 , further comprising: an analog-to-digital conversion ADC circuit coupled to each global bit line; Each ADC circuit includes: an integrator circuit configured to generate a clock signal in response to a computation output signal on the global bit line; and a counter circuit configured to count pulses of a clock signal; and a dynamic ADC multiplication control circuit configured to control a multiplication factor for counting clock signal pulses by an ADC circuit coupled to a first of the global bit lines according to a matrix dimension of a computational operation within a first memory, and to control a multiplication factor for counting clock signal pulses by an ADC circuit coupled to a second of the global bit lines according to a matrix dimension of a computational operation within a second memory.

14. The in-memory computing circuit of claim 13, further comprising: a local array select register storing bits, each bit corresponding to one of the local memory arrays and indicating whether the one local memory array is participating in one of the first in-memory computing operation and the second in-memory computing operation; and The dynamic ADC multiplication control circuit includes a processing circuit configured to process bits of a local array selection register to determine matrix dimensions of a first in-memory computing operation and a second in-memory computing operation, and select multiplication factors for counting clock signal pulses by an ADC circuit coupled to a first global bit line and a second global bit line of the global bit lines, respectively, based on the determined matrix dimensions.

15. An in-memory computing circuit, comprising: a memory array comprising a plurality of memory cells arranged in a matrix having a plurality of cell rows and a plurality of cell columns, wherein each cell row is associated with a word line coupled to the memory cells in the cell row, and wherein each cell column is associated with an output bit line coupled to the memory cells in the cell column; a control circuit configured to map a first group of memory cells to participate in a first in-memory computation operation that produces a computation output signal on a first one of the output bit lines based on a first matrix-vector multiplication of a first input vector with a first set of computation weights stored in the first group of memory cells, and to map a second group of memory cells to participate in a second in-memory computation operation that produces a computation output signal on a second one of the output bit lines that is different from the first one of the output bit lines based on a second matrix-vector multiplication of a second input vector that is different from the first input vector with a second set of computation weights stored in the second group of memory cells; as well as The first in-memory computing operation and the second in-memory computing operation are performed substantially simultaneously.

16. An in-memory computing circuit as described in claim 15, wherein the control circuit selects certain cell rows and certain cell columns to be actuated in association with each of a first in-memory computing operation and a second in-memory computing operation, and the certain cell columns used for the first in-memory computing operation are different from the certain cell columns used for the second in-memory computing operation.

17. The in-memory computing circuit of claim 15, further comprising a dynamic bias voltage control circuit, wherein the dynamic bias voltage control circuit is configured to control a voltage level of a bias voltage applied to a first output bit line among the output bit lines according to a matrix dimension of a first in-memory computing operation, and to control a voltage level of a bias voltage applied to a second output bit line among the output bit lines according to a matrix dimension of a second in-memory computing operation.

18. The in-memory computing circuit of claim 17, wherein the memory is segmented into a plurality of local memory arrays arranged in a matrix having a plurality of array rows and a plurality of array columns, and the in-memory computing circuit further comprises: a local array select register storing bits, each bit corresponding to one of the local memory arrays and indicating whether the one local memory array is participating in one of the first in-memory computing operation and the second in-memory computing operation; and The dynamic bias voltage control circuit includes a processing circuit configured to process bits of a local array selection register to determine matrix dimensions of a first in-memory computing operation and a second in-memory computing operation, and to select voltage levels of bias voltages applied to a first output bit line and a second output bit line of the output bit lines respectively based on the determined matrix dimensions.

19. An in-memory computing circuit as described in claim 15, wherein a current is derived from each computing output signal, and the in-memory computing circuit also includes a dynamic current mirror control circuit, which is configured to control the ratio of the current derived from the computing output signal to be mirrored at the first output bit line in the output bit line according to the matrix dimension of the first in-memory computing operation, and to control the ratio of the current derived from the computing output signal to be mirrored at the second output bit line in the output bit line according to the matrix dimension of the second in-memory computing operation.

20. The in-memory computing circuit of claim 19, wherein the memory is segmented into a plurality of local memory arrays arranged in a matrix having a plurality of array rows and a plurality of array columns, and the in-memory computing circuit further comprises: a local array select register storing bits, each bit corresponding to one of the local memory arrays and indicating whether the one local memory array is participating in one of the first in-memory computing operation and the second in-memory computing operation; and The dynamic current mirror control circuit includes a processing circuit configured to process bits of a local array select register to determine matrix dimensions of a first in-memory computation operation and a second in-memory computation operation, and to select a ratio of currents derived from a computation output signal to be mirrored at first and second output bit lines in the output bit lines, respectively, based on the determined matrix dimensions.

21. The in-memory computing circuit of claim 15, further comprising: Analog-to-digital conversion (ADC) circuitry coupled to each output bit line; Each ADC circuit includes: an integrator circuit configured to generate a clock signal in response to the computation output signal on the output bit line; and a counter circuit configured to count pulses of a clock signal; and a dynamic ADC multiplication control circuit configured to control a multiplication factor for counting pulses of the clock signal by an ADC circuit coupled to a first of the output bit lines according to a matrix dimension of a computational operation within a first memory, and to control a multiplication factor for counting pulses of the clock signal by an ADC circuit coupled to a second of the output bit lines according to a matrix dimension of a computational operation within a second memory.

22. The in-memory computing circuit of claim 21, wherein the memory is segmented into a plurality of local memory arrays arranged in a matrix having a plurality of array rows and a plurality of array columns, and the in-memory computing circuit further comprises: a local array select register storing bits, each bit corresponding to one of the local memory arrays and indicating whether the one local memory array is participating in one of the first in-memory computing operation and the second in-memory computing operation; and The dynamic ADC multiplication control circuit includes a processing circuit configured to process bits of a local array selection register to determine matrix dimensions of a first in-memory computing operation and a second in-memory computing operation, and to select a multiplication factor for counting clock signal pulses by an ADC circuit coupled to a first output bit line and a second output bit line of the output bit lines, respectively, based on the determined matrix dimensions.

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