Sharpley value calculation with analog CAM

Abstract

The invention provides a Shapley value calculation using an analog CAM. Examples of the disclosed technology provide hardware accelerators (referred to herein as treeShap-aCAM) that utilize the unique parallel search and simulation capabilities of the aCAM to calculate Sharpley values with improved speed / efficiency. The parallel search capability of the treeShap-aCAM enables all root-to-leaf paths (programmed into individual rows of the treeShap-aCAM) of the decision tree to be evaluated in a single clock cycle, thereby greatly shortening the time required to calculate the Shape value. In connection with this, the ability of the treeShap-aCAM to store / evaluate analog values (not merely binary values) may reduce the footprint and hardware required to perform Sharpley value calculations (e.g., reduce the number of CAM cells). Thus, the treeShap-aCAM may compute Sharpley values faster / more efficiently than other types of hardware accelerators, such as implementing algorithms that traverse the root-to-leaf paths of the decision tree in a node-to-node manner.

Description

Background Art

[0001] Content addressable memory ("CAM") is a type of computational memory in which stored data is searched by its content rather than its location. When a "word" is input to the CAM, the CAM searches for the word in its content. If the CAM finds the word (i.e., "returns a match"), the CAM returns the address of the location where the found word resides. The individual cells of the CAM (i.e., CAM cells) can be arranged in rows and columns. The CAM cells of a common row can be connected along a common match line. Words can be stored along the rows of the CAM, and each CAM cell of a given row can store an entry of the stored word. When the CAM receives an input word (e.g., a series of voltage signals, each voltage signal representing an entry of the input word, sometimes referred to as an input vector in this article), the CAM can search for the input word by entry along the columns of the CAM (i.e., the first entry of the input word can be searched down along the first column of the CAM, the second entry of the input word can be searched down along the second column of the CAM, etc.). If all CAM cells of a given row return a match for their respective entries of the input word, the CAM can "find" the input word in the given row.

[0002] An analog CAM ("aCAM") is a special type of CAM that can use the programmable conductance of a memristor to store and search a range of values ​​(in contrast to traditional digital-based CAMs that can only store / search zeros and ones). BRIEF DESCRIPTION OF THE DRAWINGS

[0003] The present disclosure is described in detail according to one or more various examples with reference to the following drawings. The drawings are provided for illustration purposes only and depict only examples.

[0004] Figure 1 An example aCAM cell is depicted according to examples of the disclosed technology.

[0005] Figure 2 Depicted is an example voltage range diagram according to an example of the disclosed technology.

[0006] Figure 3 Another example voltage range diagram is depicted according to examples of the disclosed technology.

[0007] Figure 4 An example decision tree according to an example of the disclosed technology is depicted.

[0008] Figure 5 Depicted are example feature chains according to examples of the disclosed technology.

[0009] Figure 6 Depicted is an example representation of a decision tree in an aCAM according to an example of the disclosed technology.

[0010] Figure 7 Depicted is an example process for calculating Shapley values ​​using an aCAM according to an example of the disclosed technology.

[0011] Figures 8A-8G Depicted is an example of a method for utilizing a Figure 7 Example procedure to calculate the Shapley value for an example use case.

[0012] Fig. 9 Depicted is a block diagram of an example computer system in which various examples described herein may be implemented.

[0013] The drawings are not exhaustive and do not limit the disclosure to the precise forms disclosed. DETAILED DESCRIPTION

[0014] Tree-based models (e.g., random forests, gradient boosted trees, etc., sometimes referred to herein as decision trees) are popular machine learning models because they are simple to train, perform well on small datasets (especially tabular datasets), and can provide human-interpretable explanations. Examples of human-interpretable explanations include Shapley values ​​(e.g., multi-valued vectors) that can measure the contribution of individual input features to the decisions of a tree-based model.

[0015] Traditionally, Shapley values ​​are a solution concept in cooperative game theory, where a coalition of "players" cooperates and obtains an overall benefit from the cooperation. In this context, Shapley values ​​(e.g., multi-valued vectors) measure the contribution of individual players in a coalition game to the overall benefit obtained through coalition cooperation. In other words, Shapley values ​​distribute the unique distribution of the total surplus / benefit generated through coalition cooperation among the individual players in the coalition game.

[0016] While Shapley values ​​can provide useful / insightful human-interpretable explanations for machine learning applications, the historical barrier to real-time (or near real-time) machine learning model interpretability has been the complexity, processing time, and hardware overhead required to compute Shapley values ​​by conventional methods. Real-time (or near real-time) human interpretability can be extremely advantageous in time-sensitive applications (e.g., guiding surgical interventions) where humans need to make rapid decisions based on machine learning model outputs. Therefore, there is a significant opportunity for hardware accelerators that can compute Shapley values ​​with improved speed / efficiency.

[0017] In this context, examples of the disclosed technology provide hardware accelerators (referred to herein as treeSHAP-aCAM) that exploit the unique parallel search and simulation capabilities of aCAM to compute Shapley values ​​with improved speed / efficiency. For example, the parallel search capabilities of treeSHAP-aCAM enable all root-to-leaf paths of a decision tree (programmed into separate rows of treeSHAP-aCAM) to be evaluated within a single clock cycle, thereby greatly reducing the time required to compute Shapley values. Relatedly, the ability of treeSHAP-aCAM to store / evaluate simulated values ​​(rather than just binary values) can reduce the footprint and hardware required to perform Shapley value calculations (e.g., reducing the number of CAM cells). Therefore, treeSHAP-aCAM can compute Shapley values ​​faster / more efficiently than other types of hardware accelerators, such as those that implement algorithms that traverse the root-to-leaf paths of a decision tree in a node-to-node manner.

[0018] Before describing the treeSHAP-aCAMs of the disclosed technique in more detail, it should be understood that implementing (i.e., programming and evaluating) Shapley problems using aCAMs presents technical / computational challenges because Shapley problems are traditionally formulated using binary values / expressions. In contrast, aCAMs are traditionally used to implement problems involving analog values / expressions. As mentioned above, this analog capability of aCAMs allows them to implement problems more efficiently (e.g., using less hardware) than binary / digital alternatives.

[0019] To address the technical / computational challenges described above, examples of the disclosed technology provide a new approach that enables Shapley value computation using analog values / expressions that are compatible with and take advantage of aCAM's unique analog and parallel search capabilities. Thus, using this new analog value / expression-oriented Shapley value computation approach, the disclosed technology's treeSHAP-aCAM can utilize aCAM to compute Shapley values ​​faster / more efficiently than other types of hardware accelerators.

[0020] For example, a treeShap-aCAM of the present technology may include: (1) an analog content addressable memory (aCAM), wherein each row of the aCAM is programmed to represent a separate root-to-leaf path of a decision tree, including evaluable conditions involving (M) features; and (2) one or more processing resources (e.g., a combination of logic circuits and one or more processors) that operate to: (a) apply a first foreground input vector to the aCAM, wherein: (i) a first value of the (M) total values ​​of the first foreground input vector represents a first feature of the (M) features from a foreground sample, and (ii) the remaining (M-1) values ​​of the (M) total values ​​of the first foreground input vector represent wildcard values ​​(sometimes referred to as "don't care" or "always match" values). (b) applying a first background input vector to aCAM, wherein: (i) a first value of the (M) total values ​​of the first background input vector represents a first feature of the (M) features from the background sample, and (ii) the remaining (M-1) values ​​of the (M) total values ​​of the first background input vector represent wildcard values; (c) calculating a first iteration of Shapley value calculation parameters based on the match line output from aCAM in response to applying the first foreground and background input vectors; (d) iterating steps (a)-(c) for each of the (M) features of the foreground sample and the background sample to generate subsequent iterations of Shapley value calculation parameters; and (e) calculating a Shapley value for the foreground sample based on the final iteration of the Shapley value calculation parameters. As mentioned above, the Shapley value may include a multi-value vector that measures the contribution of each feature of the foreground sample to the decision of the decision tree based model.

[0021] In various embodiments, iterating steps (a)-(c) for a second feature among the (M) features of the foreground sample and the background sample may include: (a) applying a second foreground input vector to the aCAM, wherein: (i) a second value among the (M) total values ​​of the second foreground input vector represents a second feature among the (M) features from the foreground sample, and (ii) the remaining (M-1) values ​​among the (M) total values ​​of the second foreground input vector represent wildcard values; (b) applying a second background input vector to the aCAM, wherein: (i) a second value among the (M) total values ​​of the second background input vector represents a second feature among the (M) features from the background sample, and (ii) the remaining (M-1) values ​​among the (M) total values ​​of the second background input vector represent wildcard values; and (c) calculating a second iteration of Shapley value calculation parameters based on match line output from the aCAM in response to applying the second foreground and background input vectors.

[0022] In some embodiments, the Shapley value calculation parameters may include: (1) a vector N, which, for each root-to-leaf path of the decision tree, represents the total number of unique features in the root-to-leaf path (here, the dimension of the vector N may correspond to the number of root-to-leaf paths of the decision tree); (2) a vector S, which, for each root-to-leaf path of the decision tree, represents the total number of features of the root-to-leaf path that match the foreground sample (here again, the dimension of the vector S may correspond to the number of root-to-leaf paths of the decision tree); (3) a matrix U, which, for each root-to-leaf path of the decision tree, represents the matrix S applied when calculating the Shapley value of the foreground sample. offset (here, the number of rows of matrix U may correspond to the number of root-to-leaf paths of the decision tree, and the number of columns of matrix U may correspond to the number of features of foreground / background samples); (4) a matrix V, for each root-to-leaf path of the decision tree, the matrix V represents the contribution type of the root-to-leaf path (here again, the number of rows of matrix V may correspond to the number of root-to-leaf paths of the decision tree, and the number of columns of matrix V may correspond to the number of features of foreground / background samples); and (5) a vector P, for each root-to-leaf path of the decision tree, the vector P represents the path validity of the root-to-leaf path (here again, the dimension of vector P may correspond to the number of root-to-leaf paths of the decision tree).

[0023] In some embodiments, a first iteration of calculating the vector N may include: adding the first foreground matching line output vector y to the all-zero vector f1 Output vector y matching the first background line b1 The first foreground match line output vector represents the match line output in response to applying the first foreground input vector to aCAM, and the first background match line output vector represents the match line output in response to applying the first background input vector to aCAM. Here, the all-zero vector, the first foreground match line output vector y f1 and the first background matching line output vector y b1 All may have dimensions corresponding to the number of root-to-leaf paths of the decision tree (which again also corresponds to the number of programmed rows of the aCAM). Similarly, a first iteration of computing vector S may include: adding the first foreground match line output vector y to the all-zero vector f1 Output vector y matching the first background line b1 The first iteration of computing the matrix U may include: outputting the vector y by the first foreground matching line f1 Output vector y matching the first background line b1 The first iteration of computing the matrix V may include: outputting the vector y from the first foreground matching line f1 Output vector y matching the first background lineb1 The first matching line output vector y is subtracted from the AND of the inverse f1 The inverse of the first background matching line output vector y b1 Finally, the first iteration of computing the vector P may include: adding the first foreground matching line output vector y to the all-ones vector (also having a dimension corresponding to the number of root-to-leaf paths of the decision tree / the number of programmed rows of the aCAM) f1 and the first background matching line output vector y b1 A disjunction (i.e., a logical OR operation) is performed between the two.

[0024] In various embodiments, calculating the second iteration of vector N may include: adding the second foreground matching line output vector y to the first iteration of vector N f2 Output vector y matching the second background line b2 , the second foreground match line output vector represents the match line output in response to applying the second foreground input vector to aCAM, and the second background match line output vector represents the match line output in response to applying the second background input vector to aCAM. Similarly, calculating the second iteration of vector S may include: adding the second foreground match line output vector y to the first iteration of vector S f2 Output vector y matching the second background line b2 The second iteration of calculating the matrix U may include: outputting the vector y by the second foreground matching line f2 Output vector y matching the second background line b2 The second iteration of computing the matrix V may include: by outputting the vector y from the second foreground matching line f2 Output vector y matching the second background line b2 The second foreground matching line output vector y is subtracted from the inverse of f2 The inverse of the second background matching line output vector y b2 Finally, the second iteration of calculating the vector P may include: in the first iteration of the vector P and the second foreground matching line output vector y f2 and the second background matching line output vector y b2 Between or between execute and.

[0025] Equation 1 below illustrates a generalized expression that treeSHAP-aCAM of the disclosed technology can use to calculate the Shapley value calculation parameters. Here, x f represents a foreground sample including a total of (M) features, x brepresents the background samples which also include a total of (M) features, Tl represents the lower boundary threshold programmed into aCAM, Th represents the upper boundary threshold programmed into aCAM, and the other variables / symbols represent the vectors / matrices described above.

[0026]

[0027] In some embodiments, one or more processing resources may be further operable to: in response to a final iteration of steps (a)-(c), update a final iteration of matrix V by performing an AND between the final iteration of matrix V and the final iteration of vector P. This operation may be performed to ensure that only valid root-to-leaf paths of the decision tree contribute to the calculated Shapley value. Thus, calculating the Shapley value of the foreground sample based on the final iteration of the Shapley value calculation parameters may include: calculating the Shapley value of the foreground sample based on the final iteration of vector N, the final iteration of vector S, the final iteration of matrix U, the updated final iteration of matrix V, and a vector v representing leaf values ​​of the decision tree (also having a dimension corresponding to the number of root-to-leaf paths of the decision tree).

[0028] In some embodiments, the treeShap-aCAM may further include a resistive random access memory (ReRAM) that stores leaf values ​​of the decision tree. In these examples: (1) the first row of the aCAM may be programmed to store a first root-to-leaf path of the decision tree; (2) the first row of the ReRAM may be programmed to store leaves of the first root-to-leaf path; and (3) the first row of the ReRAM may be electrically connected to the match lines of the first row of the aCAM. Similarly: (1) the second row of the aCAM may be programmed to store a second root-to-leaf path of the decision tree; (2) the second row of the ReRAM may be programmed to store leaves of the second root-to-leaf path; and (3) the second row of the ReRAM may be electrically connected to the match lines of the second row of the aCAM.

[0029] In some of the embodiments described above, the first column of the aCAM may store an evaluable condition corresponding to a first feature of a foreground sample and a background sample of a decision tree. In this regard, the second column of the aCAM may store an evaluable condition corresponding to a second feature of a foreground sample and a background sample of a decision tree. In these examples, the first value of the (M) total values ​​of the first foreground input vector (representing the first feature of the foreground sample) may be applied to the first column of the aCAM. In this regard, the first value of the (M) total values ​​of the first background input vector (representing the first feature of the background sample) may be applied to the first column of the aCAM. In these examples, the second value of the (M) total values ​​of the second foreground input vector (representing the second feature of the foreground sample) may be applied to the second column of the aCAM. In this regard, the second value of the (M) total values ​​of the second background input vector (representing the second feature of the background sample) may be applied to the second column of the aCAM. Here, the aCAM cells belonging to the first row and the first column of the aCAM may be programmed to store one or more evaluable conditions corresponding to the first feature of the foreground sample and the background sample of the first root-to-leaf path. As described in more detail below, the aCAM cell may include two memristors. Thus, programming the aCAM cell to store the one or more evaluable conditions of the first root-to-leaf path corresponding to the first characteristics of the foreground sample and the background sample may include programming the conductance of the two memristors. As mentioned above, programming the conductance of the two memristors may cause the aCAM cell to store a lower boundary threshold voltage and an upper boundary threshold voltage representing the one or more evaluable conditions of the first root-to-leaf path corresponding to the first characteristics of the foreground sample and the background sample.

[0030] Examples of the present technology will be described in more detail in conjunction with the following figures. Figure 1-6 A general background is described that may help understand the advantages provided by treeSHAP-aCAM when computing Shapley values ​​compared to conventional hardware accelerators. Figure 7 as well as Figures 8A-8G A new Shapley value calculation method for analog values / expressions is illustrated, which is utilized by examples of the disclosed technology to implement the Shapley problem in aCAM. Fig. 9 Depicted is a block diagram of an example computer system in which various examples described herein may be implemented.

[0031] Reference now Figure 1 , Figure 1 An example conventional aCAM cell 100 is depicted. The aCAM cell 100 may be an example of a 6-transistor-2-memristor (6T2M) aCAM cell.

[0032] The aCAM cell 100 is electrically connected to a match line (i.e., ML 102), which may be precharged to a high voltage. The aCAM cell 100 may "return to match" when the voltage across the ML 102 remains high, and "return to mismatch" when the voltage across the ML 102 is discharged. As described above, the aCAM cell 100 may be an aCAM cell in a row of an aCAM. In some examples, the match / mismatch results for the entire row (of which the aCAM cell 100 is a part) may be output to another circuit (e.g., a resistive random access memory array (reRAM)) for further processing / classification.

[0033] The aCAM cell 100 also includes two data lines: DL1 106 and DL2 108 (in Figure 1 ), both of which are electrically connected to an input data line: DL 104. The aCAM cell 100 may receive an analog input voltage signal V(x) along DL 104 (here, the analog input voltage signal V(x) may be an analog voltage signal converted from a digital input signal x). As depicted, both DL1 106 and DL2 108 are electrically connected to DL 104 and are electrically connected in parallel with respect to each other. Thus, the analog input voltage signal V(x) may be applied along DL1 106 and DL2 108, respectively. As mentioned above, if the analog input voltage signal V(x) exceeds the analog voltage range programmed in the aCAM cell 100, the analog input voltage signal V(x) will eventually discharge the ML 102. Here, the analog voltage range stored by the aCAM cell 100 is set / defined by the programmed conductance of the memristors M1 and M2. The programmed conductance of memristor M1 sets / defines the lower bound of the stored analog voltage range, and the programmed conductance of memristor M2 sets / defines the upper bound of the stored analog voltage range (see e.g. Figure 2 ).

[0034] As depicted, aCAM cell 100 includes a “lower bound side” 110 and an “upper bound side” 120 , so called because memristors M1 and M2 are programmed to set the lower and upper bounds, respectively, of the analog voltage range stored by aCAM cell 100 .

[0035] The lower boundary side 110 includes a transistor T1 and a memristor M1 electrically connected in series with each other. The memristor M1, in conjunction with the transistor T1, defines a voltage divider subcircuit 112. As depicted, the voltage divider subcircuit 112 generates a gate voltage G1 across the pull-down transistor T2. When the gate voltage G1 across the pull-down transistor T2 exceeds a threshold, the pull-down transistor T2 will turn on / activate and "pull down" (i.e., discharge) the voltage across the ML 102, returning the mismatch. As described above, the voltage across the pull-down transistor T2 is affected by: (1) the programmed conductance of the memristor M1; and (2) the analog input voltage signal V(x). In particular, when the analog input voltage signal V(x) is greater than or equal to a threshold voltage (e.g., T L ), transistor T1 will become more conductive (the programmed conductance of memristor M1 will remain unchanged during the search operation), and therefore the voltage between SL_hi and SL_lo (usually at ground (GND)) will drop across memristor M1, resulting in a small gate voltage G1 that does not turn on / activate pull-down transistor T2, resulting in a match result on the lower boundary side 110. Here, T L The value of (i.e., the threshold voltage that will cause transistor T1 to become more conductive relative to memristor M1) can be programmed by programming the conductance of memristor M1. In this way, the programmed conductance of memristor M1 can be used to set the lower bound of the voltage range stored by aCAM cell 100.

[0036] Similar to the lower bounding side 110, the upper bounding side 120 includes a transistor T3 and a memristor M2 electrically connected in series with each other. The memristor M2, in conjunction with the transistor T3, defines a voltage divider subcircuit 122. The upper bounding side 120 is slightly different from the lower bounding side 110 because the voltage divider subcircuit 122 is electrically connected to the input of an inverter 124 (here, the series combination of transistors T4 and T5 operate together to include the inverter 124). The inverter 124 operates to invert the voltage output by the voltage divider subcircuit 122. Because the pull-down transistor T6 is electrically connected to the output of the inverter 124, the inverted voltage output by the inverter 124 controls the gate voltage G2 across the pull-down transistor T6. Similar to the above case, when the gate voltage G2 across the pull-down transistor T6 exceeds the threshold, the pull-down transistor T6 will turn on / activate and "pull down" (i.e., discharge) the voltage across the ML 102, thereby returning the mismatch. As described above, the voltage across the pull-down transistor T6 is affected by: (1) the programmed conductance of the memristor M2; and (2) the analog input voltage signal V(x). In particular, when the analog input voltage signal V(x) is less than or equal to the threshold voltage (e.g., TH), the transistor T3 will not be highly conductive (e.g., having a conductance of approximately 10 nS compared to a higher conductance state of, for example, 10 mS), and thus the voltage between SL_hi and SL_lo (which are typically at ground (GND)) will remain high across the transistor T3, thereby producing a high voltage output of the voltage divider subcircuit 122. However, when this high voltage is inverted by the inverter 124, the inverted (now low) voltage causes a low gate voltage G2, which does not turn on / activate the pull-down transistor T6, thereby producing a matching result for the upper boundary side 120. Here, the value of TH (i.e., the threshold voltage that will cause transistor T3 to not be highly conductive relative to memristor M2) can be programmed by programming the conductance of memristor M2. In this way, the programmed conductance of memristor M2 can be used to set the upper limit of the voltage range stored by aCAM cell 100.

[0037] As mentioned above (and as will be combined with Figure 3 1 and 2. In some embodiments, the aCAM cell 100 may be programmed to a wildcard value ...

[0038] It should be understood that aCAM cell 100 is only one example of an aCAM cell that may be used in conjunction with the disclosed techniques. For example, some embodiments may utilize an aCAM cell that utilizes "pull-up" logic rather than incorporating Figure 1 The "pull-down" logic described.

[0039] Figure 2 An example diagram is depicted illustrating how memristors M1 and M2 from an aCAM cell 100 may be used to set a lower boundary voltage 202 and an upper boundary voltage 204 of a stored voltage range of the aCAM cell 100. As depicted, the aCAM cell 100 will return a match for the analog input voltage signal V(x) when the analog input voltage signal V(x) is within the voltage range defined by the lower boundary voltage 202 and the upper boundary voltage 204. The aCAM cell 100 will return a mismatch when the analog input voltage signal V(x) is outside the voltage range defined by the lower boundary voltage 202 and the upper boundary voltage 204. As described above, the conductance of the memristors M1 and M2, respectively, may be programmed to set / define the lower boundary voltage 202 and the upper boundary voltage 204.

[0040] Figure 3 An example diagram is described that illustrates how memristors M1 and M2 from an aCAM cell 100 can be programmed to store an open voltage range (i.e., a stored voltage range that is effectively unbounded on at least one end) for the aCAM cell 100. As depicted, the aCAM cell 100 will return a match for the analog input voltage signal V(x) whenever the analog input voltage signal V(x) is greater than or equal to the lower boundary voltage 302 set by the memristor M1. In other words, the aCAM cell 100 will only return a mismatch when the analog input voltage signal V(x) is less than the lower boundary voltage 302. As described above, the conductance of the memristor M1 can be programmed to set the lower boundary voltage 302.

[0041] Here, Figure 3 and Figure 2Differently, because the conductance of the memristor M2 has been programmed to a "wildcard" value (sometimes referred to as a "don't care" value) that actually always returns a match for the upper boundary side 120 of the aCAM cell 100 (i.e., returns a match for the upper boundary side 120 of the aCAM cell 100 for any value of the analog input voltage signal V(x) that will be received by the aCAM cell 100 in practice). In general, the deep conductance states of the memristor can be used as wildcard values ​​that actually set the open lower and upper boundaries of the aCAM cell. These deep conductance states (e.g., the deep low conductance state (DLCS) for the lower boundary wildcard value and the deep high conductance state (DHCS) for the upper boundary wildcard value) will be far beyond the reliably programmable conductance range of the memristor. For example, if the memristor of an aCAM cell 100 is programmed to be within the range [1uS, 100uS], then deep conductance states of, for example, 0.01uS and 1000uS can be used to actually set wildcard values ​​for the open lower and upper boundaries of the aCAM cell 100, respectively. These deep conductance states are typically difficult to program in a reliable manner, and are therefore reserved for wildcard values ​​where, for example, 10% error in programming may be acceptable. By programming the memristor of an aCAM cell 100 to the wildcard value / deep conductance state, an example can set deep state lower and upper voltage boundaries that are actually open. In other words, because in practice the input / search voltage value received by the aCAM cell / subcircuit will typically always be within the deep state lower and upper voltage boundaries set by programming the memristor of the aCAM cell / subcircuit to the wildcard value, it can be generally stated that the programmed wildcard value always returns a match.

[0042] Therefore, in Figure 3 , memristor M2 actually sets an open "upper boundary" of the analog voltage range stored by the aCAM cell 100. It will be appreciated that in other examples, the conductance of memristor M2 may be programmed to set a "real" upper boundary voltage (i.e., an upper boundary voltage that actually defines the "less than or equal to" condition at the upper boundary), and the conductance of memristor M1 may be programmed to a "wildcard" value that actually always returns a match for the lower boundary side 110 of the aCAM cell 100 (i.e., such programming may actually store an open voltage range that is only actually bounded at the upper end). Similarly, in certain examples, the conductances of memristors M1 and M2 may be programmed to "wildcard" values ​​such that the aCAM cell 100 actually always returns a match (i.e., returns a match for any value of the analog input voltage signal V(x) that the aCAM cell 100 would in practice receive).

[0043] As mentioned above, aCAM cells may be programmed to wildcard values ​​to represent features that are not evaluated in the root-to-leaf path.

[0044] Figure 4-6 Illustrates how an example decision tree 402 can be represented in aCAM.

[0045] As Figure 4 depicted therein, the decision tree 402 can include a set of decision nodes that includes a root decision node 404, various intermediate decision nodes (e.g., intermediate decision node 406), and various leaf nodes (e.g., leaf node 408) that represent the end points of the decision tree 402. It should be understood that the decision tree 402 is merely an illustrative embodiment of a decision tree.

[0046] The decision tree 402 can include multiple root-to-leaf paths. Each root-to-leaf path represents a traversal of a series of decision nodes. For example, a root-to-leaf path can start at the root decision node 404, traverse one or more intermediate decision nodes, and end at a leaf node. Each decision node traversed in a root-to-leaf path can represent an evaluable condition on which the features of the feature vector 400 can be evaluated. Thus, a root-to-leaf path represents a series of evaluable conditions that represent logical rules on which the feature vector 400 can be evaluated.

[0047] In Figure 4 the example root-to-leaf path 410 shown therein, the series of evaluable conditions can start with a condition that is evaluated at the root decision node 404, which is illustratively depicted as involving the feature f1 of the feature vector 400. In the example decision tree 402, evaluating the condition represented by any given decision node can result in one of two possible outcomes (labeled outcome "a" and outcome "b"). In some examples, outcome "b" represents that the condition is not satisfied when evaluated, and outcome "a" represents that the condition is satisfied when evaluated. For example, if the evaluable condition at the root node 404 is whether f1 is less than the value x1, then outcome "b" can represent the negated determination (i.e., f1 ≥ x1), and outcome "a" can represent the affirmative determination (i.e., f1 < x1). It should be understood that in other embodiments, more than two outcomes may be possible for the evaluable conditions associated with a decision node.

[0048] In the example root-to-leaf path 410, the result of the determination at the root decision node 404 is graphically depicted as a result "b", which indicates that the condition involving feature f1 evaluated at the root decision node 404 is not satisfied. Based on this result, the root-to-leaf path 410 transitions from the root decision node 404 to the intermediate decision node 406. The transition from the first decision node to the second decision node within a given root-to-leaf path is represented as a combination of the condition evaluated at the first decision node and the result of the evaluation. For example, the transition from the root decision node 404 to the intermediate decision node 406 in the example root-to-leaf path 410 is represented as f1 condition 1b. Using this convention, the example root-to-leaf path 410 can be represented by the following decision node transitions: f1 condition 1b to f3 condition 1b to f2 condition 2a to class 2. Each other root-to-leaf path in the decision tree 402 can also be similarly represented as a series of decision node transitions, which indicate the conditions evaluated at each decision node combined with the result of the evaluation.

[0049] In various examples, the information contained in the decision tree 402 can be converted into an alternative representation (such as a tabular representation). In particular, each root-to-leaf path in the decision tree 402 can be represented as a tabular representation (referred to herein as a "feature chain" and in Figure 5 ) in the corresponding columns in the aCAM. For example, the decision tree may be reformulated for an aCAM implementation by: reformulating the decision tree to represent each root-to-leaf path as a feature chain having a series of feature chain nodes; combining multiple evaluable conditions involving separate features for the root-to-leaf path into one feature chain node; adding a "wildcard" feature chain node to account for features that are not evaluated in the root-to-leaf path; and rotating (i.e., matrix transforming) the representation and mapping each feature chain to each row in the aCAM so that the columns of the aCAM correspond to the feature vectors.

[0050] For example, Figure 4 The example root-to-leaf path 410 illustrated in FIG. 4 may be converted into a feature chain 512. The feature chain nodes in the feature chain 512 may correspond to one or more decision node transitions in the corresponding root-to-leaf path 410. More specifically, each feature chain node in the feature chain 512 corresponds to a corresponding feature in the feature vector 400. Because the feature vector 400 is schematically depicted as including four features (f1, f2, f3, f4), each feature chain associated with the decision tree 402 may include four feature chain nodes corresponding to the four features, and leaf nodes representing the leaf nodes of the corresponding root-to-leaf path. It should be appreciated that the feature vector 400 may include any number of features, in which case the corresponding feature chain may include a corresponding number of feature chain nodes together with leaf nodes. In some examples, the leaf nodes may also correspond to features (e.g., optimization parameters) that form part of the feature vector 400.

[0051] As mentioned above, some root-to-leaf paths may not include evaluable conditions for one or more features. For example, root-to-leaf path 410 does not include evaluable conditions for feature f4. Therefore, a "wildcard" feature chain node (i.e., a feature chain node including a wildcard value) may be included to illustrate features not involved in any evaluable conditions for a given root-to-leaf path. Feature chain 512 includes such a wildcard feature chain node for feature f4 because root-to-leaf path 410 (corresponding to feature chain 512) does not include evaluable conditions involving feature f4. This means that any value specified for feature f4 in a search query will generate a match about feature f4 when evaluating feature chain 512 (after the feature chain has been encoded in aCAM).

[0052] Regarding converting the representation of the domain logic rule set from the decision tree 402 to Figure 5 400. In the tabular representation of the root-to-leaf path, when determining the sequence of corresponding feature chain nodes in the feature chain representing the root-to-leaf path, the decision nodes within a given root-to-leaf path can be merged and / or reordered. For example, in the sequence of decision nodes traversed as part of the root-to-leaf path 410, the evaluable condition involving feature f3 appears before the evaluable condition involving feature f2. However, before encoding the feature chain 512 in the aCAM, the sequence of evaluable conditions represented by the root-to-leaf path 410 can be reordered to ensure that the sequence of evaluable conditions in the corresponding feature chain 512 matches the sequence of features in the feature vector 400. As part of converting the root-to-leaf path to the corresponding feature chain in the tabular representation, this reordering can occur as needed for each root-to-leaf path in the decision tree 402.

[0053] For example, each feature chain in the table representation (e.g., each column in the table) may represent a feature chain node starting with an evaluable condition involving feature f1 in the corresponding root-to-leaf path, followed by an evaluable condition involving feature f2, and so on, until the penultimate feature chain node in the feature chain is the one involving the last feature f of the feature vector. n (e.g., feature f4 in feature vector 400), where the final node of the feature chain includes appropriate leaf nodes (alternatively, each leaf node may correspond to the last feature f in the feature vector n ).

[0054] In some examples, converting a root-to-leaf path to a corresponding feature chain may include: merging two or more decision node transitions in the root-to-leaf path into a single feature chain node in the feature chain. For example, consider a root-to-leaf path in decision tree 402 that includes the following decision node transitions: f1 condition 1a to f4 condition 1b to f1 condition 2a to class 2. The two decision node transitions in this example path occur due to evaluation conditions involving feature f1. Thus, these two decision node transitions can be merged into a single feature chain node associated with feature f1 in the corresponding feature chain 514 (represented as f1 condition 1a+2a). For example, if f1 condition 1a represents f1>x1 and if f1 condition 2a represents f1<x2, the combined result (i.e., x1<f1<x2) can be represented in the first feature chain node of feature chain 514 (i.e., the feature chain node associated with feature f1). Merging multiple decision node transitions involving a particular feature variable into a single merged feature chain node for that feature variable can increase memory density and reduce the amount of area required when encoding the set of logic rules represented by decision tree 402 into a CAM.

[0055] The set of all root-to-leaf paths represented in decision tree 402 can be converted to a corresponding set of feature chains according to the method described above.

[0056] Once the conversion process is complete and a tabular representation of the domain logic rules is generated, each feature chain in the tabular representation can be rotated and mapped to Figure 6 the corresponding rows of a CAM 616. In some examples, the sequence of feature chains in the tabular representation can be specified by a convention that defines the order in which decision tree 402 is traversed to cover all the root-to-leaf paths represented in decision tree 402. Further, in some examples, the sequence of feature chains in the tabular representation can be mapped and encoded into the rows of a CAM 616 in the same order. In other examples, the ordering of the feature chains may be irrelevant as long as each root-to-leaf node in decision tree 402 is converted to a corresponding feature chain, and each feature chain is mapped to and encoded in the corresponding row of a CAM 616.

[0057] As Figure 6 shown, feature chain 512 can be mapped to and encoded in a particular row of a CAM 616 (e.g., CAM row N-1). More specifically, the corresponding one or more CAM cells in row N-1 can be used to store each value represented in each feature chain node of feature chain 512. Each other feature chain (such as, for example, feature chain 514) can be similarly mapped to and encoded in the corresponding row of a CAM 616 (not shown).

[0058] In some examples, the values ​​represented in the feature chain nodes of feature chain 512 may actually be value ranges. As previously noted, aCAM 616 provides the ability to store and encode such value ranges. The number of aCAM cells required to encode the value / value range corresponding to a particular feature (e.g., feature f1) across all feature chains (i.e., the number of aCAM cell columns corresponding to feature f1) may depend on the level of precision required to encode such value / value range. For features in feature vector 400 that are categorical variables that present only a limited number of discrete values ​​(e.g., a set of all origin or destination airports), a single column of aCAM cells may be sufficient to represent all stored values ​​of the feature across the entire set of domain logic rules. On the other hand, for features corresponding to numerical variables that can present a large number of possible values ​​(e.g., a continuous range of values), multiple columns of aCAM cells may be required to provide the bit precision required to store such values.

[0059] In some examples, the output parameters of each feature chain (domain logic rule) encoded in aCAM 616 may actually be stored in a memory array separate from aCAM 616. Figure 4 As schematically shown in , each of the leaf nodes of the decision tree 402 represents a classification output that may be stored in a random access memory (RAM) 618 that is separate from the aCAM 616 (in some examples, the RAM 618 may include a resistive random access memory (ReRAM)). This may then allow multiple matches to be returned for the search query. In some examples, the search query may conform to the format of the feature vector 400, and a discrete value, a range of values, or a "wildcard" value may be specified for each search variable (i.e., each feature in the feature vector 400). The search query may then be searched in parallel for each row in the aCAM 616 to determine whether the search query matches a stored value in any such row. Each row of the aCAM 616 may represent a storage word that corresponds to a particular feature chain, and therefore a particular root-to-leaf path in the decision tree 402. In some examples, the storage word may include only those values ​​stored in a particular row of the aCAM 616. In other examples, a memory word may include the value of a particular aCAM row and a corresponding value of an output parameter (eg, a classification output value) stored in RAM 618 .

[0060] In some examples, the output parameter (e.g., the classification output represented by the leaf node of the decision tree 402) can be a parameter that the user is trying to optimize. For example, the search query can specify a maximum or minimum allowed value for the optimization parameter, in which case any such row in the aCAM 616 can be returned as a matching result, i.e., the row matches each of the restricted and / or flexible parameter values ​​specified in the search query and satisfies the value specified for the optimization parameter. More specifically, the address of any such matching row in the aCAM 616 can be returned as a search result. Optionally, the corresponding value of the optimization parameter stored in the RAM 618 (or the corresponding value of the memory address in the RAM 618) can also be returned.

[0061] In other examples, rather than searching the aCAM 616 for storage rows corresponding to output parameter values ​​below or above the specified value as part of the optimization process, the search query may instead specify an output parameter value that is desired to be an exact match among the output parameter values ​​stored in the RAM 618. For example, in such examples, the search query may only produce a match if: (1) all other search parameter values ​​specified in the search query match the corresponding stored values ​​in a given row of the aCAM 616; and (2) the output parameter value specified in the search query exactly matches the value stored in the RAM 618 that corresponds to the row in the aCAM 616. Thus, in such examples, such a search query would not produce a match at storage word N-1, i.e., the search query includes search variable values ​​that satisfy the first four feature chain nodes of the feature chain 512, but specifies "class 3" for the output parameter value.

[0062] In yet other examples, the search query may specify exclusive values ​​for the output parameter. For example, the search query may specify "class 2" as Figure 4 Such an example search query will then produce matching results for any row in aCAM 616, and therefore for any feature chain in the tabular representation and corresponding root-to-leaf path in decision tree 402, that matches each of the other restricted parameters in the search query and corresponds to a stored output parameter value other than "Class 2". This may represent a mechanism for optimizing output parameters by specifying values ​​to be excluded from matching rather than by iterative adjustment of the optimization parameters.

[0063] Figure 7 An example process 700 for calculating Shapley values ​​using an aCAM according to various examples of the disclosed technology is illustrated. Process 700 may be performed by treeSHAP-aCAM of the disclosed technology.

[0064] Before describing process 700 in more detail, it may be useful to provide some background regarding Shapley value calculations / Shapley values.

[0065] As mentioned above, Shapley value is a solution concept in cooperative game theory, where a coalition of "players" cooperates and obtains an overall benefit from the cooperation. In this context, Shapley value (e.g., a multi-valued vector) measures the contribution of individual players in the coalition game to the overall benefit obtained through the coalition cooperation. In other words, Shapley value distributes the unique distribution of the total surplus / benefit generated by the coalition cooperation among the individual players in the coalition game. The following equation 2 illustrates the Shapley value (i.e., ) is an example calculation.

[0066]

[0067] As depicted, The term represents the coalition occurrence probability weight, and the term v(S∪{i})-v(S) represents the marginal contribution from all coalitions. N (e.g., a matrix) may include all possible player coalitions (i.e., player subsets). Therefore, N\{i} may include all possible player coalitions excluding the i-th player. S is a coalition / subset of N, and |S| represents the size of coalition S. v is a characteristic function that maps player coalitions to real numbers. Therefore, v(S) (sometimes called the value of coalition S) describes the sum of the total expected benefits that members of coalition S can obtain through cooperation.

[0068] Related to the above, we can calculate the foreground sample x f The decision tree model of f predicts the Shapley value of the i-th feature of f, as illustrated in the following Equation 3:

[0069]

[0070] v(S)=f(h S ),in If i∈S, otherwise Equation 3

[0071] Here, x b represents background samples, which are used to represent missing features. In contrast to the conventional binary representation of features in the above-mentioned alliance game, the values ​​of foreground samples in the decision tree model can be simulated values. Unlike binary values ​​(e.g., 0 or 1), simulated values ​​do not have a single counterpart. Therefore, examples of the disclosed technology can utilize background samples (i.e., x) that include simulated values. b ), the background sample corresponds to the absence of feature(s). Thus, the presence of feature(s) may correspond to foreground samples, while the absence of feature(s) may correspond to background samples.

[0072] h is a function that maps the coalition S to a real vector. B is the number of background samples in the problem.

[0073] As mentioned above, while Shapley values ​​can provide useful / insightful human-interpretable explanations for machine learning applications, the historical barrier to real-time (or near real-time) machine learning model interpretability has been the complexity, processing time, and hardware overhead required to compute Shapley values ​​via conventional methods. Real-time (or near real-time) human interpretability can be extremely advantageous in time-sensitive applications (e.g., guiding surgical interventions) where humans need to make decisions quickly based on machine learning model outputs. Therefore, there is a significant opportunity for hardware accelerators that can compute Shapley values ​​with improved speed / efficiency.

[0074] Against this background, examples of the disclosed technology provide hardware accelerators (referred to herein as treeSHAP-aCAM) that exploit the unique parallel search and simulation capabilities of aCAM to compute Shapley values ​​with improved speed / efficiency. For example, the parallel search capabilities of treeSHAP-aCAM enable all root-to-leaf paths of a decision tree (programmed into separate rows of treeSHAP-aCAM) to be evaluated within a single clock cycle, thereby greatly reducing the time required to compute Shapley values. Relatedly, the ability of treeSHAP-aCAM to store / evaluate simulated values ​​(rather than just binary values) can reduce the footprint and hardware required to perform Shapley value calculations (e.g., reducing the number of CAM cells). Therefore, treeSHAP-aCAM can compute Shapley values ​​faster / more efficiently than other types of hardware accelerators, such as those that implement algorithms that traverse the root-to-leaf paths of a decision tree in a node-to-node manner.

[0075] As mentioned above, implementing (i.e., programming and evaluating) Shapley problems using aCAM presents technical / computational challenges because Shapley problems are traditionally formulated using binary values / expressions. In contrast, aCAMs are traditionally used to implement problems involving analog values / expressions. As mentioned above, this analog capability of aCAMs allows them to implement problems more efficiently (e.g., using less hardware) than binary / digital alternatives.

[0076] To address the technical / computational challenges described above, examples of the disclosed technology provide a new approach that enables Shapley value computation using analog values / expressions that are compatible with and exploit the unique analog and parallel search capabilities of aCAM. Thus, using this new analog value / expression-oriented Shapley value computation approach, treeSHAP-aCAM can utilize aCAM to compute Shapley values ​​faster / more efficiently than other types of hardware accelerators.

[0077] Figure 7 The process 700 of FIG. 1 illustrates such a Shapley value calculation method for analog values / expressions. Again, the process 700 may be performed by the treeSHAP-aCAM of the disclosed technology. The treeSHAP-aCAM may include: an aCAM (e.g., Figure 6 aCAM616); a combination of logic circuits (among other things) that iteratively calculate Shapley value calculation parameters based on the match line outputs from the aCAM; and one or more hardware processors (among other things) that calculate the Shapley value based on the final iteration of the Shapley value calculation parameters.

[0078] As depicted, treeSHAP-aCAM may begin process 700 by programming rows of aCAM to store root-to-leaf paths of a decision tree. For example, if a decision tree includes a number (L) of root-to-leaf paths, treeSHAP-aCAM may program the (L) root-to-leaf paths into the (L) rows of aCAM. In various embodiments, such programming may be implemented by the one or more hardware processors of treeSHAP-aCAM and / or logic circuits of treeSHAP-aCAM.

[0079] A decision tree may include evaluable conditions involving (M) features. Figure 4-6 As described, programming a row of an aCAM to store a root-to-leaf path of a decision tree may involve converting the root-to-leaf path into a feature chain representation. The feature chain representation of each root-to-leaf path may include (M) feature chain nodes corresponding to (M) features of the decision tree. These feature chain representations may then be programmed into corresponding rows of an aCAM. As described above, the leaves of the root-to-leaf path may be programmed into a row of ReRAM (e.g., RAM 618) that is electrically connected to the match lines of the aCAM row. As mentioned above, programming the feature chain representation into a row of an aCAM may involve programming the constituent aCAM cells to store evaluable conditions related to the respective features. This may be accomplished by setting a lower boundary voltage threshold (represented as Figure 7 T1 in the figure) and / or the upper boundary voltage threshold (denoted as Figure 7This can be accomplished by programming the Th in the aCAM cells. As mentioned above, this can involve programming the conductance of the memristors that make up the aCAM cells.

[0080] As depicted in line 13 of process 700, once the root-to-leaf paths of the decision tree have been programmed into individual rows of aCAM, treeSHAP-aCAM can convert the i-th prospect input vector (e.g., x fi ) is applied to aCAM. The i-th foreground input vector x fi may include (M) individual values. As mentioned above, these (M) values ​​may correspond to analog voltage signals applied to the columns of the aCAM. The i-th foreground input vector x fi One of the (M) values ​​of may represent the prospect sample x to be evaluated by the decision tree f The i-th feature of foreground sample x f (M) features may also be included, which may be evaluated based on evaluable conditions of the decision tree involving a corresponding number of (M) features.

[0081] The i-th foreground input vector x fi The remaining (M-1) values ​​of may include / to indicate that a matching wildcard value is always returned. Therefore, the i-th foreground input vector x fi Applied to aCAM, a prospect sample x can be evaluated in an isolated manner by relying on an evaluable condition involving the i-th feature of the decision tree f As mentioned above, due to the unique parallel search capability of the aCAM, such evaluation can be performed on all root-to-leaf paths of the decision tree (programmed into separate rows of the aCAM) in a single clock cycle.

[0082] As depicted, in response to applying the i-th foreground input vector x fi The matchline output (e.g., voltage signal) returned from the aCAM can be represented by the i-th foreground matchline output vector y fi express.

[0083] When the i-th foreground input vector x fi After being applied to aCAM, treeSHAP-aCAM can transform the i-th background input vector x bi Applied to aCAM (see, e.g., line 14 of process 700). The i-th background input vector x bi It may also include (M) individual values ​​(as mentioned above, these (M) values ​​may correspond to analog voltage signals applied to the columns of the aCAM). bi One of the (M) values ​​may represent the background sample x to be evaluated by the decision tree b The i-th feature of background sample xb (M) features may also be included, which may be evaluated based on evaluable conditions of the decision tree involving a corresponding number of (M) features.

[0084] The i-th background input vector x bi The remaining (M-1) values ​​of may include / to indicate that the matching wildcard value is always returned. Therefore, the i-th background input vector x bi Applied to aCAM, the background sample x can be evaluated in an isolated manner against the evaluable conditions involving the i-th feature of the decision tree b As mentioned above, due to the unique parallel search capability of the aCAM, such evaluation can be performed on all root-to-leaf paths of the decision tree (programmed into separate rows of the aCAM) in a single clock cycle.

[0085] In response to applying the i-th background input vector x bi The matchline output (e.g., voltage signal) returned from the aCAM can be represented by the i-th background matchline output vector y bi express.

[0086] According to lines 15-19 of process 700, treeSHAP-aCAM may calculate the i-th iteration of Shapley value calculation parameters (ie, parameters used by treeSHAP-aCAM to calculate the Shapley values ​​of foreground samples).

[0087] For example, line 15 of process 700 involves computing the i-th iteration of a vector N, which, for each root-to-leaf path of the decision tree, represents the total number of unique features in the root-to-leaf path. As mentioned above, vector N may have a dimension corresponding to the number of root-to-leaf paths of the decision tree (L). This dimension may also correspond to the number of programmed rows of the aCAM (also (L)).

[0088] Line 16 of process 700 involves computing the i-th iteration of a vector S, which represents, for each root-to-leaf path of the decision tree, the total number of features that matched the foreground samples for the root-to-leaf path. Again, vector S may have a dimension corresponding to the number of root-to-leaf paths of the decision tree / the number of programmed rows of the aCAM (L).

[0089] Line 17 of process 700 involves computing the i-th iteration of a matrix U that represents the offset to the vector S when computing the Shapley value of the foreground sample for each root-to-leaf path of the decision tree. The matrix U may include a number of rows corresponding to the number of root-to-leaf paths (L) for the number of decisions. The matrix U may include a number of columns corresponding to the number of features (M) for the foreground and background samples.

[0090] Line 18 of process 700 involves computing the i-th iteration of a matrix V, which represents, for each root-to-leaf path of the decision tree, the contribution type of the root-to-leaf path (e.g., positive (+1), negative (-1), or null (0)). Again, the matrix V may include a number of rows corresponding to the number of root-to-leaf paths (L) for the number of decisions. The matrix V may include a number of columns corresponding to the number of features (M) for the foreground samples and the background samples.

[0091] Line 19 of process 700 involves computing the i-th iteration of a vector P, which, for each root-to-leaf path of the decision tree, represents the path validity of the root-to-leaf path (e.g., 0 represents an invalid path and 1 represents a valid path). Again, vector P may have a dimension corresponding to the number of root-to-leaf paths of the decision tree / the number of programmed rows of the aCAM (L).

[0092] As mentioned above, treeSHAP-aCAM can iterate a total of (M) times for the operations in lines 13-19 to: (1) evaluate foreground and background samples (x f and x b ) each of the (M) features of the foreground input vector; and (2) a final iteration of calculating the Shapley value calculation parameters. Thus, when all necessary foreground input vectors and background input vectors are applied to aCAM and the final iteration of calculating the Shapley value calculation parameters is calculated, treeSHAP-aCAM can complete the iterative operations of lines 13-19 (see, e.g., line 20 of process 700).

[0093] As depicted at line 21 of process 700 , treeSHAP-aCAM may update the final iteration of matrix V by performing an AND between the final iteration of matrix V and the final iteration of vector P.

[0094] As depicted at line 22, treeSHAP-aCAM may calculate the Shapley value of the foreground sample based on the final iteration of the vector N, the final iteration of the vector S, the final iteration of the matrix U, the updated final iteration of the matrix V, and the vector v representing the leaf of the decision tree (here, the vector v may also have a dimension corresponding to the number of root-to-leaf paths (L) of the decision tree). As mentioned above, the Shapley value may include a multi-value vector that measures the contribution of various features of the foreground sample to the decision of the decision tree-based model.

[0095] In various examples, treeSHAP-aCAM may utilize the expression from the following Equation 4 to calculate the Shapley value of the foreground sample based on these final iterations of the Shapley value calculation parameters:

[0096]

[0097] Again, (L) may represent the number of root-to-leaf paths of the decision tree, and accordingly the number of programmed aCAM rows. j may include an index to (L). i may include an index to the number of features (M) of foreground and background samples.

[0098] Figures 8A-8E An example use case for calculating Shapley values ​​using process 700 according to an example of the disclosed technology is depicted. That is, Figures 8A-8E 800 illustrates how the foreground sample x evaluated according to the decision tree 800 may be calculated. f The Shapley value of .

[0099] like Fig. 8A , decision tree 800 includes eight unique root-to-leaf paths (terminating at each of leaves 1-8, respectively). Decision tree 800 also includes evaluable conditions involving three features: f1; f2; and f3. The root-to-leaf paths of decision tree 800 may be programmed into rows of an aCAM (e.g., aCAM 616) in the manner described above. Here, eight rows of an aCAM may be programmed to store eight distinct root-to-leaf paths of decision tree 800. For example, the first / top row of an aCAM may be programmed to store a first root-to-leaf path, the second / second row from the top of an aCAM may be programmed to store a second root-to-leaf path, the third / third row from the top of an aCAM may be programmed to store a third root-to-leaf path, and so on. Relatedly, the aCAM cells of the first / leftmost column of aCAM may store evaluable conditions related to feature f1; the aCAM cells of the second / middle column of aCAM may store evaluable conditions related to feature f2; and the aCAM cells of the third / rightmost column of aCAM may store evaluable conditions related to feature f3. The ReRAM (e.g., RAM 618) may store the leaves of the decision tree 800.

[0100] like Figures 8A-8G As depicted in the specific example, the foreground sample x f It includes three features: f1 = 0.2; f2 = 0.5; and f3 = 0.9. In this regard, the background sample x b Three features are also included: f1=0.6; f2=1.0; and f3=0.3. As mentioned above, by applying an input vector (e.g., a voltage signal representing features of the foreground sample and the background sample) to an aCAM programmed to store a root-to-leaf path of the decision tree 800, the features of the foreground sample and the background sample can be evaluated by relying on the evaluable conditions of the decision tree 800. That is, the value of the feature corresponding to feature f1 can be applied down the first / leftmost column of the aCAM, the value of the feature corresponding to feature f2 can be applied down the second / middle column of the aCAM, and the value of the feature corresponding to feature f3 can be applied down the third / rightmost column of the aCAM.

[0101] like Fig. 8A As depicted in the figure, the first foreground input vector x f1 Can include three values: 0.2, which means that the foreground sample x f The first feature of (i.e., f1=0.2); and two wildcard values, which are related to the foreground sample x f The second and third features of x that were not evaluated in the first iteration of process 700 correspond to the first background input vector x. b1 Three values ​​may be included: 0.6, which represents the background sample x b The first feature of (i.e., f1=0.6); and two wildcard values, which are related to the background sample x b The second and third features that were not evaluated in the first iteration of process 700 correspond.

[0102] Figure 8B The first foreground matching line output vector y is shown f1 An example of this is shown in Figure 2. Figure 8B As shown in the figure, when the first foreground input vector x f1 When applied to an aCAM, the match lines in the first / top row of the aCAM return a match (e.g., a voltage signal indicating a match). Thus, the first foreground match line output vector y f1 The value corresponding to the first row of aCAM is 1. Conversely, when the first foreground input vector x f1 When applied to an aCAM, the match line in the second row / second from the top of the aCAM returns a mismatch (e.g., a voltage signal indicating a mismatch). Thus, the first foreground match line output vector y f1 The value corresponding to the second row of aCAM is 0. Figure 8B As shown in the figure, when the first foreground input vector x f1 When applied to aCAM, the third and fourth rows of aCAM also return matches, and therefore they are in the first foreground match line output vector y f1 The corresponding value in is also 1. Conversely, when the first foreground input vector x f1 When applied to aCAM, rows 5 to 8 of aCAM return no matches, and therefore they are output vectors y in the first foreground match line f1 The corresponding value in is 0. The first background matching line output vector y can be generated in the same / similar manner b1 , which represents the response to applying the first background input vector x b1 And the matching line output of aCAM generated by subsequent iteration of foreground matching line output vector / background matching line output vector.

[0103] Figure 8Cillustrates how the vector y can be output based on the first foreground matching line f1 and the first background matching line output vector y b1 To calculate the first iteration of the Shapley value calculation parameters. As mentioned above, the first foreground matching line output vector y f1 It can be represented in response to applying the first foreground input vector x f1 The match line output from aCAM is related to the first background match line output vector y b1 It can be represented in response to applying the first background input vector x b1 And the match line output from aCAM.

[0104] As depicted, the first iteration (ie, N1) of calculating vector N may include: adding the first foreground matching line output vector y to the all-zero vector f1 Output vector y matching the first background line b1 The exclusive OR (XOR) between them.

[0105] The first iteration (ie, S1) of calculating the vector S may include: adding the first foreground matching line output vector y to the all-zero vector f1 Output vector y matching the first background line b1 The AND operation (that is, the logical AND operation) between the negation (that is, the logical NOT operation) of .

[0106] The first iteration of computing the matrix U (ie, U1) may include: outputting the vector y by matching the first foreground line f1 Output vector y matching the first background line b1 Fill the first column of matrix U with the inversions of .

[0107] The first iteration of computing the matrix V (ie, V1) may include: by outputting the vector y from the first foreground matching line f1 Output vector y matching the first background line b1 The first foreground matching line output vector y is subtracted from the inverse of f1 The inverse of the first background matching line output vector y b1 The and between are used to fill the first column of the matrix V.

[0108] Finally, the first iteration of calculating the vector P (ie, P1) may include: outputting the vector y between the all-ones vector and the first foreground matching line f1 and the first background matching line output vector y b1 An OR (i.e., a logical OR operation) is performed between the two.

[0109] Fig.8D illustrates how the vector y can be output based on the second foreground matching line f2 and the second background matching line output vector yb2 To calculate the second iteration of the Shapley value calculation parameters.

[0110] As mentioned above, the second foreground matching line output vector y f2 It can be represented that in response to applying the second foreground input vector x f2 Here, the second foreground input vector x f2 Three values ​​may also be included: a first wildcard value corresponding to a first feature of the foreground sample that was not evaluated in the second iteration of process 700; 0.5, which represents a second feature of the foreground sample (i.e., f2=0.5); and a second wildcard value corresponding to a third feature of the foreground sample that was not evaluated in the second iteration of process 700.

[0111] In this regard, the second background matching line output vector y b2 It can be represented in response to applying the second background input vector x b2 Here, the second background input vector x b2 Three values ​​may also be included: a first wildcard value corresponding to a first feature of the background sample that was not evaluated in the second iteration of process 700; 1.0, which represents a second feature of the background sample (i.e., f2=1.0); and a second wildcard value corresponding to a third feature of the background sample that was not evaluated in the second iteration of process 700.

[0112] As depicted, calculating the second iteration of vector N (ie, N2) may include adding the second foreground matching line output vector y to the first iteration of vector N (ie, N1) f2 Output vector y matching the second background line b2 The exclusive OR (XOR) between them.

[0113] Calculating the second iteration of vector S (ie, S2) may include: adding the second foreground matching line output vector y to the first iteration of vector S (ie, S1) f2 Output vector y matching the second background line b2 The AND operation (that is, the logical AND operation) between the negation (that is, the logical NOT operation) of .

[0114] The second iteration of computing the matrix U (ie, U2) may include: outputting the vector y by the second foreground matching line f2 Output vector y matching the second background line b2 The second column of matrix U is filled with the AND between the negations of .

[0115] The second iteration of computing the matrix V (ie, V2) may include: by outputting the vector y from the second foreground matching line f2 Output vector y matching the second background line b2The second foreground matching line output vector y is subtracted from the inverse of f2 The inverse of the second background matching line output vector y b2 The and between are used to fill the second column of matrix V.

[0116] Finally, calculating the second iteration of vector P (ie, P2) may include: matching the first iteration of vector P (ie, P1) with the second foreground line output vector y f2 and the second background matching line output vector y b2 An OR (i.e., a logical OR operation) is performed between the two.

[0117] Fig. 8E illustrates how the vector y can be output based on the third foreground matching line f3 and the third background matching line output vector y b3 To calculate the third iteration of the Shapley value calculation parameters. Figures 8A-8E In the specific example of , the third iteration of the Shapley value calculation parameters is the final iteration of the Shapley value calculation parameters.

[0118] As mentioned above, the third foreground matching line output vector y f3 It can be represented that in response to applying the third foreground input vector x f3 Here, the third foreground input vector x f3 Three values ​​may also be included: a first wildcard value corresponding to a first feature of the foreground sample that was not evaluated in the second iteration of process 700; a second wildcard value corresponding to a second feature of the foreground sample that was not evaluated in the second iteration of process 700; and 0.9, which represents a third feature of the foreground sample (i.e., f3=0.9).

[0119] In this regard, the third background matching line output vector y b3 It can be represented in response to applying the third background input vector x b3 Here, the third background input vector x b3 Three values ​​may also be included: a first wildcard value corresponding to a first feature of the background sample that was not evaluated in the second iteration of process 700; a second wildcard value corresponding to a second feature of the background sample that was not evaluated in the second iteration of process 700; and 0.3, which represents a third feature of the background sample (i.e., f3=0.3).

[0120] As depicted, calculating the third iteration of vector N (ie, N3) may include adding the third foreground matching line output vector y to the second iteration of vector N (ie, N2). f3 Output vector y matching the third background line b3 The exclusive OR (XOR) between them.

[0121] The third iteration of calculating vector S (ie, S3) may include: adding the third foreground matching line output vector y to the second iteration of vector S (ie, S2) f3 Output vector y matching the third background line b3 The AND operation (that is, the logical AND operation) between the negation (that is, the logical NOT operation) of .

[0122] The third iteration of computing the matrix U (ie, U3) may include: outputting the vector y by a third foreground matching line f3 Output vector y matching the third background line b3 The third column of matrix U is filled with the AND between the negations of .

[0123] The third iteration of computing the matrix V (ie, V3) may include: by outputting the vector y from the third foreground matching line f3 Output vector y matching the third background line b3 The third foreground matching line output vector y is subtracted from the inverse of f3 The inverse of the third background matching line output vector y b3 The third column of matrix V is filled by the AND between .

[0124] Finally, calculating the third iteration of vector P (ie, P3) may include: calculating the second iteration of vector P (ie, P2) and the third foreground matching line output vector y f3 and the third background matching line output vector y b3 An OR (i.e., a logical OR operation) is performed between the two.

[0125] Fig.8F It illustrates how the final iteration of the matrix V may be updated by performing an AND between the final iteration of the matrix V (ie, V3) and the final iteration of the vector P (ie, P3).

[0126] Figure 8G The diagram illustrates how the updated matrix can be constructed based on the final iteration of vector N (i.e., N3), the final iteration of vector S (i.e., S3), the final iteration of matrix U (i.e., U3), the updated final iteration of matrix V (i.e., V 更新 ), and the vector v representing the leaf of the decision tree 800 to calculate the foreground sample x f The Shapley value of .

[0127] Fig. 9 A block diagram of an example computer system 900 is depicted in which various examples described herein may be implemented.

[0128] Computer system 900 includes a bus 912 or other communication mechanism for communicating information, and one or more hardware processors 904 coupled with bus 912 for processing information. Hardware processor(s) 904 may be, for example, one or more general-purpose microprocessors.

[0129] The computer system 900 also includes a main memory 906, such as a random access memory (RAM), cache, and / or other dynamic storage device, coupled to the bus 912 for storing information and instructions to be executed by the processor 904. The main memory 906 may also be used for storing temporary variables or other intermediate information during execution of instructions to be executed by the processor 904. When stored in a storage medium accessible to the processor 904, such instructions cause the computer system 900 to appear as a special-purpose machine customized to perform the operations specified in the instructions.

[0130] The computer system 900 further includes a read only memory (ROM) 912 or other static storage device coupled to the bus 912 for storing static information and instructions for the processor 904. A storage device 914, such as a magnetic disk, optical disk, or USB thumb drive (flash drive), etc., is provided and coupled to the bus 912 for storing information and instructions.

[0131] The computer system 900 additionally includes a hardware accelerator 908. The hardware accelerator 908 may be configured to execute instructions (i.e., programming or software code) stored in the main memory 906, the read-only memory (ROM) 912, and / or the storage device 914 to encode a set of logic rules embodied in a data structure (e.g., a decision tree) into the aCAM 910. In an example embodiment, the exemplary hardware accelerator 908 may include a plurality of integrated circuits, which in turn may include an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), or other very large scale integrated circuit (VLSI). The integrated circuits of the exemplary hardware accelerator 908 may be specifically optimized to perform a discrete subset of computer processing operations or to execute a discrete subset of computer executable instructions in an accelerated manner. For example, the hardware accelerator 908 may be configured or manufactured to implement a set of logic rules embodied in a data structure (such as a decision tree) on the aCAM 910.

[0132] aCAM 910 may include non-volatile memory constructed using technologies including, for example, resistive switching memory (i.e., memristors), phase change memory, magnetoresistive memory, ferroelectric memory, some other resistive random access memory device (Re-RAM), or a combination of those technologies. More generally, aCAM 910 may be implemented using technologies that permit aCAM 910 to retain its contents even when power is lost or otherwise removed. Thus, data in aCAM 910 "persists," and aCAM 910 may function as so-called "non-volatile memory."

[0133] The computer system 900 may be coupled to a display 916, such as a liquid crystal display (LCD) (or touch screen), via bus 912 for displaying information to a computer user. An input device 918, including alphanumeric and other keys, is coupled to bus 912 for communicating information and command selections to processor 904. Another type of user input device is a cursor control 920, such as a mouse, trackball, or cursor direction keys, for communicating direction information and command selections to processor 904 and for controlling cursor movement on display 916. In some embodiments, the same direction information and command selections as a cursor control may be implemented via receiving touches on a touch screen without a cursor.

[0134] The computing system 900 may include a user interface module to implement a GUI, which may be stored in a mass storage device as executable software code executed by the computing device(s). This module and other modules may include components, such as software components, object-oriented software components, class components, and task components, processes, functions, properties, procedures, subroutines, program code segments, drivers, firmware, microcode, circuit systems, data, databases, data structures, tables, arrays, and variables, for example.

[0135] In general, as used herein, the terms "component", "engine", "system", "database", "data storage device", etc. may refer to logic embodied in hardware or firmware, or to a collection of software instructions, possibly with entry and exit points, written in a programming language such as, for example, Java, C, or C++. Software components may be compiled and linked into executable programs installed in dynamic link libraries, or may be written in interpreted programming languages ​​such as, for example, BASIC, Perl, or Python. It will be appreciated that software components may be callable from other components or themselves, and / or may be called in response to detected events or interrupts. Software components configured for execution on a computing device may be provided on a computer-readable medium such as a compact disc, digital video disc, flash drive, magnetic disk, or any other tangible medium, or provided as a digital download (and may be initially stored in a compressed or installable format that requires installation, decompression, or decryption prior to execution). Such software code may be stored in part or in whole on a memory device of an executing computing device for execution by the computing device. Software instructions may be embedded in firmware such as an EPROM. It will be further appreciated that hardware components may include connected logic units (such as gates and flip-flops), and / or may include programmable units (such as a programmable gate array or processor).

[0136] The computer system 900 may implement the techniques described herein using custom hardwired logic, one or more ASICs or FPGAs, firmware, and / or program logic that, in combination with the computer system, causes the computer system 900 to become a special-purpose machine or programs the computer system to become a special-purpose machine. According to one embodiment, the techniques herein are performed by the computer system 900 in response to the processor(s) 904 executing one or more sequences of one or more instructions contained in the main memory 906. Such instructions may be read into the main memory 906 from another storage medium, such as storage device 914. Execution of the sequences of instructions contained in the main memory 906 causes the processor(s) 904 to perform the process steps described herein. In alternative embodiments, hardwired circuitry may be used instead of or in combination with software instructions.

[0137] As used herein, the term "non-transitory media" and similar terms refer to any medium that stores data and / or instructions that cause a machine to operate in a particular manner. Such non-transitory media may include non-volatile media and / or volatile media. Non-volatile media include, for example, optical or magnetic disks, such as storage device 914. Volatile media include dynamic memory, such as main memory 906. Common forms of non-transitory media include, for example, floppy disks, floppy disks, hard disks, solid-state drives, tapes or any other magnetic data storage media, CD-ROMs, any other optical data storage media, any physical media with a pattern of holes, RAM, PROMs and EPROMs, FLASH-EPROMs, NVRAMs, any other memory chips or cassettes, and network versions thereof.

[0138] Non-transitory media are distinct from, but may be used in conjunction with, transmission media. Transmission media participate in the transfer of information between non-transitory media. For example, transmission media include coaxial cables, copper wire, and optical fiber, including the cables that comprise bus 912. Transmission media may also take the form of acoustic or light waves, such as those generated during radio wave and infrared data communications.

[0139] The computer system 900 also includes a communication / network interface 922 coupled to the bus 912. The network interface 922 provides a bidirectional data communication connection to one or more network links (the one or more network links are connected to one or more local networks). For example, the communication interface 922 can be an integrated services digital network (ISDN) card, a cable modem, a satellite modem, or a modem for providing a data communication connection to a corresponding type of telephone line. As another example, the network interface 922 can be a local area network (LAN) card to provide a data communication connection to a compatible LAN (or a WAN component for communicating with a WAN). A wireless link can also be implemented. In any such implementation, the network interface 918 sends and receives electrical, electromagnetic or optical indicators that carry digital data streams representing various types of information.

[0140] A network link typically provides data communication through one or more networks to other data devices. For example, a network link may provide a connection through a local network to a host computer or to data devices operated by an Internet Service Provider (ISP). The ISP, in turn, provides data communication services through the global packet data communication network now commonly referred to as the "Internet." Both the local network and the Internet use electrical, electromagnetic, or optical indicators that carry digital data streams. The indicators through the various networks and on the network links and through the communication interface 922 carry the digital data to and from the computer system 900, and these indicators are exemplary forms of transmission media.

[0141] Computer system 900 can send messages and receive data, including program code, through the network(s), network links and communications interface 918. In the Internet example, a server can transmit code requested for an application through the Internet, an ISP, a local network and communications interface 922.

[0142] The received code may be executed by processor 904 as it is received, and / or stored in storage device 914 or other non-volatile storage for later execution.

[0143] Each of the processes, methods and algorithms described in the foregoing sections may be embodied in a code component executed by one or more computer systems or computer processors including computer hardware, and fully or partially automated by the code component. The one or more computer systems or computer processors may also be operable to support the performance of related operations in a "cloud computing" environment or as a "software as a service" (SaaS). These processes and algorithms may be implemented in part or in whole in a dedicated circuit system. The various features and processes described above may be used independently of each other, or may be combined in various ways. Different combinations and sub-combinations are intended to fall within the scope of the present disclosure, and certain methods or process blocks may be omitted in some embodiments. The methods and processes described herein are also not limited to any particular sequence, and the blocks or states associated therewith may be executed in other appropriate sequences, or may be executed in parallel, or in some other manner. Blocks or states may be added to or removed from the disclosed example embodiments. The execution of certain operations or processes may be distributed among computer systems or computer processors, not only residing in a single machine, but also deployed across several machines.

[0144] As used herein, any form of hardware, software or combination thereof may be utilized to implement the circuit. For example, one or more processors, controllers, ASICs, PLAs, PALs, CPLDs, FGAs, logic components, software routines or other mechanisms may be implemented to form the circuit. In an embodiment, the various circuits described herein may be implemented as discrete circuits, or the functions and features described may be partially or entirely shared in the middle of one or more circuits. Even if the various features or elements of the functions may be described or claimed separately as separate circuits, these features and functions may be shared in the middle of one or more common circuits, and such descriptions should not require or imply the need for separate circuits to implement such features or functions. In the case of using software to implement the circuit in whole or in part, such software may be implemented to operate together with a computing or processing system (such as, computer system 900) that can implement the functions described therein.

[0145] As used herein, the term "or" may be interpreted in either an inclusive or exclusive sense. Furthermore, descriptions of resources, operations, or structures in the singular should not be interpreted as excluding the plural. Conditional language (such as, among others, "may," "might," "might," or "could"), unless specifically stated otherwise or otherwise understood within the context as used, is generally intended to convey that certain embodiments include certain features, elements, and / or steps, while other embodiments do not include certain features, elements, and / or steps.

[0146] Unless expressly stated otherwise, the terms and phrases used in this document and variations thereof should be interpreted as open-ended and not restrictive. Adjectives such as "conventional," "traditional," "normal," "standard," "known," and terms of similar meaning should not be interpreted as limiting the items described to a given time period or items available at a given time, but should be interpreted as covering conventional, traditional, normal, or standard technology that may be available or known at any time now or in the future. In some cases, the appearance of expanding words and phrases (such as, "one or more," "at least," "but not limited to," or other similar phrases) should not be interpreted as meaning that a narrower scope is intended or required where such expanding phrases might not exist.

Claims

1. A system comprising: an analog content addressable memory (aCAM), wherein each row of the aCAM is programmed to represent a separate root-to-leaf path of a decision tree comprising evaluable conditions involving (M) features; and One or more processing resources, the one or more processing resources operative to: (a) applying a first foreground input vector to the aCAM, wherein: A first value of the (M) total values ​​of the first foreground input vector represents a first feature of the (M) features from a foreground sample, and The remaining (M-1) values ​​of the (M) total values ​​of the first foreground input vector include wildcard values; (b) applying a first background input vector to the aCAM, wherein: A first value of the (M) total values ​​of the first background input vector represents a first feature of the (M) features from a background sample, and The remaining (M-1) values ​​of the (M) total values ​​of the first background input vector represent wildcard values; (c) calculating a first iteration of Shapley value calculation parameters based on a matchline output from the aCAM in response to applying the first foreground input vector and the first background input vector; (d) iterating steps (a)-(c) for each of the (M) features of the foreground samples and the background samples to generate subsequent iterations of the Shapley value calculation parameters; and (e) calculating a Shapley value for the foreground sample based on the final iteration of the Shapley value calculation parameters.

2. The system according to claim 1, wherein: Iterating the steps (a)-(c) for a second feature of the (M) features of the foreground sample and the background sample comprises: (a) applying a second foreground input vector to the aCAM, wherein: A second value of the (M) total values ​​of the second foreground input vector represents a second feature of the (M) features from the foreground sample, and The remaining (M-1) values ​​of the (M) total values ​​of the second foreground input vector represent wildcard values; (b) applying a second background input vector to the aCAM, wherein: A second value of the (M) total values ​​of the second background input vector represents a second feature of the (M) features from the background sample, and The remaining (M-1) values ​​of the (M) total values ​​of the second background input vector represent wildcard values; and (c) calculating a second iteration of the Shapley value calculation parameters based on the matchline output from the aCAM in response to applying the second foreground input vector and the second background input vector.

3. The system according to claim 2, wherein: The Shapley value calculation parameters include: a vector N, for each root-to-leaf path of the decision tree, the vector N representing the total number of unique features in the root-to-leaf path; A vector S, for each root-to-leaf path of the decision tree, the vector S represents the total number of features of the root-to-leaf path that match the foreground sample; a matrix U representing, for each root-to-leaf path of the decision tree, an offset to be applied to the vector S when computing the Shapley value of the foreground sample; a matrix V, for each root-to-leaf path of the decision tree, the matrix V representing a contribution type for the root-to-leaf path; and A vector P, for each root-to-leaf path of the decision tree, wherein the vector P represents the path validity of the root-to-leaf path.

4. The system of claim 3, wherein: The first iteration of calculating the vector N comprises adding the first foreground matching line output vector y to the all-zero vector f1 Output vector y matching the first background line b1 The first foreground matching line output vector y is obtained by XORing f1 In response to applying the first foreground input vector to the match line output of the aCAM, the first background match line output vector y b1 representing a matchline output responsive to applying the first background input vector to the aCAM; The first iteration of calculating the vector S comprises adding the first foreground matching line output vector y to the all-zero vector f1 The output vector y is matched with the first background line b1 The AND between the negations of ; The first iteration of computing the matrix U comprises outputting the vector y by the first foreground matching line f1 The output vector y is matched with the first background line b1 Fill the first column of the matrix U with the AND between the negations of ; The first iteration of computing the matrix V comprises outputting a vector y from the first foreground matching line f1 The output vector y is matched with the first background line b1 The first foreground matching line output vector y is subtracted from the negation of f1 The inversion of the first background matching line output vector y b1 Between and, to fill the first column of the matrix V; and The first iteration of calculating the vector P includes matching the all-ones vector with the first foreground line output vector y f1 and the first background matching line output vector y b1 Between or between execution and.

5. The system of claim 4, wherein: Calculating the second iteration of the vector N comprises adding a second foreground matching line output vector y to the first iteration of the vector N f2 Match the second background line output vector y b2 The second foreground matching line output vector y f2 In response to applying the second foreground input vector to the match line output of the aCAM, the second background match line output vector y b2 representing a matchline output responsive to applying the second background input vector to the aCAM; Calculating the second iteration of the vector S comprises adding the second foreground matching line output vector y to the first iteration of the vector S f2 The second background matching line output vector y b2 The AND between the negations of ; The second iteration of computing the matrix U comprises outputting the vector y by the second foreground matching line f2 The second background matching line output vector y b2 Fill the second column of the matrix U with the AND between the negations of ; The second iteration of computing the matrix V comprises outputting the vector y from the second foreground matching line f2 The second background matching line output vector y b2 The second foreground matching line output vector y is subtracted from the inverse of f2 The inversion of the second background matching line output vector y b2 between and to fill the second column of the matrix V; and Calculating the second iteration of the vector P includes matching the first iteration of the vector P with the second foreground matching line output vector y f2 and the second background matching line output vector y b2 Between or between execute and.

6. The system according to claim 5, wherein: The one or more processing resources are further operable to: In response to a final iteration of steps (a)-(c), updating the final iteration of the matrix V by performing an AND between the final iteration of the matrix V and the final iteration of the vector P; and Wherein, calculating the Shapley value of the foreground sample based on the final iteration of the Shapley value calculation parameters includes calculating the Shapley value of the foreground sample based on the final iteration of the vector N, the final iteration of the vector S, the final iteration of the matrix U, the updated final iteration of the matrix V, and the vector v representing the leaf value of the decision tree.

7. The system of claim 1, further comprising a resistive random access memory (ReRAM) storing leaf values ​​of the decision tree.

8. The system of claim 7, wherein: The first row of the aCAM is programmed to store a first root-to-leaf path of the decision tree; a first row of the ReRAM being programmed to store leaves of the first root-to-leaf path and electrically connected to match lines of the first row of the aCAM; A second row of the aCAM is programmed to store a second root-to-leaf path of the decision tree; and A second row of the ReRAM is programmed to store leaves of the second root-to-leaf path and is electrically connected to match lines of the second row of the aCAM.

9. The system of claim 7, wherein: The first column of the aCAM stores evaluable conditions of the decision tree corresponding to the first features of the foreground sample and the background sample; The second column of the aCAM stores the evaluable conditions of the decision tree corresponding to the second features of the foreground samples and the background samples; said first value of said (M) total values ​​of said first foreground input vector being applied to said first column of said aCAM; said first value of said (M) total values ​​of said first background input vector being applied to said first column of said aCAM; said second value of said (M) total values ​​of said second foreground input vector is applied to said second column of said aCAM; and The second value of the (M) total values ​​of the second background input vector is applied to the second column of the aCAM.

10. The system of claim 8, wherein: a first aCAM cell of the first row of the aCAM programmed to store one or more evaluable conditions of the first root-to-leaf path corresponding to the first features of the foreground samples and the background samples; The first aCAM unit comprises two memristors; and Programming the first aCAM cell to store the one or more evaluable conditions of the first root-to-leaf path corresponding to the first characteristics of the foreground samples and the background samples includes programming conductances of the two memristors.

11. The system according to claim 10, wherein: The conductances of the two memristors are programmed such that the first aCAM cell stores a lower boundary threshold voltage and an upper boundary threshold voltage.

12. A method comprising: (a) applying a first foreground input vector to an analog content addressable memory (aCAM), wherein: Each row of the aCAM is programmed to represent a separate root-to-leaf path of a decision tree comprising evaluable conditions involving (M) features, A first value of the (M) total values ​​of the first foreground input vector represents a first feature of the (M) features from a foreground sample, and The remaining (M-1) values ​​of the (M) total values ​​of the first foreground input vector include wildcard values; (b) applying a first background input vector to the aCAM, wherein: A first value of the (M) total values ​​of the first background input vector represents a first feature of the (M) features from a background sample, and The remaining (M-1) values ​​of the (M) total values ​​of the first background input vector represent wildcard values; (c) calculating a first iteration of Shapley value calculation parameters based on a matchline output from the aCAM in response to applying the first foreground input vector and the first background input vector; (d) iterating steps (a)-(c) for each of the (M) features of the foreground samples and the background samples to generate subsequent iterations of the Shapley value calculation parameters; and (e) calculating a Shapley value for the foreground sample based on the final iteration of the Shapley value calculation parameters.

13. The method according to claim 12, wherein: Iterating the steps (a)-(c) for a second feature of the (M) features of the foreground sample and the background sample comprises: (a) applying a second foreground input vector to the aCAM, wherein: A second value of the (M) total values ​​of the second foreground input vector represents a second feature of the (M) features from the foreground sample, and The remaining (M-1) values ​​of the (M) total values ​​of the second foreground input vector represent wildcard values; (b) applying a second background input vector to the aCAM, wherein: A second value of the (M) total values ​​of the second background input vector represents a second feature of the (M) features from the background sample, and The remaining (M-1) values ​​of the (M) total values ​​of the second background input vector represent wildcard values; and (c) calculating a second iteration of the Shapley value calculation parameters based on the matchline output from the aCAM in response to applying the second foreground input vector and the second background input vector.

14. The method according to claim 13, wherein the Shapley value calculation parameters include: a vector N, for each root-to-leaf path of the decision tree, the vector N representing the total number of unique features in the root-to-leaf path; A vector S, for each root-to-leaf path of the decision tree, the vector S represents the total number of features of the root-to-leaf path that match the foreground sample; a matrix U representing, for each root-to-leaf path of the decision tree, an offset to be applied to the vector S when computing the Shapley value of the foreground sample; a matrix V, for each root-to-leaf path of the decision tree, the matrix V representing a contribution type for the root-to-leaf path; and A vector P, for each root-to-leaf path of the decision tree, wherein the vector P represents the path validity of the root-to-leaf path.

15. The method according to claim 14, wherein: The first iteration of calculating the vector N comprises adding the first foreground matching line output vector y to the all-zero vector f1 Output vector y matching the first background line b1 The first foreground matching line output vector y is obtained by XORing f1 In response to applying the first foreground input vector to the match line output of the aCAM, the first background match line output vector y b1 representing a matchline output responsive to applying the first background input vector to the aCAM; The first iteration of calculating the vector S comprises adding the first foreground matching line output vector y to the all-zero vector f1 The output vector y is matched with the first background line b1 The AND between the negations of ; The first iteration of computing the matrix U comprises outputting the vector y by the first foreground matching line f1 The output vector y is matched with the first background line b1 Fill the first column of the matrix U with the AND between the negations of ; The first iteration of computing the matrix V comprises outputting a vector y from the first foreground matching line f1 The output vector y is matched with the first background line b1 The first foreground matching line output vector y is subtracted from the negation of f1 The inversion of the first background matching line output vector y b1 Between and, to fill the first column of the matrix V; and The first iteration of calculating the vector P includes matching the all-ones vector with the first foreground line output vector y f1 and the first background matching line output vector y b1 Between or between execute and.

16. The method of claim 15, wherein: Calculating the second iteration of the vector N comprises adding a second foreground matching line output vector y to the first iteration of the vector N f2 Match the second background line output vector y b2 The second foreground matching line output vector y f2 In response to applying the second foreground input vector to the match line output of the aCAM, the second background match line output vector y b2 representing a matchline output responsive to applying the second background input vector to the aCAM; Calculating the second iteration of the vector S comprises adding the second foreground matching line output vector y to the first iteration of the vector S f2 The second background matching line output vector y b2 The AND between the negations of ; The second iteration of computing the matrix U comprises outputting the vector y by the second foreground matching line f2 The second background matching line output vector y b2 Fill the second column of the matrix U with the AND between the negations of ; The second iteration of computing the matrix V comprises outputting the vector y from the second foreground matching line f2 The second background matching line output vector y b2 The second foreground matching line output vector y is subtracted from the inverse of f2 The inversion of the second background matching line output vector y b2 between and to fill the second column of the matrix V; and Calculating the second iteration of the vector P includes matching the first iteration of the vector P with the second foreground matching line output vector y f2 and the second background matching line output vector y b2 Between or between execute and.

17. The method according to claim 16, further comprising: In response to a final iteration of steps (a)-(c), updating the final iteration of the matrix V by performing an AND between the final iteration of the matrix V and the final iteration of the vector P; and Wherein, calculating the Shapley value of the foreground sample based on the final iteration of the Shapley value calculation parameters includes calculating the Shapley value of the foreground sample based on the final iteration of the vector N, the final iteration of the vector S, the final iteration of the matrix U, the updated final iteration of the matrix V, and the vector v representing the leaf value of the decision tree.

18. A system comprising: an analog content addressable memory (aCAM), wherein each row of the aCAM is programmed to represent a separate root-to-leaf path of a decision tree comprising evaluable conditions involving (M) features; a logic circuit electrically connected to a match line of the aCAM, the logic circuit operative to: (a) applying a first foreground input vector to the aCAM, wherein: A first value of the (M) total values ​​of the first foreground input vector represents a first feature of the (M) features from a foreground sample, and The remaining (M-1) values ​​of the (M) total values ​​of the first foreground input vector include wildcard values; (b) applying a first background input vector to the aCAM, wherein: A first value of the (M) total values ​​of the first background input vector represents a first feature of the (M) features from a background sample, and The remaining (M-1) values ​​of the (M) total values ​​of the first background input vector represent wildcard values; (c) calculating a first iteration of Shapley value calculation parameters based on the matchline output from the aCAM in response to applying the first foreground input vector and the first background input vector; and (d) iterating steps (a)-(c) for each of the (M) features of the foreground samples and the background samples to generate subsequent iterations of the Shapley value calculation parameters; and A processor is operative to calculate a Shapley value based on a final iteration of the Shapley value calculation parameters.

19. The system of claim 18, wherein: Iterating the steps (a)-(c) for a second feature of the (M) features of the foreground sample and the background sample comprises: (a) applying a second foreground input vector to the aCAM, wherein: A second value of the (M) total values ​​of the second foreground input vector represents a second feature of the (M) features from the foreground sample, and The remaining (M-1) values ​​of the (M) total values ​​of the second foreground input vector represent wildcard values; (b) applying a second background input vector to the aCAM, wherein: A second value of the (M) total values ​​of the second background input vector represents a second feature of the (M) features from the background sample, and The remaining (M-1) values ​​of the (M) total values ​​of the second background input vector represent wildcard values; and (c) calculating a second iteration of the Shapley value calculation parameters based on the matchline output from the aCAM in response to applying the second foreground input vector and the second background input vector.

20. The system of claim 19, wherein: The Shapley value calculation parameters include: a vector N, for each root-to-leaf path of the decision tree, the vector N representing the total number of unique features in the root-to-leaf path; A vector S, for each root-to-leaf path of the decision tree, the vector S represents the total number of features of the root-to-leaf path that match the foreground sample; a matrix U representing, for each root-to-leaf path of the decision tree, an offset to be applied to the vector S when computing the Shapley value of the foreground sample; a matrix V, for each root-to-leaf path of the decision tree, the matrix V representing a contribution type for the root-to-leaf path; and A vector P, for each root-to-leaf path of the decision tree, wherein the vector P represents the path validity of the root-to-leaf path.

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