Chip power delivery network determination method, device, computer equipment, readable storage medium and program product

Abstract

The present application relates to a chip power delivery network determination method, device, computer equipment, readable storage medium and program product. The method comprises: obtaining a design training sample of a chip power delivery network; the design training sample at least contains chip layout design information and label data of the sample chip; the label data represents the power network template identifier corresponding to each area of ​​the sample chip; according to the design training sample, a target chip power delivery network determination model is obtained by training; the chip layout design information of the chip to be designed is input into the target chip power delivery network determination model to obtain the target power network template identifier corresponding to each area of ​​the chip to be designed; according to the target power network template identifier, the chip power delivery network information of the chip to be designed is obtained. The use of this method can improve chip design efficiency.

Description

Technical Field

[0001] The present application relates to the field of chip design technology, and in particular to a method, apparatus, computer equipment, computer-readable storage medium and computer program product for determining a chip power delivery network. Background Art

[0002] In chip design, the design of the power delivery network (PDN) usually relies on traditional optimization algorithms, such as simulated annealing algorithms. These methods require a large number of iterative calculations during the design process to evaluate different wiring schemes and optimize the performance of the power network. However, as the scale and complexity of chip design increase, the amount of calculation and time consumption of traditional optimization algorithms increase significantly when faced with multi-region, large-scale design, resulting in extended design cycles and low efficiency. This makes it difficult for traditional methods to adapt to the requirements of fast iteration and high-precision design, and has become an important bottleneck in modern chip design. Summary of the invention

[0003] Based on this, it is necessary to provide a chip power delivery network determination method, device, computer equipment, computer-readable storage medium and computer program product that can improve chip design efficiency in response to the above technical problems.

[0004] In a first aspect, the present application provides a method for determining a chip power delivery network, comprising:

[0005] Acquire a design training sample of a chip power delivery network; the design training sample at least includes chip layout design information and label data of a sample chip; the label data indicates a power network template identifier corresponding to each area of ​​the sample chip;

[0006] According to the designed training samples, a target chip power delivery network determination model is obtained by training;

[0007] Inputting chip layout design information of the chip to be designed into the target chip power delivery network determination model to obtain a target power network template identifier corresponding to each area of ​​the chip to be designed;

[0008] According to the target power network template identifier, the chip power transmission network information of the chip to be designed is obtained.

[0009] In one embodiment, obtaining a design training sample of a chip power delivery network includes:

[0010] Based on the preset parameter information, a plurality of power network templates are generated, and chip layout design information of the sample chip is obtained;

[0011] A preset chip power delivery network optimization model is adopted, and a power network template identifier corresponding to each area of ​​the sample chip is obtained according to the chip layout design information of the sample chip and the multiple power network templates.

[0012] In one embodiment, the method of using a preset chip power delivery network optimization model to obtain a power network template identifier corresponding to each area of ​​the sample chip according to the chip layout design information of the sample chip and the multiple power network templates includes:

[0013] According to the chip layout design information of the sample chip and the multiple power network templates, iteratively determine the optimization evaluation information of the multiple power network templates for each area of ​​the sample chip; the optimization evaluation information at least includes voltage drop reliability index information and wiring resource occupancy rate index information;

[0014] According to the optimization evaluation information, determining the optimal power supply network template corresponding to each area of ​​the sample chip from the multiple power supply network templates;

[0015] The power supply network template identifier of the optimal power supply network template corresponding to each area of ​​the sample chip is used as the power supply network template identifier corresponding to each area of ​​the sample chip.

[0016] In one embodiment, the generating of multiple power supply network templates based on preset parameter information includes:

[0017] Generate different types of two-dimensional wiring templates according to different combinations of the preset parameter information;

[0018] The two-dimensional wiring templates are combined randomly or according to preset rules to generate a multi-layer three-dimensional power supply network template, and one of the multi-layer three-dimensional power supply network templates is used as a power supply network template.

[0019] In one embodiment, the step of inputting chip layout design information of the chip to be designed into the target chip power delivery network determination model to obtain a target power network template identifier corresponding to each area of ​​the chip to be designed includes:

[0020] Extracting chip current information and chip power pin information corresponding to each area of ​​the chip to be designed from the chip layout design information of the chip to be designed;

[0021] According to the chip current information and chip power pin information corresponding to each area of ​​the chip to be designed, the target power network template identifier corresponding to each area of ​​the chip to be designed is obtained respectively.

[0022] In one embodiment, obtaining chip power delivery network information of the chip to be designed according to the target power network template identifier includes:

[0023] Acquire a target power supply network template corresponding to the target power supply network template identifier;

[0024] The target power supply network template is applied to each area of ​​the chip to be designed, and the power supply network topology information of the chip to be designed is formed by splicing, so as to obtain the chip power supply network information of the chip to be designed.

[0025] In a second aspect, the present application further provides a chip power delivery network determination device, comprising:

[0026] A sample acquisition module is used to acquire a design training sample of a chip power delivery network; the design training sample at least includes chip layout design information and label data of the sample chip; the label data indicates a power network template identifier corresponding to each area of ​​the sample chip;

[0027] A model training module, used for training a target chip power delivery network determination model according to the design training samples;

[0028] A model reasoning module, used for inputting chip layout design information of the chip to be designed into the target chip power delivery network determination model to obtain a target power network template identifier corresponding to each area of ​​the chip to be designed;

[0029] The network determination module is used to obtain chip power transmission network information of the chip to be designed according to the target power network template identifier.

[0030] In a third aspect, the present application further provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and when the processor executes the computer program, the following steps are implemented:

[0031] Acquire a design training sample of a chip power delivery network; the design training sample at least includes chip layout design information and label data of a sample chip; the label data indicates a power network template identifier corresponding to each area of ​​the sample chip;

[0032] According to the designed training samples, a target chip power delivery network determination model is obtained through training;

[0033] Inputting chip layout design information of the chip to be designed into the target chip power delivery network determination model to obtain a target power network template identifier corresponding to each area of ​​the chip to be designed;

[0034] According to the target power network template identifier, the chip power transmission network information of the chip to be designed is obtained.

[0035] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the following steps are implemented:

[0036] Acquire a design training sample of a chip power delivery network; the design training sample at least includes chip layout design information and label data of a sample chip; the label data indicates a power network template identifier corresponding to each area of ​​the sample chip;

[0037] According to the designed training samples, a target chip power delivery network determination model is obtained through training;

[0038] Inputting chip layout design information of the chip to be designed into the target chip power delivery network determination model to obtain a target power network template identifier corresponding to each area of ​​the chip to be designed;

[0039] According to the target power network template identifier, the chip power transmission network information of the chip to be designed is obtained.

[0040] In a fifth aspect, the present application further provides a computer program product, including a computer program, which implements the following steps when executed by a processor:

[0041] Acquire a design training sample of a chip power delivery network; the design training sample at least includes chip layout design information and label data of a sample chip; the label data indicates a power network template identifier corresponding to each area of ​​the sample chip;

[0042] According to the designed training samples, a target chip power delivery network determination model is obtained through training;

[0043] Inputting chip layout design information of the chip to be designed into the target chip power delivery network determination model to obtain a target power network template identifier corresponding to each area of ​​the chip to be designed;

[0044] According to the target power network template identifier, the chip power transmission network information of the chip to be designed is obtained.

[0045] The chip power delivery network determination method, device, computer equipment, computer-readable storage medium and computer program product described above first obtain a design training sample of the chip power delivery network, wherein the design training sample at least includes chip layout design information and label data of the sample chip, and the label data indicates the power network template identifier corresponding to each area of ​​the sample chip. By obtaining the design training sample including the layout design information of the sample chip and the corresponding label data, high-quality training data can be provided for the supervised learning model. The label data clearly marks the power network template identifier corresponding to each area, so that the model can learn the mapping relationship between the layout design information and the template selection; then, according to the design training sample, the target chip power delivery network is determined by training. The model is trained to obtain a target model that can directly predict the power network template identification from the layout design information through the supervised learning process of the design training samples; then, the chip layout design information of the chip to be designed is input into the target chip power delivery network determination model to obtain the target power network template identification corresponding to each area of ​​the chip to be designed, and the layout information of the chip to be designed is input using the trained model to realize the template identification prediction of each chip area. This process only requires one forward reasoning to complete, avoiding multiple iterative calculations in traditional methods, significantly improving the design efficiency, and being able to output a template identification that meets the performance requirements in a short time; finally, according to the target power network template identification, the chip power delivery network information of the chip to be designed is obtained, and the predicted template identification is converted into the power delivery network design information, thereby generating a complete chip power delivery network structure, simplifying the workflow from design input to wiring output, making the power network design more automated, and effectively improving the design efficiency. In the above method, the design task of the power delivery network is converted into a data-driven prediction process through the supervised learning method, realizing the automation process from chip layout design information to power network design output. Compared with traditional optimization algorithms, this solution avoids tedious multiple iterative calculations, greatly improves design efficiency, shortens the design cycle, and at the same time maintains high accuracy and adaptability in large-scale chip design, effectively solving the problem of low efficiency of traditional methods in complex chip design. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the drawings required for use in the embodiments of the present application or related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0047] Figure 1A schematic diagram of a flow chart of a method for determining a chip power delivery network in one embodiment;

[0048] Figure 2 A schematic diagram of a flow chart of designing training sample determination steps in one embodiment;

[0049] Figure 3 A schematic diagram of a chip power delivery network determination system in one embodiment;

[0050] Figure 4 A schematic diagram of a chip power delivery network spliced ​​with power network templates in one embodiment;

[0051] Figure 5 A schematic diagram of a model structure of a chip power delivery network determination model in one embodiment;

[0052] Figure 6 It is a structural block diagram of a device for determining a chip power delivery network in one embodiment;

[0053] Figure 7 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0054] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0055] In one embodiment, Figure 1 As shown, a method for determining a chip power delivery network is provided. This embodiment uses the method applied to a terminal as an example. It can be understood that the method can also be applied to a server, and can also be applied to a system including a terminal and a server, and is implemented through the interaction between the terminal and the server. Among them, the terminal can be, but is not limited to, various personal computers, laptops, smart phones, and tablet computers. The server can be an independent physical server, or a server cluster or distributed system composed of multiple physical servers, or a cloud server that provides cloud computing services. In this embodiment, the method includes the following steps:

[0056] Step S101, obtaining a design training sample of a chip power delivery network.

[0057] The design training sample at least includes chip layout design information and label data of the sample chip; the label data indicates the power network template identifier corresponding to each area of ​​the sample chip.

[0058] Among them, the chip layout design information is a data set that describes the physical and electrical characteristics of the sample chip, such as the location of functional modules, the location of power pins, and power consumption requirements.

[0059] The label data is an identification of the template type required for each area of ​​the sample chip in the power delivery network design, and is represented as a specific power network template number or name.

[0060] Each area of ​​the chip can be divided according to the positions of different functional modules in the chip, and each functional module and its surrounding area are regarded as a division unit; it can also be divided in a grid manner, such as a 3×3 grid or a 4×4 grid.

[0061] Exemplarily, the terminal first obtains the chip layout design files of multiple sample chips from the historical chip design project, extracts layout information such as chip boundaries, module positions, and power pin coordinates, and generates the corresponding chip layout feature map. Next, the terminal divides the chip layout into multiple small areas according to the user's predefined division method, for example, the entire chip is divided into a 3×3 grid, and 9 small areas are generated, each of which contains power consumption information, current input and other features at its location. Then, the terminal uses an optimization algorithm (such as a simulated annealing algorithm) to select different templates in the template library for the layout design information and electrical performance requirements of each sample chip, selects the optimal power network template, and generates a template identifier for each area as label data. Finally, the terminal pairs the layout design information with the label data to form a training sample set for subsequent supervised learning model training.

[0062] Step S102: training a target chip power delivery network determination model based on the designed training samples.

[0063] The target chip power delivery network determination model is a machine learning model trained by a supervised learning method, which is used to predict the power network template identification corresponding to each area according to the chip layout design information. The input of the model is the chip layout design information, and the output is the template identification of each area.

[0064] Exemplarily, the terminal first loads the design training sample, including the input chip layout design information and the corresponding label data. The chip layout design information is used as the input feature of the model, including the power consumption requirements of the chip area, the power pin location, the module density and other feature matrices; the label data is the power network template identifier corresponding to each area.

[0065] The terminal builds an end-to-end supervised learning model to map input features to output labels. The structure of the model can be a deep learning model, such as a convolutional neural network (CNN) or a multilayer perceptron (MLP). During the training process, the terminal inputs the training sample into the model, calculates the error between the predicted output and the true label, and quantifies the error using a loss function (such as the cross entropy loss function). The terminal uses the backpropagation algorithm to adjust the model parameters according to the loss value. The optimization process usually uses the gradient descent algorithm or its variants (such as the Adam optimizer) to continuously optimize the model's predictive ability. During the training process, a batch training strategy is used to input the training samples in batches to improve computational efficiency. To prevent overfitting, the terminal can introduce regularization methods or perform training data enhancement operations.

[0066] After training is completed, the terminal evaluates the prediction effect of the model based on the performance indicators on the validation set (such as accuracy, F1 score, etc.) to ensure that it has good generalization ability on unseen data. If the validation effect is not ideal, the terminal can retrain the model by adjusting the model hyperparameters (such as learning rate, network depth, batch size, etc.) until the performance meets the requirements. Finally, the terminal generates and saves the trained target chip power delivery network determination model for the subsequent inference stage.

[0067] Step S103 , inputting the chip layout design information of the chip to be designed into the target chip power delivery network determination model to obtain a target power network template identifier corresponding to each area of ​​the chip to be designed.

[0068] Exemplarily, the terminal first receives the layout design file of the chip to be designed, and extracts information such as chip boundaries, functional module locations, and power pin coordinates. In order to ensure that the layout design information can be received and processed by the model, the terminal converts this information into a multi-dimensional matrix form, such as a power density map, a power pin map, and a module distribution map, and combines them into a tensor form that conforms to the input dimension. Subsequently, the terminal inputs the converted input tensor into the target chip power delivery network determination model to trigger the forward calculation process of the model. The model extracts local and global information from the input features through the convolution layer, such as data features such as power consumption intensity, power pin distance, and module distribution in a certain area, and sends these features to the fully connected layer to classify the power network template identification. The model outputs the template identification probability distribution corresponding to each area according to the characteristics of the area, and selects the template identification with the highest probability value as the prediction result. Finally, the model outputs a template identification list, and each element in the list represents the template identification of a certain area of ​​the chip to be designed. The terminal processes the template identification list output by the model and converts it into a readable format, such as "template 1", "template 2", etc., so as to be used to generate subsequent chip power delivery network design information.

[0069] Step S104, obtaining chip power transmission network information of the chip to be designed according to the target power network template identifier.

[0070] The target power network template identifier is an identifier of the power network template type used in each chip area, which is used to guide the wiring generation of a specific area. The chip power delivery network information is data information describing the chip power wiring structure, including specific wiring structures such as power pad location, power strip wiring, through-hole connection, and power rail.

[0071] Exemplarily, the terminal obtains the power network template corresponding to each identifier from the preset template library according to the template identifier list output by reasoning. Each template contains multi-layer information describing the power wiring method, such as the number of metal layers, strip width, wiring density, power strip direction and through-hole position. The terminal maps each power network template to the corresponding chip area according to the chip area division result. For multi-layer wiring templates, the terminal assigns them to different metal wiring layers of the chip to build a complete 3D power network structure. After the template mapping is completed, the terminal checks the connection relationship between the templates to ensure that the power strips in adjacent areas have good connectivity. When routing across layers, the terminal inserts conductive vias at the corresponding positions to connect the wiring of different metal layers to form a continuous power transmission path. At the same time, the terminal generates power pad connections at appropriate positions according to the design rules to provide sufficient contact area for power input. After completing the splicing of the power wiring structure, the terminal generates a complete chip power delivery network topology, including power pad positions, power strip direction, conductive vias and power rail information. The terminal outputs this information in a standardized design file format, such as DEF (Design Exchange Format) file or GDS (Graphic Data System) file, for subsequent wiring verification and design optimization processes.

[0072] In the above chip power delivery network determination method, first, a design training sample of the chip power delivery network is obtained, wherein the design training sample at least includes chip layout design information and label data of the sample chip, and the label data represents the power network template identifier corresponding to each area of ​​the sample chip. By obtaining the design training sample including the layout design information of the sample chip and the corresponding label data, high-quality training data can be provided for the supervised learning model. The label data clearly marks the power network template identifier corresponding to each area, so that the model can learn the mapping relationship between the layout design information and the template selection; then, according to the design training sample, the target chip power delivery network determination model is trained, and the design training sample is trained by In the supervised learning process, a target model that can directly predict the power network template identification from the layout design information is trained; then, the chip layout design information of the chip to be designed is input into the target chip power delivery network determination model to obtain the target power network template identification corresponding to each area of ​​the chip to be designed. The trained model is used to input the layout information of the chip to be designed, and the template identification prediction for each chip area is realized. This process only requires one forward reasoning to complete, avoiding multiple iterative calculations in traditional methods, significantly improving the design efficiency, and being able to output a template identification that meets the performance requirements in a short time; finally, according to the target power network template identification, the chip power delivery network information of the chip to be designed is obtained, and the predicted template identification is converted into the power delivery network design information to generate a complete chip power delivery network structure, simplifying the workflow from design input to wiring output, making the power network design more automated, and effectively improving the design efficiency. In the above method, the design task of the power delivery network is converted into a data-driven prediction process through the supervised learning method, realizing the automation process from chip layout design information to power network design output. Compared with traditional optimization algorithms, this solution avoids tedious multiple iterative calculations, greatly improves design efficiency, shortens the design cycle, and at the same time maintains high accuracy and adaptability in large-scale chip design, effectively solving the problem of low efficiency of traditional methods in complex chip design.

[0073] In an exemplary embodiment, Figure 2 As shown, the above step S101 obtains the design training sample of the chip power delivery network, which can also be implemented by the following steps:

[0074] Step S201, generating a plurality of power network templates based on preset parameter information, and obtaining chip layout design information of a sample chip;

[0075] Step S202 , using a preset chip power delivery network optimization model, according to chip layout design information of the sample chip and a plurality of power network templates, obtain a power network template identifier corresponding to each area of ​​the sample chip.

[0076] Among them, the preset parameter information is a set of rules for generating power network templates, including parameters such as wiring density, power strip direction, number of metal layers, strip width and through-hole position. The power network template is a multi-layer 3D template that describes the wiring structure of the power network, which is used to provide a stable power supply structure for each area of ​​the chip. The chip power delivery network optimization model is an optimization algorithm model for selecting the optimal power network template. By comparing the performance indicators of different templates, the optimal template identification for each area is obtained.

[0077] Exemplarily, the terminal first generates multiple power network templates with different wiring characteristics based on preset parameter information. Each template defines different wiring directions, strip spacing, and metal layer structures, forming a set of template libraries covering different power consumption requirements. Subsequently, the terminal loads the chip layout design file from the design database of the sample chip, extracts information such as chip boundaries, module locations, and power pin locations, and generates a feature map describing power consumption distribution and module density.

[0078] Next, the terminal inputs the layout design information of the sample chip into the preset chip power delivery network optimization model. The optimization model uses a heuristic algorithm or a simulated annealing algorithm to load different power network templates for each chip area in turn, and calculates the power network performance indicators, including the reliability indicator of voltage drop and the wiring resource occupancy rate indicator. The optimization model continuously compares these indicators in multiple iterations, and selects the template identification that best balances power supply stability and wiring resource efficiency as the label data for the area. Finally, the terminal generates complete sample data based on the template identification of all areas, pairs the chip layout design information with the template identification label data, and constructs a high-quality training sample set.

[0079] In this embodiment, by generating a power network template with diverse wiring characteristics and structures, and combining the optimization model to analyze and screen the layout design information, high-quality training data labels are automatically generated. The optimization algorithm is used to automatically generate label data, which improves the efficiency of training sample generation and label accuracy, thereby providing more representative and reliable training data for the supervised learning model and improving the overall performance of the power network design model.

[0080] In an exemplary embodiment, the above-mentioned step S202 adopts a preset chip power delivery network optimization model, obtains a power network template identification corresponding to each area of ​​the sample chip according to the chip layout design information of the sample chip and multiple power network templates, and also includes: iteratively determining optimization evaluation information of multiple power network templates for each area of ​​the sample chip according to the chip layout design information of the sample chip and multiple power network templates; the optimization evaluation information at least includes voltage drop reliability index information and wiring resource occupancy index information; according to the optimization evaluation information, determines the optimal power network template corresponding to each area of ​​the sample chip from the multiple power network templates; and uses the power network template identification of the optimal power network template corresponding to each area of ​​the sample chip as the power network template identification corresponding to each area of ​​the sample chip.

[0081] Among them, the chip power delivery network optimization model is an algorithm model used to select the optimal power network template. By analyzing and comparing the performance of different templates, the template identification of each area is generated. The optimization evaluation information is the performance index for evaluating the power network template when applied in a specific area, including voltage drop reliability index information and wiring resource occupancy index information. The voltage drop reliability index information is used to measure the voltage drop of the template on the power supply path to ensure the stability of power supply. The wiring resource occupancy index information is used to measure the wiring resource usage of the template on the metal layer to ensure that the resource occupancy does not exceed the limit.

[0082] Exemplarily, the terminal first divides the chip into multiple regions according to the layout design information of the sample chip, and loads multiple power network templates with different characteristics from the template library. The terminal loads different templates for each region in turn, and inputs the chip power delivery network optimization model for performance analysis. In each iteration, the model evaluates the current template based on the voltage drop reliability index information and the wiring resource occupancy index information. The voltage drop reliability index evaluates the voltage drop from the power pin to the power supply path of the region by simulating the current distribution and voltage change, ensuring that the voltage drop does not exceed the preset threshold. The wiring resource occupancy index evaluates whether the template uses resources reasonably by calculating the occupancy ratio of the wiring strip on the metal layer to avoid congestion caused by overload of wiring resources. In multiple rounds of iterations, the terminal compares the optimization results of different templates based on performance evaluation. When a template reaches a balance in terms of power supply stability and resource utilization, the terminal records it as a candidate template for the region. Finally, after all iterations are completed, the terminal selects the template with the best performance in each region and generates the optimal power network template identifier. For each area, the terminal uses the optimal template identification as the output label and generates a power network template identification list to complete the label generation process of the sample chip.

[0083] In this embodiment, the optimization algorithm is introduced in the design training sample generation stage to perform performance analysis and multiple rounds of screening on the power network template, so that the label generation process can accurately select the optimal template identification for each chip area. Since optimization algorithms such as simulated annealing and other methods have high accuracy, but require multiple iterative calculations, these algorithms are applied in the training data generation stage to ensure that the generated training data has high-quality labels and provide accurate sample input for the supervised learning model. In the design reasoning stage, the trained supervised learning model is directly used to efficiently output the template identification corresponding to each area through a forward reasoning, avoiding repeated time-consuming optimization calculations in the design stage, thereby significantly improving the design efficiency and achieving the real-time requirements of complex chip power network design while maintaining high accuracy.

[0084] In an exemplary embodiment, the above step S201 generates multiple power supply network templates based on preset parameter information, and also includes: generating different types of two-dimensional wiring templates according to different combinations of preset parameter information; randomly or according to preset rules, combining the two-dimensional wiring templates to generate a multi-layer three-dimensional power supply network template, and using a multi-layer three-dimensional power supply network template as a power supply network template.

[0085] Among them, the preset parameter information is a set of rules for generating power network templates, including parameters such as wiring direction, wiring density, number of metal layers, strip width and through-hole position. The two-dimensional wiring template is a template that describes a single-layer metal wiring structure and is used to define the wiring method of the metal layer, such as strip spacing, direction and conductive properties. The three-dimensional power network template is a multi-layer template generated by stacking multiple two-dimensional wiring templates in a specific combination. It describes the 3D structure of the entire power network, and each three-dimensional template corresponds to a different wiring strategy.

[0086] Exemplarily, the terminal first generates different types of two-dimensional wiring templates according to preset parameter information. Specifically, the terminal generates horizontal wiring templates and vertical wiring templates according to the wiring direction parameters, sets the spacing and width of the strips according to the wiring density parameters, and generates high-density, medium-density, and low-density templates. Each two-dimensional template is configured according to parameters such as metal layer thickness and conductivity characteristics to adapt to different power requirements.

[0087] After generating the two-dimensional wiring template, the terminal combines multiple two-dimensional wiring templates randomly or according to preset rules to generate a multi-layer three-dimensional power network template. The random combination method randomly selects different two-dimensional templates for stacking within the wiring direction and density range to explore a variety of wiring structure combinations; while the preset rule combination method combines different two-dimensional templates according to the strategy defined by the design requirements, such as giving priority to combining high-density templates in high-power consumption areas and combining low-density templates in low-power consumption areas. The generated three-dimensional power network template consists of multiple layers of metal wiring layers, each of which represents a specific wiring pattern and structure. The terminal regards each three-dimensional power network template as a complete power network template and saves it in the template library for subsequent power network design and optimization model performance evaluation.

[0088] In this embodiment, a template library with multiple wiring strategies is constructed by generating a variety of two-dimensional wiring templates according to preset parameter information, and combining them in a random or regular manner to generate a three-dimensional power network template. Therefore, a large number of power network templates covering different needs can be generated in a short time, which improves the flexibility and diversity of template generation, provides a wealth of options for subsequent power network design, and effectively enhances the automation and efficiency of power network design.

[0089] In an exemplary embodiment, the above step S103 inputs the chip layout design information of the chip to be designed into the target chip power delivery network determination model to obtain the target power network template identifier corresponding to each area of ​​the chip to be designed, and also includes: extracting the chip current information and chip power pin information corresponding to each area of ​​the chip to be designed from the chip layout design information of the chip to be designed; and obtaining the target power network template identifier corresponding to each area of ​​the chip to be designed according to the chip current information and chip power pin information corresponding to each area of ​​the chip to be designed.

[0090] Among them, chip current information is characteristic data describing the power consumption requirements and current density distribution of each area in the chip, reflecting the power intensity of different areas. Chip power pin information is design data describing the chip power input location, including the number, location coordinates and type of power pins (such as VDD (power supply line in power strip or power rail) or VSS (ground line in power strip or power rail)).

[0091] Exemplarily, the terminal first extracts the layout division result from the chip layout design information of the chip to be designed, and divides the chip into multiple independent areas. Then, the terminal extracts the chip current information corresponding to each area, including the power consumption value and spatial distribution of all functional modules in the area, and summarizes this information to generate a current distribution map. At the same time, the terminal extracts the location information of the chip power pin from the layout design information, and generates a distance map from each area to the nearest power pin to reflect the power supply path length of different areas. After obtaining the chip current information and power pin information, the terminal inputs these feature data into the target chip power delivery network determination model, and the model performs forward reasoning based on the input features of each area. The model analyzes the chip current distribution map and the power pin distance map through the internal feature extraction layer, captures the power consumption requirements and power supply path characteristics of different areas, and uses the fully connected layer to classify the feature data, and outputs the target power network template identification of each area. The model's calculation process for each area is independent, so that it can output the optimal power network template identification according to the local characteristics of each area.

[0092] It should be pointed out that during the model training phase, the terminal will also extract chip current information and chip power pin information from the layout design information of the sample chip as training input features. Specifically, during training, the terminal will extract feature data such as power consumption distribution and power pin distance for multiple regions of each sample chip to form an input feature matrix; at the same time, the corresponding power network template identifier is used as label data. By constructing such input-output pairs, the supervised learning model can learn the mapping relationship between the power consumption characteristics of each region and the template number, ensuring accurate matching of the optimal template during the inference phase.

[0093] In this embodiment, by extracting chip current information and chip power pin information from chip layout design information, fine-grained analysis of each regional feature is achieved, ensuring the integrity and pertinence of input data. The chip current information describes the power consumption requirements and current density distribution of each region, so that the model can perceive the different requirements of high power consumption areas and low power consumption areas, thereby outputting a matching power network template, improving the refinement of the power network design, and avoiding insufficient power supply or waste of resources. The chip power pin information provides the location information of the power input port, so that the model can calculate the length of the power supply path and select a low-impedance wiring template suitable for long-distance power supply, thereby reducing voltage drop and improving power supply stability. In addition, the combination of these two input parameters enables the model to comprehensively consider the characteristics of power consumption and power supply paths during reasoning, and improves the local adaptability of template selection. In areas with high power consumption and far away from the pins, the model can select a high-density wiring scheme, while in areas with low power consumption or close to the pins, a low-density scheme can be selected to avoid excessive wiring and resource congestion, and improve the utilization efficiency of wiring resources. Therefore, through fine-grained input feature analysis, the selection of power network templates is more accurate, the flexibility and adaptability of power network design are enhanced, and the overall design efficiency and power supply performance are improved. In addition, compared with the simple global layout feature input method, this embodiment performs independent feature extraction and inference for each region, avoiding the problem of inaccurate local prediction caused by global parameter averaging, ensuring the refinement and efficiency of power network template matching, and improving the overall efficiency and accuracy of chip power delivery network design.

[0094] In an exemplary embodiment, the above step S104 obtains the chip power delivery network information of the chip to be designed according to the target power network template identifier, and also includes: obtaining the target power network template corresponding to the target power network template identifier; applying the target power network template to each area of ​​the chip to be designed, splicing to form the power delivery network topology structure information of the chip to be designed, and obtaining the chip power delivery network information of the chip to be designed.

[0095] Among them, the chip power delivery network topology information refers to the layout structure of the power network on the entire chip, including the specific positions and connection relationships of wiring components such as power pads, power strips, conductive vias and power rails.

[0096] Exemplarily, the terminal first loads the target power network template corresponding to the target power network template identifier of each area obtained by reasoning from the template library. Each template contains the wiring information of multiple metal layers, such as the direction and density of the power strip, the wiring structure of the power rail, and the location of the conductive vias connected across layers. After loading the template, the terminal maps the target power network template to the corresponding area of ​​the chip to be designed. For each area, the terminal generates the power strip wiring structure according to the rules defined by the template, and applies the wiring information in the template to different metal layers of the chip. The terminal splices at the boundary of the area to ensure that the power strips between adjacent areas are connected at the boundary, and inserts conductive vias at the cross-layer position to ensure the connection continuity between different metal layers. After completing the template mapping and splicing of all areas, the terminal generates a complete chip power delivery network topology, including power pads, power strip direction, conductive via location and power rail information. The terminal outputs this information in a standardized design file format (such as DEF or GDS format) for subsequent design verification and optimization links.

[0097] In this embodiment, by loading the corresponding target template according to the target power network template identifier and performing a splicing operation, the construction from the template identifier to the complete power network topology structure is realized. By automatically completing the wiring generation process and ensuring the connection continuity across regions and layers during the splicing process, the automation level and consistency of the power transmission network design are improved, the risk of errors in manual operations is reduced, and the design efficiency and overall power supply performance are significantly improved.

[0098] In an exemplary embodiment, Figure 3 As shown, the present application provides a chip power delivery network determination system, including a macro unit layout module 301, a network template generation module 302, a data set generation module 303, a machine learning algorithm training module 304 and a power network generation module 305.

[0099] Among them, (1) the macro cell layout module 301 is responsible for generating layout results and obtaining a layout design file (DEF file). The DEF file serves as the input of the entire chip power delivery network determination system.

[0100] (2) Network template generation module 302, used to generate a series of different power network templates. The template is a 3D structure, divided into different layers, the total number of layers is the same as the number of layers that can be wired in the chip (the specific number of layers depends on the process, generally about 9 layers); a 2D power transmission network with a certain density is designed on each layer. The design of this system makes the 2D network density of the corresponding layer different between different 3D templates. A set of custom data structures is designed to store template information, and these different 3D templates are numbered to obtain a template library set.

[0101] (3) Dataset generation module 303 is used to generate a data set for training a machine learning algorithm based on the designed template. The independent variables of the data set are the existing chip current map and chip power pin map, and the label to be generated is the template number to be applied to each area of ​​the chip. A method with high accuracy in designing power delivery networks (such as simulated annealing algorithm) is used to generate labels based on the current map and power pin map, in which a voltage drop evaluator and a fast router are required to respectively evaluate the voltage drop reliability index and the routing resource occupancy index.

[0102] (4) A machine learning algorithm training module 304, which uses the generated data set to train a machine learning classification module.

[0103] (5) Power network generation module 305: In a new power transmission network design task, given the upstream file to be designed, the trained machine learning model is used to infer the template to be applied in each area, and the result is generated as a network topology and outputs the design file. Figure 4 A schematic diagram showing the use of power network templates to splice a chip power delivery network.

[0104] Furthermore, the key structure of the chip power delivery network determination model based on machine learning classification algorithm is as follows: Figure 5 The convolutional neural network (CNN) model shown in the figure. (1) The function of the convolution layer is to extract features from the input data, and it contains multiple convolution kernels. When the convolution kernel is working, it will regularly scan the input features, perform matrix element multiplication and sum the input features within the receptive field, and superimpose the bias. The ReLU excitation function is used in the convolution layer to help express complex features, and its representation is as follows: f(x)=max(0,x). (2) The pooling layer uses max-pooling. (3) The number of categories after the fully connected layer is the number of templates N. (4) The activation function uses Softmax to predict the probability of each category and obtain the most suitable power delivery network template for each chip area.

[0105] Furthermore, the power network generation module 305 generates the abstract design result into a real chip power network through a series of custom data structures and functions. The classes are as follows:

[0106] (1) The top-level module GridManager class that implements power network management. Functions include: (a) defining power network parameters, including power strip type VDD (power line in power strip or power rail) or VSS (ground line in power strip or power rail), region shape (rectangular or irregular), and power strip direction (horizontal or vertical); (b) defining the data structure PDNGridTemplate class representing the template, and the PDNGridRegion class representing the specific information in the region; (c) reading chip parameters of the upstream design, including chip length and width, chip macro unit layout position, power pin position, template library information, and template number.

[0107] (2) Implement the specific routing module PowerRouter class, which converts the above information into actual chip parameters according to the standard DEF file format, including power pads, power stripes, vias, power rails, etc.

[0108] (3) Design the interaction module DatabaseInteract class between parameters and system database.

[0109] In this embodiment, (1) by using a machine learning algorithm, the forward reasoning process of generating a power delivery network runs very fast, which improves efficiency. The problem of the time-consuming iterative method of using a power delivery network analyzer after generating a power delivery network is overcome; the running speed is also better than the method of using machine learning to predict voltage drop. (2) Under the constraint of meeting the design rule check, the power supply strips in different areas of a single wiring metal layer are allowed to be designed to be non-uniform. Such a design can adapt to the irregular placement of components in the chip under different processes, flexibly adjust the wiring density, and improve robustness. (3) In the generation of training samples of the model, information including voltage drop and wiring congestion is used, and these two evaluation indicators are comprehensively considered, so that on the basis of meeting the power supply voltage drop constraint, the occupation of wiring metal layer resources is reduced as much as possible, the wiring congestion problem is avoided, and the reliability is improved. (4) The convolutional neural network used in the algorithm is an end-to-end model, which directly generates a layout design file based on the upstream file, avoids the cyclic iteration process, and reduces the complexity of the process steps.

[0110] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0111] Based on the same inventive concept, the embodiment of the present application also provides a chip power delivery network determination device for implementing the chip power delivery network determination method involved above. The implementation scheme for solving the problem provided by the device is similar to the implementation scheme recorded in the above method, so the specific limitations in one or more embodiments of the chip power delivery network determination device provided below can refer to the limitations of the chip power delivery network determination method above, and will not be repeated here.

[0112] In an exemplary embodiment, Figure 6 As shown, a device for determining a chip power delivery network is provided, comprising: a sample acquisition module 601, a model training module 602, a model reasoning module 603 and a network determination module 604, wherein:

[0113] The sample acquisition module 601 is used to acquire a design training sample of a chip power delivery network; the design training sample at least includes chip layout design information and label data of the sample chip; the label data indicates a power network template identifier corresponding to each area of ​​the sample chip;

[0114] A model training module 602 is used to train a target chip power delivery network determination model according to a design training sample;

[0115] The model reasoning module 603 is used to input the chip layout design information of the chip to be designed into the target chip power delivery network determination model to obtain the target power network template identifier corresponding to each area of ​​the chip to be designed;

[0116] The network determination module 604 is used to obtain chip power transmission network information of the chip to be designed according to the target power network template identifier.

[0117] In one of the embodiments, the sample acquisition module 601 is also used to generate multiple power network templates based on preset parameter information and obtain chip layout design information of the sample chip; using a preset chip power delivery network optimization model, according to the chip layout design information of the sample chip and multiple power network templates, obtain the power network template identification corresponding to each area of ​​the sample chip.

[0118] In one of the embodiments, the sample acquisition module 601 is further used to iteratively determine optimization evaluation information of multiple power supply network templates for each area of ​​the sample chip based on the chip layout design information of the sample chip and multiple power supply network templates; the optimization evaluation information at least includes voltage drop reliability index information and wiring resource occupancy index information; based on the optimization evaluation information, determine the optimal power supply network template corresponding to each area of ​​the sample chip from the multiple power supply network templates; and use the power supply network template identifier of the optimal power supply network template corresponding to each area of ​​the sample chip as the power supply network template identifier corresponding to each area of ​​the sample chip.

[0119] In one of the embodiments, the sample acquisition module 601 is also used to generate different types of two-dimensional wiring templates according to different combinations of preset parameter information; randomly or according to preset rules, the two-dimensional wiring templates are combined to generate a multi-layer three-dimensional power supply network template, and a multi-layer three-dimensional power supply network template is used as a power supply network template.

[0120] In one of the embodiments, the above-mentioned model reasoning module 603 is also used to extract the chip current information and chip power pin information corresponding to each area of ​​the chip to be designed from the chip layout design information of the chip to be designed; according to the chip current information and chip power pin information corresponding to each area of ​​the chip to be designed, the target power network template identifier corresponding to each area of ​​the chip to be designed is obtained respectively.

[0121] In one of the embodiments, the network determination module 604 is further used to obtain a target power network template corresponding to the target power network template identifier; apply the target power network template to each area of ​​the chip to be designed, splice to form the power delivery network topology structure information of the chip to be designed, and obtain the chip power delivery network information of the chip to be designed.

[0122] Each module in the above chip power delivery network determination device can be implemented in whole or in part by software, hardware, or a combination thereof. Each module can be embedded in or independent of a processor in a computer device in the form of hardware, or can be stored in a memory in a computer device in the form of software, so that the processor can call and execute operations corresponding to each module.

[0123] In an exemplary embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as shown in FIG. Figure 7 As shown. The computer device includes a processor, a memory, an input / output interface, a communication interface, a display unit and an input device. The processor, the memory and the input / output interface are connected through a system bus, and the communication interface, the display unit and the input device are connected to the system bus through the input / output interface. The processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal in a wired or wireless manner, and the wireless manner can be implemented through WIFI, a mobile cellular network, near field communication (NFC) or other technologies. When the computer program is executed by the processor, a chip power delivery network determination method is implemented. The display unit of the computer device is used to form a visually visible picture, which can be a display screen, a projection device or a virtual reality imaging device. The display screen can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covering the display screen, or a button, trackball or touchpad set on the computer device shell, or an external keyboard, touchpad or mouse.

[0124] Those skilled in the art will understand that Figure 7 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0125] In one embodiment, a computer device is further provided, including a memory and a processor, wherein a computer program is stored in the memory, and the processor implements the steps in the above method embodiments when executing the computer program.

[0126] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0127] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.

[0128] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0129] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., but are not limited to this.

[0130] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0131] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A method for determining a chip power delivery network, characterized in that: The method comprises: Acquire a design training sample of a chip power delivery network; the design training sample at least includes chip layout design information and label data of a sample chip; the label data indicates a power network template identifier corresponding to each area of ​​the sample chip; According to the designed training samples, a target chip power delivery network determination model is obtained through training; Inputting chip layout design information of the chip to be designed into the target chip power delivery network determination model to obtain a target power network template identifier corresponding to each area of ​​the chip to be designed; Obtaining chip power transmission network information of the chip to be designed according to the target power network template identifier; The step of obtaining a design training sample of a chip power delivery network includes: Based on preset parameter information, multiple power network templates are generated, and chip layout design information of the sample chip is obtained; the preset parameter information includes wiring density, power strip direction, number of metal layers, strip width and through-hole position; the power network template is a multi-layer 3D template that describes the power network wiring structure; Iteratively determine optimization evaluation information of the multiple power network templates for each area of ​​the sample chip according to the chip layout design information of the sample chip and the multiple power network templates; According to the optimization evaluation information, determining the optimal power supply network template corresponding to each area of ​​the sample chip from the multiple power supply network templates; The power supply network template identifier of the optimal power supply network template corresponding to each area of ​​the sample chip is used as the power supply network template identifier corresponding to each area of ​​the sample chip.

2. The method according to claim 1, characterized in that The optimization evaluation information at least includes voltage drop reliability index information and wiring resource occupancy rate index information.

3. The method according to claim 1, characterized in that The generating of multiple power supply network templates based on the preset parameter information includes: Generate different types of two-dimensional wiring templates according to different combinations of the preset parameter information; The two-dimensional wiring templates are combined randomly or according to preset rules to generate a multi-layer three-dimensional power supply network template, and one of the multi-layer three-dimensional power supply network templates is used as a power supply network template.

4. The method according to claim 1, characterized in that: The step of inputting chip layout design information of the chip to be designed into the target chip power delivery network determination model to obtain a target power network template identifier corresponding to each area of ​​the chip to be designed includes: Extracting chip current information and chip power pin information corresponding to each area of ​​the chip to be designed from the chip layout design information of the chip to be designed; According to the chip current information and chip power pin information corresponding to each area of ​​the chip to be designed, the target power network template identifier corresponding to each area of ​​the chip to be designed is obtained respectively.

5. The method according to claim 1, characterized in that The step of obtaining chip power transmission network information of the chip to be designed according to the target power network template identifier includes: Acquire a target power supply network template corresponding to the target power supply network template identifier; The target power supply network template is applied to each area of ​​the chip to be designed, and the power supply network topology information of the chip to be designed is formed by splicing, so as to obtain the chip power supply network information of the chip to be designed.

6. A device for determining a chip power delivery network, characterized in that: The device comprises: A sample acquisition module is used to acquire a design training sample of a chip power delivery network; the design training sample at least includes chip layout design information and label data of the sample chip; the label data indicates a power network template identifier corresponding to each area of ​​the sample chip; A model training module, used for training a target chip power delivery network determination model according to the design training samples; A model reasoning module, used for inputting chip layout design information of the chip to be designed into the target chip power delivery network determination model to obtain a target power network template identifier corresponding to each area of ​​the chip to be designed; A network determination module, configured to obtain chip power transmission network information of the chip to be designed according to the target power network template identifier; The sample acquisition module is also used to generate multiple power supply network templates based on preset parameter information, and obtain chip layout design information of the sample chip; the preset parameter information includes wiring density, power strip direction, number of metal layers, strip width and through-hole position; the power supply network template is a multi-layer 3D template that describes the power supply network wiring structure; according to the chip layout design information of the sample chip and the multiple power supply network templates, iteratively determine the optimization evaluation information of the multiple power supply network templates for each area of ​​the sample chip; according to the optimization evaluation information, determine the optimal power supply network template corresponding to each area of ​​the sample chip from the multiple power supply network templates; and use the power supply network template identifier of the optimal power supply network template corresponding to each area of ​​the sample chip as the power supply network template identifier corresponding to each area of ​​the sample chip.

7. The device according to claim 6, characterized in that The optimization evaluation information at least includes voltage drop reliability index information and wiring resource occupancy rate index information.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 5 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 5 are implemented.

10. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 5 are implemented.

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