Wiring track grid generation method and related equipment for FinFET process

Abstract

The present application discloses a wiring track grid generation method for a FinFET process and related equipment, and relates to the field of EDA software. The method comprises: projecting the default grids of each wiring layer adjacent to a target wiring layer of the FinFET to the target wiring layer to obtain an alternative grid of the target wiring layer; obtaining a design check rule evaluation value of the default grid of the target wiring layer and a design check rule evaluation value of the alternative grid of the target wiring layer; and obtaining a wiring track grid of the target wiring layer from the default grid and the alternative grid of the target wiring layer according to the design check rule evaluation value of the default grid of the target wiring layer and the design check rule evaluation value of the alternative grid of the target wiring layer.

Description

Technical Field

[0001] The present specification relates to the field of EDA software, and more specifically, to a wiring track grid generation method and related equipment for FinFET process. Background Art

[0002] With the development of integrated circuit technology, chip design is moving towards higher density and smaller size. Especially in the FinFET (Fin Field-Effect Transistor) process, due to the introduction of three-dimensional structure, multi-layer metal wiring has become the core link in the design. In this process, the design of the wiring layer is particularly critical. It is used to connect transistors, logic units and other components inside the chip to realize the function of the complete circuit.

[0003] Each wiring layer is composed of metal wires, and the wires connect different levels of wiring layers through vias. In the FinFET process, multiple mask technology and high-density wiring requirements make the design rules of the wiring layer more stringent. In the scenario of multi-layer wiring, the traditional two-dimensional track grid often cannot efficiently handle the complexity of cross-layer wiring. The existing wiring method is mainly based on the single-layer grid generation of the target wiring layer, lacking multi-level grid information integration, resulting in limitations in path selection.

[0004] Therefore, it is necessary to propose a wiring track grid generation method and related equipment for FinFET process to at least solve some of the above problems. Summary of the invention

[0005] A series of simplified concepts are introduced in the Summary of the Invention section, which will be further described in detail in the Detailed Description of the Invention section. The Summary of the Invention section of this application does not mean to attempt to define the key features and essential technical features of the claimed technical solution, nor does it mean to attempt to determine the scope of protection of the claimed technical solution.

[0006] In a first aspect, the present application proposes a method for generating a wiring track grid for a FinFET process, comprising:

[0007] Projecting the default grids of each wiring layer adjacent to the target wiring layer of the FinFET to the target wiring layer to obtain a candidate grid for the target wiring layer;

[0008] Obtaining a design check rule evaluation value of a default grid of the target wiring layer and a design check rule evaluation value of an alternative grid of the target wiring layer;

[0009] According to the design check rule evaluation value of the default grid of the target wiring layer and the design check rule evaluation value of the candidate grid of the target wiring layer, the wiring track grid of the target wiring layer is obtained from the default grid and the candidate grid of the target wiring layer.

[0010] In a feasible implementation manner, the obtaining of the wiring track grid of the target wiring layer from the default grid and the candidate grid of the target wiring layer includes:

[0011] According to a global optimal strategy, select available candidate grids of the target wiring layer from the candidate grids of the target wiring layer;

[0012] According to the default grid of the target wiring layer and the available candidate grids, a wiring track grid of the target wiring layer is obtained.

[0013] In a feasible implementation manner, the obtaining of the design check rule evaluation value of the default grid of the target wiring layer and the design check rule evaluation value of the candidate grid of the target wiring layer includes:

[0014] According to the prediction algorithm and the wiring design rule of the target wiring layer, obtaining the design check rule evaluation value of the grid node of each default grid in the above target wiring layer;

[0015] According to the prediction algorithm and the adjacent wiring design rule of the target wiring layer, obtaining the design check rule evaluation value of the grid node of each candidate grid in the target wiring layer;

[0016] Among them, the above-mentioned prediction algorithm includes one or more of heuristic algorithm, machine learning algorithm and maximum likelihood estimation, and the above-mentioned wiring design inspection rules include one or more of short circuit rules, parallel routing length rules, loop rules and special rules of multiple mask technology.

[0017] In a feasible implementation manner, the above method further includes:

[0018] Obtaining wiring parameter information of the target wiring layer;

[0019] According to the wiring parameter information of the target wiring layer, a preset grid of the target wiring layer is established;

[0020] An alignment operation is performed based on the preset grid of the target wiring layer and the reference coordinates of the standard cells of the target wiring layer to generate a default grid of the target wiring layer.

[0021] In a feasible implementation manner, the above method further includes:

[0022] Establishing a wiring track array of the target wiring layer in three-dimensional space;

[0023] The steps of generating the candidate grids of the current wiring layer, obtaining the available candidate grids of the current wiring layer and determining the available wiring grids of the current wiring layer are executed through the wiring track array, wherein the wiring track array includes logical nodes, physical nodes, edges, default directions, custom directions and design check rule evaluation values, the logical nodes are abstract points in the wiring track grids, the physical nodes are mapping points of the logical nodes on the actual metal layer, the edges are wiring paths connecting two nodes, the default directions are directions corresponding to the default grids of the wiring layer, the custom directions are the candidate grids of the wiring layer, and the design check rule evaluation values ​​are six design check rule evaluation values ​​corresponding to the logical nodes in the six degrees of freedom directions.

[0024] In a feasible implementation manner, the above method further includes:

[0025] Determine the wiring process according to the FinFET process file;

[0026] Determine the dimension information of the grid to be generated based on the above wiring process;

[0027] When the dimension information of the grid to be generated is three-dimensional, a projection control instruction is generated, wherein the projection control instruction is used to trigger the execution of the operation of projecting the default grids of each wiring layer adjacent to the target wiring layer of the FinFET to the target wiring layer.

[0028] In a feasible implementation manner, the above method further includes:

[0029] Obtaining line spacing difference information between track grids of each wiring layer of the FinFET;

[0030] The wiring track grid of the target wiring layer is optimized based on a multi-objective optimization algorithm and the line spacing difference information to obtain an optimized wiring track grid of the target wiring layer.

[0031] In a second aspect, the present application proposes a wiring track grid generation device for FinFET process, comprising:

[0032] A projection unit, used for projecting the default grids of each wiring layer adjacent to the target wiring layer of the FinFET to the target wiring layer to obtain the candidate grid of the target wiring layer;

[0033] A first acquisition unit is used to acquire a design check rule evaluation value of a default grid of the target wiring layer and a design check rule evaluation value of a candidate grid of the target wiring layer;

[0034] The second acquisition unit is used to acquire the wiring track grid of the target wiring layer from the default grid and the alternative grid of the target wiring layer according to the design check rule evaluation value of the default grid of the target wiring layer and the design check rule evaluation value of the alternative grid of the target wiring layer.

[0035] In a third aspect, an electronic device comprises: a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor is configured to implement the steps of a wiring track grid generation method for a FinFET process as described in any one of the first aspects above when executing the computer program stored in the memory.

[0036] In a fourth aspect, the present application further proposes a computer-readable storage medium having a computer program stored thereon, and when the computer program is executed by a processor, the wiring track grid generation method for the FinFET process of any one of the first aspects is implemented.

[0037] In summary, this method generates alternative grids by projecting the default grids of adjacent layers to the target wiring layer. The default grids of adjacent layers and the default grids of the target wiring layer together provide diversified path selection for the wiring algorithm, significantly improving the utilization of wiring resources. By eliminating high-risk nodes through the design inspection rule evaluation value, the wiring track grid finally generated has higher design reliability and reduces violation problems. By projecting and integrating the default grids of adjacent layers and the target wiring layer, the cross-layer wiring path is optimized to ensure the coherence and rule consistency of the wiring track, which is particularly suitable for complex scenarios of multi-layer wiring. This method greatly reduces the solution space of the wiring algorithm by pre-integrating multi-level information and rule evaluation when generating the track grid, thereby improving the efficiency of the algorithm. Due to its three-dimensional structural characteristics, the FinFET process has higher requirements for the generation of wiring track grids. This method meets the design requirements of the FinFET process for high-density wiring through the integration and optimization of multi-level information. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present specification. Also, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

[0039] Figure 1 A schematic diagram of a process for generating a wiring track grid for a FinFET process provided in an embodiment of the present application;

[0040] Figure 2 A schematic diagram of the structure of a wiring track grid generation device for a FinFET process provided in an embodiment of the present application;

[0041] Figure 3 A schematic structural diagram of a wiring track grid generation electronic device for a FinFET process provided in an embodiment of the present application. DETAILED DESCRIPTION

[0042] The terms "first", "second", "third", "fourth", etc. (if any) in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments described herein can be implemented in an order other than that illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices. The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments.

[0043] Figure 1 A schematic diagram of a process for generating a wiring track grid for a FinFET process provided in an embodiment of the present application. Figure 1 As shown, the wiring track grid generation method of the FinFET process includes at least the following steps S110 to S130.

[0044] S110 , projecting the default grids of each wiring layer adjacent to the target wiring layer of the FinFET to the target wiring layer to obtain a candidate grid of the target wiring layer.

[0045] In some embodiments, the routing layer refers to the metal layer used to arrange the signal or power / ground network in the physical design of the chip. These metal layers connect the endpoints of the transistors (or other components) to each other through specific layouts and rules to realize the chip functions. The routing layer is the area used to arrange metal wires in the chip design. Each routing layer is composed of a group of metal wires, which are usually made of aluminum or copper materials. Its function is to connect the various components in the chip (such as transistors, logic units) to each other through metal wires to form a complete circuit. Integrated circuits usually have multiple layers of wiring, each layer is separated from each other and connected through "vias".

[0046] If the target wiring layer is the bottom layer, the adjacent wiring layer is the upper layer of the bottom layer. If the target wiring layer is the middle layer, the adjacent wiring layers are the upper and lower layers of the target wiring layer. If the target wiring layer is the top layer, the adjacent wiring layers are the lower layer adjacent to the top layer. By projecting the default grids of each wiring layer adjacent to the target wiring layer to the target wiring layer, a cross-layer spare grid can be generated for the target wiring layer, providing multiple path options for the wiring algorithm. The target wiring layer therefore has the default grid generated by the target wiring layer itself and the alternative grids projected from the adjacent layers.

[0047] S120 , obtaining a default grid design check rule evaluation value of the target wiring layer and a design check rule evaluation value of the candidate grid of the target wiring layer.

[0048] In some embodiments, a design rule check (DRC) evaluation is performed on a default grid and an alternative grid of a target wiring layer to obtain an evaluation value of each grid, that is, a design rule check evaluation value of the default grid of the target wiring layer and a design rule check evaluation value of the alternative grid of the target wiring layer are obtained.

[0049] The evaluation value of the grid includes the feasibility of evaluating the various network nodes that make up the grid in different routing directions to avoid potential DRC violations. Each grid node of the default grid and the alternative grid is evaluated in 6 degrees of freedom (up and down, left and right, front and back). The evaluation value includes possible DRC violations, such as short spacing, long parallel run length, etc.

[0050] S130, acquiring a routing track grid of the target wiring layer from the default grid and the candidate grids of the target wiring layer according to the design check rule evaluation value of the default grid of the target wiring layer and the design check rule evaluation value of the candidate grid of the target wiring layer.

[0051] In some embodiments, according to the design check rule evaluation value of the default grid of the target wiring layer and the design check rule evaluation value of the candidate grid of the target wiring layer, the grids that meet the design rules are screened out from the default grid and the candidate grids to generate the wiring track grid. By integrating multi-level grid information, it is ensured that the wiring track meets the DRC rules and provides an optimization path for the wiring algorithm.

[0052] In some embodiments, nodes with high violation risk are eliminated based on the design check rule evaluation value of the default grid of the target wiring layer and the design check rule evaluation value of the candidate grid of the target wiring layer. The remaining default grid and the candidate grid are merged to generate a wiring track grid of the target wiring layer.

[0053] In summary, this method generates alternative grids by projecting the default grids of adjacent layers to the target wiring layer. The default grids of adjacent layers and the default grids of the target wiring layer provide diversified path selection for the wiring algorithm, significantly improving the utilization of wiring resources. High-risk nodes are eliminated by designing the inspection rule evaluation value, so that the generated wiring track grid of the target wiring layer has higher design reliability and reduces violation problems. Through the projection and integration of the default grids of adjacent layers and the target wiring layer, this method optimizes the cross-layer wiring path, ensures the coherence and rule consistency of the wiring track, and is particularly suitable for complex scenarios of multi-layer wiring. This method greatly reduces the solution space of the wiring algorithm by pre-integrating multi-level information and rule evaluation when generating the track grid, thereby improving the efficiency of the algorithm. Due to the three-dimensional structural characteristics of the FinFET process, higher requirements are placed on the generation of the wiring track grid. This method meets the design requirements of the FinFET process for high-density wiring through the integration and optimization of multi-level information.

[0054] In some embodiments, the above-mentioned obtaining of the wiring track grid of the target wiring layer from the default grid and the alternative grids of the target wiring layer includes: screening out the available alternative grids of the target wiring layer from the alternative grids of the target wiring layer according to the global optimal strategy; obtaining the wiring track grid of the target wiring layer according to the default grid of the target wiring layer and the available alternative grids.

[0055] Exemplarily, according to the global optimal strategy, available candidate grids that meet the DRC evaluation value are screened out from the candidate grids of the target wiring layer.

[0056] It should be noted that the target wiring layer is the wiring layer currently being processed, which is used to carry the signal connection in the chip design. Each wiring layer currently being processed of FinFET can be used as the target wiring. The wiring track grid of the target wiring layer needs to be dynamically adjusted in combination with the design rules and the adjacent layer information. The default grid is the initial wiring track grid generated by the target wiring layer according to its own design rules, which is mainly determined by the Pitch (wiring spacing), Width (wiring width) and direction constraints of the layer.

[0057] The candidate grid is a cross-level grid generated by projecting the default grid of the adjacent routing layer of the target routing layer to the target routing layer. The candidate grid provides more routing options for the target routing layer. Each candidate grid node calculates an evaluation value according to the requirements of DRC, indicating the availability of the node in different routing directions. DRC includes but is not limited to whether the minimum spacing (Pitch) is met, whether the minimum width (Width) is met, and whether there is metal overlap or short circuit (Short).

[0058] In some embodiments, selecting available candidate grids that meet DRC evaluation values ​​from candidate grids of the target wiring layer according to a global optimal strategy may include: selecting available candidate grids that meet DRC evaluation values ​​from candidate grids according to a global optimal strategy and rule constraints.

[0059] In some embodiments, a DRC evaluation value is calculated for each candidate grid node, and the DRC evaluation values ​​of different candidate grid nodes are compared. According to the comparison result, illegal or high-risk nodes are eliminated to obtain nodes that meet the rule constraints. The nodes that meet the rule constraints are marked as available candidate grid nodes, and all available candidate grid nodes form an available candidate grid.

[0060] By integrating the default grid of the target wiring layer and the available alternative grids after screening, a wiring track grid of the target wiring layer that meets the design requirements is jointly generated. It should be noted that after the grid nodes of the default grid and the grid nodes of the alternative grid are generated in the logical space, they need to be converted into the physical coordinates of the chip through a mapping algorithm to ensure the alignment of the logical grid with the actual physical grid.

[0061] The available candidate grids that meet the global optimal strategy are merged with the default grid, and the routing track grid of the target routing layer is generated. Each grid node has six routing degrees of freedom (x positive, x negative, y positive, y negative, z positive, z negative). The routing degrees of freedom in each direction are associated with the corresponding DRC evaluation value to guide the routing algorithm to select the optimal path.

[0062] In some embodiments, obtaining the design check rule evaluation value of the default grid of the target wiring layer and the design check rule evaluation value of the candidate grid of the target wiring layer includes:

[0063] According to the prediction algorithm and the wiring design rules of the target wiring layer, the design check rule evaluation value of the grid node of each default grid in the above target wiring layer is obtained; according to the prediction algorithm and the adjacent wiring design rules of the target wiring layer, the design check rule evaluation value of the grid node of each alternative grid in the above target wiring layer is obtained.

[0064] Among them, the above-mentioned prediction algorithm includes one or more of heuristic algorithm, machine learning algorithm and maximum likelihood estimation, and the above-mentioned wiring design inspection rules include one or more of short circuit rules, parallel routing length rules, loop rules and special rules of multiple mask technology.

[0065] Exemplarily, the target wiring layer is the metal layer currently undergoing wiring optimization, and its grid nodes need to meet specific rules of process and design. The default grid is the initial wiring track grid automatically generated by the target wiring layer according to its metal pitch (Pitch), wiring width (Width) and other rules. The design check rule of the target wiring layer is that the grid nodes of the default grid must meet the wiring design rules of the target wiring layer. These rules are defined by the manufacturing process to ensure that the wiring can be reliably manufactured and meet electrical performance.

[0066] Wiring design rules include short circuit rule, parallel run length rule (PRL Rule) and multi-mask technology rules.

[0067] The short circuit rule is used to determine whether the node spacing is greater than the minimum allowed value n. The parallel routing length rule is used to determine whether the parallel routing length between nodes is less than the maximum allowed value. The loopback rule is used to detect whether there are unnecessary loops in the path formed by the grid nodes. The multi-mask technology rule is used to check whether the grid nodes meet the special rules of the multi-mask process, such as whether the metal wire overlap of the cross-layer routing meets the spacing requirements, the overlap of three parallel routings, the loopback routing, and other complex DRC rules.

[0068] For the grid solution of each default grid and the network nodes of each candidate grid in each target wiring layer, the prediction algorithm predicts whether the grid node meets the rule requirements based on the design rules and the position of the grid node, and generates the evaluation value of the grid node based on the prediction results. Common prediction algorithms include heuristic algorithms, machine learning algorithms, maximum likelihood estimation, etc. Heuristic algorithms can quickly evaluate the design rule compliance of nodes through rule-driven methods, which is suitable for rapid detection of simple rules. Machine learning algorithms are trained with training data to predict the evaluation values ​​of grid nodes, so that they can predict the risks of complex design rules, especially suitable for processing nonlinear and high-dimensional rules. Maximum likelihood estimation calculates the probability of violation of each grid node based on historical data.

[0069] Initialize the track nodes of the default grid according to the design rules of the target routing layer. Use the prediction algorithm to evaluate the grid nodes of each default grid, calculate the spacing between the grid node and other grid nodes, and check whether it meets the short circuit rule. Check the connection direction and length of adjacent nodes to evaluate whether it meets the parallel routing length rule. Analyze the path shape of the node and detect whether there is a loop. Generate a design check rule evaluation value (DRC evaluation value) for each grid node. A high evaluation value indicates a high risk of violation.

[0070] In summary, the method proposed in accordance with the embodiment of the present application supports the detection of short circuit rules, parallel routing length rules, loop rules and multiple mask technology rules, covering the main constraints of modern wiring design. In some embodiments, the most suitable evaluation method can be selected from heuristic algorithms, machine learning algorithms and maximum likelihood estimation according to the design complexity of FinFET. The information of the default grid and the alternative grid is integrated to improve the utilization of wiring resources and reduce conflicts. The method provided in this embodiment can handle the rule differences between the target wiring layer and the adjacent wiring layer, and support complex cross-layer wiring design.

[0071] In some embodiments, the above-mentioned wiring track grid generation method also includes: obtaining the wiring parameter information of the above-mentioned target wiring layer; establishing a preset grid of the current wiring layer according to the wiring parameter information of the current wiring layer; and performing an alignment operation based on the preset grid of the current wiring layer and the reference coordinates of the standard unit of the current layer to generate the default grid of the above-mentioned current wiring layer.

[0072] Exemplarily, the wiring parameter information of the target wiring layer can be extracted from the process file. The wiring parameter information is important data for defining the physical and logical characteristics of the target wiring layer, and the wiring parameter information includes but is not limited to wiring spacing, wiring width, wiring direction, and reference coordinates of standard cells.

[0073] The wiring pitch is the minimum spacing between adjacent wiring tracks, which is usually determined by the process technology. For example, in a 7nm process, the wiring pitch may be 16 nm. The wiring width is the width of a single wiring line, which is used to ensure signal integrity and manufacturing reliability. The wiring direction mainly includes horizontal or vertical. The reference coordinates of the standard cell are the reference coordinates corresponding to the standard cell, and the wiring grid needs to be aligned with the Fin (fin structure) track of the standard cell to ensure the accuracy of the logical function and physical layout.

[0074] Based on the wiring parameter information, a basic preset grid is established to provide an initial framework for subsequent grid alignment and optimization. According to the wiring spacing and wiring width, the logical coordinates of the grid nodes are calculated. For example, assuming that the wiring spacing is 16nm and the wiring width is 8nm. The generated grid node distribution is: (0, 0), (16, 0), (32, 0)...

[0075] Generate grids according to the routing direction. The grid nodes in the horizontal routing layer are The grid nodes in the vertical wiring layer are extended in the negative direction of the axis. The grid is extended in the negative direction of the axis. The grid boundary is defined according to the size range of the target wiring layer. For example, the chip size is , the grid nodes need to cover the entire range.

[0076] By aligning the preset grid with the reference coordinates of the standard cell, a default grid is generated that accurately matches the physical design. The standard cell reference coordinates are the Fin track coordinates inside the standard cell, indicating the exact start or end point of the cell-level routing. For example, the lower left corner of the standard cell is the standard cell reference coordinate; the standard cell reference coordinates are .

[0077] Calculate the offset between the lower left corner node of the preset grid and the standard unit reference coordinates .

[0078] Assume that the lower left corner node of the preset grid is , the alignment offset is:

[0079]

[0080] Adjust all mesh nodes of the preset mesh by the above offset:

[0081]

[0082] in, is the adjusted grid node horizontal coordinate, is the adjusted grid node ordinate. The adjusted grid is the default grid of the current wiring layer, ensuring that each grid node is accurately aligned with the reference coordinate of the standard cell.

[0083] The default grid is aligned with the standard cell reference coordinates to ensure seamless connection between the routing track and the physical design. The fast generation and alignment of the preset grid reduces the time cost of design iterations and complex adjustments.

[0084] In some embodiments, a routing track grid of a target routing layer may be generated in a pre-established three-dimensional space.

[0085] Establishing a wiring track array of the target wiring layer in three-dimensional space;

[0086] The steps of generating the candidate grids of the current wiring layer, obtaining the available candidate grids of the current wiring layer and determining the available wiring grids of the current wiring layer are executed through the wiring track array, wherein the wiring track array includes logical nodes, physical nodes, edges, default directions, custom directions and design check rule evaluation values, the logical nodes are abstract points in the wiring track grids, the physical nodes are mapping points of the logical nodes on the actual metal layer, the edges are wiring paths connecting two nodes, the default directions are directions corresponding to the default grids of the wiring layer, the custom directions are the candidate grids of the wiring layer, and the design check rule evaluation values ​​are six design check rule evaluation values ​​corresponding to the logical nodes in the six degrees of freedom directions.

[0087] Exemplarily, based on the characteristics of the FinFET process, a routing track array including logic nodes, physical nodes, edges, default directions, custom directions, and design check rule evaluation values ​​is created for the target routing layer.

[0088] A logical node is an abstract point in the wiring track grid, representing a coordinate point in the grid for calculation and analysis. The coordinates are expressed as (x, y, z) and are defined in the logical coordinate system.

[0089] The physical node is the mapping point of the logical node on the actual metal layer, which is used for physical layout. Through the mapping algorithm, the coordinates of the logical node are converted into physical coordinates to match the actual layout of the metal layer.

[0090] An edge is a routing path connecting two nodes, defining possible routing directions. Each edge is associated with a corresponding routing degree of freedom, such as the default direction or a custom direction.

[0091] The default direction is the primary routing direction of the routing layer (such as horizontal or vertical), generated by the default grid. Each edge connects adjacent logical nodes in the default direction, representing 2 routing degrees of freedom.

[0092] Custom directions are routing options other than the default directions, generated by alternative grids. Custom directions add additional routing freedom for routing across layers or in non-straight lines.

[0093] The design check rule evaluation value (DRC evaluation value) has a corresponding DRC evaluation value for each logical node in the six degrees of freedom directions (x positive, x negative, y positive, y negative, z positive, z negative), which measures the design rule compliance of the node in this direction.

[0094] In summary, by constructing a three-dimensional routing track array, combined with the generation and screening of the default grid and the candidate grid, the routing track grid of the target routing layer is finally determined. This method improves routing accuracy, optimizes routing resource allocation, and ensures full compliance with design rules, which is particularly suitable for complex routing scenarios in high-density integrated circuit design.

[0095] In some embodiments, the above method also includes: determining a wiring process according to a FinFET process file; determining dimension information of a grid to be generated based on the above wiring process; and generating a projection control instruction when the dimension information of the grid to be generated is three-dimensional, wherein the above projection control instruction is used to trigger the execution of the above operation of projecting the default grids of each wiring layer adjacent to the target wiring layer of the FinFET to the above target wiring layer.

[0096] In some embodiments, when the dimension information of the grid to be generated is two-dimensional, a simple two-dimensional grid is generated, and the above steps S110 to S130 do not need to be performed.

[0097] Exemplarily, the type of wiring process used in the current chip design is automatically identified by parsing the process file. The process file is a file that describes the chip manufacturing rules and restrictions. The content of the process file includes but is not limited to process nodes, wiring rules, multiple mask information and three-dimensional layout information.

[0098] The software parses the process file to extract key parameters, such as process nodes and routing rules. For example, if the process features of FinFET (such as nodes less than 16nm, 3D layout information, and multiple masks) are detected, it is judged to be a FinFET process. Otherwise, it is judged to be a mature process (such as a planar process of 28nm or above).

[0099] The dimension of the grid is dynamically determined according to the type of wiring process, i.e., two-dimensional or three-dimensional, to adapt to the requirements of different processes.

[0100] FinFET processes usually require the definition of routing track grids in three-dimensional space to support cross-layer routing and more degrees of freedom. In mature processes, the metal layer routing rules are relatively simple, and only a planar routing track grid needs to be generated. When the grid dimension is three-dimensional, the default grid of the adjacent routing layer is projected to the target routing layer by generating projection control instructions.

[0101] In summary, through the self-checking judgment logic, the scheme can dynamically adjust the wiring grid generation process according to the process file. For the FinFET process, a three-dimensional wiring track grid is generated, and the projection control instruction is used to complete the mapping of adjacent layer grids. For mature processes, a simple two-dimensional grid is generated. In this way, a balance between efficiency and accuracy is achieved. The method provided in this embodiment has good flexibility and adaptability and can be widely used in modern integrated circuit design.

[0102] In some embodiments, the above method also includes: obtaining the line spacing difference information between the wiring track grids of each layer of the above FinFET; optimizing the wiring track grid of the above target wiring layer based on the multi-objective optimization algorithm and the above line spacing difference information to obtain the optimized wiring track grid of the above target wiring layer.

[0103] Exemplarily, the track grids of each wiring layer have different track spacings, and the line spacing difference information describes the variation of the track spacings between layers.

[0104] For example: The Pitch of the metal track is , No. The Pitch of the metal track is , then the line distance difference is:

[0105]

[0106] Extract the track pitch parameters of each layer from the process file.

[0107] For example:

[0108] Layer 1:

[0109] Layer 2:

[0110] difference:

[0111] For a multi-layer routing grid, generate an inter-layer difference matrix:

[0112]

[0113] The multi-objective optimization algorithm is used to balance the pitch differences between different layers and generate an optimized routing track grid for the target routing layer, thereby reducing routing conflicts and improving resource utilization efficiency.

[0114] The multi-objective optimization algorithm is used to find a balance between multiple optimization objectives. The optimization objectives of this solution may include: 1. Minimizing the pitch difference between layers; 2. Maximizing the utilization of the routing grid; 3. Ensuring the consistency of routing rules and cross-layer coordination.

[0115] Dynamically assign weights based on design requirements:

[0116]

[0117] is the weight for the pitch difference between layers, is the weight for grid utilization, is the weight for rule consistency.

[0118] Overall objective function It can be determined based on the following formula:

[0119]

[0120] It represents the Pitch difference between the i-th layer and the j-th layer, Utilization represents the resource utilization of the routing grid, and Inconsistency represents the overall inconsistency of cross-layer routing.

[0121] By optimizing the routing track grid of the target routing layer based on the multi-objective optimization algorithm and the line spacing difference information, the method provided in this embodiment can balance the differences between layers and improve the continuity of the routing path. By optimizing the track density, waste can be reduced and the rules of each layer of tracks can be ensured to meet the design and manufacturing requirements.

[0122] like Figure 2 As shown, the present application proposes a wiring track grid generation device for FinFET process, including:

[0123] A projection unit 21 is used to project the default grids of each wiring layer adjacent to the target wiring layer of the FinFET to the target wiring layer to obtain the candidate grid of the target wiring layer;

[0124] A first acquisition unit 22 is used to acquire a default grid design check rule evaluation value of the target wiring layer and a design check rule evaluation value of a candidate grid of the target wiring layer;

[0125] The second acquisition unit 23 is used to acquire the wiring track grid of the target wiring layer from the default grid and the alternative grid of the target wiring layer according to the design check rule evaluation value of the default grid of the target wiring layer and the design check rule evaluation value of the alternative grid of the target wiring layer.

[0126] The wiring track grid generation device of the FinFET process may further perform the following steps:

[0127] In a feasible implementation manner, the obtaining of the wiring track grid of the target wiring layer from the default grid and the candidate grid of the target wiring layer includes:

[0128] According to a global optimal strategy, select available candidate grids of the target wiring layer from the candidate grids of the target wiring layer;

[0129] According to the default grid of the target wiring layer and the available candidate grids, a wiring track grid of the target wiring layer is obtained.

[0130] In a feasible implementation manner, the obtaining of the design check rule evaluation value of the default grid of the target wiring layer and the design check rule evaluation value of the candidate grid of the target wiring layer includes:

[0131] According to the prediction algorithm and the wiring design rule of the target wiring layer, obtaining the design check rule evaluation value of the grid node of each default grid in the above target wiring layer;

[0132] According to the prediction algorithm and the adjacent wiring design rule of the target wiring layer, obtaining the design check rule evaluation value of the grid node of each candidate grid in the target wiring layer;

[0133] Among them, the above-mentioned prediction algorithm includes one or more of heuristic algorithm, machine learning algorithm and maximum likelihood estimation, and the above-mentioned wiring design inspection rules include one or more of short circuit rules, parallel routing length rules, loop rules and special rules of multiple mask technology.

[0134] In a feasible implementation, it also includes:

[0135] Obtaining wiring parameter information of the target wiring layer;

[0136] According to the wiring parameter information of the target wiring layer, a preset grid of the target wiring layer is established;

[0137] An alignment operation is performed based on the preset grid of the target wiring layer and the reference coordinates of the standard cells of the target wiring layer to generate a default grid of the target wiring layer.

[0138] In a feasible implementation, it also includes:

[0139] Establishing a wiring track array of the target wiring layer in three-dimensional space;

[0140] The steps of generating the candidate grids of the current wiring layer, obtaining the available candidate grids of the current wiring layer and determining the available wiring grids of the current wiring layer are executed through the wiring track array, wherein the wiring track array includes logical nodes, physical nodes, edges, default directions, custom directions and design check rule evaluation values, the logical nodes are abstract points in the wiring track grids, the physical nodes are mapping points of the logical nodes on the actual metal layer, the edges are wiring paths connecting two nodes, the default directions are directions corresponding to the default grids of the wiring layer, the custom directions are the candidate grids of the wiring layer, and the design check rule evaluation values ​​are six design check rule evaluation values ​​corresponding to the logical nodes in the six degrees of freedom directions.

[0141] In a feasible implementation, it also includes:

[0142] Determine the wiring process according to the FinFET process file;

[0143] Determine the dimension information of the grid to be generated based on the above wiring process;

[0144] When the dimension information of the grid to be generated is three-dimensional, a projection control instruction is generated, wherein the projection control instruction is used to trigger the execution of the operation of projecting the default grids of each wiring layer adjacent to the target wiring layer of the FinFET to the target wiring layer.

[0145] In a feasible implementation, it also includes:

[0146] Obtaining line spacing difference information between track grids of each wiring layer of the FinFET;

[0147] The wiring track grid of the target wiring layer is optimized based on a multi-objective optimization algorithm and the line spacing difference information to obtain an optimized wiring track grid of the target wiring layer.

[0148] In summary, this device generates alternative grids by projecting the default grids of adjacent layers to the target wiring layer. The default grids of adjacent layers and the default grids of the target wiring layer together provide diversified path selection for the wiring algorithm, significantly improving the utilization of wiring resources. By eliminating high-risk nodes through the design inspection rule evaluation value, the wiring track grid finally generated has higher design reliability and reduces violation problems. Through the projection and integration of the default grids of adjacent layers and the target wiring layer, this device optimizes the cross-layer wiring path, ensures the coherence and rule consistency of the wiring track, and is particularly suitable for complex scenarios of multi-layer wiring. This device greatly reduces the solution space of the wiring algorithm by pre-integrating multi-level information and rule evaluation when generating the track grid, thereby improving the efficiency of the algorithm. Due to its three-dimensional structural characteristics, the FinFET process puts forward higher requirements for the generation of wiring track grids. Through the integration and optimization of multi-level information, this device meets the design requirements of the FinFET process for high-density wiring.

[0149] like Figure 3 As shown, an embodiment of the present application also provides an electronic device 300, including a memory 310, a processor 320, and a computer program 311 stored in the memory 310 and executable on the processor, and when the processor 320 executes the computer program 311, the steps of any method for generating a wiring track grid for the above-mentioned FinFET process are implemented.

[0150] Since the electronic device introduced in this embodiment is a device used for implementing a wiring track grid generation device of a FinFET process in the embodiment of the present application, based on the method introduced in the embodiment of the present application, the technical personnel in this field can understand the specific implementation mode of the electronic device of the present embodiment and its various variations. Therefore, how the electronic device implements the method in the embodiment of the present application is not introduced in detail here. As long as the equipment used by the technical personnel in this field to implement the method in the embodiment of the present application is adopted, it belongs to the scope of protection of this application.

[0151] During the specific implementation process, when the computer program 311 is executed by a processor, any implementation method in the embodiments corresponding to the first aspect can be implemented.

[0152] It should be noted that in the above embodiments, the description of each embodiment has its own emphasis, and for parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0153] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0154] The present application is described with reference to the flowcharts and / or block diagrams of the methods, devices (systems), and computer program products according to the embodiments of the present application. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded computer, or other programmable data processing device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0155] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0156] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0157] An embodiment of the present application also provides a computer program product, which includes computer software instructions. When the computer software instructions are executed on a processing device, the processing device executes a process for generating a wiring track grid for the FinFET process in the corresponding embodiment.

[0158] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on the computer, the process or function according to the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from one website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium may be any available medium that a computer can store or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid state disk (SSD)), etc.

[0159] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0160] In the several embodiments provided in the present application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.

[0161] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0162] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0163] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including a number of instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) to execute all or part of the steps of the various embodiments of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (ROM), random access memory (RAM), disk or optical disk and other media that can store program codes.

[0164] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for generating a wiring track grid of a FinFET, characterized in that: include: Projecting the default grids of each wiring layer adjacent to the target wiring layer of the FinFET to the target wiring layer to obtain a candidate grid of the target wiring layer; Acquire a design check rule evaluation value of a default grid of the target wiring layer and a design check rule evaluation value of an alternative grid of the target wiring layer; According to the design check rule evaluation value of the default grid of the target wiring layer and the design check rule evaluation value of the candidate grid of the target wiring layer, the wiring track grid of the target wiring layer is obtained from the default grid and the candidate grid of the target wiring layer, wherein: The step of acquiring the routing track grid of the target routing layer from the default grid and the candidate grid of the target routing layer comprises: According to a global optimal strategy, selecting available candidate grids of the target wiring layer from the candidate grids of the target wiring layer; Obtaining a routing track grid of the target routing layer according to a default grid of the target routing layer and the available candidate grids; The obtaining of the design check rule evaluation value of the default grid of the target wiring layer and the design check rule evaluation value of the candidate grid of the target wiring layer includes: According to the prediction algorithm and the wiring design rule of the target wiring layer, obtaining the design check rule evaluation value of the grid node of each default grid in the target wiring layer; According to the prediction algorithm and the wiring design rules of the adjacent wiring layers of the target wiring layer, obtaining the design check rule evaluation value of the grid node of each candidate grid in the target wiring layer; The prediction algorithm includes one or more of a heuristic algorithm, a machine learning algorithm and a maximum likelihood estimation, and the wiring design inspection rule includes one or more of a short circuit rule, a parallel routing length rule, a loop rule and a special rule of a multiple mask technology; The method further comprises: Acquire wiring parameter information of the target wiring layer; Establishing a preset grid of the target wiring layer according to the wiring parameter information of the target wiring layer; An alignment operation is performed based on the preset grid of the target wiring layer and the reference coordinates of the standard cells of the target wiring layer to generate a default grid of the target wiring layer.

2. The method for generating a wiring track grid of a FinFET according to claim 1, characterized in that: The method further comprises: Establishing a wiring track array of the target wiring layer in three-dimensional space; The steps of generating an alternative grid of the current wiring layer, obtaining an available alternative grid of the current wiring layer, and determining an available wiring grid of the current wiring layer are executed through the wiring track array, wherein the wiring track array includes logical nodes, physical nodes, edges, default directions, custom directions, and design check rule evaluation values, the logical nodes are abstract points in the wiring track grid, the physical nodes are mapping points of the logical nodes on the actual metal layer, the edges are wiring paths connecting two nodes, the default directions are directions corresponding to the default grid of the wiring layer, the custom directions are alternative grids of the wiring layer, and the design check rule evaluation values ​​are six design check rule evaluation values ​​corresponding to the logical nodes in the six degrees of freedom directions.

3. The method for generating a wiring track grid of FinFET according to claim 1, characterized in that: The method further comprises: Determine the wiring process according to the FinFET process file; Determining dimension information of a grid to be generated based on the wiring process; When the dimension information of the grid to be generated is three-dimensional, a projection control instruction is generated, wherein the projection control instruction is used to trigger the execution of the operation of projecting the default grids of each wiring layer adjacent to the target wiring layer of the FinFET to the target wiring layer.

4. The method for generating a wiring track grid of a FinFET according to claim 1, characterized in that: The method further comprises: Acquire line spacing difference information between wiring track grids of each wiring layer of the FinFET; The routing track grid of the target routing layer is optimized based on a multi-objective optimization algorithm and the line spacing difference information to obtain an optimized routing track grid of the target routing layer.

5. A wiring track grid generation device for FinFET process, characterized in that: include: A projection unit, used for projecting the default grids of each wiring layer adjacent to the target wiring layer of the FinFET to the target wiring layer to obtain an alternative grid of the target wiring layer; A first acquisition unit, configured to acquire a design check rule evaluation value of a default grid of the target wiring layer and a design check rule evaluation value of an alternative grid of the target wiring layer; The second acquisition unit is used to acquire the routing track grid of the target routing layer from the default grid and the candidate grid of the target routing layer according to the design check rule evaluation value of the default grid of the target routing layer and the design check rule evaluation value of the candidate grid of the target routing layer; wherein, The second acquisition unit is specifically used to screen out the available candidate grids of the target wiring layer from the candidate grids of the target wiring layer according to the global optimal strategy; and obtain the wiring track grid of the target wiring layer according to the default grid of the target wiring layer and the available candidate grids; The first acquisition unit is specifically used to acquire a design check rule evaluation value of a grid node of each default grid in the target wiring layer according to a prediction algorithm and a wiring design rule of the target wiring layer; and to acquire a design check rule evaluation value of a grid node of each candidate grid in the target wiring layer according to the prediction algorithm and a wiring design rule of an adjacent wiring layer of the target wiring layer, wherein the prediction algorithm includes one or more of a heuristic algorithm, a machine learning algorithm, and a maximum likelihood estimation, and the wiring design check rule includes one or more of a short circuit rule, a parallel routing length rule, a loopback rule, and a special rule of a multiple mask technology; The projection unit is also used to obtain wiring parameter information of the target wiring layer; establish a preset grid of the target wiring layer according to the wiring parameter information of the target wiring layer; and perform an alignment operation based on the preset grid of the target wiring layer and the reference coordinates of the standard cells of the target wiring layer to generate a default grid of the target wiring layer.

6. An electronic device comprising: A memory and a processor, wherein the processor is used to implement the steps of the FinFET wiring track grid generation method as described in any one of claims 1 to 5 when executing the computer program stored in the memory.

7. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method for generating a wiring track grid of a FinFET according to any one of claims 1 to 5 are implemented.

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