Hardware accelerator, method, device and storage medium for data format conversion

Abstract

The present application provides a hardware accelerator, method, device and storage medium for data format conversion, which are applied to the field of data processing technology. The hardware accelerator includes: a data preprocessing module, a first data processing module, a second data processing module and a data writing module which are electrically connected in sequence; wherein the data preprocessing module can perform data preprocessing on YUV420LEGACY encoding format data to obtain intermediate data, the first data processing module can extract the Y component that conforms to the arrangement characteristics of NV12 encoding format data from the intermediate data, the second data processing module can extract the U component and V component that conform to the arrangement characteristics of NV12 encoding format data from the intermediate data from which the Y component has been extracted, and the data writing module combines the Y component extracted by the first data module and the U component and V component extracted by the second data module into NV12 format data. Thus, the conversion of YUV420LEGACY encoding format data to NV12 encoding format data can be realized, which has high economy and adaptability.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to a hardware accelerator, method, device and storage medium for data format conversion. Background Art

[0002] The YUV420LEGACY encoding format is an earlier color encoding format, commonly used in video and image storage or processing. With the optimization and iteration of color encoding formats, the YUV420LEGACY encoding format has been gradually replaced by new encoding formats. Among them, the NV12 encoding format has become the current mainstream color encoding format due to its many advantages in storage, device compatibility, and processing speed.

[0003] Since different hardware and software devices support different data formats, data format conversion is required when data flows between multiple hardware and software devices to meet the needs of different hardware and software devices. At present, in scenarios such as image and video processing or storage, there are fewer and fewer hardware and software devices that can support the YUV420LEGACY encoding format, but in order to be compatible with some hardware and software devices that use the YUV420LEGACY encoding format. A common way is to convert the YUV420LEGACY encoding format to the NV12 encoding format, and then process or store the NV12 encoding format data.

[0004] Currently, there are two main solutions for converting YUV420LEGACY encoding format data to NV12 encoding format data: the first solution is to use CPU to process YUV420LEGACY encoding format to NV12 encoding format; the second solution is to design a special hardware accelerator to process YUV420LEGACY encoding format to NV12 encoding format. However, the solution of using CPU to process YUV420LEGACY encoding format to NV12 encoding format will occupy a lot of CPU resources and have low calculation efficiency; the solution of using special hardware accelerator to process YUV420LEGACY format to NV12 encoding format will increase design cost and hardware cost. Summary of the invention

[0005] The embodiments of the present application provide a hardware accelerator, method, device and storage medium for data format conversion, which can realize the conversion from YUV420LEGACY encoding format to NV12 encoding format without increasing costs and occupying CPU resources.

[0006] In a first aspect, the present application provides a hardware accelerator for data format conversion, comprising:

[0007] A data pre-processing module, a first data processing module, a second data processing module, and a data writing module electrically connected in sequence;

[0008] A data preprocessing module is configured to perform data preprocessing on YUV420LEGACY encoding format data according to an rgb_pack operator, a CCM operator, and an RGGB2Bayer operator to obtain intermediate data; the intermediate data includes a Y component, a U component, a V component, and a placeholder component; the Y component is arranged in a first data row of the intermediate data, the U component and the placeholder component are arranged in a second data row of the intermediate data, the V component and the placeholder component are arranged in a third data row of the intermediate data, the first data row is arranged in alternate rows, and the second data row and the third data row are alternately arranged between two rows of the first data row;

[0009] A first data processing module is configured to read the intermediate data in alternate lines according to the DMA operator to obtain a first portion of data and a second portion of data, wherein the first portion of data includes a Y component, and the second portion of data includes a U component, a V component, and a placeholder component;

[0010] The second data processing module is configured to cross-merge the second data row and the third data row in the second part of data according to the Bayer2RGGB operator to obtain a merged second part of data;

[0011] The second data processing module is further configured to remove the placeholder component included in the merged second part of data according to the unpack operator to obtain the third part of data; the third part of data includes the U component and the V component arranged in an interlaced manner;

[0012] The data writing module is configured to write the first part of data and the third part of data in the storage space in sequence according to the DMA operator to obtain NV12 encoding format data.

[0013] In some embodiments, the data preprocessing module performs data preprocessing on the YUV420LEGACY encoding format data according to the rgb_pack operator, the CCM operator and the RGGB2Bayer operator to obtain intermediate data, and is specifically configured as follows:

[0014] Fill the placeholder components in the YUV420LEGACY encoding format data according to the rgb_pack operator to obtain the first process data;

[0015] exchanging positions of components in the first process data according to a CCM operator to obtain second process data;

[0016] The data rows in the second process data are split according to the RGGB2Bayer operator to obtain intermediate data.

[0017] In some embodiments, the YUV420LEGACY encoding format data includes odd rows and even rows, the odd rows are arranged in an interlaced manner according to U component, Y component, and Y component, and the even rows are arranged in an interlaced manner according to V component, Y component, and Y component;

[0018] The data preprocessing module executes the filling of placeholder components in the YUV420LEGACY encoding format data according to the rgb_pack operator to obtain the first process data, which is specifically configured as follows:

[0019] In each data row of the YUV420LEGACY encoding format data, a placeholder component is added at each interval of a preset data bit width to obtain first process data;

[0020] The odd rows of the first process data are arranged in an interlaced manner according to U component, Y component, Y component, and placeholder component, and the even rows of the first process data are arranged in an interlaced manner according to V component, Y component, Y component, and placeholder component.

[0021] In some embodiments, the data preprocessing module performs the step of exchanging the positions of components in the first process data according to the CCM operator to obtain the second process data, and is specifically configured as follows:

[0022] According to a preset conversion relationship, the positions of the Y component and the U component of the odd-numbered rows in the first process data are exchanged, and the positions of the Y component and the V component of the even-numbered rows in the first process data are exchanged to obtain the second process data;

[0023] The odd-numbered rows of the second process data are arranged in an alternating manner according to Y component, Y component, U component, and placeholder component, and the even-numbered rows of the second process data are arranged in an alternating manner according to Y component, Y component, V component, and placeholder component.

[0024] In some embodiments, the data preprocessing module performs splitting of the data rows in the second process data according to the RGGB2Bayer operator to obtain the intermediate data, and is specifically configured as follows:

[0025] According to a preset conversion format, the odd-numbered rows in the second process data are split into a first data row and a second data row, and the even-numbered rows are split into a first data row and a third data row, to obtain intermediate data;

[0026] The first data row includes a Y component; the second data row includes a U component and a placeholder component, and the U component and the placeholder component are arranged alternately; the third data row includes a V component and a placeholder component, and the V component and the placeholder component are arranged alternately.

[0027] In some embodiments, the merged second part of data is arranged in an interlaced manner in the order of U component, placeholder component, V component, and placeholder component; the U component and the V component are first flag bit data, and the placeholder component is second flag bit data;

[0028] The unpack operator includes a first mode and a second mode, the first mode is used to remove the second flag bit data; the second mode is used to remove the first flag bit data;

[0029] The second data processing module removes the placeholder component included in the merged second part of data according to the unpack operator to obtain the third part of data, and is configured as follows:

[0030] Use the first mode of the unpack operator to remove the second identification bit data of the merged second part of data to obtain the third part of data;

[0031] The third part of the data is arranged in an interlaced manner in the order of U component and V component.

[0032] In some embodiments, the hardware accelerator includes a cascade of an rgb_pack operator, a CCM operator, an RGGB2Bayer operator, a DMA operator, a Bayer2RGGB operator, and an unpack operator.

[0033] In a second aspect, the present application provides a method for data format conversion, the method comprising:

[0034] Preprocessing the YUV420LEGACY encoding format data according to the rgb_pack operator, the CCM operator and the RGGB2Bayer operator to obtain intermediate data; the intermediate data includes a Y component, a U component, a V component and a placeholder component; the Y component is arranged in a first data row of the intermediate data, the U component and the placeholder component are arranged in a second data row of the intermediate data, the V component and the placeholder component are arranged in a third data row of the intermediate data, the first data row is arranged in alternate rows, and the second data row and the third data row are alternately arranged between two rows of the first data row;

[0035] Read the intermediate data in alternate lines according to the DMA operator to obtain a first portion of data and a second portion of data, wherein the first portion of data includes a Y component, and the second portion of data includes a U component, a V component, and a placeholder component;

[0036] Cross-merge the second data row and the third data row in the second part of data according to the Bayer2RGGB operator to obtain a merged second part of data;

[0037] The placeholder component included in the merged second part of data is removed according to the unpack operator to obtain the third part of data; the third part of data includes the U component and the V component arranged in an interlaced manner;

[0038] According to the DMA operator, the first part of data and the third part of data are written into the storage space in sequence to obtain NV12 encoding format data.

[0039] In a third aspect, the present application provides an electronic device, comprising a processor and a memory, wherein the memory is used to store at least one program, and the at least one program is loaded by the processor and executes the method for data format conversion as described in the second aspect above.

[0040] In a fourth aspect, the present application provides a computer-readable storage medium, wherein at least one program is stored in the computer-readable storage medium, and the at least one program is loaded and executed by a processor to implement the method for data format conversion as described in the second aspect above.

[0041] It can be known from the above technical content that the present application provides a hardware accelerator for data format conversion, the hardware accelerator includes a data preprocessing module, a first data processing module, a second data processing module and a data writing module which are electrically connected in sequence, wherein the data preprocessing module can perform data preprocessing on YUV420LEGACY encoding format data to obtain intermediate data, the first data processing module can extract the Y component that conforms to the arrangement characteristics of NV12 encoding format data from the intermediate data, the second data processing module can extract the U component and V component that conform to the arrangement characteristics of NV12 encoding format data from the intermediate data from which the Y component has been extracted, and the data writing module writes the Y component extracted by the first data module and the U component and V component extracted by the second data module into the memory in sequence to obtain NV12 encoding format data. In this way, the arrangement characteristics of the data output by the hardware accelerator conform to the arrangement characteristics of the NV12 encoding format data, and the conversion of YUV420LEGACY encoding format data to NV12 encoding format data is realized.

[0042] Since all operators used in the data format conversion process are general operators on the current chip, these general operators usually also undertake other tasks, for example, the rgb_pack operator is used to pack data, the DMA operator is also used to read and write other data, the Bayer2RGGB operator is also used to process the conversion of Bayer format data to RGGB4channel format data, and the unpack operator is also used to unpack data, etc. Therefore, the hardware accelerator provided by this application can realize the conversion of YUV420LEGACY encoding format data to NV12 encoding format data without re-designing special hardware and occupying CPU resources, and has high economy and adaptability. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solution of the present application, the drawings required for use in the embodiments are briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0044] Figure 1 An example diagram of the arrangement of YUV420LEGACY encoding format data provided in an embodiment of the present application;

[0045] Figure 2 An example diagram of data arrangement in NV12 encoding format provided in an embodiment of the present application;

[0046] Figure 3 A schematic diagram of the structure of a hardware accelerator for data format conversion provided in an embodiment of the present application;

[0047] Figure 4 A schematic diagram of the structure of a data preprocessing module provided in an embodiment of the present application;

[0048] Figure 5 A schematic diagram of data arrangement in a YUV420LEGACY encoding format provided in an embodiment of the present application;

[0049] Figure 6 A schematic diagram of data arrangement of the first process data provided in an embodiment of the present application;

[0050] Figure 7 A schematic diagram of data arrangement of the second process data provided in an embodiment of the present application;

[0051] Figure 8 A schematic diagram of data arrangement of intermediate data provided in an embodiment of the present application;

[0052] Fig. 9 A schematic diagram of data arrangement of the first part of data and the second part of data provided in an embodiment of the present application;

[0053] Fig.10 A schematic diagram of the structure of a second data processing module provided in an embodiment of the present application;

[0054] Fig.11 A schematic diagram of data arrangement of the merged second part of data provided in an embodiment of the present application;

[0055] Fig.12 A schematic diagram of data arrangement of the third part of data provided in an embodiment of the present application;

[0056] Fig.13 A schematic diagram of data arrangement of NV12 encoding format data provided in an embodiment of the present application;

[0057] Fig.14 A processing flow chart of a hardware accelerator for data format conversion provided in an embodiment of the present application;

[0058] Fig.15An example diagram of a method for data format conversion provided in an embodiment of the present application. DETAILED DESCRIPTION

[0059] The embodiments will be described in detail below, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation methods described in the following embodiments do not represent all implementation methods consistent with the present application. They are only examples of systems and methods consistent with some aspects of the present application.

[0060] In this application, the terms "first", "second", etc. are used to distinguish between identical or similar items with substantially the same effects and functions. It should be understood that there is no logical or temporal dependency between "first", "second", and "nth", nor is there a limitation on the quantity and execution order. It should also be understood that although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by the terms.

[0061] These terms are only used to distinguish one element from another element. For example, without departing from the scope of various examples, a first action can be referred to as a second action, and similarly, a second action can also be referred to as a first action. Both the first action and the second action can be actions, and in some cases, can be separate and different actions.

[0062] Here, at least one means one or more than one, for example, at least one action can be one action, two actions, three actions, or any other action that is an integer greater than or equal to one. And multiple means two or more than two, for example, multiple actions can be two actions, three actions, or any other action that is an integer greater than or equal to two.

[0063] YUV is a color space widely used in video processing, image coding and other fields. YUV decomposes color information into luminance and chrominance, where Y represents the luminance component, U represents the blue chrominance component, and V represents the red chrominance component.

[0064] YUV includes a variety of encoding formats, wherein the encoding format includes a sampling format and a data arrangement method.

[0065] YUV sampling formats include: YUV444, YUV422, YUV420, etc.

[0066] Among them, YUV420 means that the sampling rate of the chrominance component in the horizontal and vertical directions is half of the sampling rate of the brightness component, that is, every 4 Y components correspond to one U component and one V component; YUV422 means that the sampling rate of the U component and the V component in the horizontal direction is half of the Y component, that is, every two Y components correspond to one U component and one V component; YUV444 means that the sampling rates of brightness and chrominance in the horizontal and vertical directions are the same, that is, each Y component corresponds to one U component and one V component.

[0067] Among the above three sampling formats, the data volume of the YUV420 sampling format is the smallest compared to the other two sampling formats, so the requirements for storage and data transmission are relatively low, and it has high applicability and is widely used in some live broadcast platforms, short video platforms, etc.; the YUV422 sampling format is suitable for some more professional video editing and film and television production scenes. Compared with the YUV420 sampling format, it has higher color reproduction, but at the same time, the data volume is also higher than that of YUV420. It is suitable for some professional video editing, film and television production scenes; the YUV444 sampling format has the highest color reproduction among the three sampling formats, but at the same time, it also has the highest requirements for storage and data transmission. It is suitable for scenes such as high-end film and television production.

[0068] YUV data arrangement modes include: planar mode and packed mode.

[0069] In planar mode, YUV data is stored sequentially according to the brightness component and the chrominance component. For example, a planar mode arranges all Y components in sequence first, then arranges all U components in sequence, and finally arranges all V components in sequence.

[0070] In the packing mode, YUV data is stored in a mixed order. For example, one packing mode is to arrange all Y components in sequence first, and then interleave U components and V components.

[0071] Different sampling methods and different data arrangement methods can form different YUV encoding formats. The following introduces the YUV420LEGACY encoding format and NV12 encoding format suitable for the application scenarios of the embodiments of the present application.

[0072] The YUV420LEGACY encoding format uses a mixed arrangement of odd-numbered lines UYY loop and even-numbered lines VYY loop for encoding. For example, Figure 1This is an example of how a 4×4 pixel image is arranged using the YUV420LEGACY encoding format. A 4×4 pixel image has 16 pixels, which means that the Y component in the YUV420LEGACY encoding format is 16, and the U component and V component are 4 respectively. The data arrangement of a 4×4 pixel image in the YUV420LEGACY encoding format is as follows:

[0073] Odd rows odd1: [U00, Y00, Y01, U01, Y02, Y03];

[0074] Even rows even1: [V00, Y04, Y05, V01, Y06, Y07];

[0075] Odd rows odd2: [U02, Y08, Y09, U03, Y10, Y11];

[0076] Even rows even2: [V02, Y12, Y13, V03, Y14, Y15].

[0077] The NV12 encoding format is a common YUV encoding format, which uses the method of first arranging the Y component continuously, and then arranging the U component and the V component alternately. For example, Figure 2 This is an example of the data arrangement of a 4×4 pixel image using the NV12 encoding format, as shown below:

[0078] Data row Row1: [Y00, Y01, Y02, Y03];

[0079] Data row Row2: [Y04, Y05, Y06, Y07];

[0080] Data row Row3: [Y08, Y09, Y10, Y11];

[0081] Data row Row4: [Y12, Y13, Y14, Y15];

[0082] Data row Row5: [U00, V00, U01, V01];

[0083] Data row Row6: [U02, V02, U03, V03].

[0084] Since all Y components of the NV12 encoding format are stored continuously, followed by alternating U and V components. This interleaved storage method makes the data arrangement in the memory more compact, which is conducive to improving the hit rate of the data cache and reducing the delay of data access. At the same time, when processing the video, it is convenient to obtain brightness information and color information at the same time, without the need to search and process different data blocks separately, which improves the efficiency and parallelism of processing. Therefore, the NV12 encoding format is widely used.

[0085] Since different hardware and software devices support different data formats, data format conversion is required. At present, in scenarios such as image and video processing or storage, there are fewer and fewer hardware and software devices that can support the YUV420LEGACY encoding format, but in order to be compatible with some hardware and software devices that use the YUV420LEGACY encoding format. A common way is to convert the YUV420LEGACY encoding format to the NV12 encoding format, and then process or store the NV12 encoding format data.

[0086] Currently, the common solutions for converting YUV420LEGACY encoding format data to NV12 encoding format data include:

[0087] The first solution: using the CPU to convert YUV420LEGACY encoding format data into NV12 encoding format data. Due to the architectural characteristics of the CPU, it often takes a long time to process parallel operation tasks, and the task of converting YUV420LEGACY encoding format data into NV12 encoding format data requires a large number of parallel operations. Therefore, this solution will occupy a large amount of CPU resources and has a very low efficiency.

[0088] The second solution is to design a hardware accelerator specifically for converting YUV420LEGACY encoding format data into NV12 encoding format data. Although this solution can quickly process the task of converting YUV420LEGACY encoding format data into NV12 encoding format data, due to the small number of hardware and software devices using the YUV420LEGACY encoding format on the market, designing a hardware accelerator specifically for this purpose will increase design costs and hardware costs.

[0089] Based on the above problems, the present application provides a hardware accelerator for data format conversion. The hardware accelerator only relies on a combination of general operators to realize the conversion from YUV420LEGACY encoding format to NV12 encoding format. Since the hardware accelerator processes data format conversion faster than the CPU and does not require specially designed hardware structure, it can meet the requirements of economy and adaptability.

[0090] General operators refer to operating units in hardware accelerators that can perform general functions on multiple data types and different computing tasks. General operators have the characteristics of versatility, functional clarity, and reusability. Among them, versatility means that such operators can be applied to different data types, multiple application scenarios, or different algorithm architectures; functional clarity means that relatively clear and basic functional operations are performed, such as arithmetic operations, logical judgments, and data conversion; reusability means that they can be reused in multiple different specific projects or processing flows.

[0091] Common, general operators include, for example: rgb_pack operator, CCM operator, RGGB2Bayer operator, DMA operator, Bayer2RGGB operator, unpack operator.

[0092] The core function of the rgb_pack operator is to integrate and pack RGB color data into a specific data storage format. One of the main functions of the rgb_pack operator is to convert 3-channel RGB data into 4-channel RGB0 data.

[0093] In the embodiment of the present application, the rgb_pack operator is used to convert the UYY interlaced arrangement of the YUV420LEGACY encoding format data into the UYY0 interlaced arrangement, and the VYY interlaced arrangement into the VYY0 interlaced arrangement.

[0094] The CCM operator can perform linear calculations on RGB data or YUV data to achieve functions such as color correction and style adjustment. The CCM operator supports 4-channel data, such as RGB0 data and YUV0 data.

[0095] In the embodiment of the present application, the CCM operator can be used to exchange the positions of the Y component and the U component, or the positions of the Y component and the V component data.

[0096] The Bayer2RGGB operator is mainly used in the processing of image sensor output data. The image sensor outputs raw image data in Bayer encoding format, and the Bayer2RGGB operator converts the data in Bayer encoding format into data in RGGB encoding format.

[0097] In the embodiment of the present application, the Bayer2RGGB operator is used to convert two rows of data into one row of data according to a preset transformation rule.

[0098] The RGGB2Bayer operator is the reverse operation of the Bayer2RGGB operator. In the embodiment of the present application, the RGGB2Bayer operator is used to convert one row of data into two rows of data according to a preset change rule.

[0099] The DMA operator is an operation operator that is mainly used to write data directly without bypassing the CPU.

[0100] In an embodiment of the present application, the DMA operator can read and write data in alternate lines to separate the Y component. The remaining U, V, and placeholder components are further processed by other operators. The DMA operator can also write the Y component data first in order and then write the interlaced U and V component data, so that the data conforms to the arrangement characteristics of the NV12 encoding format.

[0101] The unpack operator is a data processing operation unit whose core function is to disassemble and separate the packaged data according to specific rules or formats.

[0102] In an embodiment of the present application, the unpack operator is used to remove the placeholder components so that the U and V components meet the arrangement characteristics of the NV12 data format.

[0103] It can be known that the above only introduces the main functions of some general operators and their applications in the embodiments of the present application. Specifically, the chip also includes other general operators. Among other general operators, there may be operators with the same functions as the operators introduced in the above examples. These operators that can achieve the same functions can replace the operators introduced in the embodiments of the present application to achieve the same data format conversion function, and the embodiments of the present application will not be introduced one by one.

[0104] A hardware accelerator for data format conversion provided in an embodiment of the present application can be deployed in a terminal device, and the terminal device product form may include: a smart phone, a wearable device, a personal computer, a tablet computer, a smart TV, a car terminal, etc.

[0105] In some embodiments, the terminal device may also deploy other hardware or software devices, including upstream devices that produce YUV420LEGACY encoding format data and downstream devices that consume NV12 encoding format data. The upstream device produces YUV420LEGACY encoding format data and hands it over to the hardware accelerator for processing. The hardware accelerator converts the YUV420LEGACY encoding format data into NV12 encoding format data. The downstream device obtains the NV12 encoding format data for further processing (for example, including video editing and processing, video playback, image recognition, target detection, encoding and decoding, etc.).

[0106] In some embodiments, YUV420LEGACY encoding format data can be generated by some upstream devices such as image signal processors. These image signal processors convert the image data collected by the camera into YUV420LEGACY encoding format data, and then send it to the hardware accelerator for processing. The hardware accelerator converts the YUV420LEGACY encoding format data into NV12 encoding format data, which is then further processed by other downstream devices that support NV12 encoding format data.

[0107] In some embodiments, YUV420LEGACY encoding format data may also be output by some editing software that supports YUV420LEGACY encoding format data. After outputting the YUV420LEGACY encoding format data, the hardware accelerator converts the data format and outputs NV12 encoding format data. Then, the NV12 encoding format data is sent to other downstream devices that support NV12 encoding format data for further processing.

[0108] Figure 3 A structural schematic diagram of a hardware accelerator for data format conversion provided in an embodiment of the present application is introduced, including: a data preprocessing module, a first data processing module, a second data processing module, and a data writing module that are electrically connected in sequence.

[0109] The data preprocessing module is configured to perform data preprocessing on the YUV420LEGACY encoding format data according to the rgb_pack operator, the CCM operator and the RGGB2Bayer operator to obtain intermediate data. The intermediate data includes a Y component, a U component, a V component and a placeholder component; the Y component is arranged in the first data row of the intermediate data, the U component and the placeholder component are arranged in the second data row of the intermediate data, the V component and the placeholder component are arranged in the third data row of the intermediate data, the first data row is arranged in alternate rows, and the second data row and the third data row are alternately arranged between two rows of the first data row.

[0110] In some embodiments, the data preprocessing module performs data preprocessing on the YUV420LEGACY encoding format data, including: performing operations such as component padding, component position exchange, and data row splitting on the YUV420LEGACY encoding format data. These operations are implemented by corresponding operators.

[0111] Figure 4 A structural schematic diagram of a data preprocessing module provided in an embodiment of the present application is introduced, where the data preprocessing module includes an rgb_pack operator, a CCM operator and an RGGB2Bayer operator.

[0112] In some embodiments, Figure 4As shown, the rgb_pack operator, the CCM operator and the RGGB2Bayer operator are cascaded. The rgb_pack operator performs component filling processing on the YUV420LEGACY encoding format data to obtain the first process data; then the CCM operator performs component position exchange processing on the first process data to obtain the second process data; then, the RGGB2Bayer operator performs data row splitting processing on the second process data to obtain the intermediate data.

[0113] The cascade of the rgb_pack operator, the CCM operator and the RGGB2Bayer operator can make the first process data not stored in registers but directly received and processed by the CCM operator. The second process data can also not be stored in registers but directly received and processed by the RGGB2Bayer operator, forming a hardware pipeline.

[0114] The following is an exemplary introduction to the process in which the data preprocessing module performs data preprocessing operations on YUV420LEGACY encoding format data.

[0115] Figure 5 This article introduces a schematic diagram of the arrangement of YUV420LEGACY encoding format data. Figure 5 In the YUV420LEGACY encoding format, the data arrangement is as follows:

[0116] Odd rows odd1: [U00, Y00, Y01, U01, Y02, Y03];

[0117] Even rows even1: [V00, Y04, Y05, V01, Y06, Y07].

[0118] like Figure 5 As shown, the data is arranged in a UYY cycle for odd rows and a VYY cycle for even rows, and the data bit width of each component is 8 bits.

[0119] It can be known that the above Figure 5 The data arrangement of the YUV420LEGACY encoding format introduced here can be all the data of an image or part of the data, which is only used as an example.

[0120] In some embodiments, the rgb_pack operator can pack the YUV420LEGACY encoding format data according to a preset packing format to obtain the first process data.

[0121] The preset packing format includes, for example: in each data row of the YUV420LEGACY encoding format data, a placeholder component is added at every interval of the preset data bit width.

[0122] The placeholder component is data with a data width of 8 bits and does not include brightness and chrominance information. The placeholder component is used to change the data arrangement of the YUV420LEGACY encoding format.

[0123] In some embodiments, the preset data width is, for example, 24 bits. Since the data width of each component is 8 bits, the preset data width is set to 24 bits, so that the original data arrangement of odd rows UYY cycle and even rows VYY cycle can be changed to the data arrangement of odd rows UYY0 cycle and even rows VYY0 cycle, which is convenient for subsequent operators to process it. Where 0 represents a placeholder component.

[0124] In some embodiments, the hardware accelerator obtains YUV420LEGACY encoding format data, and then the YUV420LEGACY encoding format data is processed by the hardware pipeline of the data preprocessing module. First, the rgb_pack operator performs component filling processing on the YUV420LEGACY encoding format data to obtain first process data.

[0125] Figure 6 A schematic diagram of data arrangement of the first process data is introduced. The first process data is based on the rgb_pack operator for the above Figure 5 The data is obtained by processing the YUV420LEGACY encoding format shown in FIG. Figure 6 In the first process data, the data arrangement is as follows:

[0126] Odd row odd1: [U00, Y00, Y01, 8bit0, U01, Y02, Y03, 8bit0];

[0127] Even row even1: [V00, Y04, Y05, 8bit0, V01, Y06, Y07, 8bit0].

[0128] like Figure 6 As shown, the rgb_pack operator adds an 8-bit0 component (placeholder component) every three components to obtain the first process data.

[0129] After the rgb_pack operator processes the YUV420LEGACY encoding format data to obtain the first process data, the first process data is sent to the CCM operator for component position exchange processing to obtain the second process data. The CCM operator can exchange the positions of the Y component and the U component of the odd lines in the first process data according to a preset conversion relationship, and exchange the positions of the Y component and the V component of the even lines in the first process data to obtain the second process data.

[0130] The preset conversion relationship is shown in the following formula 1:

[0131] (Formula 1).

[0132] Wherein, k is a 4×4 coefficient matrix, A is the first process data, and b is a 4×1 offset matrix.

[0133] The coefficient matrix k is shown below:

[0134] .

[0135] The offset matrix b is as follows:

[0136] .

[0137] It can be seen that since each element of the offset matrix b is 0, the first process data does not change after passing through the offset matrix b. After the first process data passes through the coefficient matrix k, the positions of the Y component and the U component in the first process data are exchanged, and the positions of the Y component and the V component in the first process data are exchanged to obtain the second process data.

[0138] Figure 7 A data arrangement diagram of the second process data is introduced. Figure 7 The second process data shown is based on the CCM operator for the above Figure 6 The first process data shown is obtained after processing. Figure 7 In the data arrangement of the second process data, the data is as follows:

[0139] Odd row odd1: [Y00, Y01, U00, 8bit0, Y02, Y03, U01, 8bit0];

[0140] Even row even1: [Y04, Y05, V00, 8bit0, Y06, Y07, V01, 8bit0].

[0141] It can be seen that after the first process data is processed by the CCM operator, the original data arrangement of UYY0 loop for odd rows and VYY0 loop for even rows is changed to YYU0 loop for odd rows and YYV0 loop for even rows.

[0142] After the first process data is sent to the CCM operator for processing to obtain the second process data, the second process data is sent to the RGGB2Bayer operator for data row splitting processing to obtain intermediate data.

[0143] In some embodiments, the RGGB2Bayer operator can split the odd rows in the second process data into the first data row and the second data row, and split the even rows into the first data row and the third data row according to a preset conversion format to obtain intermediate data.

[0144] The preset conversion format includes, for example: extracting two 8-bit data widths of data every two 8-bit data widths for odd and even rows, and then arranging the retained data into a row and arranging the extracted data into a row.

[0145] Figure 8 A schematic diagram of the data arrangement of intermediate data is introduced. Figure 8 The intermediate data shown is based on the RGGB2Bayer operator for the above Figure 7 The second process data shown is obtained after processing.

[0146] exist Figure 8 In the data layout of the intermediate data, the data is arranged as follows:

[0147] Data row Row1: [Y00, Y01, Y02, Y03];

[0148] Data row Row2: [U00, 8bit0, U01, 8bit0];

[0149] Data row Row3: [Y04, Y05, Y06, Y07];

[0150] Data row Row4: [V00, 8bit0, V01, 8bit0].

[0151] It can be seen that the second process data is processed by the RGGB2Bayer operator, and the original one odd row and one even row are decomposed into four rows of data. Among them, according to the data distribution characteristics, Row1 and Row3 are generally called the first data row, and the first data row only includes Y component data. Row2 is called the second data row, and Row4 is called the third data row. The second data row is staggered to distribute U component and 8bit0 component, and the third data row is staggered to distribute V component and 8bit0 component.

[0152] After the data preprocessing module performs data preprocessing on the YUV420LEGACY encoding format data to obtain intermediate data, the first data processing module acquires the intermediate data.

[0153] In some embodiments, the first data processing module is configured to read the intermediate data in interlaced lines according to a DMA operator to obtain a first portion of data and a second portion of data, wherein the first portion of data includes the Y component and the second portion of data includes a U component, a V component and a placeholder component.

[0154] In some embodiments, the DMA operator can read the intermediate data in alternate lines. For example, according to the data arrangement characteristics of the intermediate data, the data with a certain bit width can be set to be read at intervals.

[0155] The data is read once every 4 8-bit widths to obtain the first part of the data.

[0156] Fig. 9 A data arrangement diagram of a first part of data and a second part of data is introduced. Fig. 9 The first part of data and the second part of data shown are based on the DMA operator for the above Figure 8 The intermediate data in the example is processed.

[0157] exist Fig. 9 The data arrangement diagram of the first part of data and the second part of data is as follows:

[0158] The first part of the data:

[0159] [Y00, Y01, Y02, Y03];

[0160] [Y04, Y05, Y06, Y07];

[0161] The second part of data:

[0162] [U00, 8bit0, U01, 8bit0];

[0163] [V00, 8bit0, V01, 8bit0].

[0164] It can be seen that the intermediate data is divided into the first part of data and the second part of data after being processed by the DMA operator. The first part of data consists of the Y component, and the second part of data consists of the U component, the V component, and the 8bit0 component. The first part of data conforms to the data arrangement characteristics of the Y component in the NV12 data format.

[0165] After the first data processing module divides the intermediate data into the first part of data and the second part of data, the second data processing module processes the second part of data.

[0166] In some embodiments, the second data processing module is configured to cross-merge the second data row and the third data row in the second portion of data according to the Bayer2RGGB operator to obtain the merged second portion of data. The second data processing module is further configured to: remove the placeholder component included in the merged second portion of data according to the unpack operator to obtain the third portion of data; the third portion of data includes U components and V components arranged in an interlaced manner.

[0167] Fig.10A structural schematic diagram of a second data processing module is introduced. The second data processing module includes: a Bayer2RGGB operator and an unpack operator.

[0168] In some embodiments, the Bayer2RGGB operator and the unpack operator are cascaded. After the Bayer2RGGB operator processes the second part of data, a merged second part of data is obtained; and then the unpack operator processes the merged second part of data to obtain a third part of data.

[0169] In some embodiments, the Bayer2RGGB operator is the inverse operation of the RGGB2Bayer operator, that is, the Bayer2RGGB operator merges the data rows of the second portion of data in pairs according to a conversion format opposite to that of the RGGB2Bayer operator to obtain the merged second portion of data.

[0170] Fig.11 A schematic diagram of data arrangement of the merged second part of data is introduced. Fig.11 The second part of the merged data shown is based on the unpack operator on the above Fig. 9 The second part of the data shown is obtained after processing.

[0171] exist Fig.11 In the data layout of the merged second part of the data, the data is arranged as follows:

[0172] [U00, 8bit0, V00, 8bit0, U01, 8bit0, V01, 8bit0].

[0173] It can be seen that the merged second part of the data is arranged in an interlaced manner according to U0V0.

[0174] In some embodiments, the unpack operator includes an MSB mode (first mode) and an LSB mode (second mode), the first mode is used to remove low-order data (second flag bit data), and the second mode is used to remove the high-order data (first flag bit data).

[0175] In the second part of the merged data, the data width of each component is 8 bits, and two components form a 16-bit data. Fig.11As shown, the merged second part of data has 4 groups of 16-bit data [U00+8bit0], [V00+8bit0], [U01+8bit0], [V01+8bit0]. Among them, U00, V00, U01, V01 are the high-order data in each 16-bit data, and 8bit0 is the low-order data in each 16-bit data. The first mode of using the unpack operator can retain the high-order data of the merged second part of data and remove the low-order data. Among them, the retained high-order data constitutes the third part of data.

[0176] Fig.12 A schematic diagram of data arrangement of the third part of data is introduced. In some embodiments, Fig.12 The third part of the data shown is based on the unpack operator on the above Fig.11 The result is obtained after processing the merged second part of data shown.

[0177] exist Fig.12 In the data of the third part, the data is arranged as follows:

[0178] [U00, V00, U01, V01].

[0179] It can be seen that the third part of the data is arranged in an interlaced manner according to the order of UV. The data arrangement characteristics of the third part of the data conform to the arrangement characteristics of the UV component in the NV12 data format.

[0180] In some embodiments, the data writing module is configured to write the first part of data and the third part of data in sequence in the storage space based on the DMA operator to obtain NV12 encoded format data.

[0181] Fig.13 A schematic diagram of data arrangement of NV12 encoding format data is introduced. In some embodiments, Fig.13 The NV12 encoding format data shown is based on the above Fig.12 The third part of the data shown above Fig. 9 The first part of the data shown is obtained.

[0182] exist Fig.13 In the NV12 encoding format, the data is arranged as follows:

[0183] [Y00, Y01, Y02, Y03];

[0184] [Y04, Y05, Y06, Y07];

[0185] [U00, V00, U01, V01].

[0186] It can be seen that all Y components are arranged in order, and then the UV components are arranged in an interlaced manner, which conforms to the characteristics of the NV12 encoding format.

[0187] In some embodiments, the data writing module writes the Y component and the UV component into a continuous address space of the memory based on a DMA operator.

[0188] In some embodiments, the hardware accelerator includes a cascade of an rgb_pack operator, a CCM operator, an RGGB2Bayer operator, a DMA operator, a Bayer2RGGB operator, and an unpack operator.

[0189] Cascading the above operators can form a complete hardware pipeline for processing YUV420LEGACY encoded format data to NV12 encoded format data. Since each operator cascade does not need to store intermediate results, the hardware accelerator has the advantages of fast processing speed and low latency.

[0190] The following introduces a hardware accelerator for data format conversion provided by an embodiment of the present application. The hardware accelerator includes an rgb_pack operator, a CCM operator, an RGGB2Bayer operator, a DMA operator, a Bayer2RGGB operator, and an unpack operator, which are executed by software. The logic combination. Fig.14 The following describes the processing flow of the hardware accelerator for data format conversion:

[0191] First, the hardware accelerator obtains YUV420LEGACY encoding format data from the memory, and the YUV420LEGACY encoding format data can be written into the memory by an upstream device such as an image signal processor. Then, based on the rgb_pack operator, the hardware accelerator adds a placeholder component every three components in each row of the YUV420LEGACY encoding format data to obtain the first process data. Then, based on the CCM operator, the hardware accelerator exchanges the positions of the Y component and the U component, and the positions of the Y component and the V component in the first process data according to a preset conversion relationship to obtain the second process data. Then, based on the RGGB2Bayer operator and according to the preset conversion format, the hardware accelerator splits each row of data in the second process data into two rows of data to obtain intermediate data. Then, based on the DMA operator, the hardware accelerator reads the intermediate data alternately to obtain the first part of the data (in Fig.13The first part of the data meets the arrangement characteristics of the Y component of the NV12 encoding format. Then, the hardware accelerator combines the data rows of the second part of the data in pairs based on the Bayer2RGGB operator according to the conversion format opposite to the RGGB2Bayer operator to obtain the combined second part of the data. Finally, the hardware accelerator removes the placeholder components of the combined second part of the data based on the first mode of the unpack operator to obtain the third part of the data (in Fig.14 The third part of the data satisfies the arrangement characteristics of the NV component of the NV12 encoding format.

[0192] The present application also provides a method for data format conversion. Fig.15 An example diagram of the method for data format conversion is shown, the method comprising:

[0193] S1501. Preprocess the YUV420LEGACY encoding format data according to the rgb_pack operator, the CCM operator and the RGGB2Bayer operator to obtain intermediate data; the intermediate data includes a Y component, a U component, a V component and a placeholder component; the Y component is arranged in the first data row of the intermediate data, the U component and the placeholder component are arranged in the second data row of the intermediate data, the V component and the placeholder component are arranged in the third data row of the intermediate data, the first data row is arranged in alternate rows, and the second data row and the third data row are alternately arranged between two rows of the first data row.

[0194] S1502 , read the intermediate data in alternate lines according to the DMA operator to obtain a first portion of data and a second portion of data, where the first portion of data includes a Y component, and the second portion of data includes a U component, a V component, and a placeholder component.

[0195] S1503 . Cross-merge the second data row and the third data row in the second part of data according to the Bayer2RGGB operator to obtain a merged second part of data.

[0196] S1504 , removing the placeholder components included in the merged second part of data according to the unpack operator to obtain the third part of data; the third part of data includes U components and V components arranged in an interlaced manner.

[0197] S1505. Write the first part of data and the third part of data in the storage space in sequence according to the DMA operator to obtain NV12 encoding format data.

[0198] It should be noted that the hardware accelerator for data format conversion provided in the above embodiment and the method embodiment for data format conversion belong to the same concept, and the specific implementation process is detailed in the device embodiment, which will not be repeated here.

[0199] In an embodiment of the present application, the hardware accelerator includes a data preprocessing module, a first data processing module, a second data processing module and a data writing module, and the data preprocessing module performs data preprocessing on the YUV420LEGACY encoding format data to obtain intermediate data. The first data processing module can extract the Y component that conforms to the arrangement characteristics of the NV12 encoding format data from the intermediate data based on the DMA operator, and the second data processing module can extract the U component and the V component that conform to the arrangement characteristics of the NV12 encoding format data from the intermediate data from which the Y component has been extracted based on the Bayer2RGGB operator and the unpack operator. In this way, the arrangement characteristics of the data output by the hardware accelerator can conform to the arrangement characteristics of the NV12 encoding format data, and the conversion of the YUV420LEGACY encoding format data to the NV12 encoding format data can be realized. The hardware accelerator provided in the present application can realize the conversion of the YUV420LEGACY encoding format data to the NV12 encoding format data without re-designing the special hardware and without occupying the resources of the CPU, and has high economy and adaptability.

[0200] The present application also provides an electronic device, comprising: a processor, and a memory communicatively connected to the processor; wherein the memory stores instructions executable by the processor so that the processor performs the steps of the method as described in any one of the first aspects.

[0201] In some embodiments, the processor may include one or more processing cores, such as a 4-core processor, a 4-core processor, and the like. The processor may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor may also include a main processor and a coprocessor. The main processor is a processor for processing data in an awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0202] The memory may include one or more computer-readable storage media, which may be non-transitory. The memory may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In some embodiments, the non-transitory computer-readable storage medium in the memory is used to store at least one program code, and the at least one program code is used to be executed by the processor to implement the process executed by the terminal in the method for data format conversion provided in the method embodiment of the present application.

[0203] The embodiment of the present application also provides a computer-readable storage medium, the computer-readable storage medium includes a stored computer program, wherein when the computer program is running, the device where the computer-readable storage medium is located is controlled to execute the above method for data format conversion. Optionally, the computer-readable storage medium can be a read-only memory (ROM), a random access memory (RAM), a compact disc (CD-ROM), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0204] Similar parts between the embodiments provided in this application can be referenced to each other. The specific implementation methods provided above are only a few examples under the general concept of this application and do not constitute a limitation on the protection scope of this application. For those skilled in the art, any other implementation methods expanded based on the scheme of this application without creative work belong to the protection scope of this application.

Claims

1. A hardware accelerator for data format conversion, characterized in that: include: A data pre-processing module, a first data processing module, a second data processing module, and a data writing module electrically connected in sequence; The data preprocessing module is configured to perform data preprocessing on the YUV420LEGACY encoding format data according to the rgb_pack operator, the CCM operator and the RGGB2Bayer operator to obtain intermediate data; the intermediate data includes a Y component, a U component, a V component and a placeholder component; The Y component is arranged in a first data row of the intermediate data, the U component and the placeholder component are arranged in a second data row of the intermediate data, the V component and the placeholder component are arranged in a third data row of the intermediate data, the first data rows are arranged in alternate rows, and the second data rows and the third data rows are alternately arranged between two rows of the first data rows; The first data processing module is configured to read the intermediate data in alternate lines according to the DMA operator to obtain a first portion of data and a second portion of data, wherein the first portion of data includes the Y component, and the second portion of data includes the U component, the V component, and the placeholder component; The second data processing module is configured to merge the data rows in the second part of data in pairs according to the Bayer2RGGB operator in a conversion format opposite to the RGGB2Bayer operator to obtain a merged second part of data; the Bayer2RGGB operator is used to convert the data in the Bayer encoding format into the data in the RGGB encoding format; The second data processing module is further configured to remove the placeholder component included in the merged second part of data according to the unpack operator to obtain a third part of data; the third part of data includes the U component and the V component arranged in an interlaced manner; The data writing module is configured to write the first part of data and the third part of data in sequence in the storage space according to the DMA operator to obtain NV12 encoding format data.

2. The hardware accelerator for data format conversion according to claim 1, characterized in that: The data preprocessing module performs data preprocessing on the YUV420LEGACY encoding format data according to the rgb_pack operator, the CCM operator and the RGGB2Bayer operator to obtain intermediate data, and is specifically configured as follows: Fill the placeholder component in the YUV420LEGACY encoding format data according to the rgb_pack operator to obtain first process data; exchanging positions of components in the first process data according to the CCM operator to obtain second process data; The data rows in the second process data are split according to the RGGB2Bayer operator to obtain the intermediate data.

3. The hardware accelerator for data format conversion according to claim 2, characterized in that: The YUV420LEGACY encoding format data includes odd rows and even rows, the odd rows are arranged in an interlaced manner according to the U component, the Y component, and the Y component, and the even rows are arranged in an interlaced manner according to the V component, the Y component, and the Y component; The data preprocessing module performs filling of the placeholder component in the YUV420LEGACY encoding format data according to the rgb_pack operator to obtain the first process data, and is specifically configured as follows: In each data row of the YUV420LEGACY encoding format data, one placeholder component is added at every interval of a preset data bit width to obtain the first process data; The odd rows of the first process data are arranged in an interlaced manner according to the U component, the Y component, the Y component, and the placeholder component, and the even rows of the first process data are arranged in an interlaced manner according to the V component, the Y component, the Y component, and the placeholder component.

4. The hardware accelerator for data format conversion according to claim 2, characterized in that: The data preprocessing module exchanges the positions of components in the first process data according to the CCM operator to obtain the second process data, and is specifically configured as follows: According to a preset conversion relationship, the positions of the Y component and the U component of the odd-numbered rows in the first process data are exchanged, and the positions of the Y component and the V component of the even-numbered rows in the first process data are exchanged to obtain second process data; The odd-numbered rows of the second process data are arranged in an alternating manner according to the Y component, the Y component, the U component, and the placeholder component, and the even-numbered rows of the second process data are arranged in an alternating manner according to the Y component, the Y component, the V component, and the placeholder component.

5. The hardware accelerator for data format conversion according to claim 3, characterized in that: The data preprocessing module performs splitting of the data rows in the second process data according to the RGGB2Bayer operator to obtain the intermediate data, and is specifically configured as follows: According to a preset conversion format, the odd-numbered rows in the second process data are split into the first data row and the second data row, and the even-numbered rows are split into the first data row and the third data row, to obtain the intermediate data; The first data row includes the Y component; the second data row includes the U component and the placeholder component, and the U component and the placeholder component are arranged alternately; the third data row includes the V component and the placeholder component, and the V component and the placeholder component are arranged alternately.

6. The hardware accelerator for data format conversion according to any one of claims 1 to 5, characterized in that: The merged second part of data is arranged in an interlaced manner in the order of the U component, the placeholder component, the V component, and the placeholder component; the U component and the V component are first flag bit data, and the placeholder component is second flag bit data; The unpack operator includes a first mode and a second mode, the first mode is used to remove the second flag bit data; the second mode is used to remove the first flag bit data; The second data processing module removes the placeholder component included in the merged second part of data according to the unpack operator to obtain the third part of data, and is configured as follows: Using the first mode of the unpack operator to remove the second identification bit data of the merged second part of data, to obtain a third part of data; The third portion of data is arranged in an interlaced manner according to the order of the U component and the V component.

7. The hardware accelerator for data format conversion according to claim 1, characterized in that: The rgb_pack operator, the CCM operator, the RGGB2Bayer operator, the DMA operator, the Bayer2RGGB operator, and the unpack operator are cascaded.

8. A method for data format conversion, characterized in that: include: Preprocessing the YUV420LEGACY encoding format data according to the rgb_pack operator, the CCM operator and the RGGB2Bayer operator to obtain intermediate data; the intermediate data includes a Y component, a U component, a V component and a placeholder component; The Y component is arranged in a first data row of the intermediate data, the U component and the placeholder component are arranged in a second data row of the intermediate data, the V component and the placeholder component are arranged in a third data row of the intermediate data, the first data rows are arranged in alternate rows, and the second data rows and the third data rows are alternately arranged between two rows of the first data rows; Read the intermediate data in alternate lines according to the DMA operator to obtain a first portion of data and a second portion of data, wherein the first portion of data includes the Y component, and the second portion of data includes the U component, the V component, and the placeholder component; According to the Bayer2RGGB operator and in a conversion format opposite to the RGGB2Bayer operator, the data rows in the second part of the data are merged in pairs to obtain the merged second part of the data; the Bayer2RGGB operator is used to convert the data in the Bayer encoding format into the data in the RGGB encoding format; removing the placeholder component included in the merged second part of data according to the unpack operator to obtain a third part of data; the third part of data includes the U component and the V component arranged in an interlaced manner; The first part of data and the third part of data are written into the storage space in sequence according to the DMA operator to obtain NV12 encoding format data.

9. An electronic device, characterized in that: The electronic device comprises a processor and a memory, wherein the memory is used to store at least one program, and the at least one program is loaded by the processor and executes the method for data format conversion as claimed in claim 8.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores at least one program, and the at least one program is loaded and executed by the processor to implement the method for data format conversion as claimed in claim 8.

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