Display device and electronic device including the same

Abstract

Disclosed are a display device capable of operating in a normal mode or a standby mode including a low afterimage mode, and an electronic apparatus including the display device, the display device including: a display panel including pixels; a gate driver providing a gate signal to the pixel; an emission driver providing emission signals defining a non-emission period and an emission period to the pixels; a data driver supplying a data voltage to the pixels; and a controller controlling the gate driver, the emission driver, and the data driver. The number of pulses of the gate signal in the non-emission period in the low afterimage mode is greater than the number of pulses of the gate signal in the non-emission period in the normal mode. The ratio of the non-transmission period to the frame period in the low afterimage mode is smaller than the ratio of the non-transmission period to the frame period in the normal mode.

Description

Technical Field

[0001] Embodiments relate to a display device, and more particularly, to a display device in which occurrence of an afterimage is reduced, and an electronic device including the display device. Background Art

[0002] The display device may include a plurality of pixels that display an image. Each of the pixels may include a drive transistor that generates a drive current and a light emitting diode that emits light based on the drive current. The drive transistor may have a hysteresis characteristic in which a threshold voltage shifts and a drive current changes depending on a change in a voltage applied to a gate electrode of the drive transistor.

[0003] In a display device included in an electronic device such as a smart watch, the display device may operate in an always-on display (AOD) mode to display a still image (eg, a watch interface) when the electronic device is not in use.

[0004] When the display device is operated in the normal mode after displaying a still image in the AOD mode for a long time, the still image displayed in the AOD mode may be visible as an afterimage due to the hysteresis characteristic of the driving transistor. Summary of the invention

[0005] Embodiments as described herein may provide a display device in which visibility of afterimages is reduced.

[0006] Embodiments may provide an electronic device including a display device in which visibility of an afterimage is reduced.

[0007] A display device capable of operating in a normal mode or a standby mode including a low afterimage mode according to an embodiment may include: a display panel including pixels; a gate driver providing a gate signal to the pixels; an emission driver providing an emission signal defining a non-emission period and an emission period to the pixels; a data driver providing a data voltage to the pixels; and a controller controlling the gate driver, the emission driver, and the data driver. The number of pulses of the gate signal within the non-emission period in the low afterimage mode may be greater than the number of pulses of the gate signal within the non-emission period in the normal mode. The ratio of the non-emission period to the frame period in the low afterimage mode may be less than the ratio of the non-emission period to the frame period in the normal mode.

[0008] In an embodiment, a pixel may include: a first transistor including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a second transistor including a gate electrode receiving a write gate signal, a first electrode receiving a data voltage, and a second electrode connected to the second node; a third transistor including a gate electrode receiving a write gate signal, a first electrode connected to the third node, and a second electrode connected to the first node; a fourth transistor including a gate electrode receiving an initialization gate signal, a first electrode receiving an initialization voltage, and a second electrode connected to the first node; a fifth transistor including a gate electrode receiving an emission signal, a first electrode receiving a first power voltage, and a second electrode connected to the second node; a sixth transistor including a gate electrode receiving an emission signal, a first electrode connected to the third node, and a second electrode connected to the fourth node; a storage capacitor including a first electrode connected to the first node and a second electrode receiving the first power voltage; and a light emitting diode including a first electrode connected to the fourth node and a second electrode receiving the second power voltage.

[0009] In an implementation, the gate signal may include an initialization gate signal and a write gate signal.

[0010] In an embodiment, a hysteresis variation amount of the first transistor in the low afterimage mode may be smaller than a hysteresis variation amount of the first transistor in the normal mode.

[0011] In an embodiment, a range of the data voltage in the low afterimage mode may be smaller than a range of the data voltage in the normal mode.

[0012] In an embodiment, the number of pulses of the emission signal within a frame period in the low afterimage mode may be greater than the number of pulses of the emission signal within a frame period in the normal mode.

[0013] In an embodiment, the display device may further include a power management circuit that provides a high gate voltage and a low gate voltage to the gate driver. A voltage level of the high gate voltage in the low afterimage mode may be lower than a voltage level of the high gate voltage in the normal mode.

[0014] In an embodiment, a voltage level of the low gate voltage in the low afterimage mode may be equal to a voltage level of the low gate voltage in the normal mode.

[0015] In an embodiment, the standby mode may further include an illuminance sensing mode in which ambient illuminance is detected.

[0016] In an embodiment, a ratio of a non-emission period to a frame period in the illumination sensing mode may be greater than a ratio of a non-emission period to a frame period in the low afterimage mode.

[0017] In an embodiment, when a user views an image displayed by the display panel, an illumination sensing mode may be performed.

[0018] In an embodiment, the standby mode may further include a low power mode. The number of pulses of the gate signal in the non-emission period in the low power mode may be smaller than the number of pulses of the gate signal in the non-emission period in the low afterimage mode.

[0019] In an embodiment, the low afterimage mode is executed after the low power mode is executed for a predetermined time.

[0020] In an embodiment, the standby mode may be a mode in which the display panel displays an always-on display (AOD) image.

[0021] An electronic device according to an embodiment may include: a display device capable of operating in a normal mode or a standby mode including a low afterimage mode; a gyro sensor detecting a rotation state of the display device; and an illuminance sensor detecting the ambient illuminance around the display device. The display device may include: a display panel including pixels; a gate driver providing a gate signal to the pixels; an emission driver providing an emission signal defining a non-emission period and an emission period to the pixels; a data driver providing a data voltage to the pixels; and a controller controlling the gate driver, the emission driver, and the data driver. The number of pulses of the gate signal within the non-emission period in the low afterimage mode may be greater than the number of pulses of the gate signal within the non-emission period in the normal mode. The ratio of the non-emission period to the frame period in the low afterimage mode may be less than the ratio of the non-emission period to the frame period in the normal mode.

[0022] In an embodiment, a range of the data voltage in the low afterimage mode may be smaller than a range of the data voltage in the normal mode.

[0023] In an embodiment, the display device may further include a power management circuit that provides a high gate voltage and a low gate voltage to the gate driver. A voltage level of the high gate voltage in the low afterimage mode may be lower than a voltage level of the high gate voltage in the normal mode.

[0024] In an embodiment, the standby mode may further include an illuminance sensing mode in which the illuminance sensor detects ambient illuminance.

[0025] In an embodiment, a ratio of a non-emission period to a frame period in the illumination sensing mode may be greater than a ratio of a non-emission period to a frame period in the low afterimage mode.

[0026] In an embodiment, a gyro sensor may be used to determine whether a user is viewing an image displayed by a display device. When a user is viewing an image, an illumination sensing mode may be performed.

[0027] In a display device and an electronic device including the display device according to an embodiment, the number of pulses of a gate signal in a non-emission period in a low afterimage mode may be greater than the number of pulses of a gate signal in a non-emission period in a normal mode, and a ratio of a non-emission period to a frame period in a low afterimage mode may be less than a ratio of a non-emission period to a frame period in a normal mode, so that a hysteresis variation amount of a driving transistor included in a pixel in a low afterimage mode may be less than a hysteresis variation amount of the driving transistor in a normal mode. Therefore, an image displayed in a low afterimage mode may be prevented from being recognized as an afterimage in a normal mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Illustrative, non-limiting embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings.

[0029] Figure 1 is a block diagram illustrating a display device according to an embodiment of the present disclosure.

[0030] Figure 2 It is shown that the Figure 1 Circuit diagram of a pixel in a display device in FIG.

[0031] Figure 3 It is shown in Figure 2 1 is a timing diagram of gate signals and emission signals during operation of a pixel in a normal mode and a low afterimage mode.

[0032] Figure 4 is a timing diagram showing transmission signals in the normal mode and the low afterimage mode.

[0033] Figure 5 The range of data voltages in the normal mode and the low afterimage mode are shown.

[0034] Figure 6 High and low gate voltages in normal mode and low afterimage mode are shown.

[0035] Figure 7 Shows Figure 1 An example of operation of a display device in a normal mode and a standby mode.

[0036] Figure 8 Shows Figure 1 An example of operation of a display device in standby mode.

[0037] Fig. 9 is a block diagram illustrating an electronic device according to an embodiment of the present disclosure.

[0038] Fig.10 It shows that Fig. 9 FIG. 1 is an example of an electronic device being a smart watch. DETAILED DESCRIPTION

[0039] Hereinafter, a display device and an electronic device according to an embodiment of the present disclosure will be described in more detail with reference to the accompanying drawings. The same reference numerals may be used to identify similar or identical elements in the drawings.

[0040] Figure 1 is a block diagram showing a display device 100 according to an embodiment of the present disclosure.

[0041] refer to Figure 1 , the display device 100 may include a display panel 110 , a gate driver 120 , an emission driver 130 , a data driver 140 , a power management circuit 150 , and a controller 160 .

[0042] The display panel 110 may include pixels PX arranged in an array including rows (sometimes referred to as pixel rows) and columns (sometimes referred to as pixel columns). In an embodiment, the pixel PX may include a first pixel emitting light having a first color, a second pixel emitting light having a second color, and a third pixel emitting light having a third color. For example, the first color, the second color, and the third color may be red, green, and blue, respectively.

[0043] The gate driver 120 may provide a gate signal GS to the pixel PX. The gate driver 120 may sequentially generate a first gate signal GS to an nth gate signal GS corresponding to a first pixel row to an nth pixel row (n is a natural number of 2 or more), respectively. The gate driver 120 may generate the gate signal GS based on a first control signal CNT1. The first control signal CNT1 may include a gate clock signal, a gate start signal, and the like.

[0044] The emission driver 130 may provide an emission signal EM to the pixel PX. The emission signal EM may define, for each pixel PX, a non-emission period in which the pixel PX does not emit light and an emission period in which the pixel PX emits light. The emission driver 130 may sequentially generate first to n-th emission signals EM corresponding to the first to n-th pixel rows, respectively, based on the second control signal CNT2. The second control signal CNT2 may include an emission clock signal, an emission start signal, and the like.

[0045] The data driver 140 may provide a data voltage VDAT to the pixel PX. The data driver 140 may generate first to m-th data voltages VDAT corresponding to the first to m-th pixel columns (m is a natural number of 2 or more) based on the second image data IMD2 and the third control signal CNT3. In an embodiment, the second image data IMD2 may include grayscale values ​​corresponding to the pixels PX respectively. The third control signal CNT3 may include a data clock signal, a horizontal start signal, a load signal, etc.

[0046] The power management circuit 150 may provide the high gate voltage VGH and the low gate voltage VGL to the gate driver 120. The power management circuit 150 may change the voltage level of the high gate voltage VGH based on the fourth control signal CNT4.

[0047] The controller 160 may control the operation (or driving) of the gate driver 120, the operation (or driving) of the emission driver 130, the operation (or driving) of the data driver 140, and the operation (or driving) of the power management circuit 150. The controller 160 may generate a first control signal CNT1, a second control signal CNT2, a second image data IMD2, a third control signal CNT3, and a fourth control signal CNT4 based on the first image data IMD1 and the control signal CNT. In an embodiment, the first image data IMD1 may include grayscale values ​​corresponding to the pixels PX, respectively. The controller 160 may convert the first image data IMD1 into the second image data IMD2. The control signal CNT may include a main clock signal, a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and the like.

[0048] The display device 100 may be driven in a normal mode or a standby mode. In an embodiment, the standby mode may be a mode in which the display panel 110 displays a low brightness always-on display (AOD) image. In an embodiment, the standby mode may include a low afterimage mode, a low power mode, an illumination sensing mode, etc.

[0049] In an embodiment, the controller 160 may include a register 162. The user may set whether to operate in a standby mode, whether to operate in a low power mode, the operation time of the low power mode, whether to operate in a low afterimage mode, whether to operate in an illumination sensing mode, etc., and the user's settings may be stored in the register 162. The controller 160 may control the operation of the standby mode, the operation of the low power mode, the operation of the low afterimage mode, and the operation of the illumination sensing mode based on the user's settings stored in the register 162.

[0050] In an embodiment, the number of pulses of the gate signal GS within the non-emission period in the low afterimage mode may be greater than the number of pulses of the gate signal GS within the non-emission period in the normal mode, and the ratio of the non-emission period to the frame period in the low afterimage mode may be less than the ratio of the non-emission period to the frame period in the normal mode. Therefore, in the low afterimage mode, the amount of change in the hysteresis of the driving transistor included in each of the pixels PX may be reduced, and the AOD image displayed in the low afterimage mode may be less visible or invisible as an afterimage in a subsequent image displayed in the normal mode.

[0051] Figure 2 It is shown that the Figure 1 1 is a circuit diagram of one of the pixels PX in the display device 100.

[0052] refer to Figure 1 and Figure 2 , the pixel PX may include a driving transistor (hereinafter referred to as the first transistor) T1, a writing transistor (hereinafter referred to as the second transistor) T2, a compensation transistor (hereinafter referred to as the third transistor) T3, an initialization transistor (hereinafter referred to as the fourth transistor) T4, a first emission transistor (hereinafter referred to as the fifth transistor) T5, a second emission transistor (hereinafter referred to as the sixth transistor) T6, a bypass transistor (hereinafter referred to as the seventh transistor) T7, a storage capacitor CST and a light emitting diode EL. Figure 2 In the example of FIG. 1 , the gate signal GS may include an initialization gate signal GI and a write gate signal GW.

[0053] The first transistor T1 may include a gate electrode connected to the first node N1, a first electrode connected to the second node N2, and a second electrode connected to the third node N3. Therefore, the first transistor T1 may be connected between the second node N2 and the third node N3, and may be turned on or off in response to the voltage of the first node N1. The first transistor T1 may generate a driving current corresponding to a voltage difference between the first node N1 and the second node N2.

[0054] The second transistor T2 may be connected between the second node N2 and the data line transmitting the data voltage VDAT, and may be turned on in response to the write gate signal GW. The second transistor T2 may include a gate electrode receiving the write gate signal GW, a first electrode receiving the data voltage VDAT, and a second electrode connected to the second node N2. The second transistor T2 may transmit the data voltage VDAT to the second node N2 in response to the write gate signal GW.

[0055] The third transistor T3 may be connected between the third node N3 and the first node N1 and may be turned on in response to the write gate signal GW. The third transistor T3 may include a gate electrode receiving the write gate signal GW, a first electrode connected to the third node N3, and a second electrode connected to the first node N1. The third transistor T3 may connect the third node N3 and the first node N1 in response to the write gate signal GW.

[0056] The fourth transistor T4 may be connected between the first node N1 and an initialization voltage line transmitting the initialization voltage VINT, and may be turned on in response to the initialization gate signal GI. The fourth transistor T4 may include a gate electrode receiving the initialization gate signal GI, a first electrode receiving the initialization voltage VINT, and a second electrode connected to the first node N1. The fourth transistor T4 may transmit the initialization voltage VINT to the first node N1 in response to the initialization gate signal GI.

[0057] The fifth transistor T5 may be connected between the second node N2 and the first power voltage line transmitting the first power voltage ELVDD, and may be turned on in response to the emission signal EM. The fifth transistor T5 may include a gate electrode receiving the emission signal EM, a first electrode receiving the first power voltage ELVDD, and a second electrode connected to the second node N2. The fifth transistor T5 may transmit the first power voltage ELVDD to the second node N2 in response to the emission signal EM.

[0058] The sixth transistor T6 may be connected between the third node N3 and the fourth node N4 and may be turned on in response to the emission signal EM. The sixth transistor T6 may include a gate electrode receiving the emission signal EM, a first electrode connected to the third node N3, and a second electrode connected to the fourth node N4. The sixth transistor T6 may connect the third node N3 and the fourth node N4 in response to the emission signal EM.

[0059] The seventh transistor T7 may be connected between the initialization voltage line and the fourth node N4, and may be turned on in response to the write gate signal GW. The seventh transistor T7 may include a gate electrode receiving the write gate signal GW, a first electrode receiving the initialization voltage VINT, and a second electrode connected to the fourth node N4. The seventh transistor T7 may transmit the initialization voltage VINT to the fourth node N4 in response to the write gate signal GW.

[0060] Figure 2An embodiment in which each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 is a P-type transistor (e.g., a PMOS transistor) is shown, but the present disclosure is not limited thereto. In another embodiment, at least one of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be an N-type transistor (e.g., an NMOS transistor).

[0061] The storage capacitor CST may be connected between the first node N1 and the first power voltage line. The storage capacitor CST may include a first electrode connected to the first node N1 and a second electrode receiving the first power voltage ELVDD. The storage capacitor CST may store or maintain the voltage of the first node N1.

[0062] Figure 2 An embodiment in which the pixel PX includes seven transistors and one capacitor is shown, but the present disclosure is not limited thereto. In another embodiment, the pixel PX may include three to six or eight or more transistors and / or two or more capacitors.

[0063] The light emitting diode EL may be connected between the fourth node N4 and the second power voltage line transmitting the second power voltage ELVSS. The light emitting diode EL may include a first electrode (e.g., an anode) connected to the fourth node N4 and a second electrode (e.g., a cathode) receiving the second power voltage ELVSS. The light emitting diode EL may emit light having an intensity depending on the driving current.

[0064] In an embodiment, the light emitting diode EL may be an organic light emitting diode. In another embodiment, the light emitting diode EL may be an inorganic light emitting diode, a micro light emitting diode or a quantum dot light emitting diode.

[0065] Figure 3 Shown in Figure 2 The emission signal EM, the initialization gate signal GI, and the write gate signal GW during operation of the pixel PX in the normal mode MD_NM and the low afterimage mode MD_LA.

[0066] refer to Figures 1 to 3 , the voltage level of the emission signal EM may define a non-emission period PNE and an emission period PE. A period in which the emission signal EM has a high voltage (e.g., a cut-off voltage) may be defined as a non-emission period PNE, and a period in which the emission signal EM has a low voltage (e.g., a turn-on voltage) may be defined as an emission period PE.

[0067] The pulse of the gate signal GS may be provided to the pixel PX during the non-emission period PNE. The pulse PSG of the initialization gate signal GI and the pulse PSG' of the write gate signal GW may be provided to the pixel PX during the non-emission period PNE. Each pulse PSG or PSG' may include a falling edge at which the high gate voltage VGH transitions to the low gate voltage VGL, an interval during which the signal voltage is maintained at the low gate voltage VGL, and a rising edge at which the low gate voltage VGL transitions to the high gate voltage VGH.

[0068] Pulses PSG of the initialization gate signal GI and pulses PSG' of the write gate signal GW may alternate. In an embodiment, the waveform of the write gate signal GW may be the same as that of the initialization gate signal GI but shifted in time so that pulses PSG do not overlap with pulses PSG'.

[0069] In response to the pulse PSG of the initialization gate signal GI, the initialization voltage VINT may be applied to the first node N1 and thus to the gate electrode of the first transistor T1. Therefore, the gate electrode of the first transistor T1 may be initialized to the initialization voltage VINT, which may turn on the first transistor T1 during the pulse PSG of the initialization gate signal GI.

[0070] In response to the pulse PSG' of the write gate signal GW, the data voltage VDAT may be applied to the gate electrode of the first transistor T1 through the second transistor T2, the first transistor T1, and the third transistor T3, and the first transistor T1 (initialized to be on-biased) applies the data voltage VDAT compensated for the threshold voltage of the first transistor T1 to the first node N1. Therefore, in response to the pulse PSG', the data voltage VDAT compensated for the threshold voltage may be stored in the storage capacitor CST, and the first transistor T1 may be off-biased. In addition, in response to the pulse PSG' of the write gate signal GW, the initialization voltage VINT is applied to the first electrode of the light emitting diode EL. Therefore, the first electrode of the light emitting diode EL may be initialized.

[0071] The on bias state and the off bias state of the first transistor T1 may be repeated or cycled in the non-emission period PNE, so that the hysteresis variation amount of the first transistor T1 may be reduced.

[0072] The number of pulses of the gate signal GS within the non-emission period PNE in the low afterimage mode MD_LA (e.g., the number of pulses PSG of the initialization gate signal GI) may be greater than the number of pulses of the gate signal GS within the non-emission period PNE in the normal mode MD_NM (e.g., the number of pulses PSG of the initialization gate signal GI). Figure 3As shown in, the number of pulses of the gate signal GS within the non-emission period PNE in the low afterimage mode MD_LA may be three, and the number of pulses of the gate signal GS within the non-emission period PNE in the normal mode MD_NM may be two. As the number (or number of times) of repeating the on-bias state and the off-bias state of the first transistor T1 increases, the hysteresis change amount of the first transistor T1 may decrease. Therefore, the hysteresis change amount of the first transistor T1 in the low afterimage mode MD_LA may be less than the hysteresis change amount of the first transistor T1 in the normal mode MD_NM.

[0073] In the emission period PE, the first transistor T1 may generate a driving current based on the data voltage VDAT stored in the storage capacitor CST compensated for the threshold voltage, and the light emitting diode EL may emit light having brightness corresponding to the driving current.

[0074] Figure 4 is a timing diagram showing the emission signal EM in the normal mode MD_NM and the low afterimage mode MD_LA. Figure 5 The corresponding ranges of the data voltage VDAT in the normal mode MD_NM and the low afterimage mode MD_LA are shown.

[0075] refer to Figure 4 and Figure 5 , in the normal mode MD_NM, the emission off ratio, which is the ratio of the duration of the non-emission period PNE to the frame period FRM, may be greater than the minimum emission off ratio. For example, the minimum emission off ratio may be about 40%. In the normal mode MD_NM, the illuminance sensor may detect the ambient illuminance around the display device during the non-emission period PNE, and the brightness of the image displayed in the normal mode MD_NM may be adjusted according to the ambient illuminance measured around the display device. In the normal mode MD_NM, the minimum non-emission period PNE within the frame period FRM may need to be long enough for the operation of the illuminance sensor.

[0076] The number of pulses PSE of the emission signal EM within the frame period FRM in the low afterimage mode MD_LA may be greater than the number of pulses PSE of the emission signal EM within the frame period FRM in the normal mode MD_NM. In a standby mode for displaying an AOD image with low brightness, when the number of pulses PSE of the emission signal EM within the frame period FRM is small, flicker may be visible, and thus the number of pulses PSE of the emission signal EM within the frame period FRM in the low afterimage mode MD_LA may be increased to prevent flicker from being visible. Since the number of pulses PSE of the emission signal EM within the frame period FRM in the low afterimage mode MD_LA is increased, the available time of the non-emission period PNE in the low afterimage mode MD_LA may be too short for the operation of the illumination sensor. In an embodiment, as Figure 4 As shown in , the number of pulses PSE of the emission signal EM within the frame period FRM in the low afterimage mode MD_LA may be eight, and the number of pulses PSE of the emission signal EM within the frame period FRM in the normal mode MD_NM may be one.

[0077] The ratio of the non-emission period PNE to the frame period FRM in the low afterimage mode MD_LA may be smaller than the ratio of the non-emission period PNE to the frame period FRM in the normal mode MD_NM, and the range of the data voltage VDAT in the low afterimage mode MD_LA may be smaller than the range of the data voltage VDAT in the normal mode MD_NM. Since the illumination sensor does not operate in the low afterimage mode MD_LA, the ratio of the non-emission period PNE to the frame period FRM may be reduced, and as the emission time per frame in the low afterimage mode MD_LA increases accordingly, the range of the data voltage VDAT in the low afterimage mode MD_LA may be reduced. In an embodiment, the ratio of the non-emission period PNE to the frame period FRM in the low afterimage mode MD_LA may be about 14%, and the ratio of the non-emission period PNE to the frame period FRM in the normal mode MD_NM may be about 43.2%. In an embodiment, a voltage level of the black data voltage VDAT_BL in the low afterimage mode MD_LA may be substantially equal to that in the normal mode MD_NM, and a voltage level of the white data voltage VDAT_WH in the low afterimage mode MD_LA may be higher than that in the normal mode MD_NM.

[0078] As the range of the data voltage VDAT narrows, the amplitude of the voltage change of the gate electrode of the first transistor T1 can be reduced, so that the hysteresis change amount of the first transistor T1 can be reduced. Therefore, the hysteresis change amount of the first transistor T1 in the low afterimage mode MD_LA can be smaller than the hysteresis change amount of the first transistor T1 in the normal mode MD_NM.

[0079] Figure 6 The levels of the high gate voltage VGH and the low gate voltage VGL in the normal mode MD_NM and the low afterimage mode MD_LA are shown.

[0080] refer to Figure 6 , the voltage level VL_HL of the high gate voltage VGH in the low afterimage mode MD_LA may be lower than the voltage level VL_HN of the high gate voltage VGH in the normal mode MD_NM, and the voltage level VL_LL of the low gate voltage VGL in the low afterimage mode MD_LA may be substantially equal to the voltage level VL_LN of the low gate voltage VGL in the normal mode MD_NM. Therefore, the difference between the voltage level VL_HL of the high gate voltage VGH and the voltage level VL_LL of the low gate voltage VGL in the low afterimage mode MD_LA may be smaller than the difference between the voltage level VL_HN of the high gate voltage VGH and the voltage level VL_LN of the low gate voltage VGL in the normal mode MD_NM.

[0081] When the gate signal GS changes from the high gate voltage VGH to the low gate voltage VGL (or from the low gate voltage VGL to the high gate voltage VGH), a kickback voltage corresponding to the change of the gate signal GS may appear at the gate electrode of the first transistor T1. As the change of the gate signal GS (in other words, the difference between the high gate voltage VGH and the low gate voltage VGL) decreases, the kickback voltage can be reduced, and accordingly, due to the reduction in the voltage change amplitude at the gate electrode of the first transistor T1, the hysteresis change amount of the first transistor T1 can be reduced. Therefore, the hysteresis change amount of the first transistor T1 in the low afterimage mode MD_LA can be less than the hysteresis change amount of the first transistor T1 in the normal mode MD_NM.

[0082] Figure 7 Shows Figure 1 An example of the operation of the display device 100 is shown.

[0083] refer to Figure 1 and Figure 7 , the display device 100 may be driven in a normal mode MD_NM or a standby mode MD_SB, and the standby mode MD_SB may include a low power mode MD_LP and a low afterimage mode MD_LA.

[0084] The number of pulses of the gate signal in the non-emission period in the low power mode MD_LP may be less than the number of pulses of the gate signal in the non-emission period in the low afterimage mode MD_LA. As the number of pulses of the gate signal decreases, the power consumption of the display device 100 may be reduced. Therefore, the power consumption of the display device 100 in the low power mode MD_LP may be less than the power consumption of the display device 100 in the low afterimage mode MD_LA.

[0085] When the driving mode of the display device 100 is switched from the normal mode MD_NM to the standby mode MD_SB, the display device 100 may be driven in the low power mode MD_LP. Therefore, the display device 100 may be driven in the low power mode MD_LP to minimize power consumption during an initial period of the standby mode MD_SB.

[0086] The low afterimage mode MD_LA may be executed after the low power mode MD_LP is executed for a predetermined time T_PD. The predetermined time T_PD during which the low power mode MD_LP is executed may be set by a user.

[0087] In the prior art, when the display device is driven in the normal mode MD_NM after being driven in the standby mode MD_SB for a long time, the AOD image displayed in the standby mode MD_SB may be recognized as an afterimage in the normal mode MD_NM due to the hysteresis characteristics of the driving transistor T1 included in the pixel PX. However, in an embodiment of the present disclosure, the hysteresis variation amount of the driving transistor T1 included in the pixel PX can be reduced in the low afterimage mode MD_LA, so that the AOD image displayed in the standby mode MD_SB may not be recognized as an afterimage in the normal mode MD_NM.

[0088] Figure 8 Shows Figure 1 An example of the operation of the display device 100 is shown.

[0089] refer to Figure 1 and Figure 8 , the standby mode MD_SB may include a low afterimage mode MD_LA and an illuminance sensing mode MD_LS. In the illuminance sensing mode MD_LS, the illuminance sensor may detect the ambient illuminance of the environment around the display device 100.

[0090] The ratio of the non-emission period to the frame period in the illuminance sensing mode MD_LS may be greater than the ratio of the non-emission period to the frame period in the low afterimage mode MD_LA. When the ratio of the non-emission period to the frame period increases (i.e., when the emission period decreases and the non-emission period increases), the time for the illuminance sensor to operate may be ensured. Therefore, the illuminance sensor may detect the ambient illuminance around the display device 100 in the illuminance sensing mode MD_LS, and the display device 100 may optimize the brightness of the displayed image according to the detected ambient illuminance.

[0091] When a user views an image displayed by the display panel 110, the illuminance sensing mode MD_LS may be performed. Figure 8 As shown in , a gyro sensor that detects the rotation state of the display device 100 can be used to determine that a user is viewing an image displayed by the display panel 110 at time T_GZ, and the display device 100 can operate in an illuminance sensing mode MD_LS, thereby sensing the ambient illuminance and optimizing the brightness of the displayed image according to the detected ambient illuminance.

[0092] Fig. 9 is a block diagram showing an electronic device 1000 according to an embodiment of the present disclosure. Fig.10 It shows that Fig. 9 The electronic device 1000 is implemented as an example of a smart watch.

[0093] refer to Fig. 9 and Fig.10 , the electronic device 1000 may include a processor 1010, a memory device 1020, a storage device 1030, a display device 1040, a gyro sensor 1050, and an illumination sensor 1060. The electronic device 1000 may also include a plurality of ports capable of communicating with a video card, a sound card, a memory card, a USB device, etc. or with other systems.

[0094] According to the implementation mode, Fig.10 As shown in , the electronic device 1000 may be implemented as a smart watch. However, the present disclosure is not limited thereto, and according to another embodiment, the electronic device 1000 may be implemented as a TV, a mobile phone, a video phone, a smart board, a tablet PC, a vehicle navigation, a laptop computer, a head-mounted display, etc.

[0095] The processor 1010 may perform specific calculations or tasks. Depending on the implementation, the processor 1010 may be a microprocessor, a central processing unit (CPU), etc. The processor 1010 may be connected to other components via an address bus, a control bus, a data bus, etc. Depending on the implementation, the processor 1010 may also be connected to an expansion bus such as a peripheral component interconnect (PCI) bus. Depending on the implementation, the processor 1010 may Figure 1 The first image data IMD1 and Figure 1 The control signal CNT is provided to the display device 1040.

[0096] The memory device 1020 may store data required for the operation of the electronic device 1000. For example, the memory device 1020 may include: a nonvolatile memory device such as an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a phase change random access memory (PRAM), a resistive random access memory (RRAM), a nano floating gate memory (NFGM), a polymer random access memory (PoRAM), a magnetic random access memory (MRAM), or a ferroelectric random access memory (FRAM); and / or a volatile memory device such as a dynamic random access memory (DRAM), a static random access memory (SRAM), or a mobile DRAM.

[0097] The storage device 1030 may include a solid state drive (SSD), a hard disk drive (HDD), a CD-ROM, or the like.

[0098] The display device 1040 can be connected to other components via a bus or other communication links. Figure 1 The display device 1040 may correspond to Figure 7 Normal mode MD_NM or Figure 7 Standby mode MD_SB driver. Standby mode MD_SB can include Figure 7 Low power mode MD_LP, Figure 7 Low afterimage mode MD_LA and Figure 8 The illuminance sensing mode MD_LS.

[0099] The gyro sensor 1050 may detect a rotation state of the display device 1040. In the standby mode MD_SB, when the gyro sensor 1050 detects a motion indicating that a user is viewing an image displayed by the display device 1040, the illuminance sensing mode MD_LS may be performed.

[0100] The illuminance sensor 1060 may detect the ambient illuminance of the environment around the display device 1040. In the illuminance sensing mode MD_LS, the ambient illuminance may be detected using the illuminance sensor 1060, and the brightness of an image displayed by the display device 1040 may be optimized according to the detected ambient illuminance.

[0101] The display device according to the disclosed embodiment may be applied to display devices included in computers, notebooks, mobile phones, smart phones, smart pads, smart watches, PMPs, PDAs, MP3 players, and the like.

[0102] Although the display device and the electronic device according to the embodiments have been described with reference to the accompanying drawings, the illustrated embodiments are examples and may be modified and changed by a person of ordinary skill in the relevant technical field without departing from the technical spirit described in the appended claims.

Claims

1. A display device capable of operating in a normal mode or a standby mode including a low afterimage mode, the display device comprising: A display panel, including pixels; A gate driver, providing a gate signal to the pixel; an emission driver for providing an emission signal defining a non-emission period and an emission period to the pixel; A data driver for providing a data voltage to the pixel; as well as a controller to control the gate driver, the emission driver and the data driver, wherein the number of pulses of the gate signal within the non-emission period in the low afterimage mode is greater than the number of pulses of the gate signal within the non-emission period in the normal mode, and Wherein, a ratio of the non-emission period to the frame period in the low afterimage mode is smaller than a ratio of the non-emission period to the frame period in the normal mode.

2. The display device according to claim 1, wherein: The pixels include: a first transistor including a gate electrode connected to a first node, a first electrode connected to a second node, and a second electrode connected to a third node; a second transistor including a gate electrode receiving a write gate signal, a first electrode receiving the data voltage, and a second electrode connected to the second node; a third transistor including a gate electrode receiving the write gate signal, a first electrode connected to the third node, and a second electrode connected to the first node; a fourth transistor including a gate electrode receiving an initialization gate signal, a first electrode receiving an initialization voltage, and a second electrode connected to the first node; a fifth transistor including a gate electrode receiving the transmission signal, a first electrode receiving a first power voltage, and a second electrode connected to the second node; a sixth transistor including a gate electrode receiving the emission signal, a first electrode connected to the third node, and a second electrode connected to a fourth node; a storage capacitor including a first electrode connected to the first node and a second electrode receiving the first power voltage; and The light emitting diode includes a first electrode connected to the fourth node and a second electrode receiving a second power voltage.

3. The display device according to claim 1, wherein: A range of the data voltage in the low afterimage mode is smaller than a range of the data voltage in the normal mode.

4. The display device according to claim 1, wherein: The number of pulses of the emission signal within the frame period in the low afterimage mode is greater than the number of pulses of the emission signal within the frame period in the normal mode.

5. The display device according to claim 1, further comprising: a power management circuit that provides a high gate voltage and a low gate voltage to the gate driver, Wherein, a voltage level of the high gate voltage in the low afterimage mode is lower than a voltage level of the high gate voltage in the normal mode.

6. The display device according to claim 5, wherein: A voltage level of the low gate voltage in the low afterimage mode is equal to a voltage level of the low gate voltage in the normal mode.

7. The display device according to claim 1, wherein: The standby mode also includes an illuminance sensing mode in which ambient illuminance is detected.

8. The display device according to claim 7, wherein: A ratio of the non-emission period to the frame period in the illumination sensing mode is greater than the ratio of the non-emission period to the frame period in the low afterimage mode.

9. The display device according to claim 1, wherein: The standby mode also includes a low power mode, and wherein the number of the pulses of the gate signal within the non-emission period in the low power mode is smaller than the number of the pulses of the gate signal within the non-emission period in the low afterimage mode.

10. An electronic device, comprising: A display device capable of operating in a normal mode or a standby mode including a low afterimage mode; a gyro sensor, detecting a rotation state of the display device; as well as an illumination sensor, for detecting the ambient illumination around the display device, Wherein, the display device comprises: Display panel, including pixels; A gate driver, providing a gate signal to the pixel; an emission driver for providing an emission signal defining a non-emission period and an emission period to the pixel; a data driver for providing a data voltage to the pixel; and a controller to control the gate driver, the emission driver and the data driver, wherein the number of pulses of the gate signal within the non-emission period in the low afterimage mode is greater than the number of pulses of the gate signal within the non-emission period in the normal mode, and Wherein, a ratio of the non-emission period to the frame period in the low afterimage mode is smaller than a ratio of the non-emission period to the frame period in the normal mode.

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