Pixel driving circuit and display panel

Abstract

The invention provides a pixel driving circuit and a display panel, and the pixel driving circuit is used for driving a sub-pixel, and is characterized in that the pixel driving circuit comprises a driving transistor which is configured to generate a driving current to drive the sub-pixel; the write transistor is used for writing a data signal into one of the source electrode or the drain electrode of the driving transistor under the control of a write signal; the compensation transistor is configured to write a data signal into the grid electrode of the driving transistor under the control of a compensation signal; the isolation module is connected in series between the grid electrode of the driving transistor and the compensation transistor; wherein the isolation module is configured to adjust the refresh frequency of the sub-pixels under the control of an isolation signal. The technical problem that the use scene is limited due to the fact that the whole display panel enters low-frequency display in the prior art is solved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a pixel driving circuit and a display panel. Background Art

[0002] OLED (Organic Light-Emitting Diode) products are occupying an increasingly large share of the market, and consumers have higher and higher requirements for the usage time of the entire device. LTPO (Low Temperature Polysilicon Oxide) low-power products are becoming more and more popular among consumers and mobile phone manufacturers. LTPO can enter low-frequency mode when in standby or when using special APPs, saving IC power consumption and increasing the usage time of the phone. However, the entire display panel enters low-frequency display, which limits the usage scenarios. Summary of the invention

[0003] Embodiments of the present invention provide a pixel driving circuit and a display panel to solve the technical problem in the related art that the entire display panel enters low-frequency display, which limits the use scenarios.

[0004] To solve the above problems, the technical solution provided by the present invention is as follows:

[0005] In a first aspect, an embodiment of the present application provides a pixel driving circuit for driving a sub-pixel, comprising: a driving transistor, wherein the driving transistor is configured to generate a driving current to drive the sub-pixel;

[0006] A write transistor, which writes a data signal to one of the source or drain of the drive transistor under the control of a write signal; a compensation transistor, which is configured to write the data signal to the gate of the drive transistor under the control of the compensation signal; an isolation module, which is connected in series between the gate of the drive transistor and the compensation transistor; wherein the isolation module is configured to adjust the refresh frequency of the sub-pixel under the control of the isolation signal.

[0007] In one embodiment, the isolation module includes an isolation transistor, one of the source or the drain of the isolation transistor is electrically connected to the compensation transistor, the other of the source or the drain of the isolation transistor is electrically connected to the gate of the driving transistor, and the gate of the isolation transistor is used to receive the isolation signal.

[0008] In one embodiment, under the control of the isolation signal, the isolation transistor adjusts the frequency at which the compensation transistor writes the data signal to the gate of the driving transistor, so as to adjust the refresh frequency of the sub-pixel.

[0009] In one embodiment, when the isolation transistor is turned off, the voltage of the data signal is a constant value.

[0010] In one embodiment, the pixel driving circuit also includes a first reset transistor, which is configured to reset the gate voltage of the driving transistor under the control of a first reset signal, one of the source or drain of the first reset transistor is electrically connected to one of the source or drain of the isolation transistor, and the other of the source or drain of the first reset transistor is used to receive a gate reset signal.

[0011] In a second aspect, an embodiment of the present application further provides a display panel, comprising a plurality of pixel driving circuits as described in any one of the above items.

[0012] In one embodiment, the display panel includes a first partition and a second partition in the row direction, and the multiple isolation signals include multiple first isolation signals and multiple second isolation signals; wherein the isolation module corresponding to the pixel driving circuit of the first partition receives the first isolation signal, and the isolation module corresponding to the pixel driving circuit of the second partition receives the second isolation signal.

[0013] In one embodiment, when the isolation signal is at a valid level, the isolation module is turned on to enable the corresponding compensation transistor to write the data signal to the gate of the driving transistor; wherein the display panel includes a plurality of subframes in a unit time, and among the plurality of subframes, the number of subframes in which the first isolation signal is at a valid level is less than the number of subframes in which the second isolation signal is at a valid level.

[0014] In one embodiment, the ratio of the number of subframes in which the first isolation signal is at an effective level to the number of subframes in which the first isolation signal is at an effective level is 1:4.

[0015] In one embodiment, the display panel also includes a plurality of data signal lines and a plurality of isolation signal lines, the plurality of isolation signal lines are respectively connected to the isolation modules of the plurality of pixel driving circuits to transmit the plurality of isolation signals, the data signal lines are used to transmit the data signals, and the isolation signal lines are arranged in parallel with the data signal lines.

[0016] The beneficial effect of the present invention is as follows: by setting the isolation module between the compensation transistor and the gate of the driving transistor, the isolation module can control the frequency of writing the data signal into the gate of the driving transistor according to the isolation signal, thereby controlling the refresh frequency of the sub-pixel. Therefore, based on the display panel composed of the pixel driving circuit, the refresh frequencies of the pixel driving circuits in different areas of the display panel can be different by adjusting the isolation modules of the pixel driving circuits in different areas of the display panel, so that the display panel can achieve frequency division display, thereby solving the technical problem in the related art that the entire display panel enters low-frequency display, which limits the usage scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0018] Attached Figure 1 is a structural schematic diagram of a pixel driving circuit in the related art of the present invention;

[0019] Attached Figure 2 is a schematic structural diagram of a pixel driving circuit in an embodiment of the present invention;

[0020] Attached Figure 3 is a schematic structural diagram of a pixel driving circuit in an embodiment of the present invention;

[0021] Attached Figure 4 is a timing diagram of a pixel driving circuit in an embodiment of the present invention;

[0022] Attached Figure 5 is a schematic structural diagram of a pixel driving circuit in a display panel in an embodiment of the present invention;

[0023] Attached Figure 6 is a schematic diagram of a partition structure of a display panel in an embodiment of the present invention;

[0024] Attached Figure 7 Schematic diagram of the structure of a pixel driving circuit in an embodiment of the present invention. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0026] Figure 1 Schematic diagram of the structure of a pixel driving circuit in the related art.

[0027] In the related art, the display panel is composed of the above-mentioned pixel driving circuit and sub-pixels arranged in an array, such as Figure 1 As shown, the pixel driving circuit includes a driving transistor T1, a writing transistor T2, a compensation transistor T3 and a first reset transistor T4, one of the source or drain of the writing transistor T2 is electrically connected to one of the source or drain of the driving transistor T1, the other of the source or drain of the writing transistor T2 receives a data signal, one of the source or drain of the compensation transistor T3 is electrically connected to the other of the source or drain of the driving transistor T1, the other of the source or drain of the compensation transistor T3 is electrically connected to the gate of the driving transistor T1, one of the source or drain of the first reset transistor T4 is electrically connected to the gate of the driving transistor T1, the other of the source or drain of the first reset transistor T4 receives a gate reset signal. The gate of the compensation transistor T3 is electrically connected to a compensation signal line to receive a compensation signal, the gate of the reset transistor is electrically connected to a first reset signal line to receive a first reset signal, and the gate of the writing transistor T2 is electrically connected to a writing signal line to receive a writing signal.

[0028] Each frame of the display panel includes a reset phase, a write phase, and a light-emitting phase. In the reset phase, the first reset transistor T4 is turned on, and the gate reset signal is written to the gate of the driving transistor T1 to reset the gate of the driving transistor T1. In the write phase, the write transistor T2 and the compensation transistor T3 are turned on, and the data signal is written to the gate of the driving transistor T1. In the light-emitting phase, the driving transistor T1 drives the light-emitting element to emit light.

[0029] Therefore, the refresh frequency of the sub-pixel can be changed by controlling the compensation transistor T3 to control the frequency of writing the data signal, and by controlling the first reset transistor T4 to control the frequency of resetting the gate of the driving transistor T1.

[0030] Since in the display panel, the compensation signal lines and the first reset signal lines are arranged in rows, that is, the display panel includes multiple rows of the compensation signal lines and the first reset signal lines, and each row of the compensation signal lines and the first reset signal lines drives the sub-pixels in the corresponding row, therefore, the display panel based on the above pixel driving circuit can only realize up-down frequency division display.

[0031] The embodiments of the present application provide a novel pixel driving circuit, which can not only provide a new method for realizing frequency division display, but also further realize left-right frequency division display on the basis of realizing frequency division display, thereby solving the technical problem of not being able to realize left-right frequency division display in related technologies.

[0032] Figure 2 It is a pixel driving circuit in an embodiment of the present application.

[0033] like Figure 2 As shown, the pixel driving circuit includes a driving transistor T1, a writing transistor T2, a compensation transistor T3 and an isolation module.

[0034] One of the source or drain of the driving transistor T1 is electrically connected to the first power signal line, one of the source or drain of the driving transistor T1 is electrically connected to the anode of the light emitting element, and the gate of the driving transistor T1 is electrically connected to the first node Q. The cathode of the light emitting element is electrically connected to the second power signal line. One of the source or drain of the writing transistor T2 is electrically connected to one of the source or drain of the driving transistor T1, the other of the source or drain of the writing transistor T2 is electrically connected to the data signal line, and the gate of the writing transistor T2 is electrically connected to the writing signal line. One of the source or drain of the compensation transistor T3 is electrically connected to the other of the source or drain of the driving transistor T1, the other of the source or drain of the compensation transistor T3 is connected to the second node D, and the gate of the compensation transistor T3 is electrically connected to the compensation signal line. The isolation module is electrically connected between the first node Q and the second node D. The control end of the isolation module is electrically connected to the isolation signal line.

[0035] It should be noted that the first power signal line provides a first power signal VDD, the second power signal line provides a second power signal VSS, the write signal line provides a write signal Pscan1(n), the compensation signal line provides a compensation signal scan1(n), and the isolation signal line provides an isolation signal Control.

[0036] It can be understood that the connection between the compensation transistor T3 and the gate of the driving transistor T1 can be controlled by the isolation module, and therefore, the frequency of writing the data signal into the gate of the driving transistor T1 can be controlled by the isolation module, thereby controlling the refresh frequency of the sub-pixel, and further adjusting the refresh frequency of the display panel. Therefore, by adjusting the isolation modules of the pixel driving circuits in different areas of the display panel, the refresh frequencies of the pixel driving circuits in different areas can be made different, so that the display panel can achieve frequency division display.

[0037] In this embodiment, by setting the isolation module between the compensation transistor T3 and the gate of the driving transistor T1, the isolation module can control the frequency of writing the data signal into the gate of the driving transistor T1 according to the isolation signal, thereby controlling the refresh frequency of the sub-pixel, and then by adjusting the isolation modules of the pixel driving circuits in different areas of the display panel, the refresh frequencies of the pixel driving circuits in different areas can be different, so that the display panel can achieve frequency division display, which solves the technical problem in the related art that the entire display panel enters low-frequency display, which limits the usage scenarios.

[0038] Figure 3 Schematic diagram of the structure of the pixel driving circuit in the embodiment of the present application.

[0039] Please refer to Figure 3 In one embodiment, the pixel driving circuit further includes a first reset transistor T4, a second reset transistor T7, a first light emission control transistor T5, a second light emission control transistor T6, a first capacitor and a second capacitor.

[0040] One of the sources or drains of the first reset transistor T4 is electrically connected to one of the sources or drains of the isolation transistor, the other of the sources or drains of the first reset transistor T4 is electrically connected to a gate reset signal line, and the gate of the first reset transistor T4 is electrically connected to a first reset signal line. One of the sources or drains of the second reset transistor T7 is electrically connected to an anode of the light emitting element, the other of the sources or drains of the second reset transistor T7 is electrically connected to an anode reset signal line, and the gate of the second reset transistor T7 is electrically connected to a second reset signal line. One of the sources or drains of the first light emitting control transistor T5 is electrically connected to a first power supply signal line, the other of the sources or drains of the first light emitting control transistor T5 is electrically connected to one of the sources or drains of the driving transistor T1, and the gate of the first light emitting control transistor T5 is electrically connected to a light emitting signal line. One of the source or drain of the second light-emitting control transistor T6 is electrically connected to the other of the source or drain of the driving transistor T1, the other of the source or drain of the second light-emitting control transistor T6 is electrically connected to the anode of the light-emitting element, and the gate of the second light-emitting control transistor T6 is electrically connected to the light-emitting signal line. One end of the first capacitor is electrically connected to the first power line, and the other end of the first capacitor is electrically connected to the first node Q. One end of the second capacitor is electrically connected to the write signal line, and the other end of the second capacitor is electrically connected to the second node D.

[0041] The isolation module includes an isolation transistor, one of the source or drain of the isolation transistor is electrically connected to the compensation transistor T3, the other of the source or drain of the isolation transistor is electrically connected to the gate of the driving transistor T1, and the gate of the isolation transistor is electrically connected to the isolation signal line.

[0042] It should be noted that the first reset signal line provides a first reset signal Nscan1 (n-7), the second reset signal line provides a second reset signal Pscan2 (n), the gate reset signal line provides a gate reset signal Vi_Gate, the anode reset signal line provides an anode reset signal Vi_Ano, the light-emitting signal line provides a light-emitting signal EM, and the isolation signal line provides an isolation signal Control.

[0043] Figure 4 for Figure 3 A schematic diagram of the timing sequence of various signals of the pixel driving circuit.

[0044] Please refer to Figure 4 In each frame, the pixel driving circuit at least includes a first stage S1, a second stage S2, a third stage S3 and a fourth stage S4.

[0045] In the first stage S1 , the first reset transistor T4 is turned on, and the gate reset signal is written into the gate of the driving transistor T1 to reset the gate of the driving transistor T1 .

[0046] In the second stage S2, the write transistor T2 and the compensation transistor T3 are turned on, and the data signal is written into the gate of the drive transistor T1 through the write transistor T2 and the compensation transistor T3, and is stored in the first capacitor and the second capacitor.

[0047] In the third stage S3, the second reset transistor T7 is turned on, and the anode reset signal is written into the anode of the light emitting element to reset the anode of the light emitting element.

[0048] In the fourth stage S4, the first light emission control transistor T5 and the second light emission control transistor T6 are turned on, and the light emitting element starts to emit light.

[0049] It can be understood that by controlling the isolation transistor to be disconnected in the first stage, the gate reset signal can be prevented from resetting the gate of the driving transistor T1, and by controlling the isolation transistor to be disconnected in the second stage, the data signal can be prevented from being written to the gate of the driving transistor T1. Therefore, by controlling the isolation transistor, the pixel driving circuit can keep the data signal of the previous frame from continuing to emit light, thereby changing the refresh frequency of the pixel driving circuit. Therefore, when the isolation module that controls the pixel driving circuit of the corresponding area of ​​the display panel makes the corresponding pixel driving circuit refresh at different refresh rates, different areas of the display panel can be displayed at different frequencies.

[0050] In one embodiment, when the isolation transistor is disconnected, the voltage of the data signal is a constant value. It is understandable that when the isolation transistor is disconnected, the data signal will no longer be written into the gate of the driving transistor T1. Therefore, in order to reduce power consumption, the voltage of the data signal is kept unchanged. It is understandable that the voltage value of the data signal at this time can be set according to requirements, and this application does not limit it here.

[0051] In one embodiment, if Figure 7As shown, the pixel driving circuit further includes a third reset transistor T8, one of the source or drain of the third reset transistor T8 is electrically connected to one of the source or drain of the driving transistor T1, the other of the source or drain of the third reset transistor T8 is used to receive the third reset signal Vi_3, and the gate of the third reset transistor T8 is used to receive the second reset signal. It can be understood that under the control of the second reset signal, the third reset transistor T8 can reset one of the source or drain of the driving transistor T1.

[0052] Based on the pixel driving circuit provided in the above embodiment, an embodiment of the present application provides a display panel, and the display panel is composed of the above pixel driving circuit arranged in an array.

[0053] The display panel includes a first partition in a row direction ( Figure 7 The left partition in the middle) and the second partition ( Figure 7 The display panel further comprises a plurality of isolation signal lines, and the plurality of isolation signal lines are respectively connected to the isolation modules of the plurality of pixel driving circuits to transmit the plurality of isolation signals. The isolation signal lines are arranged in parallel with the data signal lines. The plurality of isolation signal lines comprise a first isolation signal line and a second isolation signal line. The first isolation signal line is used to transmit a first isolation signal, and the second isolation signal line is used to transmit a second isolation signal. The isolation module of the pixel driving circuit corresponding to the first partition receives the first isolation signal through the first isolation signal line, and the isolation module of the pixel driving circuit corresponding to the second partition receives the second isolation signal through the second isolation signal line.

[0054] It can be understood that since the pixel driving circuits located in the first partition all receive the first isolation signal through the first isolation signal line, and the pixel driving circuits located in the second partition all receive the second isolation signal through the second isolation signal line, the refresh rates of the first partition and the second partition can be different by controlling the pixel driving circuits in the corresponding areas to refresh at different refresh frequencies through the first isolation signal and the second isolation signal.

[0055] It can be understood that the isolation signal line in this embodiment is arranged in parallel with the data signal line to control the pixel driving circuit in the corresponding column direction, so that the present application can divide the row direction into multiple partitions with different refresh frequencies, that is, the present application can realize left and right frequency division display.

[0056] In one embodiment, the maximum refresh rate of the display panel is 120 Hz, that is, the display panel refreshes a maximum of 120 frames in 1 second, and each frame refresh takes 1 / 120=8.3 ms. Therefore, the display panel can have 120 subframes per second, and in each subframe, the write signal, the compensation signal, the first reset signal, and the second reset signal are all as follows: Figure 4 The timing shown is with valid levels.

[0057] like Figure 4 As shown, in any four adjacent subframes, the ratio of the number of subframes in which the first isolation signal is at a valid level to the number of subframes in which the first isolation signal is at a valid level is 1:4.

[0058] The first isolation signal has a valid level in the first subframe, and an invalid level in the second subframe, the third subframe, and the fourth subframe. Therefore, the isolation module of the pixel driving circuit corresponding to the first isolation signal is only turned on in the first subframe, so that the data signal is written to the gate of the driving transistor T1, and remains closed in the second subframe, the third subframe, and the fourth subframe, so that the first reset transistor T4 and the compensation transistor T3 cannot write signals to the gate of the driving transistor T1, and the gate of the driving transistor T1 maintains the data voltage written in the first subframe, so that the luminous state of the display panel from the second subframe to the fourth subframe will be the same as the luminous state of the first subframe. Therefore, in 120 subframes, the pixel driving circuit corresponding to the first isolation signal has one subframe for writing the data signal every four subframes, so that the refresh period of the pixel driving circuit corresponding to the first isolation signal is 8.3ms*4=33.3ms, that is, the corresponding refresh frequency of the first partition is 1 / 33.3ms=30Hz.

[0059] The second isolation signal is at a valid level in the first subframe to the fourth subframe. Therefore, the isolation module of the pixel driving circuit corresponding to the second isolation signal remains in an open state in the first subframe to the fourth subframe, so that the data signal is written into the gate of the driving transistor T1 in each subframe, so that the refresh period of the pixel driving circuit corresponding to the second isolation signal is 8.3ms, that is, the corresponding refresh frequency of the second partition is 1 / 8.3ms=120Hz.

[0060] It can be understood that the number of partitions of the above display panel and the refresh rates corresponding to the partitions are examples. According to the structure of the display panel of the present application, the display panel can be divided into multiple partitions parallel in the row direction, and the multiple partitions can be displayed at refresh rates including but not limited to the above embodiments. For example, the display panel may include four partitions, and the refresh rates of each partition are 15Hz, 30HZ, 60Hz and 120Hz respectively.

[0061] In one embodiment, a plurality of the first isolation signal lines are electrically connected to receive the first isolation signal, and a plurality of the second isolation signal lines are electrically connected to receive the same isolation signal. It can be understood that the above configuration can save output ports of the isolation signal output circuit.

[0062] In summary, although the present invention has been disclosed as above in terms of preferred embodiments, the above preferred embodiments are not intended to limit the present invention. A person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined in the claims.

Claims

1. A pixel driving circuit for driving a sub-pixel, characterized in that: include: a driving transistor configured to generate a driving current to drive the sub-pixel; a write transistor, wherein the write transistor writes a data signal to one of a source or a drain of the drive transistor under the control of a write signal; a compensation transistor configured to write a data signal into a gate of the driving transistor under the control of a compensation signal; an isolation module, wherein the isolation module is connected in series between the gate of the driving transistor and the compensation transistor; Wherein, the isolation module is configured to adjust the refresh frequency of the sub-pixel under the control of the isolation signal.

2. The pixel driving circuit according to claim 1, characterized in that: The isolation module includes an isolation transistor, one of the source or the drain of the isolation transistor is electrically connected to the compensation transistor, the other of the source or the drain of the isolation transistor is electrically connected to the gate of the driving transistor, and the gate of the isolation transistor is used to receive the isolation signal.

3. The pixel driving circuit according to claim 2, characterized in that: Under the control of the isolation signal, the isolation transistor adjusts the frequency at which the compensation transistor writes the data signal to the gate of the driving transistor, so as to adjust the refresh frequency of the sub-pixel.

4. The pixel driving circuit according to claim 2, characterized in that: When the isolation transistor is turned off, the voltage of the data signal is a constant value.

5. The pixel driving circuit according to claim 2, characterized in that: The pixel driving circuit also includes a first reset transistor, which is configured to reset the gate voltage of the driving transistor under the control of a first reset signal, one of the source or drain of the first reset transistor is electrically connected to one of the source or drain of the isolation transistor, and the other of the source or drain of the first reset transistor is used to receive a gate reset signal.

6. A display panel, characterized in that: The invention comprises a plurality of pixel driving circuits as described in any one of claims 1 to 5.

7. The image display panel according to claim 6, characterized in that: The display panel includes a first partition and a second partition in a row direction, and the plurality of isolation signals include a plurality of first isolation signals and a plurality of second isolation signals; The isolation module corresponding to the pixel driving circuit of the first partition receives the first isolation signal, and the isolation module corresponding to the pixel driving circuit of the second partition receives the second isolation signal.

8. The image display panel according to claim 6, characterized in that: When the isolation signal is at a valid level, the isolation module is turned on to enable the corresponding compensation transistor to write the data signal into the gate of the driving transistor; The display panel includes a plurality of subframes in a unit time, and among the plurality of subframes, the number of subframes in which the first isolation signal is at a valid level is less than the number of subframes in which the second isolation signal is at a valid level.

9. The image display panel according to claim 8, characterized in that: The ratio of the number of subframes in which the first isolation signal is at an effective level to the number of subframes in which the first isolation signal is at an effective level is 1:

4.

10. The image display panel according to claim 6, characterized in that: The display panel also includes multiple data signal lines and multiple isolation signal lines. The multiple isolation signal lines are respectively connected to the isolation modules of the multiple pixel driving circuits to transmit multiple isolation signals. The data signal lines are used to transmit the data signals. The isolation signal lines are arranged in parallel with the data signal lines.

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