Data writing method and device of quasi-two-end SOT device

Abstract

The invention provides a data writing method and device for a quasi-two-end SOT device, and the method comprises the steps: carrying out the erasing operation of a target device, and enabling all magnetic tunnel junctions of the target device to be in an initial state; and performing selective write operation on the target device for multiple times to change the state of the target magnetic tunnel junction of the target device so as to realize the write-in of target data. The device is used for executing the method. According to the data writing method and device of the quasi-two-end SOT device provided by the embodiment of the invention, the writing error rate of the selected magnetic tunnel junctions is reduced, the writing error rate of the unselected magnetic tunnel junctions is balanced, and the gating performance of the target device is improved through multiple selective writing operations.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a method and device for writing data into a quasi-two-terminal spin-orbit torque (SOT) device. Background Art

[0002] As a writing scheme for the third-generation magnetic random access memory (MRAM), spin-orbit torque has the advantages of high speed and high durability.

[0003] Integration density is another key issue that limits SOT-MRAM. The three-port structure means two-transistor control, which requires additional area redundancy. Quasi-two-terminal SOT devices are one of the important solutions to optimize the storage unit area of ​​SOT-MRAM. Quasi-two-terminal SOT devices form quasi-two terminals by sharing SOT channels, greatly reducing the number of transistors. In the quasi-two-terminal structure, quasi-two-terminal SOT devices usually require two-step operations to achieve multi-bit data writing, including erase operations and selective write operations. Among them, the selective write operation requires that the selected unit be reliably written, and the data of the unselected write unit is not disturbed, that is, the selectability of the quasi-two-terminal SOT device must meet the requirements. However, the current selectability of quasi-two-terminal SOT devices is far from meeting the application requirements of storage. Summary of the invention

[0004] In view of the problems in the prior art, an embodiment of the present invention provides a method and device for writing data into a quasi-two-terminal SOT device, which can at least partially solve the problems in the prior art.

[0005] In a first aspect, the present invention provides a method for writing data into a quasi-two-terminal SOT device, comprising:

[0006] Performing an erase operation on the target device so that all magnetic tunnel junctions (MTJs) of the target device become an initial state;

[0007] A plurality of selective write operations are performed on the target device so that the target magnetic tunnel junction of the target device changes state to achieve the writing of target data.

[0008] Furthermore, the parameters of each selective write operation in the multiple selective write operations are the same.

[0009] Furthermore, the write voltages corresponding to the multiple selective write operations are the same.

[0010] Furthermore, the multiple selective write operations are two selective write operations.

[0011] Further, the write voltage corresponding to the second selective write operation is different from the write voltage corresponding to the first selective write operation.

[0012] Furthermore, the data writing method of the quasi-two-terminal SOT device provided by the embodiment of the present invention further includes:

[0013] After the multiple selective write operations are completed, reading the storage data corresponding to the target device;

[0014] If it is determined that the storage data corresponding to the target device is inconsistent with the target data, obtaining the inconsistent data;

[0015] Based on the inconsistent data, multiple selective write operations are performed on the target device again until the storage data corresponding to the target device is consistent with the target data or the number of repeated writes reaches an upper limit.

[0016] On the other hand, the present invention provides a data writing device for a quasi-two-terminal SOT device, comprising:

[0017] An erasing module, used for performing an erasing operation on a target device to make all magnetic tunnel junctions of the target device become an initial state;

[0018] The writing module performs multiple selective writing operations on the target device to change the state of the target magnetic tunnel junction of the target device to achieve the writing of target data.

[0019] In a third aspect, the present invention provides a computer device, comprising a memory, a processor, and a computer program stored in the memory, wherein the processor executes the program to implement the data writing method of the quasi-two-terminal SOT device described in any of the above embodiments.

[0020] In a fourth aspect, the present invention provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program / instruction, and when the computer program / instruction is executed by a processor, the data writing method of the quasi-two-terminal SOT device described in any of the above embodiments is implemented.

[0021] In a fifth aspect, the present invention provides a computer program product, including a computer program / instruction, which, when executed by a processor, implements the data writing method for the quasi-two-terminal SOT device described in any of the above embodiments.

[0022] The data writing method and device for a quasi-two-terminal SOT device provided in an embodiment of the present invention can perform an erasing operation on a target device so that all magnetic tunnel junctions of the target device become an initial state; perform multiple selective write operations on the target device so that the target magnetic tunnel junctions of the target device change state to achieve the writing of target data, while reducing the write error rate of the selected magnetic tunnel junctions, balancing the write error rate of the unselected magnetic tunnel junctions, and improving the gating performance of the target device through multiple selective write operations. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the prior art descriptions. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings:

[0024] Figure 1 It is a schematic structural diagram of a quasi-two-terminal SOT device provided in the first embodiment of the present invention.

[0025] Figure 2 It is a schematic structural diagram of a quasi-two-terminal SOT device provided in the second embodiment of the present invention.

[0026] Figure 3 It is a flow chart of a method for writing data into a quasi-two-terminal SOT device provided in a third embodiment of the present invention.

[0027] Figure 4 It is a flow chart of a method for writing data into a quasi-two-terminal SOT device provided in a fourth embodiment of the present invention.

[0028] Figure 5 It is a structural schematic diagram of a data writing device for a quasi-two-terminal SOT device provided in a fifth embodiment of the present invention.

[0029] Figure 6 It is a structural schematic diagram of a data writing device for a quasi-two-terminal SOT device provided in a sixth embodiment of the present invention.

[0030] Figure 7 It is a schematic diagram of the physical structure of an electronic device provided by the seventh embodiment of the present invention. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical scheme and advantages of the embodiments of the present invention clearer, the embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings. Here, the illustrative embodiments of the present invention and their descriptions are used to explain the present invention, but are not intended to limit the present invention. It should be noted that, in the absence of conflict, the embodiments in this application and the features in the embodiments can be combined arbitrarily with each other. The acquisition, storage, use, and processing of data in the technical scheme in this application all comply with the relevant provisions of laws and regulations.

[0032] In order to facilitate understanding of the technical solution provided by this application, the relevant contents of the technical solution of this application are first explained below.

[0033] Conventional SOT-MTJ devices are three-terminal structures. An M-bit SOT-MTJ device requires M write transistors and M read transistors. The quasi-two-terminal SOT device in the embodiment of the present invention reduces the number of write transistors by sharing the write path. Figure 1 and Figure 2 Taking the structure as an example, an M-bit SOT-MTJ device requires 1 write transistor and M read transistors.

[0034] Figure 1 is a schematic diagram of the structure of a quasi-two-terminal SOT device provided in the first embodiment of the present invention, such as Figure 1 As shown, the quasi-two-terminal SOT device provided in the embodiment of the present invention includes a write transistor 101, a plurality of read transistors 102, a spin-orbit coupling layer 103, and a plurality of magnetic tunnel junctions 104 arranged on the spin-orbit coupling layer 103, wherein:

[0035] The write transistor 101 is connected to the spin-orbit coupling layer 103 for writing operations; each read transistor 102 is connected to a magnetic tunnel junction 104 for reading operations; each magnetic tunnel junction 104 includes a free layer A1, a barrier layer A2 and a fixed layer A3 arranged in sequence from bottom to top.

[0036] Figure 2 is a schematic diagram of the structure of a quasi-two-terminal SOT device provided by the second embodiment of the present invention, such as Figure 2 As shown, the quasi-two-terminal SOT device provided by the embodiment of the present invention includes a write transistor 201 and a plurality of parallel-connected storage units, wherein:

[0037] Each memory cell includes a read transistor 202 , a spin-orbit coupling layer 203 , and a magnetic tunnel junction 204 disposed on the spin-orbit coupling layer 203 ; the magnetic tunnel junction 204 includes a free layer A1 , a barrier layer A2 , and a fixed layer A3 disposed sequentially from bottom to top.

[0038] The write transistor 101 is connected to each spin-orbit coupling layer 203 for performing a write operation; each read transistor 202 is connected to a corresponding magnetic tunnel junction 204 for performing a read operation.

[0039] The data writing method of the quasi-two-terminal SOT device provided in the embodiment of the present invention is not only applicable to the above-mentioned 2-bit SOT-MTJ device, but also applicable to SOT-MTJ devices greater than 2 bits. The data writing method provided in the embodiment of the present invention is suitable for other structures sharing a write channel, and an M-bit SOT-MTJ device requires less than M write transistors and M read transistors. For another example, an M-bit SOT-MTJ device requires less than M write transistors and less than M read transistors.

[0040] In order to improve the gating performance of quasi-two-terminal SOT devices, the field has been looking for a material system that optimizes the voltage-controlled magnetic anisotropy (VCMA) coefficient from the perspective of material engineering to optimize the gating performance. The gating performance is insufficient under ordinary material systems. Unconventional systems have not yet formed an effective integration solution. In addition, as the write voltage increases, the downward trend of the write error rate gradually slows down, which deteriorates the threshold of the write error rate of the selected write unit and the interference rate of the unselected write unit.

[0041] The present invention optimizes the magnitude of gating by specially and innovatively designing a dedicated write strategy for a quasi-two-terminal SOT device, while reducing the WER of a selected MTJ and balancing the DER of an unselected MTJ, without the need to develop a special material system and a new integration solution, thereby solving the storage application problem of existing quasi-two-terminal SOT devices.

[0042] Figure 3 FIG. 1 is a flow chart of a method for writing data into a quasi-two-terminal SOT device according to a third embodiment of the present invention. Figure 3 As shown, the data writing method of the quasi-two-terminal SOT device provided by the embodiment of the present invention includes:

[0043] S301, performing an erase operation on a target device to make all magnetic tunnel junctions of the target device become an initial state;

[0044] Specifically, a SOT current is applied to the magnetic tunnel junction of the target device, and the SOT current brushes all the magnetic tunnel junctions of the target device into the same initial state. Wherein, during the erase operation, no voltage is applied to the top of the magnetic tunnel junction. The target device may be a multi-bit SOT device, a quasi-two-terminal SOT device with a shared bottom electrode, etc.

[0045] S302, performing multiple selective write operations on the target device to change the state of the target magnetic tunnel junction of the target device to achieve writing of target data.

[0046] Specifically, each selective write operation of the target device will select a magnetic tunnel junction that needs to be written with data, that is, a target magnetic tunnel junction, apply a SOT current of opposite polarity, and apply a VCMA voltage that reduces the potential barrier to change the initial state of the selected magnetic tunnel junction to promote data writing. For magnetic tunnel junctions that do not need to be written with data, that is, magnetic tunnel junctions that maintain the initial state, a protection operation can be performed to apply a VCMA voltage that increases the potential barrier to prevent the change of the initial state. Due to a single write, the gating of the target device is difficult to meet the requirements, so multiple selective write operations are used to achieve the selected magnetic tunnel junction can reliably write data, and the state of the unselected magnetic tunnel junction can remain unchanged, thereby improving the gating of the target device. Among them, the specific number of selective write operations is selected according to actual needs, such as 2 times, 3 times, 4 times, etc., and the embodiment of the present invention is not limited.

[0047] The data writing method for a quasi-two-terminal SOT device provided in an embodiment of the present invention performs an erasing operation on a target device so that all magnetic tunnel junctions of the target device become an initial state; performs multiple selective write operations on the target device so that the target magnetic tunnel junctions of the target device change state to achieve the writing of target data, while reducing the WER of the selected MTJ, balancing the DER of the unselected MTJ, and improving the gating property of the target device through multiple selective write operations.

[0048] On the basis of the above embodiments, further, the parameters of each selective write operation in the multiple selective write operations are the same, that is, each selective write operation is the same.

[0049] On the basis of the above embodiments, further, the write voltages corresponding to the multiple selective write operations are the same, that is, in each selective write operation, the write voltage applied to the magnetic tunnel junction where data needs to be written is the same, and the SOT currents of opposite polarities generated are the same.

[0050] On the basis of the above embodiments, further, the multiple selective write operations are two selective write operations: a first selective write operation and a second selective write operation.

[0051] The WER (Write Error Rate) curve reflects the write error rate of the selected magnetic tunnel junction. After two selective write operations, WER2 = WER1xWER1. WER2 represents the write error rate of the magnetic tunnel junction after two selective write operations, and WER1 represents the write error rate of the magnetic tunnel junction after one selective write operation. If WER1 = 10 -3 , then theoretically WER2=(WER1) 2 =10 -6, achieving a doubling of the magnitude. The DER (Disturb Error Rate) curve reflects the error write rate of the unselected magnetic tunnel junction. After two selective write operations, DER2 = DER1 + DER1 + (DER1) 2 DER2 represents the error write rate of the magnetic tunnel junction after two selective write operations, and DER1 represents the error write rate of the magnetic tunnel junction after one selective write operation. When DER1 is small, DER2 is approximately twice DER1. DER2 does not double in magnitude. Therefore, through two selective write operations, the selectivity will be significantly optimized. The final optimization result of the selectivity is subject to actual testing and is not limited in the embodiments of the present invention.

[0052] On the basis of the above embodiments, further, the write voltage corresponding to the second selective write operation is different from the write voltage corresponding to the first selective write operation.

[0053] The write voltage may include an SOT voltage and a VCMA voltage. The write voltage corresponding to the second selective write operation is different from the write voltage corresponding to the first selective write operation, and the SOT voltage included in the write voltage corresponding to the second selective write operation may be different from the SOT voltage included in the write voltage corresponding to the first selective write operation, the VCMA voltage included in the write voltage corresponding to the second selective write operation may be different from the VCMA voltage included in the write voltage corresponding to the first selective write operation, or the SOT voltage and VCMA voltage included in the write voltage corresponding to the second selective write operation may be different from the SOT voltage and VCMA voltage included in the write voltage corresponding to the first selective write operation.

[0054] The SOT voltage and VCMA voltage included in the write voltage corresponding to each selective write operation may not be synchronized in timing, and the amplitudes of the SOT voltage and VCMA voltage may be different. The SOT voltage and VCMA voltage included in the write voltage corresponding to the selective write operation may also have other situations, which are not specifically limited in the present invention.

[0055] In the second selective write operation, by increasing the amplitude of the VCMA voltage, the WER and DER of the second selective write operation can be reduced, thereby improving the data write success rate. Based on the above embodiments, further, the write voltage corresponding to the second selective write operation is less than the write voltage corresponding to the first selective write operation. When the gating performance of the target device can meet the requirements, reducing the write voltage corresponding to the second selective write operation is conducive to improving the service life of the target device.

[0056] Figure 4 FIG. 4 is a flow chart of a method for writing data into a quasi-two-terminal SOT device according to a fourth embodiment of the present invention. Figure 4As shown, based on the above embodiments, further, the data writing method of the quasi-two-terminal SOT device provided by the embodiment of the present invention also includes:

[0057] S401, after the multiple selective write operations are completed, reading the storage data corresponding to the target device;

[0058] Specifically, after the multiple selective write operations are completed, the storage data corresponding to the target device may be read.

[0059] S402: if it is determined that the storage data corresponding to the target device is inconsistent with the target data, obtaining inconsistent data;

[0060] Specifically, the storage data corresponding to the target device is compared with the target data. If the storage data corresponding to the target device is inconsistent with the target data, it means that the data is wrong, that is, there is a situation where the selected magnetic tunnel junction has not been written with data or the initial state of the unselected magnetic tunnel junction has changed. Then, inconsistent data is obtained, that is, data in the storage data that is different from the target data.

[0061] S403: re-perform multiple selective write operations on the target device based on the inconsistent data until the storage data corresponding to the target device is consistent with the target data or the number of repeated writes reaches an upper limit.

[0062] Specifically, according to the inconsistent data, the target device is re-selected for multiple write operations to make the storage data corresponding to the target device consistent with the target data. If the number of repetitions of the multiple selective write operations on the target device reaches an upper limit, the repeated writing will also be stopped. After the number of repeated writing reaches the upper limit, the inconsistent data that exists can be recorded and reported.

[0063] By checking the storage data corresponding to the target device and rewriting the inconsistent data, the reliability of data writing to the target device is further improved.

[0064] On the basis of the above embodiments, further, the data writing method of the quasi-two-terminal SOT device provided by the embodiment of the present invention further includes:

[0065] A write count of a selective write operation is received, and a selective write operation is performed on the target device according to the write count.

[0066] Specifically, in different application scenarios, the requirements for selectivity are different. The number of write times of the selective write operation can be set according to the needs of the actual application scenario to meet the selectivity requirements in different application scenarios. Before writing data to the target device, the number of write times of the selective write operation can be set, and the selective write operation can be performed on the target device according to the number of write times.

[0067] For example, if the number of write times is set to 1, then the target device will be selectively written once. If the number of write times is set to 2, then the target device will be selectively written twice. If the number of write times is set to 3, then the target device will be selectively written three times. And so on.

[0068] On the basis of the above embodiments, further, the data writing method of the quasi-two-terminal SOT device provided by the embodiment of the present invention further includes:

[0069] The duration of each selective write operation is obtained according to the total write operation time and the number of writes of the selective write operation.

[0070] When the number of writes of the selective write operation is greater than or equal to 2, there is a delay time between adjacent selective write operations. The duration of each selective write operation and the delay time between adjacent selective write operations are set according to actual needs and are not limited in the embodiment of the present invention.

[0071] For example, the total write operation time is 100ns. When the number of writes of the selective write operation is set to 1, there is only one write pulse, and the duration of the selective write operation can be 100ns. When the number of writes of the selective write operation is set to 2, each selective write operation corresponds to a write pulse, there are 2 write pulses, and there is a delay time between the two selective write operations. For example, the first write pulse and the second write pulse are 40ns, and the delay time between the two selective write operations is 20ns. When the number of writes is set to 3, there are 3 write pulses. For example, the first write pulse, the second write pulse and the second write pulse are all 20ns, the delay time between the first write pulse and the second write pulse is 20ns, and the delay time between the second write pulse and the third write pulse is 20ns. For example, the first write pulse, the second write pulse and the second write pulse are all 25ns, the delay time between the first write pulse and the second write pulse is 15ns, and the delay time between the second write pulse and the third write pulse is 10ns.

[0072] Figure 5 FIG. 5 is a schematic diagram of a data writing device for a quasi-two-terminal SOT device according to a fifth embodiment of the present invention. Figure 5As shown, the data writing device of the quasi-two-terminal SOT device provided in the embodiment of the present invention includes an erasing module 501 and a writing module 502, wherein:

[0073] The erase module 501 is used to perform an erase operation on the target device to change all magnetic tunnel junctions of the target device to an initial state; the write module 502 performs multiple selective write operations on the target device to change the state of the target magnetic tunnel junction of the target device to achieve the writing of target data.

[0074] Specifically, the erasing module 501 applies a SOT current to the magnetic tunnel junction of the target device, and the SOT current brushes all the magnetic tunnel junctions of the target device into the same initial state. Wherein, during the erasing operation, no voltage is applied to the top of the magnetic tunnel junction. The target device can be a multi-bit SOT device, a quasi-two-terminal SOT device with a shared bottom electrode, etc.

[0075] For each selective write operation of the target device, the write module 502 will select the magnetic tunnel junction that needs to be written with data, that is, the target magnetic tunnel junction, apply a SOT current of opposite polarity, and apply a VCMA voltage that reduces the potential barrier to change the initial state of the selected magnetic tunnel junction to promote data writing. For the magnetic tunnel junction that does not need to be written with data, that is, the magnetic tunnel junction that maintains the initial state, a protection operation can be performed, and a VCMA voltage that increases the potential barrier is applied to prevent the change of the initial state. Due to a single write, the gating property of the target device is difficult to meet the requirements, so multiple selective write operations are used to achieve the selected magnetic tunnel junction can reliably write data, and the state of the unselected magnetic tunnel junction can remain unchanged, thereby improving the gating property of the target device. Among them, the specific number of selective write operations is selected according to actual needs, such as 2 times, 3 times, 4 times, etc., and the embodiment of the present invention is not limited.

[0076] The data writing device for a quasi-two-terminal SOT device provided in an embodiment of the present invention performs an erasing operation on a target device so that all magnetic tunnel junctions of the target device become an initial state; performs multiple selective writing operations on the target device so that the target magnetic tunnel junctions of the target device change state to achieve the writing of target data, and improves the gating property of the target device through multiple selective writing operations.

[0077] On the basis of the above embodiments, further, the parameters of each selective write operation in the multiple selective write operations are the same.

[0078] On the basis of the above embodiments, further, the write voltages corresponding to the multiple selective write operations are the same.

[0079] On the basis of the above embodiments, further, the multiple selective write operations are two selective write operations.

[0080] On the basis of the above embodiments, further, the write voltage corresponding to the second selective write operation is different from the write voltage corresponding to the first selective write operation.

[0081] On the basis of the above embodiments, further, the write voltage corresponding to the second selective write operation is smaller than the write voltage corresponding to the first selective write operation.

[0082] Figure 6 is a structural schematic diagram of a data writing device for a quasi-two-terminal SOT device provided in a sixth embodiment of the present invention, such as Figure 6 As shown, based on the above embodiments, further, the data writing device for the quasi-two-terminal SOT device provided in the embodiment of the present invention further includes a reading module 503, an acquisition module 504 and a re-writing module 505, wherein:

[0083] The reading module 503 is used to read the storage data corresponding to the target device after the multiple selective write operations are completed; the acquisition module 504 is used to obtain the inconsistent data if it is determined that the storage data corresponding to the target device is inconsistent with the target data; the re-writing module 505 is used to re-perform multiple selective write operations on the target device based on the inconsistent data until the storage data corresponding to the target device is consistent with the target data or the number of repeated writes reaches an upper limit.

[0084] The embodiments of the apparatus provided in the embodiments of the present invention can be specifically used to execute the processing flow of the above-mentioned method embodiments, and its functions are not described in detail here, and reference can be made to the detailed description of the above-mentioned method embodiments.

[0085] The data writing method for the quasi-two-terminal SOT device provided in the embodiment of the present invention has no limitation on the type of magnetic tunnel junction, for example, a perpendicular magnetic anisotropic device, an in-plane anisotropic device, etc.

[0086] The selection of the reading circuit of the quasi-two-terminal SOT device can cover solutions such as resistance comparator, current comparator, voltage comparator, etc.; it can also include a selector with multiple inputs.

[0087] In the write circuit of the storage function of the quasi-two-terminal SOT device, multiple groups of write square wave pulses with different amplitudes can be used, and triangular waves, periodic pulses, irregular pulses, step pulses, etc. can be used.

[0088] The quasi-two-terminal SOT device may include additional circuit modules, such as an ECC correction module.

[0089] The bottom electrode of the quasi-two-terminal SOT device may be a strip type, a cross type, a Y-branch type, or a 6P or 8P electrode type, which is not specifically limited in the present invention.

[0090] The quasi-two-terminal SOT device allows different bottom electrode widths at different MTJ locations; allows different MTJs to have different sizes; allows different MTJs to have different spacings; and allows multiple MTJs to be placed on the same heavy metal.

[0091] Quasi-two-terminal SOT devices allow actual connections to be made through bottom-side vias / top-side vias of the SOT channel.

[0092] Depending on the material of the underlying spin-orbit coupling layer, the sign of the spin Hall angle is different, and the polarization direction of the resulting spin current is also different. It is preferred to use metals with negative spin Hall angles such as W, while for metals such as Pt, the spin Hall angle is positive. The different signs of the spin Hall angles mean that the directions of the applied current are opposite.

[0093] In an optional embodiment, the external magnetic field in the quasi-two-terminal SOT device can be realized in a variety of ways. Specifically, the external magnetic field can be formed by at least one of the following ways:

[0094] The quasi-two-terminal SOT device includes a magnetic field generating device that provides the external magnetic field or is equivalent to the external magnetic field;

[0095] The magnetic tunnel junction may include a fixed layer A3, a barrier layer A2 and a free layer A1 arranged in sequence from top to bottom, and at least one of the fixed layer A3, the barrier layer A2 and the free layer A1 has a trapezoidal cross section for providing the external magnetic field;

[0096] The material of the spin-orbit coupling layer is an antiferromagnetic material, and the spin-orbit coupling layer and the free layer A1 form an exchange bias field for providing the external magnetic field;

[0097] The magnetic tunnel junction includes a magnetic material layer (such as a Co layer) for providing the external magnetic field;

[0098] The magnetic tunnel junction has a shape capable of forming a shape anisotropic field (non-uniform demagnetization field) for providing the external magnetic field. In some embodiments, the magnetic tunnel junction can be in the shape of a rectangle, an ellipse, an isosceles right angle, etc. Taking the ellipse as an example, the demagnetization field in the long axis direction is weaker than that in the short axis direction, and the demagnetization field can be equivalent to the external magnetic field;

[0099] The free layer A1 has a gradient perpendicular magnetic anisotropy, which is used to provide an equivalent magnetic field of the external magnetic field. Specifically, when making a magnetic tunnel junction, the concentration of the target material can be adjusted so that the free layer A1 has a gradient perpendicular magnetic anisotropy, further destroying the symmetry of the magnetic moment distribution, which can be used to provide an equivalent external magnetic field. At this time, the free layer A1 can still be affected by interface interactions such as the DMI effect and other external magnetic fields.

[0100] It should be noted that the magnetic field generating device or equivalent device that can form an external magnetic field is a conventional technical means in the art, and those skilled in the art can flexibly set it according to needs, which will not be repeated here. In addition, the external magnetic field can also be provided by making the cross section of at least one of the fixed layer A3, the barrier layer A2 and the free layer A1 trapezoidal, using antiferromagnetic materials to form an exchange bias field with the free layer A1, and setting a magnetic material layer. In practical applications, the external magnetic field can also be formed by other feasible methods, and the present invention is not limited to this.

[0101] In an optional embodiment, the quasi-two-terminal SOT device includes a read circuit and a peripheral conversion circuit (encoding, MUX, decoder, etc.).

[0102] In alternative embodiments, the magnetic tunnel junction may include multiple free layers, barrier layers, insertion layers, and the like.

[0103] In an optional embodiment, the available shapes of the magnetic tunnel junction include but are not limited to ellipses, isosceles triangles, rectangles, rhombuses and the like. In addition to ellipses, rectangles, triangles and the like also have the same effect. Tilted semicircles, isosceles triangles and the like that do not have x / y axis symmetry after tilting are also within the scope of protection. Here, various symmetrical structures based on these shapes are within the scope of protection of this patent.

[0104] The SOT channel can be above the MTJ, that is, from top to bottom are the SOT channel, free layer, barrier layer, reference layer, and pinning layer. It can be set up in the form of two MTJs above and below the SOT.

[0105] For perpendicular magnetic anisotropy devices, or when the SOT current direction is parallel to the long axis of the in-plane magnetic anisotropy device, additional factors are required to cooperate with the SOT current, including but not limited to: ① an external magnetic field in the same direction as the SOT ② the ferromagnetic layer or barrier layer of the magnetic tunnel junction is made into a trapezoidal structure ③ when making a magnetic tunnel junction, the concentration of the target material can be adjusted so that the free layer has a gradient of perpendicular magnetic anisotropy, further destroying the symmetry of the magnetic moment distribution ④ by using magnetic materials such as the built-in Co layer to achieve the equivalent effect of the external magnetic field ④ the strong spin coupling layer can use antiferromagnetic materials to form an exchange bias field to replace the use of the external magnetic field, etc.

[0106] In a preferred embodiment, the magnetic tunnel junction includes a fixed layer A3, a barrier layer A2 and a free layer A1 arranged in sequence from top to bottom. The bottom surface of the free layer A1 is fixedly connected to the spin-orbit coupling layer. It can be understood that the resistance of the magnetic tunnel junction depends on the magnetization direction of the fixed layer A3 and the free layer A1, and the magnetization direction of the free layer A1 and the fixed layer A3 is determined by the direction of the magnetic moment. Among them, when the magnetic moment directions of the fixed layer A3 and the free layer A1 are the same, the magnetic tunnel junction is in a low resistance state (low resistance state), and when the magnetic moment directions of the fixed layer A3 and the free layer A1 are opposite, the magnetic tunnel junction is in a high resistance state (high resistance state). The high resistance state and low resistance state of the magnetic tunnel junction can be pre-set to correspond to different data, for example, the high resistance state is pre-set to correspond to data "1", and the low resistance state is pre-set to correspond to data "0", and then a current or voltage is input to the magnetic tunnel junction through a reading circuit, and the resistance state of the magnetic tunnel junction can be determined to be a high resistance state or a low resistance state according to the change of the current or voltage, and the data stored in the magnetic tunnel junction can be determined to be "1" or "0" according to the resistance state of the magnetic tunnel junction. Among them, the range of the high resistance state and the low resistance state is determined by a common technical means in the field, and those skilled in the art can determine the resistance value range of the high resistance state and the low resistance state of the magnetic tunnel junction according to common knowledge, and the present invention will not be repeated here.

[0107] The magnetic tunnel junction may also include at least one of the layer structures such as an insertion layer, a pinning layer, a seed layer and a capping layer. Among them, the arrangement of each layer structure may be arranged as one or more layers according to actual needs, and those skilled in the art may arrange the arrangement order of each layer structure of the magnetic tunnel junction from top to bottom according to needs, and the present invention is not limited to this.

[0108] Optionally, the shape of the magnetic tunnel junction on the spin-orbit coupling layer can be any one of a cube, a cylinder, a cube or an elliptical cylinder. The bottom surface shape of at least one magnetic tunnel junction arranged on the spin-orbit coupling layer, that is, the lower surface of the free layer A1 is coupled to the spin-orbit coupling layer.

[0109] Preferably, the spin-orbit coupling layer can be rectangular, so that the top surface area of ​​the spin-orbit coupling layer is larger than the area occupied by at least one magnetic tunnel junction arranged on the spin-orbit coupling layer, that is, at least one magnetic tunnel junction can be arranged on the spin-orbit coupling layer, and the outer edge of at least one magnetic tunnel junction is located on the inner side of the outer edge of the spin-orbit coupling layer. Wherein, the spin-orbit coupling layer can be preferably selected from heavy metal strip films or antiferromagnetic strip films.

[0110] It should be noted that the number of magnetic tunnel junctions on the spin-orbit coupling layer can be one or more. Preferably, multiple magnetic tunnel junctions can be arranged on the same spin-orbit coupling layer, so that a one-time data writing operation can be implemented for multiple magnetic tunnel junctions, which can reduce the number of control transistors for inputting the first current or the second current, thereby improving integration and reducing circuit power consumption.

[0111] In a preferred embodiment, when the magnetic random access memory unit inputs current to the spin-orbit coupling layer and the magnetic tunnel junction, the current can be input by setting electrodes on the spin-orbit coupling layer and the magnetic tunnel junction, for example, setting a top electrode on the top of the magnetic tunnel junction, and setting an input electrode and an output electrode on opposite sides of the spin-orbit coupling layer. Preferably, the material of the electrode can be any one of tantalum Ta, aluminum Al, gold Au or copper Cu.

[0112] Preferably, the material of the free layer A1 and the fixed layer A3 may be a ferromagnetic metal, and the material of the barrier layer A2 may be an oxide. The magnetic tunnel junction has a perpendicular magnetic anisotropy, which means that the magnetization direction of the free layer A1 and the fixed layer A3 forming the magnetic tunnel junction is in the perpendicular direction. Among them, the ferromagnetic metal may be a mixed metal material formed by at least one of cobalt iron CoFe, cobalt iron boron CoFeB or nickel iron NiFe, and the proportion of the mixed metal materials may be the same or different. The oxide may be one of oxides such as magnesium oxide MgO or aluminum oxide Al2O3, which is used to produce a tunneling magnetoresistance effect. In practical applications, ferromagnetic metals and oxides may also use other feasible materials, and the present invention is not limited to this.

[0113] The free layer A1 of the magnetic tunnel junction is in contact and fixed with the spin-orbit coupling layer. The layers of the magnetic tunnel junction and the spin-orbit coupling layer can be plated on the substrate in sequence from bottom to top by conventional methods such as ion beam epitaxy, atomic layer deposition or magnetron sputtering, and then multiple magnetic tunnel junctions can be prepared by conventional nanodevice processing techniques such as photolithography and etching.

[0114] In a preferred embodiment, the spin-orbit coupling layer is a spin-orbit coupling layer composed of a heavy metal film, an antiferromagnetic film or other materials. The heavy metal film or the antiferromagnetic film can be made into a rectangular shape, and its top area is preferably larger than the bottom area of ​​the outline formed by all magnetic tunnel junctions, so that one or more magnetic tunnel junctions can be set, and the bottom surface shape of the magnetic tunnel junction is completely embedded in the top surface shape of the heavy metal film or the antiferromagnetic film. Preferably, the material of the spin-orbit coupling layer can be selected from one of platinum Pt, tantalum Ta or tungsten W. In practical applications, the spin-orbit coupling layer can also be formed using other feasible materials, and the present invention is not limited to this.

[0115] In this embodiment, the magnetic tunnel junction includes a fixed layer A3 at the top, a free layer A1 in contact with the spin-orbit coupling layer, and a barrier layer A2 disposed between the fixed layer A3 and the free layer A1. The magnetic tunnel junction is a three-layer structure and includes only one free layer A1. In other embodiments, the free layer A1 may be provided as a plurality, that is, more than two layers of free layers A1. Then the magnetic tunnel junction includes a fixed layer A3 at the top, a plurality of free layers A1, and a barrier layer A2 disposed between each two adjacent layers, and the bottom free layer A1 is disposed in contact with the spin-orbit coupling layer. For example, in a specific example, when two free layers A1 are included, the magnetic storage unit structure may include a spin-orbit coupling layer, a first free layer A1 disposed sequentially on the spin-orbit coupling layer, a barrier layer A2, a second free layer A1, a barrier layer A2, and a fixed layer A3.

[0116] The devices, modules or units described in the above embodiments may be implemented by computer chips or entities, or by products with certain functions. A typical implementation device is an electronic device, and the electronic device may be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or a combination of any of these devices.

[0117] In a typical example, the electronic device specifically includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, the steps of the data writing method for the quasi-two-terminal SOT device are implemented.

[0118] Reference below Figure 7 , which shows a schematic diagram of the physical structure of an electronic device 600 suitable for implementing an embodiment of the present application.

[0119] like Figure 7 As shown, the electronic device 600 includes a central processing unit (CPU) 601, which can perform various appropriate operations and processes according to a program stored in a read-only memory (ROM) 602 or a program loaded from a storage portion 608 into a random access memory (RAM) 603. In the RAM 603, various programs and data required for the operation of the electronic device 600 are also stored. The CPU 601, the ROM 602, and the RAM 603 are connected to each other via a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0120] The following components are connected to the I / O interface 605: an input section 606 including a keyboard, a mouse, etc.; an output section 607 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage section 608 including a hard disk, etc.; and a communication section 609 including a network interface card such as a LAN card, a modem, etc. The communication section 609 performs communication processing via a network such as the Internet. A drive 610 is also connected to the I / O interface 605 as needed. A removable medium 611, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 610 as needed, so that a computer program read therefrom is installed as needed as the storage section 608.

[0121] In particular, according to an embodiment of the present invention, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present invention provides a computer-readable storage medium having a computer program stored thereon, which implements the steps of the data writing method of the quasi-two-terminal SOT device when executed by a processor.

[0122] For example, an embodiment of the present invention provides a computer program product, which includes a computer program stored on a non-transitory computer-readable storage medium, and the computer program includes program instructions. When the program instructions are executed by a computer, the computer can execute the steps of the data writing method of the above-mentioned quasi-two-terminal SOT device.

[0123] In such an embodiment, the computer program may be downloaded and installed from a network via the communication section 609 , and / or installed from the removable medium 611 .

[0124] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0125] For the convenience of description, the above device is described in various units according to their functions. Of course, when implementing the present application, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0126] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0127] These computer program instructions may also be stored in a computer readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0128] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process in the computer or other programmable device. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0129] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0130] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0131] The present application may be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. The present application may also be practiced in distributed computing environments where tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules may be located in local and remote computer storage media, including storage devices.

[0132] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0133] The above is only an embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included in the scope of the claims of the present application.

Claims

1. A method for writing data into a quasi-two-terminal SOT device, characterized in that: include: Performing an erasing operation on a target device so that all magnetic tunnel junctions of the target device become an initial state; A plurality of selective write operations are performed on the target device so that the target magnetic tunnel junction of the target device changes state to achieve the writing of target data.

2. The method according to claim 1, characterized in that The parameters of each selective writing operation in the multiple selective writing operations are the same.

3. The method according to claim 1, characterized in that The write voltages corresponding to the multiple selective write operations are the same.

4. The method according to claim 1, characterized in that: The multiple selective write operations are two selective write operations.

5. The method according to claim 4, characterized in that The write voltage corresponding to the second selective write operation is different from the write voltage corresponding to the first selective write operation.

6. The method according to any one of claims 1 to 5, characterized in that: Also includes: After the multiple selective write operations are completed, reading the storage data corresponding to the target device; If it is determined that the storage data corresponding to the target device is inconsistent with the target data, obtaining the inconsistent data; Based on the inconsistent data, multiple selective write operations are performed on the target device again until the storage data corresponding to the target device is consistent with the target data or the number of repeated writes reaches an upper limit.

7. A data writing device for a quasi-two-terminal SOT device, characterized in that: include: An erasing module, used for performing an erasing operation on a target device to make all magnetic tunnel junctions of the target device become an initial state; The writing module performs multiple selective writing operations on the target device to change the state of the target magnetic tunnel junction of the target device to achieve the writing of target data.

8. A computer device comprising a memory, a processor and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the steps of the method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program / instruction, which implements the steps of the method according to any one of claims 1 to 6 when executed by a processor.

10. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instructions are executed by a processor, the steps of the method according to any one of claims 1 to 6 are implemented.

Images