61 results about "Magnetic tunnelling" patented technology

The invention provides a semiconductor structure, which comprises a plurality of magnetic tunnel junction (MTJ) elements. Seen from a top view, the MTJ elements are arranged in an array, at least one second contact structure is located in the array arranged by the MTJ elements, and at least one first mask layer covers a top surface and two sidewalls of each MTJ element, when seen from a cross-sectional view, a sidewall of the first mask layer is aligned with a sidewall of a second metal layer which is disposed below the second contact structure.

A semiconductor device includes a first substrate, a transistor, an interconnection structure, a first bonding pad, a magnetic tunnel junction (MTJ) structure, a conductive line and a second substrate. The transistor is formed on the first substrate. The interconnection structure is formed on the first substrate and electrically connected to the transistor. The first bonding pad is formed on and electrically connected to the interconnection structure. The MTJ structure is disposed on and electrically connected to the first bonding pad, wherein the MTJ structure comprises a free layer, a tunnel barrier layer, a synthetic antiferromagnet layer sequentially stacked up over the first bonding pad. The conductive line is disposed on the MTJ structure. The second substrate is disposed on the conductive line.

Provided are a reconfigurable neuron device based on ion gate regulation and a method of preparing the same. The device includes: a synthetic antiferromagnetic layer, a metal oxide layer, an ionic liquid layer and a top electrode layer which are sequentially stacked from bottom to top. A left boundary antiferromagnetic layer and a right boundary antiferromagnetic layer having opposite magnetization directions are provided on two opposite edges of a bottom end of the synthetic antiferromagnetic layer, and a magnetic tunnel junction configured to output a spike signal is further provided in a middle portion of the bottom end of the synthetic antiferromagnetic layer. The metal oxide layer, the ionic liquid layer and the top electrode layer constitute an ion gate, the ionic liquid layer includes a positive ion and a negative ion.

A memory device and a manufacturing method thereof are provided. The memory device includes a magnetic tunneling junction (MTJ) and a spin Hall electrode (SHE). The MTJ includes a free layer, a reference layer and a barrier layer lying between the free layer and the reference layer. The SHE is in contact with the MTJ, and configured to convert a charge current to a spin current for programming the MTJ. The SHE is formed of an alloy comprising at least one heavy metal element and at least one light transition metal element. The heavy metal element is selected from metal elements with one or more valence electrons filling in 5d orbitals, and the light transition metal element is selected from transition metal elements with one or more valence electrons partially filling in 3d orbitals.

A method for fabricating semiconductor device includes first forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate, performing an atomic layer deposition (ALD) process or a high-density plasma (HDP) process to form a passivation layer on the first MTJ and the second MTJ, performing an etching process to remove the passivation layer adjacent to the first MTJ and the second MTJ, and then forming an ultra low-k (ULK) dielectric layer on the passivation layer.

A semiconductor device includes an inter-metal dielectric (IMD) layer on a substrate, a metal interconnection in the IMD layer, a bottom electrode on the metal interconnection, and a magnetic tunneling junction (MTJ) on the metal interconnection, in which a sidewall of the MTJ comprises a first slope and a second slope. Preferably, the MTJ further includes a pinned layer on the bottom electrode, in which a first angle included by a bottom surface of the bottom electrode and the sidewall of the MTJ is equal to a second angle included by a bottom surface of the pinned layer and the sidewall of the MTJ.

A spintronic device and an in-memory computing apparatus. The spintronic device comprises: a substrate; and a complex oxide layer and a magnetic tunnel junction structure, which are sequentially formed from bottom to top on the substrate, wherein there is a two-dimensional electron gas region at an interface of the complex oxide layer, and when a read / write voltage is applied to the spintronic device, a spin current generated by the magnetic tunnel junction structure tunnels into the two-dimensional electron gas region at the interface of the complex oxide layer, so as to change the density of a two-dimensional electron gas, such that the magnetic tunnel junction structure completes the reading or writing of data. Therefore, the effect of improving the reading reliability of the device is achieved.

Magnetic storage (100, 100', 100'', 100''', 200, 200', 250, 300, 300', 300'', 300''', 300'''', 300''''), comprising the following: a plurality of magnetic contacts (110, 110', 110'', 110''', 210, 260, 310, 310', 310'', 310''', 310''''), wherein each of the plurality of magnetic contacts (110, 110', 110'', 110''', 210, 260, 310, 310', 310'', 310''', 310''') has a data storage layer (112, 112', 112'', 112''', 212, 212''') wherein the data storage layer (112, 112', 112'', 112''', 212) is magnetic; and at least one active spin-orbit coupling layer, active SO layer (120, 120', 120'', 120''', 220, 270, 320, 320', 320', 320'', 320''''), adjacent to the data storage layer (112, 112', 112'', 112''', 212,) of the magnetic contact (110, 110', 110'', 110''', 210, 260, 310, 310', 310'', 310''', 310'''), wherein the at least one active SO layer (120, 120', 120'', 120''', 220, 270, 320, 320', 320'', 320''', 320'''') is configured so that it exerts an SO torque on the data storage layer (112, 112', 112'', 112''', 212) due to a current,which is connected by the at least one active SO layer (120, 120', 120'', 120''', 220, 270, 320, 320', 320''', 320'''', 320'''') in a direction substantially perpendicular to a direction between the at least one active SO layer (120, 120', 120'', 120''', 220, 270, 320, 320', 320'', 320''', 320'''') and the data storage layer (112, 112', 112'', 112''', 212,) of a magnetic contact (110, 110', 110'', 110''', 210, 260, 310, 310', 310'', 310'''', 310'''') of the majority of magnetic contacts (110, 110', 110'', 110'''', 210, 260, 310, 310', 310'', 310''', 310''') nearest to the at least one active SO layer (120, 120', 120'', 120''', 220, 270, 320, 320', 320'', 320''', 320''''); Without the current, at least one active SO layer (120, 120', 120", 120"', 220, 270, 320, 320', 320", 320"', 320"") is also configured to exert no SO torque on the data storage layer (112, 112', 112", 112"', 212), where the data storage layer (112,112', 112", 112"', 212) is configured so that it can be switched using at least the SO torque, , wherein at least one active SO layer (120, 120', 120", 120"', 220, 270, 320, 320', 320", 320"', 320"") extends over at least two of the plurality of magnetic contacts (110, 110', 110", 110"', 210, 260, 310, 310', 310", 310"', 310"").

Semiconductor device with: a pair of transistors (110, 120) on a semiconductor substrate (102); an interconnect structure across the pair of transistors (110, 120), wherein the interconnect structure has the following: Metal leads (182, 184) and metal vias (160, 210) arranged above and connected to the pair of transistors (110, 120), and a composite spin-Hall electrode (340, 530) over the metal conductors (182, 184) and metal vias (160, 210), wherein the composite spin-Hall electrode is electrically connected to the pair of transistors (110, 120) via the metal conductors and metal vias and has a first metal layer (342, 348, 531, 535, 539), a second metal layer (342, 348, 535, 535, 539) and a first spacer layer (344, 532, 536) between the first and the second metal layer, wherein the first metal layer contains a heavy metal in a first mixture of a stable and a metastable state of the heavy metal, the second metal layer contains the heavy metal in a second mixture of the stable and the metastable state of the heavy metal, and the first spacer layer contains a first material that is the first metal layer differs; and a magnetic tunnel contact (270) over the composite spin Hall electrode (340, 530); wherein the first spacer layer (344, 532, 536) comprises a crystalline metal or a crystalline metal oxide; and wherein the first spacer layer (344, 532, 536) further comprises an amorphous ferromagnetic material.

The invention relates to a probabilistic bit (p-bit) generator (D1) comprising: - a magnetic tunnel junction (MTJ) having a resistance that fluctuates between at least two distinct resistive states (P, AP) according to its magnetization; - a biasing circuit (POL) configured to inject a control current (Ic) through the magnetic tunnel junction, which varies according to a first input voltage (Vin1); the biasing circuit (POL) comprising: ∘ a control transistor (T1) mounted in series with the magnetic tunnel junction between two power supply nodes and comprising an insulating layer (BOX) embedded in a semiconductor substrate (2) forming a back gate (G2,T1); - control means (CONT) configured to apply the first input voltage (Vin1) to said back gate; - a detection circuit (DET) configured to generate a detection signal (s1) that varies according to the resistive state of the magnetic tunnel junction.

A three-dimensional (3D) magnetoresistive random access memory (MRAM) device includes a plurality of stacked cells, a plurality of stacked insulating layers, and a first interconnect structure of a first type. The plurality of cells are stacked in a direction perpendicular to a major surface of a substrate of the 3D MRAM device. Each cell of the first plurality of cells is separated by an insulating layer of the plurality of insulating layers from another cell of the plurality of cells. Each cell of the first plurality of cells includes a magnetic tunnel junction (MTJ) structure and a second interconnect structure of a second type configured to interface with the MTJ structure of the cell. The first interconnect structure is oriented orthogonally to the second interconnect of each cell of the plurality of cells, and extends through the plurality of cells to interface with the MTJ structure in each cell.

The application discloses a random number conversion system based on a self-calibration magnetic tunnel junction and a working method thereof, and the system comprises a magnetic tunnel junction, a magnetic tunnel junction random writing module, a pre-charge sensing amplification module and a real-time feedback calibration module; the magnetic tunnel junction is a source of physical randomness of the system, and the resistance state of the magnetic tunnel junction randomly flips based on thermal fluctuation; the output end of the magnetic tunnel junction random writing module is connected with the magnetic tunnel junction; the input end of the pre-charge sensing amplification module is connected with the magnetic tunnel junction; the real-time feedback calibration module comprises a period counter, a flip counter and a digital comparator; the input end of the flip counter is connected with the output end of the pre-charge sensing amplification module; the output end of the digital comparator is connected with the input end of the magnetic tunnel junction random writing module, and the flip current of the magnetic tunnel junction random writing module is dynamically adjusted. The application solves the problem of flip probability deviation of a traditional true random number generator caused by process deviation and environmental temperature fluctuation.

A keyword spotting method and apparatus based on magnetic tunnel junction arrays. The method comprises: using a statistically-aware training method to train a neural network, so as to obtain weight data of the neural network, mapping the weight data to high and low resistance state data of magnetic tunnel junction arrays, on the basis of an actual network structure of the neural network, selecting a magnetic tunnel junction array of a corresponding size, and pre-programming magnetic tunnel junctions into corresponding resistance states (S101); extracting a Mel-frequency cepstral coefficient (MFCC) feature from a speech keyword signal (S102); and during performing keyword spotting, continuously inputting binarized speech MFCC features into the magnetic tunnel junction array in the form of voltage amplitudes, acquiring a multiply-accumulate operation result by means of measuring an output current of a target column of the magnetic tunnel junction array, and finally outputting a hardware-based keyword spotting result after performing normalization and layer-by-layer inference (S103).

An exemplary magnetoresistive random-access memory (MRAM) cell is configured to store more than one bit. The MRAM cell includes a first magnetic tunneling junction (MTJ) and a second MTJ connected in parallel. The first MTJ has a first diameter, the second MTJ has a second diameter, and the second diameter is less than the first diameter. The MRAM cell further includes a transistor connected to the first MTJ and the second MTJ, a bit line connected to the first MTJ and the second MTJ, a word line connected to the transistor, and a source line connected to the transistor. A method of writing to the MRAM cell can include supplying one or more write voltages to the MRAM cell (e.g., having different levels) depending on an initial memory state and a desired memory state of the MRAM cell.

A method of forming integrated circuits includes forming Magnetic Tunnel Junction (MTJ) stack layers, depositing a conductive etch stop layer over the MTJ stack layers, depositing a conductive hard mask over the conductive etch stop layer, and patterning the conductive hard mask to form etching masks. The patterning is stopped by the conductive etch stop layer. The method further includes etching the conducive etch stop layer using the etching masks to define patterns, and etching the MTJ stack layers to form MTJ stacks.

The application discloses a preparation method of a nano or atomic scale spin valve, which comprises the following steps: preparing a buffer layer and a metal electrode on a substrate surface, preparing a magnetic metal point contact device based on a proximity effect photolithography method, placing the device on a vacuum probe station, preparing an atomic scale point contact structure by using a current feedback control method, and preparing a magnetic tunnel junction with a magnetic resistance of up to 40% by natural oxidation, so as to obtain the nano or atomic scale spin valve. The preparation method can effectively control the contact width of the atomic contact point, and compared with the prior art, the complexity of the spin valve structure is reduced, and the device power consumption is reduced to a certain extent. The preparation method is simple, the magnetic tunnel junction has a large magnetic resistance, and is compatible with a traditional CMOS process, so that an advantage is provided for the integration of subsequent devices.

This disclosure relates to a semiconductor device and a method for manufacturing the same. The semiconductor device includes: an interlayer insulating film disposed on a substrate and having a recessed portion of the substrate exposed; a bottom electrode contact embedded in at least a portion of the recessed portion; a magnetic tunnel junction (MTJ) layer disposed on the interlayer insulating film and the bottom electrode contact; and a offset cancellation layer with a magnetization direction parallel to the antiparallel side of a fixed layer, wherein the offset cancellation layer may include a Co alloy, Fe alloy, Ni alloy, or Mn alloy comprising at least one selected from the group consisting of Al, Ga, B, Ir, Zr, Hf, and rare earth metals, or a ternary or quaternary Co alloy, Fe alloy, or Ni alloy comprising one selected from the group consisting of Pt or Pd and at least one selected from the group consisting of Cr, Al, Tb, Si, and B.

This invention relates to the field of magnetic electronic devices, and more particularly to a magnetic tunnel junction, its fabrication method, and its applications. The magnetic tunnel junction includes: a lower electrode layer, a tunneling barrier layer, and an upper electrode layer; the tunneling barrier layer is disposed between the upper and lower electrode layers; wherein the tunneling barrier layer includes a self-supporting hafnium zirconium oxide film; the thickness of the self-supporting hafnium zirconium oxide film is 1-3 nm. The fabrication of this magnetic tunnel junction includes: firstly, growing an ultrathin LSMO / HZO bilayer structure on a substrate using PLD; utilizing LSMO as a sacrificial layer that can be selectively removed by a mixed solution of HCl and KI to release HZO in a self-supporting form; then, attaching the HZO to an FGT electrode to finally form the magnetic tunnel junction. The magnetic tunnel junction provided by this invention exhibits a tunneling magnetoresistance ratio (TMR) of approximately 140% at 2 K, indicating that the combination of this ultrathin ferroelectric barrier and the two-dimensional ferromagnetic electrode can achieve significant spin-polarized tunneling.

The present invention provides a control method for sidewall contamination of an MRAM magnetic tunnel. In the control method, there is no need to additionally coat an insulation protection layer on the sidewall of an MTJ layer, but a unique funnel-shaped trench is formed during the etching process; the funnel-shaped trench comprises a first area away from a plane where a substrate is located and a second area adjacent to the plane where the substrate is located; the size of the first area in a first direction gradually increases, and the size of the second area in the first direction does not change; and in removing metal contamination on the bottom of the funnel-shaped trench, the funnel-shaped trench can prevent the metal contamination from being attached to the sidewall of the MTJ layer, so as to improve the apparatus performance of an MRAM.

A variable resistance memory device includes a substrate at least partially defining a peripheral area surrounding a cell area, a lower insulating layer in the cell and peripheral areas, a magnetic tunnel junction structure in the cell area, a capping layer conformally covering both the magnetic tunnel junction structure and a first portion of the lower insulating layer in the cell area, a buried insulating layer burying the magnetic tunnel junction structure in the cell area, and an interlayer insulating layer covering a second portion of the lower insulating layer in the peripheral area. The buried and interlayer insulating layers include respective tapered contact surfaces. Respective vertical contact surfaces of the buried and interlayer insulating layers contact each other at an interface extending in the vertical direction from a top surface of the second portion of the lower insulating layer in the peripheral area to a first height.

A semiconductor device and a method for manufacturing the same are disclosed. The semiconductor device includes a plurality of first wires extending in a first direction, a plurality of second wires disposed over the first wires and extending in a second direction crossing the first direction, and a plurality of memory cells respectively overlapping with intersection regions between the first wires and the second wires, wherein each of the memory cells includes a selector pattern and a magnetic tunnel junction (MTJ) pattern disposed in an upper portion or a lower portion of the selector pattern, and wherein each of the second wires is disposed between the MTJ patterns.

A magnetic random access memory (MRAM), a memory array, and an electronic device are disclosed. The MRAM includes: a drive signal module for providing a read signal; a memory array comprising multiple arrayed memory cells, each memory cell including a magnetic tunnel junction (MTJ) with a magnetically fixed layer and a magnetically free layer disposed opposite to each other; a data cell for loading the read signal and outputting a data voltage; a reference cell including a parallel-state reference cell and an anti-parallel-state reference cell; the magnetically free layer of the parallel-state reference cell is coupled to the magnetically fixed layer of the anti-parallel-state reference cell to form a reference output terminal; the reference cell is used to load the read signal and output a reference voltage through the reference output terminal; and a comparator circuit for reading data from the data cell based on the relative magnitude of the data voltage and the reference voltage. This invention helps reduce the possibility of the reference cell's resistive state flipping during read operations, ensuring the reliability of the reference cell and improving the performance of the MRAM.

The application discloses a magnetic recording device, a multi-state disk and a read-write method, and belongs to the field of magnetic storage. The magnetic recording device comprises a substrate and a magnetic recording film above the substrate. The magnetic recording film is circular and comprises three ferromagnetic layers separated by two non-magnetic intermediate layers. The easy magnetization directions of the three ferromagnetic layers are along the x, y and z directions respectively. The z direction is the vertical direction, and the x and y directions are in-plane directions and are along the radial direction and the tangential direction respectively. The multi-state disk comprises the magnetic recording device, a read head, a write head and magnetic shielding layers on both sides of the read head. The write head comprises a vertical magnetic pole and two pairs of horizontal magnetic poles, and coils wound on the magnetic poles. The read head comprises a spin current generation layer and a film layer structure (a magnetic tunnel junction, a spin valve or a Hall bar). The application can improve the storage density of the magnetic recording device, thereby greatly improving the storage density of the disk based on the magnetic recording device.

This application provides a memory cell and a memory array, relating to the semiconductor field. The memory cell includes a spin-orbit layer and a magnetic tunnel junction (MTJ), with the MMT stacked on top of the spin-orbit layer. The top electrode of the MMT is connected to a source line. A first end of the spin-orbit layer is connected to a bit line via a first switch, and a second end of the spin-orbit layer is connected to a bit line via a second switch. The control terminal of the first switch is connected to a first word line, and the control terminal of the second switch is connected to a second word line. This reduces the complexity of the memory cell's peripheral control circuitry and timing control.

A method of manufacturing a magnetoresistive memory device may include forming a magnetic tunnel junction layer over a substrate; forming a hard mask pattern on the magnetic tunnel junction layer; etching the magnetic tunnel junction layer using the hard mask pattern to form a residual hard mask pattern; adjusting a thickness of the residual hard mask pattern remaining after etching the magnetic tunnel junction layer to form a passivation pattern; and forming at least one signal line using an additional hard mask pattern and the passivation pattern to protect the magnetic tunnel junction layer.

The present application relates to a magnetoresistive memory device and a method of manufacturing the same. The method of manufacturing the magnetoresistive memory device can include forming a magnetic tunnel junction layer over a substrate; forming a hard mask pattern on the magnetic tunnel junction layer; etching the magnetic tunnel junction layer using the hard mask pattern to form a residual hard mask pattern; adjusting a thickness of the residual hard mask pattern remaining after etching the magnetic tunnel junction layer to form a passivation pattern; and forming at least one signal line using an additional hard mask pattern and the passivation pattern to protect the magnetic tunnel junction layer.

An apparatus comprises an artificial neuron including a magnetic domain wall racetrack (racetrack), a first magnetic tunnel junction, a second magnetic tunnel junction, a first terminal, and a second terminal configured to cooperate to reliably create, propagate, readout, and reset a magnetic domain over multiple continuous operational cycles. The racetrack provides a propagation path for the magnetic domain. The first magnetic tunnel junction, coupled to the racetrack proximate to the first terminal, nucleates the magnetic domain in the racetrack. The first terminal is located proximate to one end of the racetrack, and receives a train of input voltage pulses that drive the magnetic domain along the racetrack. The second magnetic tunnel junction, coupled to the racetrack proximate to the second terminal, fires in response to passage of the magnetic domain. The second terminal, located proximate to another end of the racetrack, ejects the magnetic domain from the racetrack.

A semiconductor device including a magnetic tunnel junction (MTJ) stack, a dielectric encapsulation layer surrounding vertical side surfaces of the MTJ stack, a metal encapsulation layer surrounding an upper horizontal surface and a portion of a vertical side surface of the dielectric encapsulation layer, and a dielectric surrounding a remaining portion of the vertical side surface of the dielectric encapsulation layer. A method including method includes forming a magnetic tunnel junction (MTJ) stack, forming a dielectric encapsulation layer surrounding vertical side surfaces of a top electrode, a free layer, a tunneling barrier, a reference layer and a bottom electrode of the MTJ stack, and forming a metal encapsulation layer surrounding an upper horizontal surface and a portion of a vertical side surface of the dielectric encapsulation layer.

A self-referencing PUF device, a read-write circuit, and a read-write circuit array. The PUF device comprises: an intermediate magnetic tunnel junction (MTJ) (10), and a first MTJ (20) and a second MTJ (30) respectively located on two sides of the intermediate MTJ (10). There are gaps between the first MTJ (20) and the intermediate MTJ (10) and between the second MTJ (30) and the intermediate MTJ (10), respectively. The first MTJ (20), the intermediate MTJ (10), and the second MTJ (30) use the same free layer. The width of the free layer gradually decreases from the part located on the intermediate MTJ (10) to the part located on the first MTJ (20) and to the part located on the second MTJ (30), respectively, so as to form magnetic anisotropy gradients. A voltage control layer (40) is disposed on the free layer and in an area located on the intermediate MTJ (10). In the present application, the MTJs at two ends can serve as read-write devices, and in an initial state, a magnetic domain wall is fixed in an area of the intermediate MTJ (10), so that by driving the magnetic domain wall to randomly relax toward two sides on the basis of anisotropy, a low-resistance state is formed when the magnetic domain wall is stabilized on the MTJ at one side, while the MTJ at the other side is in a high-resistance state, so as to form a self-referencing structure of the device, thereby increasing the read margin of the device.

A memory device includes a bottom electrode, a magnetic tunnel junction (MTJ) stack, a top electrode, and a sidewall spacer. The MTJ stack is over the bottom electrode. The top electrode is over the MTJ stack. The sidewall spacer laterally surrounds the MTJ stack and the top electrode. The sidewall spacer has an outermost sidewall laterally set back from an outermost sidewall of the bottom electrode.