A fault testing method and system for phase-change memory arrays

Abstract

This invention discloses a fault testing method and system for phase-change memory arrays, relating to the field of integrated circuit technology. The method includes analyzing multiple fault modes in the phase-change memory array, extracting the necessary and sufficient conditions for each fault mode, where the necessary and sufficient conditions are the failure characteristics of one or more cells in the array; deriving a test sequence suitable for fault testing of the phase-change memory array based on the necessary and sufficient conditions; constructing a fault detection circuit based on the test sequence and embedding it into the phase-change memory array; and using the fault detection circuit to perform fault testing on the phase-change memory array, determining the health status of each memory cell in the array, and completing the fault testing. The algorithm of this invention can detect PCRAM-specific faults that traditional detection circuits cannot identify, thereby significantly improving fault coverage.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a fault testing method and system for phase-change memory arrays. Background Technology

[0002] PCRAM is an emerging memory technology that competes with current mainstream Dynamic Random Access Memory (DRAM) and Flash Memory (FLASH). Compared to traditional memory technologies, PCRAM stores data through resistive states rather than relying on charge storage. This characteristic frees it from the scaling limitations associated with charge storage and demonstrates broad application potential in various fields such as memory technology, in-memory computing, and logic systems, thus making it a promising alternative to traditional memory in the future. In PCRAM read and write operations, data access is performed by applying voltage to the storage elements. Specifically, the operation involves controlling the voltage level of the memory cells to achieve data writing and reading. During a READ operation, an appropriate read voltage is applied to the bit line (BL) of the addressed cell, while simultaneously turning on the transfer transistor by biasing its gate terminal. The low voltage on BL provides the necessary read current and ensures that the data stored in the addressed cell is not unintentionally altered. The SET operation is used to write a logic "1" to the addressed cell. This process is achieved by applying a high voltage to BL while simultaneously biasing the word line (WL) and turning on the transfer transistor. A forced high current flows through the memory cell, heating the material to a temperature above its glass transition temperature but below the melting point of the GST material, thus inducing the material to transform into a crystalline phase. The BL, source line (SL), and WL of unaddressed cells are grounded to suppress their programming. The RESET operation is used to write logic "0" into the cell. This is achieved by applying a high current to the germanium-antimony-tellurium (GST) layer of the selected cell, heating the material to a temperature above its melting point, and then rapidly cooling it to form an amorphous state. This operation is accomplished by applying a high voltage to the BL and simultaneously applying an appropriate voltage to the gate terminal to turn on the transfer transistor. For unaddressed cells, their BL, SL, and WL are also kept grounded to avoid interference.

[0003] Studies have shown that PCRAM not only experiences static and dynamic faults common to conventional memory, but also some unique, special faults. PCRAM operation relies on thermal variations to store information; therefore, the design and implementation of its memory cells must ensure effective isolation between cells. Furthermore, voltage must be maintained within design limits under different operating conditions to ensure normal device operation and reliable data retention. Failure to meet these requirements can lead to various PCRAM-specific faults. Traditional testing techniques cannot accurately distinguish between the five states of PCRAM, resulting in many faults going undetected. Therefore, to improve fault detection coverage, it is necessary to develop entirely new test circuits and algorithms specifically for PCRAM. Summary of the Invention

[0004] The purpose of this section is to outline some aspects of embodiments of the present invention and to briefly describe some preferred embodiments. Simplifications or omissions may be made in this section, as well as in the abstract and title of this application, to avoid obscuring the purpose of these documents; however, such simplifications or omissions should not be construed as limiting the scope of the invention.

[0005] In view of the aforementioned existing problems, the present invention is proposed.

[0006] Therefore, the present invention provides a fault testing method and system for phase change memory arrays, which can solve the problems mentioned in the background art.

[0007] To solve the above-mentioned technical problems, the present invention provides the following technical solution:

[0008] In a first aspect, the present invention provides a fault testing method for a phase change memory array, comprising: analyzing multiple fault modes in the phase change memory array and extracting the necessary and sufficient conditions for each fault mode, wherein the necessary and sufficient conditions are the failure characteristics of one or more units in the array.

[0009] Based on the necessary and sufficient conditions, a test sequence suitable for fault testing of phase change memory arrays is derived;

[0010] A fault detection circuit based on the test sequence is constructed and embedded into a phase-change memory array;

[0011] The fault detection circuit is used to perform fault testing on the phase-change memory array, determine the health status of each memory cell in the array, and complete the fault test.

[0012] As a preferred embodiment of the fault testing method for the phase-change memory array described in this invention, the analysis of multiple fault modes in the phase-change memory array includes:

[0013] The operating characteristics of phase-change memory arrays are modeled, and the behavior of cells under different conditions is analyzed.

[0014] Under different operating conditions, the impact of environmental factors on storage units should be considered;

[0015] The environmental factors include voltage fluctuations, temperature changes, and current density;

[0016] The behavior of phase-change memory under different operating conditions is described through theoretical modeling and experimental data.

[0017] As a preferred embodiment of the fault testing method for the phase-change memory array of the present invention, the testing method further includes:

[0018] During the testing process, a fault detection circuit is used. This circuit can monitor the electrical performance of the phase change memory in real time, such as parameters like current, voltage, and temperature, and determine whether the memory cell has failed based on the changes in the monitored parameters.

[0019] The fault detection circuit includes multiple modules, including a module for simulating the electrical parameter adjustment of the phase change memory under different fault modes, so as to simulate and detect fault behavior under various environmental conditions, and test and verify the memory unit based on the simulation results.

[0020] As a preferred embodiment of the fault testing method for the phase-change memory array of the present invention, the fault modes include read fault, write fault, hold fault and thermal fault.

[0021] The fault modes are derived by analyzing the working state and operating conditions of the phase change memory array, and extracting the necessary and sufficient conditions for each fault mode.

[0022] The necessary and sufficient conditions include the effects of environmental factors such as voltage, current, and temperature on the storage cell, as well as the effects of electrical stress and thermal stress on the performance of the storage cell.

[0023] As a preferred embodiment of the fault testing method for the phase change memory array of the present invention, the necessary and sufficient conditions are achieved by adjusting the operating current, voltage and ambient temperature of the memory cell to simulate the working state of the memory cell under different operating conditions, and to determine the fault behavior of the memory cell under specific operating conditions.

[0024] By analyzing the impact of different operating conditions on phase-change memory arrays, test sequences are provided for the detection of fault modes.

[0025] As a preferred embodiment of the fault testing method for the phase change memory array of the present invention, the test sequence is based on the operating characteristics and fault modes of the phase change memory array, and adopts a combination of sensitization sequence and detection sequence;

[0026] The sensitization sequence is used to activate potential faults in the array, and the detection sequence is used to determine whether a fault has occurred.

[0027] By optimizing the test sequence, fault modes can be triggered and detected under various operating conditions;

[0028] The test sequences were generated using an improved March-PCRAM algorithm, which optimized the generation process of sensitization and detection sequences for the characteristics of phase change memory arrays.

[0029] The specific process of the improved March-PCRAM algorithm is as follows:

[0030] {M0↑↓(w0;M1↑(r) ref0 w1 r ref1 M2↓(w1 r) ref1 w0 r ref0 M3↓(r) ref0 w1 r ref1 M4↑↓(r) ref1 )}

[0031] Where M0-M4 represent the steps in the algorithm, ↑ indicates ascending address access, ↓ indicates descending address access, and ↑↓ indicates access can be either ascending or descending. w0 indicates writing logical 0 data to the selected memory location, w1 indicates writing logical 1 data to the selected location, r0 indicates reading data from the selected location with a desired value of 0, r1 indicates reading with a desired value of 1, and r ref0 and r ref1 This is a special read operation for detecting PCRAM-specific faults;

[0032] During the test, if the data read from a certain test address does not match the expected value, the address is considered to be faulty, indicating that there is an abnormality in the PCRAM read / write operation and the fault detection fails; if the data read from all addresses matches the expected value, the fault detection is considered to have passed.

[0033] Secondly, the present invention provides a fault test circuit for a phase-change memory array, comprising:

[0034] The fault detection circuit includes multiple electrical performance monitoring modules and a PRR-based verification module.

[0035] The electrical performance monitoring module is used to monitor the current, voltage and temperature of the storage unit in real time. When an abnormal change is detected, the fault detection circuit can generate an early warning signal and feed it back to the external controller for fault analysis.

[0036] The PRR-based verification module is used to monitor the electrical response of the storage unit in real time during the test, evaluate the health status of the storage unit based on the response, perform in-depth analysis of the failure modes, and generate a failure test report through the feedback loop, thereby assisting in locating and analyzing potential failures of the storage unit.

[0037] Thirdly, the present invention provides a fault testing system for a phase-change memory array, which includes: a fault analysis module, a test sequence module, a test circuit construction module, and a fault detection module;

[0038] The fault analysis module is used to analyze multiple fault modes in the phase change memory array and extract the necessary and sufficient conditions for each fault mode. The necessary and sufficient conditions are the failure characteristics of one or more units in the array.

[0039] The test sequence module is used to derive a test sequence suitable for fault testing of phase change memory arrays based on the necessary and sufficient conditions.

[0040] The test circuit construction module is used to construct a fault detection circuit based on the test sequence and embed it into the phase change memory array;

[0041] The fault detection module is used to perform fault testing on the phase change memory array using the fault detection circuit, determine the health status of each memory cell in the array, and complete the fault test.

[0042] Fourthly, the present invention provides a computer device, including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the steps of a fault testing method for a phase-change memory array.

[0043] Fifthly, the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein: when the computer program is executed by a processor, it implements the steps of a fault testing method for a phase-change memory array.

[0044] Compared with existing technologies, the advantages of this invention are that by employing four reference currents to reference and read the five states of PCRAM cells in parallel, efficiency is greatly improved compared to traditional read circuits that can only set one reference current to distinguish between two storage states. This significantly reduces the time required for MBIST circuit fault testing. Based on in-depth analysis of PCRAM conventional and unique fault models, this method derives a comprehensive March-PCRAM algorithm. This algorithm can detect not only all static single-cell and static double-cell faults, but also most dynamic single-cell, dynamic double-cell, and PCRAM-specific faults. Because it uses four reference currents, the algorithm can detect PCRAM-specific faults that traditional detection circuits cannot identify, thus significantly improving fault coverage. Attached Figure Description

[0045] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1The MBIST overall circuit structure diagram of a fault testing method and system for a phase-change memory array provided in one embodiment of the present invention;

[0047] Figure 2 An internal structural diagram of a computer device for a fault testing method and system for a phase-change memory array provided in one embodiment of the present invention;

[0048] Figure 3 The March-PCRAM algorithm of a phase-change memory array fault testing method and system provided in one embodiment of the present invention is shown in the PD fault test waveform diagram.

[0049] Figure 4 The March-PCRAM algorithm of a phase-change memory array fault testing method and system provided in one embodiment of the present invention is shown in the IPF fault test waveform diagram. Detailed Implementation

[0050] To make the above-mentioned objects, features, and advantages of the present invention more readily understood, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present invention, and not all of them. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the protection scope of the present invention.

[0051] Many specific details are set forth in the following description in order to provide a full understanding of the invention. However, the invention may also be practiced in other ways different from those described herein, and those skilled in the art can make similar extensions without departing from the spirit of the invention. Therefore, the invention is not limited to the specific embodiments disclosed below.

[0052] Secondly, the term "one embodiment" or "embodiment" as used herein refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a single or selective embodiment that is mutually exclusive with other embodiments.

[0053] Example 1

[0054] Reference Figures 1-2 This is the first embodiment of the present invention, which provides a fault testing method for a phase-change memory array, including:

[0055] This application provides a method that can effectively solve the problems mentioned above. The following will describe in detail how to implement the fault testing method of the phase change memory array with reference to several embodiments.

[0056] Figure 1A flowchart of a fault testing method and system for a phase-change memory array is shown, including:

[0057] S1: Analyze multiple fault modes in the phase change memory array and extract the necessary and sufficient conditions for each fault mode. The necessary and sufficient conditions are the failure characteristics of one or more units in the array.

[0058] Furthermore, the functional fault types of the phase change memory array are analyzed to determine the failure characteristics that each fault type may cause.

[0059] Based on the working principle of phase-change memory arrays, possible fault modes are identified, including read faults, write faults, and hold faults.

[0060] A thorough analysis of each failure mode is conducted to explore how failures affect the performance of storage units and identify possible failure manifestations, such as loss of data retention capability, inability to write or read data, and data read / write errors.

[0061] Furthermore, the operating characteristics of the phase-change memory array are modeled, and the behavior of the cells under different conditions is analyzed;

[0062] Under different operating conditions, the impact of environmental factors (such as voltage fluctuations, temperature changes, current density, etc.) on the storage cells is considered.

[0063] Through theoretical modeling and experimental data, the behavior of phase-change memory under different operating conditions is described, especially the triggering conditions for fault modes (such as excessive write current, excessively low read voltage, etc.).

[0064] The PCRAM fault model encompasses both special and conventional faults. To detect these faults in the memory, sensitization and detection sequences need to be derived from the corresponding fault primitives. Elements in the March-PCRAM algorithm must first trigger potential faults through the sensitization sequence, and then determine whether a memory cell is faulty through the detection sequence. This example analyzes the PCRAM fault model and lists all possible fault types, causes, and corresponding fault primitives, as shown in Table 1 below.

[0065] Table 1. Causes and Primitives of Special PCRAM Faults

[0066]

[0067] Based on the working mechanism of the array structure and storage unit, the necessary and sufficient conditions for each fault mode are identified and summarized. These conditions are used to detect fault segments in the sequence.

[0068] Based on the physical and electrical characteristics of the unit, the necessary and sufficient conditions for each failure mode are proposed to ensure that detection can effectively trigger and discover problems.

[0069] For each fault mode, the minimum conditions that lead to the fault (such as time, temperature, voltage, etc.) are extracted and transformed into necessary and sufficient conditions in the fault detection sequence. Each necessary and sufficient condition should cover the corresponding detection segment or multiple segments.

[0070] This invention employs a device-aware testing method for fault injection, simulating faults in actual operation by adjusting the electrical parameters of the PCRAM model. Specifically, it modifies the electrical parameters in the Verilog-A model of the PCRAM. By adjusting the voltage value or programming time of the RESET or SET operation, it can simulate insufficient or excessive phase transition of phase change material, resulting in a shift in resistance value, and thus simulating the behavioral characteristics of different faults.

[0071] Table 2 below lists the specific adjustment methods for electrical parameters during different fault simulation processes. By combining the Device-aware test method and the March-PCRAM algorithm, various potential faults of PCRAM can be effectively simulated and detected, significantly improving test coverage and optimizing memory design and reliability.

[0072] Table 2. Electrical parameter adjustment methods for PCRAM fault simulation.

[0073] Fault Name Electrical parameter adjustment method PD failure <![CDATA[R set : Adjust from 7K to 100K; R reset : Adjusted from 200K to 500K SR failure <![CDATA[V h Adjusted from 0.45 to 0.7; V th Adjusted from 0.8 to 1.0 FWR malfunction <![CDATA[R on : Adjust from 0.5K to 10K; R set : Adjusted from 7K to 50K SS fault <![CDATA[R set : Adjusted from 7K to 1M; R reset : Adjusted from 200K to 1M]]> RRD failure <![CDATA[V s : Adjusted from 3 to 1.5; I C Adjust from 0 to 0.2 RD failure <![CDATA[R set : Adjusted from 7K to 20K; V h Adjusted from 0.45 to 0.65 IPF failure <![CDATA[R reset : Adjusted from 200K to 1M; V s Adjusted from 3 to 2.8 CDF failure <![CDATA[V th Adjusted from 0.8 to 0.5; R set : Adjusted from 7K to 10K IRF failure <![CDATA[I s Adjusted from 0.6m to 0.3m; V s : Adjusted from 3 to 1.0]]> DRF failure <![CDATA[R set : Adjusted from 7K to 15K; V h Adjusted from 0.45 to 0.6]]> PRF failure <![CDATA[R set : Adjusted from 7K to 50K; R on : Adjusted from 0.5K to 5K WPF failure <![CDATA[T rc Adjust from 0.1μ to 0.2μ; V h Adjusted from 0.45 to 0.5]]> SCF failure <![CDATA[V s Adjusted from 3 to 0.1; I C Adjust from 0 to 1]]> PDCF failure <![CDATA[V h Adjust from 0.45 to 0.4; R set : Adjusted from 7K to 30K

[0074] The effectiveness of the proposed necessary and sufficient conditions is verified through experiments and simulations to ensure that the failure characteristics of memory cells can be accurately captured.

[0075] The accuracy and feasibility of the proposed necessary and insufficient conditions are verified through experiments and simulations.

[0076] Implement these necessary and sufficient conditions in a real phase-change memory array and record whether its performance meets expectations. If the conditions are not entirely accurate, parameters or testing methods need to be adjusted to ensure that failure characteristics of phase-change memory cells can be captured.

[0077] S2: Derive a test sequence suitable for fault testing of phase change memory arrays based on the necessary and sufficient conditions;

[0078] Furthermore, based on the necessary and sufficient conditions for the failure modes obtained in step 1, corresponding test sequences are designed to cover different types of failures;

[0079] Based on the failure modes and necessary and sufficient conditions, a set of test sequences is constructed to cover all identified failure modes.

[0080] Each necessary and sufficient condition corresponds to a detection segment in one or more test sequences. Different test strategies are designed according to different fault types, such as read / write faults and hold faults, to ensure accurate detection under different fault modes.

[0081] Furthermore, each detection segment in the test sequence is matched with the necessary and sufficient conditions to ensure that the test sequence can effectively trigger the fault and detect the corresponding problem;

[0082] Ensure that each segment in the test sequence can effectively detect the specific failure mode;

[0083] Match segments in the test sequence according to necessary and sufficient conditions to ensure that the test segments are triggered and faults are detected at the appropriate time; for example, for write faults, the test segments should consider different voltage and current conditions to trigger potential write errors.

[0084] Furthermore, based on different fault types, the test sequence is optimized, and special test segments (such as read / write stress tests, long-term retention tests, etc.) are added to enhance the sensitivity of the test.

[0085] To address the unique characteristics of phase-change memory arrays, test sequences were optimized to enhance their fault detection capabilities.

[0086] Special segments such as pressure tests and temperature change tests are added to the test sequence to simulate stress and failure modes in real working environments, ensuring that the test can accurately detect even minor faults.

[0087] Furthermore, tests were conducted in an experimental environment to adjust the execution order and timing of the sequence to ensure maximum coverage of potential faults;

[0088] The completeness and effectiveness of the designed test sequence were verified through experiments.

[0089] Execute the test sequence in the actual phase-change memory array and record the test results; if some fault modes are not detected, adjust the timing or order of the test sequence execution and add new detection steps.

[0090] S3: Construct a fault detection circuit based on the test sequence and embed it into a phase-change memory array;

[0091] Furthermore, the test circuit includes a 1T1R array memory cell, a read / write circuit, and a PRR DFT module;

[0092] The 1T1R array consists of 4×4 memory cells, each containing an NMOS transistor and a PCRAM element;

[0093] NMOS transistors MOS1-MOS in each column of memory cells 16The drains of the two transistors are connected to the output of the tri-state gate, while their sources are connected to the NMOS transistor MOS. 17 -MOS 20 The source and pole are connected;

[0094] The gate is connected to the input signal terminals WL0-WL3, and the source is connected to the positive terminal of the PCRAM;

[0095] The negative terminal of the PCRAM is connected to the output of the tri-state gate and the NMOS transistor. 21 -MOS 24 The drain electrode;

[0096] The PRR DFT module consists of a transmission circuit, a reference current generation circuit, and an inverter circuit, and is used to generate multiple sets of reference currents required during the test.

[0097] Furthermore, the MBIST circuit consists of a control generator, an address generator, a data generator, a comparator, and a diagnostic unit.

[0098] The control generator is responsible for coordinating the operation of each module in the MBIST circuit and executing the March-PCRAM test algorithm in the order of M0 to M4.

[0099] The address generator and data generator generate the address and data signals required by the algorithm, respectively; the comparator is used to compare the actual data of the PCRAM cell with the expected data to determine whether the memory read and write operation is correct.

[0100] When the test result is correct, the output signal Test_fail remains low, and the fault address logger will not record any information.

[0101] If an error is detected, the Test_fail signal is set high, and the fault address logger is triggered to record the address of the faulty unit.

[0102] The diagnostic tool outputs the recorded fault unit address via the address signal Fail_adr.

[0103] During the test, if the data read from a certain address does not match the expected data, the address is considered to be faulty, indicating that the PCRAM read / write operation has failed the test; if the data read from all addresses matches the expected value, the fault detection passes.

[0104] Furthermore, the reference current I ref Generated by the NMOS transistor within the PRR DFT circuit. When the read / write circuit is operating, the voltage across the PCRAM is the input signal V. read In logic 0 state, the resistance of the PCRAM is R. HRS In logic 1 state, its resistance is R.LRS The operating resistance states of PCRAM are refined into five types, and the upper boundary resistance values ​​and definition formulas of these resistance states are listed in Table 3 below.

[0105] Table 3. Upper Boundary Resistance Values ​​and Definition Formulas for PCRAM Resistor State Division

[0106] PCRAM resistive state upper boundary resistance Definition Formula Deep 1 state None None Logic 1 <![CDATA[R ref3 ]]> <![CDATA[R ref3 =R LRS ]]> Undefined state (USF) <![CDATA[R ref2 ]]> <![CDATA[R ref2 =R HRS +2 / 5*(R HRS -R LRS )]]> Logic 0 state <![CDATA[R ref1 ]]> <![CDATA[R ref1 =R LRS +3 / 5*(R HRS -R LRS )]]> Deep 0 state <![CDATA[R ref0 ]]> <![CDATA[R ref0 =R HRS ]]>

[0107] Based on the upper boundary resistance value of the PCRAM resistive state, the reference current I generated by the four NMOS transistors in the PRR DFT circuit can be calculated respectively. ref0 I ref1 I ref2 I ref3 The calculation formula is:

[0108]

[0109] Similarly, we can obtain I ref1 =V read1 / R ref1 I ref2 =V read2 / R ref2 I ref3 =V read3 / R ref3 ;

[0110] Will I ref0 I ref1 I ref2 I ref3 Substituting these values ​​into the formula for calculating the width-to-length ratio (W / L) of an NMOS transistor, the width-to-length ratio of each NMOS transistor in the PRRDFT circuit can be calculated:

[0111]

[0112] Among them, V th It is the threshold voltage of the NMOS transistor, V gs It is the voltage between the gate and the source, μ n It is electron mobility, C ox This is the gate oxide capacitance per unit area. This calculation process ensures that the reference current generated by each NMOS transistor precisely matches the state of the PCRAM, enabling accurate fault detection.

[0113] The MBIST circuit, serving as a test circuit in addition to the regular functions of the PCRAM memory, separates the test signal from the external logic signal using a 2-to-1 data selector, controlled by the BIST_EN enable signal. When the BIST_EN signal is 1, the PCRAM memory enters test mode, and the MBIST circuit begins operation. In test mode, the MBIST circuit executes operations sequentially according to a preset algorithm. During the read operation, the comparator compares the actual signal with the expected signal to check for faults in the PCRAM. If a fault is detected at the end of the algorithm execution, the Test_fail signal is pulled high, and the corresponding faulty cell address is recorded. The MBIST circuit includes modules such as a control generator, address generator, data generator, comparator, and diagnostic unit. Figure 1 As shown. The modules work together, executing the test process in the order of the March-PCRAM test algorithm. The following is a detailed description of the function of each module:

[0114] Control Generator: Controls the operation of the entire MBIST circuit, driving each module to perform its corresponding operation sequentially according to the steps of the March-PCRAM test algorithm M0-M4. The main function of the control generator is to coordinate the timing of the test process, ensuring that each step is executed in sequence.

[0115] Address Generator: Responsible for generating the address signals required by the test algorithm. The March-PCRAM test algorithm involves accessing memory cells one by one, so the address generator generates the address signal for each memory cell in sequence to ensure that the test algorithm can cover all memory cells of the PCRAM.

[0116] Data Generator: Used to generate data signals corresponding to the test steps. The March-PCRAM algorithm involves writing to different states, so the data generator produces corresponding write data according to the test steps, ensuring that each memory cell of the PCRAM receives the correct write information.

[0117] Comparator: During testing, the comparator compares the actual data read from the PCRAM with the expected data. After each read operation, the comparator compares the actual data read from the memory cell with the expected data. If they match, it indicates that the memory cell is not faulty; if they do not match, it indicates that the memory cell has failed.

[0118] Test_fail signal: When the comparator detects a data mismatch, the Test_fail signal goes high, indicating that the test has failed. If the read / write operation is successful, the Test_fail signal remains low, indicating that the test has passed.

[0119] Fault Address Logger: When the Test_fail signal goes high, the fault address logger records the address of the current memory cell. In this way, the logger can accurately locate the faulty memory cell.

[0120] Diagnostic Unit: The diagnostic unit further records the addresses of all faulty memory cells and outputs the specific address of the faulty cell via the Fail_adr signal. This address is in coded form, which facilitates diagnosis of which specific NMOS transistor in the memory array has caused the PCRAM failure.

[0121] The algorithm covers both special and common faults of PCRAM. Special faults include proximity faults, read faults, read recovery faults, and write faults. Common fault types include static single-cell faults, static double-cell faults, dynamic single-cell faults, and dynamic double-cell faults. The specific process of the March-PCRAM test algorithm is as follows:

[0122] {M0↑↓(w0;M1↑(r) ref0 w1 r ref1 M2↓(w1 r) ref1 w0 r ref0 M3↓(r) ref0 w1 r ref1 M4↑↓(r) ref1 )}

[0123] Where M0-M4 represent the steps in the algorithm, ↑ indicates ascending address access, ↓ indicates descending address access, and ↑↓ indicates access can be in either ascending or descending order. w0 indicates writing logical 0 data to the selected memory location, w1 indicates writing logical 1 data to the selected location; r0 indicates reading data from the selected location with a desired value of 0, r1 indicates reading with a desired value of 1; r ref0 and r ref1 This is a special read operation for detecting PCRAM-specific faults. During the test, if the data read from a certain test address does not match the expected value, it is determined that the address has a fault, indicating that there is an abnormality in the PCRAM read / write operation, and the fault detection fails; if the data read from all addresses matches the expected value, the fault detection is considered to have passed.

[0124] S4: Use the fault detection circuit to perform fault testing on the phase change memory array and determine the health status of each memory cell in the array.

[0125] Furthermore, a test sequence is executed to monitor each memory cell in real time through the embedded fault detection circuitry.

[0126] The embedded fault detection circuitry monitors the state of the memory cells in real time and executes a preset test sequence.

[0127] Start the test sequence, monitor the read and write behavior of each storage unit one by one, determine whether it meets the normal state, and record the state changes of each unit in real time.

[0128] Furthermore, the system collects and analyzes the health status of each storage unit to determine whether a fault exists and the type of fault.

[0129] Based on the results of the fault test, locate the faulty storage unit and analyze the cause of the fault, such as abnormal voltage or current, excessive write cycles, etc.

[0130] Generate fault detection reports, provide status assessment results for each storage unit, and provide decision support for subsequent repair or replacement.

[0131] Outputs fault detection reports, providing detailed fault analysis and decision support.

[0132] Based on the fault detection results, a status assessment report for each memory cell is generated, providing detailed information such as fault type, location, and possible causes to help with subsequent repair or replacement decisions. As shown in Table 4 below, the March-PCRAM algorithm detects various PCRAM special faults described in Table 1 in detail.

[0133] Table 4. Triggering and Detecting Special Faults in PCRAM using the March-PCRAM Algorithm

[0134]

[0135]

[0136] Furthermore, this embodiment also provides a fault testing system for a phase-change memory array, including:

[0137] Fault analysis module, test sequence module, test circuit construction module, and fault detection module;

[0138] The fault analysis module is used to analyze multiple fault modes in the phase change memory array and extract the necessary and sufficient conditions for each fault mode. The necessary and sufficient conditions are the failure characteristics of one or more units in the array.

[0139] The test sequence module is used to derive a test sequence suitable for fault testing of phase change memory arrays based on the necessary and sufficient conditions.

[0140] The test circuit construction module is used to construct a fault detection circuit based on the test sequence and embed it into the phase change memory array;

[0141] The fault detection module is used to perform fault testing on the phase-change memory array using the fault detection circuit, determine the health status of each memory cell in the array, and complete the fault test.

[0142] This embodiment also provides a computer device, which may be a terminal, and its internal structure diagram may be as follows. Figure 2 As shown, the computer device includes a processor, memory, communication interface, display screen, and input devices connected via a system bus. The processor provides computing and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The communication interface is used for wired or wireless communication with external terminals; wireless communication can be achieved through Wi-Fi, carrier networks, NFC (Near Field Communication), or other technologies. When executed by the processor, the computer program implements a comprehensive evaluation method suitable for the orderly access of large-scale distributed power sources. The display screen can be an LCD screen or an e-ink screen. The input devices can be a touch layer covering the display screen, buttons, a trackball, or a touchpad on the computer device casing, or an external keyboard, touchpad, or mouse.

[0143] This embodiment also provides a computer-readable storage medium on which a computer program is stored, and when the computer program is executed by a processor, it performs the following steps:

[0144] Multiple fault modes in a phase-change memory array are analyzed, and the necessary and sufficient conditions for each fault mode are extracted. The necessary and sufficient conditions are the failure characteristics of one or more units in the array.

[0145] Based on the necessary and sufficient conditions, a test sequence suitable for fault testing of phase change memory arrays is derived;

[0146] A fault detection circuit based on the test sequence is constructed and embedded into a phase-change memory array;

[0147] The fault detection circuit is used to perform fault testing on the phase-change memory array, determine the health status of each memory cell in the array, and complete the fault test.

[0148] Example 2

[0149] Reference Figure 3 - Figure 4This is the second embodiment of the present invention, which provides a fault testing method for a phase-change memory array. In order to verify the beneficial effects of the present invention, scientific demonstration is carried out through economic benefit calculation and simulation experiments.

[0150] The testing process employed a hybrid numerical simulation environment, including fault simulators from NC-Verilog and Virtuoso, to verify the effectiveness of all algorithms in detecting common faults. Taking PD faults and IPF faults as examples, the fault detection performance of the March-PCRAM algorithm was demonstrated. Figure 3 and Figure 4 As shown. When the BIST_EN signal is driven by the clock signal and the BIST_EN signal is 1, the PCRAM memory enters test mode, and the MBIST circuit starts working; V BLSL The <3:0> signal reflects the complete read / write operation flow during the March-PCRAM algorithm execution; X0-X3 output the waveforms of the PRR DFT cells. The Test_fail signal is used to mark faults. When the circuit is fault-free, the Test_fail signal remains low; once a fault occurs, the Test_fail signal rises, and the system outputs the address of the faulty cell through the Fail_adr<3:0> signal. This address is represented using a 4-bit code 8421, covering test cells from 0 to 15, corresponding to MOS1-MOS in the test array. 16 PCRAM at that location.

[0151] Figure 3 The test waveform diagram of the PD proximity interference fault is shown. This fault is triggered by the w0 operation of M0 and transmitted through the r in M1. ref0 Operation detected. This fault is explained as the unexpected loss of data stored in an adjacent PCRAM cell when it was programmed to a RESET state, primarily caused by thermal crosstalk during programming. The affected cell for a PD fault must be in a RESET state before the fault occurs. To trigger this fault, the MOS... 11 The adjacent cell in the PCRAM is programmed to a RESET state. The victim cell, MOS... 11 The final state of the PCRAM at address 0001 changes from a high-impedance state to an undefined state of 0011. Simultaneously, the Test_fail signal rises, and the Fail_adr<3:0> signal displays 1010, indicating that the March-PCRAM algorithm is at address 10, i.e., MOS. 11 The PCRAM at that location successfully detected the PD fault.

[0152] Figure 4 The test waveform diagram for the IPF incomplete programming fault is shown. This fault is triggered by the w0 operation in M2 and by the r operation in M3. ref0Operational detection. This type of fault is prone to occur when the memory cell is in a RESET operation, resulting in a cell resistance value lower than the typical value, exhibiting resistance close to that of the SET state. The cause of the fault is attributed to contaminants and impurities in the active region of the GST material. These impurities form low-resistance parallel conductive paths, thereby reducing the overall resistance of the memory cell. The final state of the PCRAM at MOS6 changes from a high-resistance state of 0001 to a low-resistance state of 0111. At the same time, the Test_fail signal increases, and the Fail_adr<3:0> signal displays 0101, indicating that the March-PCRAM algorithm successfully detected the IPF fault at address 5, i.e., the PCRAM at MOS6.

[0153] The fault models of PCRAM include specific faults and general faults, covering static single-cell faults, static double-cell faults, dynamic single-cell faults, and dynamic double-cell faults. Table 5 below summarizes the comparison of fault detection coverage between the March-PCRAM algorithm and previously developed algorithms.

[0154] Table 5 Fault coverage of the March-PCRAM algorithm and previously developed algorithms

[0155]

[0156]

[0157] As shown in Table 5, this embodiment effectively covers static single-cell faults, static dual-cell faults, dynamic single-cell faults, dynamic dual-cell faults, and special faults of PCRAM. Using the March-PCRAM testing algorithm, this embodiment achieves a fault coverage rate of 91.43% for PCRAM, a significant improvement compared to other testing algorithms, demonstrating higher fault detection capability and coverage.

[0158] It should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

[0159] Those skilled in the art will understand that embodiments of this application can be provided as methods, systems, or computer program products. Therefore, this application can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this application can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code. The solutions in the embodiments of this application can be implemented in various computer languages, such as the object-oriented programming language Java and the interpreted scripting language JavaScript.

[0160] This application is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0161] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0162] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0163] Although preferred embodiments of this application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of this application.

[0164] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A fault testing method for a phase-change memory array, characterized in that: This includes analyzing multiple failure modes in a phase-change memory array and extracting the necessary and sufficient conditions for each failure mode, wherein the necessary and sufficient conditions are the failure characteristics of one or more units in the array. Based on the necessary and sufficient conditions, a test sequence suitable for fault testing of phase change memory arrays is derived; A fault detection circuit based on the test sequence is constructed and embedded into a phase-change memory array; The fault detection circuit is used to perform fault testing on the phase change memory array, determine the health status of each memory cell in the array, and complete the fault test. The test sequence is based on the operating characteristics and fault modes of the phase change memory array, and uses a combination of sensitization sequence and detection sequence. The sensitization sequence is used to activate potential faults in the array, and the detection sequence is used to determine whether a fault has occurred. By optimizing the test sequence, fault modes can be triggered and detected under various operating conditions; The test sequences were generated using an improved March-PCRAM algorithm, which optimized the generation process of sensitization and detection sequences for the characteristics of phase change memory arrays. The specific process of the improved March-PCRAM algorithm is as follows: {M0↑↓(w0);M1↑(r ref0 w1 r ref1 );M2↓(w1 r ref1 w0 r ref0 );M3↓(r ref0 w1 r ref1 );M4↑↓(r ref1 )}; Where M0-M4 represent the steps in the algorithm, ↑ indicates ascending address access, ↓ indicates descending address access, and ↑↓ indicates access can be either ascending or descending. w0 indicates writing logical 0 data to the selected memory location, w1 indicates writing logical 1 data to the selected location, r0 indicates reading data from the selected location with a desired value of 0, r1 indicates reading with a desired value of 1, and r ref0 and r ref1 This is a special read operation for detecting PCRAM-specific faults; During the test, if the data read from a certain test address does not match the expected value, the address is considered to be faulty, indicating that there is an abnormality in the read / write operation of the phase-change memory, and the fault detection fails; if the data read from all addresses matches the expected value, the fault detection is considered to have passed.

2. The fault testing method for a phase-change memory array as described in claim 1, characterized in that: The analysis of multiple fault modes in phase-change memory arrays includes... The operating characteristics of phase-change memory arrays are modeled, and the behavior of cells under different conditions is analyzed. Under different operating conditions, the impact of environmental factors on storage units should be considered; The environmental factors include voltage fluctuations, temperature changes, and current density; The behavior of phase-change memory under different operating conditions is described through theoretical modeling and experimental data.

3. The fault testing method for a phase-change memory array as described in claim 2, characterized in that: The testing method further includes: During the testing process, a fault detection circuit is used. This circuit can monitor the electrical performance of the phase change memory in real time, such as current, voltage, and temperature parameters, and determine whether the memory cell has failed based on the changes in the monitored parameters. The fault detection circuit includes multiple modules, including a module for simulating the electrical parameter adjustment of the phase change memory under different fault modes, so as to simulate and detect fault behavior under various environmental conditions, and test and verify the memory unit based on the simulation results.

4. The fault testing method for a phase-change memory array as described in claim 3, characterized in that: The failure modes include read failure, write failure, hold failure, and thermal failure; By analyzing the working state and operating conditions of the phase change memory array, the necessary and sufficient conditions for each fault mode are extracted.

5. The fault testing method for a phase-change memory array as described in claim 4, characterized in that: The necessary and sufficient conditions are obtained by adjusting the operating current, voltage and ambient temperature of the storage unit to simulate the working state of the storage unit under different operating conditions, and to determine the fault behavior of the storage unit under specific operating conditions. By analyzing the impact of different operating conditions on phase-change memory arrays, test sequences are provided for the detection of fault modes.

6. A fault testing circuit for a phase-change memory array, implemented based on the fault testing method for a phase-change memory array according to any one of claims 1 to 5, characterized in that: The fault detection circuit includes multiple electrical performance monitoring modules and a PRR-based verification module. The electrical performance monitoring module is used to monitor the current, voltage and temperature of the storage unit in real time. When an abnormal change is detected, the fault detection circuit can generate an early warning signal and feed it back to the external controller for fault analysis. The PRR-based verification module is used to monitor the electrical response of the storage unit in real time during the test, evaluate the health status of the storage unit based on the response, perform in-depth analysis of the failure modes, and generate a failure test report through the feedback loop, thereby assisting in locating and analyzing potential failures of the storage unit.

7. A fault testing system for a phase-change memory array, implemented based on the fault testing method for a phase-change memory array according to any one of claims 1 to 5, characterized in that: It includes a fault analysis module, a test sequence module, a test circuit construction module, and a fault detection module; The fault analysis module is used to analyze multiple fault modes in the phase change memory array and extract the necessary and sufficient conditions for each fault mode. The necessary and sufficient conditions are the failure characteristics of one or more units in the array. The test sequence module is used to derive a test sequence suitable for fault testing of phase change memory arrays based on the necessary and sufficient conditions. The test circuit construction module is used to construct a fault detection circuit based on the test sequence and embed it into the phase change memory array; The fault detection module is used to perform fault testing on the phase change memory array using the fault detection circuit, determine the health status of each memory cell in the array, and complete the fault test.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that: When the processor executes the computer program, it implements the steps of the fault testing method for any one of the phase-change memory arrays according to claims 1 to 5.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by the processor, it implements the steps of the fault testing method for any one of the phase change memory arrays according to claims 1 to 5.

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