Time sequence margin detection device and method, electronic equipment, chip and storage medium

Abstract

The embodiment of the invention provides a time sequence margin detection device, a time sequence margin detection method, a time sequence margin detection device, a chip and a storage medium. The circuit comprises a reference signal acquisition module and a detection signal acquisition module. The reference signal acquisition module acquires a reference signal according to a transmission signal of a detected path, the detected path is connected with the time sequence margin detection device, and the reference signal indicates whether the transmission signal jumps or not; the detection signal acquisition module responds to jumping of the transmission signal and acquires a detection signal corresponding to the transmission signal, the detection signal is obtained after delay processing is conducted on the transmission signal, and the reference signal and the detection signal are used for determining whether the time sequence margin of the detected path is sufficient or not. The circuit can accurately determine whether the time sequence margin of the detected path is sufficient or not, and further accurately adjust the working voltage.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a timing margin detection device, a timing margin detection method, an electronic device, a chip, and a storage medium. Background Art

[0002] As the performance of computing chips increases, power consumption has become a new bottleneck for chip performance improvement. Due to the small size of the chip and the high power consumption density, the heat generated by the chip during operation cannot be fully dissipated, which will cause the chip temperature to rise. When the temperature exceeds the threshold, the chip may fail or even burn out. Therefore, the current approach is to strictly control the power consumption density, thereby controlling the temperature of the chip. Limiting the power consumption density is usually achieved by limiting the maximum operating frequency and operating voltage of the chip, which in turn affects the maximum performance of the chip.

[0003] The power consumption of a chip is approximately proportional to the square of the operating voltage. Reducing the operating voltage can significantly reduce the power consumption of the chip. However, low voltage will cause the chip to not work properly, so finding the lowest reliable operating voltage of the chip is an important means to reduce chip power consumption and improve chip performance. Summary of the invention

[0004] One or more embodiments of the present disclosure provide a timing margin detection device, a timing margin detection method, an electronic device, a chip, and a storage medium, which are used to solve technical problems such as high cost and poor versatility of customized IP circuits.

[0005] In a first aspect, at least one embodiment of the present disclosure provides a timing margin detection device, comprising: a reference signal acquisition module, configured to acquire a reference signal based on a transmission signal of a detected path, wherein the detected path is connected to the timing margin detection device, and the reference signal indicates whether a jump occurs in the transmission signal; a detection signal acquisition module, configured to acquire a detection signal corresponding to the transmission signal in response to a jump in the transmission signal, wherein the detection signal is obtained after delaying the transmission signal, and wherein the reference signal and the detection signal are used to determine whether the timing margin of the detected path is sufficient.

[0006] Optionally, in the timing margin detection device provided according to at least one embodiment of the present disclosure, the detected path is a critical path in the chip, and the critical path is a detected path with the largest delay among multiple detected paths in a clock domain of the chip.

[0007] Optionally, in the timing margin detection device provided according to at least one embodiment of the present disclosure, the reference signal acquisition module includes: a first trigger unit configured to output a reference signal according to rising edges of a transmission signal and a clock signal.

[0008] Optionally, in the timing margin detection device provided according to at least one embodiment of the present disclosure, the reference signal acquisition module also includes: a first XOR unit, connected to the detected path, configured to perform an XOR operation on the transmission signal and the sampling result of the transmission signal to obtain a first XOR result, and input the first XOR result into the first trigger unit to obtain a reference signal.

[0009] Optionally, in the timing margin detection device provided according to at least one embodiment of the present disclosure, the reference signal acquisition module also includes: a second trigger unit, configured to output a trigger signal based on the sampling result of the transmission signal and the rising edge of the clock signal; and a second XOR unit, connected to the detected path and the second trigger unit, configured to perform an XOR operation on the sampling result of the transmission signal and the trigger signal to obtain a second XOR result, and input the second XOR result into the first trigger unit to obtain a reference signal.

[0010] Optionally, in the timing margin detection device provided according to at least one embodiment of the present disclosure, the detection signal acquisition module includes: a delay unit, connected to the detected path, configured to receive a transmission signal, delay the transmission signal, and obtain a delayed signal; a third XOR unit, connected to the delay unit, configured to perform an XOR operation on the sampling result of the transmission signal and the delayed signal to obtain a third XOR result; and a third trigger unit, connected to the third XOR unit, configured to output a detection signal based on the third XOR result and the rising edge of the clock signal.

[0011] Optionally, the timing margin detection device provided according to at least one embodiment of the present disclosure further includes: a sampling unit, connected to the detected path, configured to receive the transmission signal, sample the transmission signal, and obtain a sampling result of the transmission signal.

[0012] Optionally, in the timing margin detection device provided according to at least one embodiment of the present disclosure, at least one of the first trigger unit, the second trigger unit and the third trigger unit is implemented by a trigger.

[0013] Optionally, the timing margin detection device provided according to at least one embodiment of the present disclosure further includes: a detection module, connected to the reference signal acquisition module and the detection signal acquisition module, and configured to determine the timing margin of the detected path based on the reference signal and the detection signal.

[0014] Optionally, the timing margin detection device provided according to at least one embodiment of the present disclosure further includes: an adjustment module, connected to the detection module, and configured to adjust the operating voltage of the detected path according to the timing margin of the detected path.

[0015] Optionally, in a timing margin detection device provided according to at least one embodiment of the present disclosure, the detection module is configured to perform timing analysis on a reference signal and a detection signal to determine whether the reference signal and the detection signal jump, wherein when the reference signal jumps and the detection signal jumps, it is determined that the timing margin of the detected path is sufficient; when the reference signal jumps and the detection signal does not jump, it is determined that the timing margin of the detected path is insufficient.

[0016] Optionally, in the timing margin detection device provided according to at least one embodiment of the present disclosure, the adjustment module is configured to: increase the operating voltage in response to insufficient timing margin of the detected path; and reduce the operating voltage or maintain the operating voltage in response to sufficient timing margin of the detected path.

[0017] In a second aspect, at least one embodiment of the present disclosure provides a timing margin detection method, which comprises: obtaining a reference signal based on a transmission signal of a detected path, wherein the detected path is connected to a timing margin detection device, and the reference signal indicates whether a jump occurs in the transmission signal; in response to a jump in the transmission signal, obtaining a detection signal corresponding to the transmission signal, wherein the detection signal is obtained after delaying the transmission signal, and wherein the reference signal and the detection signal are used to determine whether the timing margin of the detected path is sufficient.

[0018] Optionally, in the timing margin detection method provided according to at least one embodiment of the present disclosure, the detected path is a critical path in the chip, and the critical path is a detected path with the largest delay among multiple detected paths in a clock domain of the chip.

[0019] In a third aspect, at least one embodiment of the present disclosure provides a timing margin detection device, which comprises: at least one processing device and a memory; wherein a computer program is stored in the memory, and when the computer program is executed by at least one processing device, a timing margin detection method as described in any one of the second aspects above is implemented.

[0020] In a fourth aspect, at least one embodiment of the present disclosure provides a chip, comprising: a timing margin detection device as described in any one of the first aspect or the third aspect above, or a timing margin detection device as described in the third aspect.

[0021] Optionally, in a chip provided according to at least one embodiment of the present disclosure, the chip includes multiple clock domains, and the detected path is a critical path of the object clock domain, wherein the critical path is a path with the largest delay among multiple paths in the object clock domain.

[0022] In a fifth aspect, at least one embodiment of the present disclosure provides an electronic device comprising a chip according to any one of the fourth aspects.

[0023] In a sixth aspect, at least one embodiment of the present disclosure provides a computer-readable storage medium having computer-executable instructions stored thereon, wherein when the instructions are executed by a processor, any method in the second aspect is implemented.

[0024] The timing margin detection device, timing margin detection method, timing margin detection device, chip and storage medium provided by at least one embodiment of the present disclosure can accurately determine whether the timing margin of the detected path is sufficient by obtaining a reference signal and a detection signal, and further accurately adjust the operating voltage. The timing margin detection device has simple functions and structures, low costs, and is not dependent on the process or design of the chip, so it has high versatility. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0026] Figure 1 A schematic diagram of a timing margin detection device provided according to an embodiment of the present disclosure is shown.

[0027] Figure 2 A schematic diagram of a reference signal acquisition module provided according to an embodiment of the present disclosure is shown.

[0028] Figure 3A A schematic diagram of another reference signal acquisition module provided according to an embodiment of the present disclosure is shown.

[0029] Figure 3B FIG. 4 shows a timing diagram of a reference signal acquisition module 300 provided according to an embodiment of the present disclosure.

[0030] Figure 4A A schematic diagram of another reference signal acquisition module provided according to an embodiment of the present disclosure is shown.

[0031] Figure 4B A timing diagram of the reference signal acquisition module 400 provided according to an embodiment of the present disclosure is shown.

[0032] Figure 5A A schematic diagram of a detection signal acquisition module provided according to an embodiment of the present disclosure is shown.

[0033] Figure 5B A timing diagram of the detection signal acquisition module 500 provided according to an embodiment of the present disclosure is shown.

[0034] Figure 6A schematic diagram of a timing margin detection device provided according to an embodiment of the present disclosure is shown.

[0035] Fig. 7A A schematic diagram of a timing margin detection device provided according to an embodiment of the present disclosure is shown.

[0036] Figure 7B A schematic diagram showing an implementation of a timing margin detection device 700 provided according to an embodiment of the present disclosure is shown.

[0037] Figure 7C A schematic diagram showing another implementation of a timing margin detection device 700 provided according to an embodiment of the present disclosure is shown.

[0038] Fig.7D Shown as Figure 7C The timing diagram of the timing margin detection device is shown.

[0039] Figure 8 A flowchart of a timing margin detection method provided according to an embodiment of the present disclosure is shown.

[0040] Fig. 9 A schematic structural diagram of a timing margin detection device provided according to an embodiment of the present disclosure is shown.

[0041] Fig.10 A schematic diagram of a chip provided according to an embodiment of the present disclosure is shown.

[0042] Fig.11 A schematic diagram of an electronic device provided according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0043] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0044] Unless otherwise defined, all terms (including technical and scientific terms) used in the embodiments of the present disclosure have the same meanings as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It should also be understood that terms such as those defined in common dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant technology, and should not be interpreted in an idealized or extremely formal sense, unless the embodiments of the present disclosure explicitly define such meanings.

[0045] The words "first", "second" and similar words used in the embodiments of the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "one", "an" or "the" and similar words do not indicate a quantity limitation, but indicate the existence of at least one. Similarly, words such as "include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" and similar words are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. Flowcharts are used in the embodiments of the present disclosure to illustrate the steps of the method according to the embodiments of the present disclosure. It should be understood that the previous or subsequent steps are not necessarily carried out in order. On the contrary, various steps can be processed in reverse order or simultaneously. At the same time, other operations can also be added to these processes, or one or more steps can be removed from these processes.

[0046] The inventor of the present disclosure has noticed that the operating voltage of a chip can be dynamically adjusted by adaptive voltage and frequency adjustment technology, which can automatically adjust the operating voltage of the chip according to the working state and performance requirements of the chip, thereby ensuring the normal operation of the chip with high performance. In engineering implementation, the adaptive voltage and frequency adjustment technology is usually implemented in the chip using a customized IP (Intellectual Property) circuit, which has the following problems:

[0047] 1. Customized IP circuits can only monitor the area near the customized IP circuit in the chip. Therefore, multiple or even a large number of customized IP circuits need to be set up on the entire chip to ensure that the entire chip can be monitored, which increases costs and power consumption.

[0048] 2. Multiple ring oscillators may need to be set up in the custom IP circuit to simulate the real working circuit. However, since the ring oscillator is not part of the real circuit, the circuit working conditions simulated by the ring oscillator are different from the real circuit working conditions. In order to compensate for this difference, it is usually necessary to reserve a margin for the chip's operating voltage, which cannot achieve precise control;

[0049] 3. Customized IP circuits are not universal. When the chip process or design changes, the customized IP circuits need to be redesigned, which is costly.

[0050] In addition, in this disclosure, timing margin is also called timing margin or timing slack, which refers to the extra time available when the timing constraints are met. Timing constraints are the key to ensuring the normal operation of the chip, including many timing requirements such as data transmission and instruction execution. For details, please refer to the timing constraints in the relevant technology, which are not limited here.

[0051] The timing margin is related to the theoretical maximum frequency of the chip. The existence of the timing margin can provide the possibility of increasing the theoretical maximum frequency. When the theoretical maximum frequency is increased, more timing margin is needed to ensure the normal and stable operation of the chip. The theoretical maximum frequency of the chip is the highest operating frequency that the chip can reach, and the operating frequency is related to the operating voltage and power consumption, so the timing margin is also related to the operating voltage and power consumption.

[0052] Based on the relationship between the timing margin, the theoretical maximum frequency and the operating voltage, the inventors of the present disclosure proposed a timing margin detection device, a timing margin detection method, a timing margin detection device, a chip and a storage medium in the embodiments of the present disclosure. Through the reference signal and the detection signal, it can be determined whether the current timing margin is sufficient. According to whether the timing margin is sufficient, it can be further determined whether the operating voltage needs to be adjusted, thereby realizing dynamic power consumption adjustment.

[0053] One or more embodiments of the present disclosure will be explained below in conjunction with the accompanying drawings. It should be understood that the embodiments of the present disclosure are only for illustrative purposes and are not intended to limit the scope of the present disclosure.

[0054] Figure 1 A schematic diagram of a timing margin detection device provided according to an embodiment of the present disclosure is shown.

[0055] like Figure 1 As shown, a timing margin detection device (e.g., a timing margin detection circuit) 100 includes a reference signal acquisition module 110 and a detection signal acquisition module 120. The timing margin detection device 100 is connected to a detected path 10. The detected path 10 may be a path that needs to perform timing margin detection among multiple combinational logic paths in a chip.

[0056] The reference signal acquisition module 110 is connected to the detected path 10 . The reference signal acquisition module 110 acquires a reference signal according to a transmission signal of the detected path 10 .

[0057] The detection signal acquisition module 120 is connected to the detected path 10. The detection signal acquisition module 120 obtains the detection signal corresponding to the transmission signal in response to the jump of the transmission signal. The detection signal is obtained after delaying the transmission signal. In this embodiment, the reference signal and the detection signal are used to determine whether the timing margin of the detected path 10 is sufficient.

[0058] The transmission signal includes the signal transmitted in the detected path 10, the sampling result of the signal transmitted in the detected path 10, etc. For example, for any combinational logic path of the chip, the path has a starting point and an end point, and the transmission signal can be a signal between the starting point and the end point, or a signal output by the end point. For example, the end point of the path can be implemented using devices such as registers, triggers, and logic gates.

[0059] Optionally, the detected path is a critical path in the chip, and the critical path is a detected path with the largest delay among multiple detected paths in a clock domain of the chip.

[0060] Chips usually include multiple clock domains, and the clock frequency of each clock domain is different. For example, the critical path is the combinational logic path with the longest delay in each clock domain. The critical path determines the clock period of the corresponding clock domain. The clock period must be greater than or equal to the delay of the critical path, otherwise the critical path will not work properly. The delay of the critical path can also be called the length of the critical path.

[0061] In the embodiment of the present disclosure, the detected path 10 may be a critical path or other path that needs to be tested for timing margin. For example, in some scenarios, the timing margin of the path needs to be monitored, but the operating voltage does not need to be adjusted.

[0062] Optionally, the reference signal acquisition module includes a first trigger unit, and the first trigger unit is configured to output a reference signal according to rising edges of the transmission signal and the clock signal.

[0063] Figure 2 A schematic diagram of a reference signal acquisition module provided according to an embodiment of the present disclosure is shown.

[0064] exist Figure 2 In the embodiment, the reference signal acquisition module 200 includes a trigger unit 210. The trigger unit 210 is connected to the detected path so as to receive the transmission signal. The trigger unit 210 also receives a clock signal, for example, the trigger unit 210 is also connected to a clock.

[0065] The trigger unit 210 can output a reference signal according to the rising edge of the transmission signal and the clock signal, and the reference signal indicates that the transmission signal has jumped. The jump of the transmission signal can also be called a level flip, that is, the level value of the transmission signal changes from 0 to 1 or from 1 to 0. In this embodiment, the transmission signal jumps in the first clock cycle, and the reference signal indicates that the transmission signal jumps in the next clock cycle of the first clock cycle, and the first clock cycle may be any clock cycle. The first trigger unit in this embodiment can be implemented using the trigger unit 210.

[0066] Optionally, the trigger unit 210 can be implemented with a trigger, such as a D trigger. The transmission signal is an output signal of the end point of the detected path. The transmission signal is used as the input of the trigger, so that according to the rising edge of the clock signal, a reference signal with the same jump can be output in the next clock cycle of the clock cycle in which the transmission signal jumps.

[0067] Optionally, the reference signal acquisition module also includes a first XOR unit, which is connected to the detected path and is configured to perform an XOR operation on the transmission signal and the sampling result of the transmission signal to obtain a first XOR result, and input the first XOR result into the first trigger unit to obtain a reference signal.

[0068] Figure 3A A schematic diagram of another reference signal acquisition module provided according to an embodiment of the present disclosure is shown.

[0069] like Figure 3A As shown, the reference signal acquisition module 300 includes a trigger unit 310 and an XOR unit 320. The trigger unit 310 is connected to the XOR unit 320, and the XOR unit 320 is connected to the detected path. The XOR unit 320 performs an XOR operation on the transmission signal and the sampling result of the transmission signal to obtain an XOR result, and inputs the XOR result to the trigger unit 310 to obtain the reference signal.

[0070] In this embodiment, the waveforms of the transmission signal and the sampling result of the transmission signal are not necessarily the same, and there is a certain delay. The transmission signal is a signal transmitted in the detected path, and the sampling result of the transmission signal is an output signal obtained by sampling the transmission result at the end point of the detected path. For example, a sampler, a trigger, or other device may be used to sample the transmission signal.

[0071] For example, the XOR unit 320 can be implemented using a NAND gate or an XOR gate circuit, which is also implemented using firmware, hardware, or a combination thereof that can implement an XOR operation. The trigger unit 310 generates a reference signal based on the XOR result of the XOR unit 320 and the clock signal. The reference signal is used to indicate that a jump has occurred in the transmission signal. The reference signal can be designed to output a high level when the transmission signal jumps, and output a low level when the transmission signal does not jump; or it can be designed to output a low level when the transmission signal jumps, and output a high level when the transmission signal does not jump. Optionally, the trigger unit 310 can be implemented using a trigger, such as a D trigger.

[0072] In a possible implementation, a trigger is used to sample the transmission signal, and the trigger is a part of the detected path and does not belong to the reference signal acquisition module 300. The XOR unit 320 is connected to the input and output ends of the trigger, for example, the trigger is a D trigger, and the XOR unit 320 is connected to the D pin and Q pin of the D trigger.

[0073] Figure 3B FIG. 4 shows a timing diagram of a reference signal acquisition module 300 provided according to an embodiment of the present disclosure.

[0074] like Figure 3B As shown, CLK is a clock signal, and the figure also shows a transmission signal, a sampling result of the transmission signal, an input of the trigger unit 310, and an output of the trigger unit 310.

[0075] The input of the trigger unit 310 is the XOR result of the transmission signal and the sampling result of the transmission signal. When the transmission signal is at a low level and the sampling result of the transmission signal is at a high level, the input of the trigger unit 310 is at a high level. The trigger unit 310 starts to output a high level after the rising edge of the T2 clock cycle. The sampling result of the transmission signal starts to become a low level after the rising edge of the T2 clock cycle. Since the transmission signal and the sampling result of the transmission signal are both low levels during the T2 clock cycle, the input of the trigger unit 310 is a low level. Accordingly, after the rising edge of the T3 clock cycle arrives, the output of the trigger unit 310 becomes a low level. According to Figure 3B It can be seen that when the transmission signal jumps within the T1 clock cycle, the reference signal will have a high level with a length equal to or approximately equal to 1 clock cycle. Whether the transmission signal jumps can be determined based on the high level of the reference signal and the length corresponding to the high level.

[0076] In this embodiment, the reference signal can be simply acquired through an XOR unit and a trigger unit, which is low-cost and easy to implement.

[0077] Optionally, the reference signal acquisition module also includes a second trigger unit and a second XOR unit, the second trigger unit is configured to output a trigger signal based on the sampling result of the transmission signal and the rising edge of the clock signal; the second XOR unit is connected to the detected path and the second trigger unit, and is configured to perform an XOR operation on the sampling result of the transmission signal and the trigger signal to obtain a second XOR result, and input the second XOR result into the first trigger unit to obtain the reference signal.

[0078] Figure 4A A schematic diagram of another reference signal acquisition module provided according to an embodiment of the present disclosure is shown.

[0079] exist Figure 4AIn the embodiment, the reference signal acquisition module 400 includes a trigger unit 410, an XOR unit 420 and a trigger unit 430. The trigger unit 410 is similar to the trigger unit 310, and the relevant description of the trigger unit 310 can be referred to, which will not be expanded here. The XOR unit 420 is similar to the XOR unit 320, but the XOR unit 420 is connected to the trigger unit 430 and the output end of the trigger at the end of the detected path, and is not connected to the input end of the trigger at the end of the detected path.

[0080] The trigger unit 430 outputs a trigger signal according to the sampling result of the transmission signal and the rising edge of the clock signal. The XOR unit 420 generates an XOR result according to the sampling result of the transmission signal and the trigger signal of the trigger unit 430. The trigger unit 410 generates a reference signal according to the XOR result of the XOR unit 420 and the rising edge of the clock signal.

[0081] Figure 4B A timing diagram of the reference signal acquisition module 400 provided according to an embodiment of the present disclosure is shown.

[0082] Figure 4B 4 shows the CLK clock signal, the transmission signal, the sampling result of the transmission signal, the input and output of the trigger unit 430, and the input and output of the trigger unit 410 in the clock cycles T1, T2 and T3.

[0083] The input of the trigger unit 430 is the sampling result of the transmission signal, and the input of the trigger unit 410 is the XOR result of the sampling result of the transmission signal and the output signal (ie, the trigger signal) of the trigger unit 430. Figure 4B It can be seen that the transmission signal jumps in the T1 clock cycle, and the trigger unit 410 outputs the reference signal that jumps in the T3 clock cycle.

[0084] Figure 4A The reference signal acquisition module 400 in Figure 3A The reference signal acquisition module 300 shown is added with a trigger unit, which can further isolate the reference signal acquisition module from the detected path, so that the reference signal acquisition module will not affect the timing of the circuit in the detected path at all.

[0085] Optionally, the detection signal acquisition module includes a delay unit, a third XOR unit and a third trigger unit. The delay unit is connected to the detected path and is configured to receive a transmission signal, delay the transmission signal, and obtain a delayed signal; the third XOR unit is connected to the delay unit and is configured to perform an XOR operation on the sampling result of the transmission signal and the delayed signal to obtain a third XOR result; the third trigger unit is connected to the third XOR unit and is configured to output a detection signal according to the third XOR result and the rising edge of the clock signal.

[0086] Figure 5A A schematic diagram of a detection signal acquisition module provided according to an embodiment of the present disclosure is shown.

[0087] exist Figure 5A In the embodiment, the detection signal acquisition module 500 includes a delay unit 510, an XOR unit 520 and a trigger unit 530. The input end of the delay unit 510 is connected to the detected path, and the input signal of the delay unit 510 is the transmission signal. The output end of the delay unit 510 is connected to the XOR unit 520, and the output of the delay unit 510 is used as an input of the XOR unit 520. The other input end of the XOR unit 520 is connected to the output end of the trigger at the end of the detected path, that is, the other input of the XOR unit 520 is the sampling result of the transmission signal. The output end of the XOR unit 520 is connected to the trigger unit 530.

[0088] The delay unit 510 receives the transmission signal, performs delay processing on the transmission signal, and obtains the delayed signal. The XOR unit 520 performs an XOR operation on the sampling result of the transmission signal and the delayed signal to obtain an XOR result. The trigger unit 530 outputs a detection signal according to the XOR result and the rising edge of the clock signal.

[0089] In this embodiment, the delay unit 510 may be a delay circuit, and the trigger unit 530 may be a trigger, such as a D trigger. The delay duration of the delay unit 510 may be set and adjusted according to actual needs, and is not limited here. By delaying the transmission signal and whether the detection signal can normally output a high level, it can be determined whether the detected path has sufficient timing margin. When the detected path has sufficient timing margin, the trigger unit 530 can normally output a high level even if the transmission signal is delayed. When the detected path does not have sufficient timing margin, delaying the transmission signal will cause the trigger unit 530 to be unable to normally output a high level, that is, the detection signal does not output a high level. Therefore, based on the detection signal, it is possible to simply and accurately determine whether the timing margin of the detected path is sufficient.

[0090] Figure 5B A timing diagram of the detection signal acquisition module 500 provided in an embodiment of the present disclosure is shown.

[0091] Figure 5B FIG. 5 shows the CLK clock signal, the transmission signal, the sampling result of the transmission signal, the output of the delay unit 510 , and the input and output of the trigger unit 530 in the clock cycles T1 , T2 , and T3 .

[0092] like Figure 5BAs shown, the delay unit 510 delays the transmission signal, and the waveform of the output of the delay unit 510 is the same as the waveform of the transmission signal. The input of the trigger unit 530 is the XOR result of the output of the delay unit 510 and the sampling result of the transmission signal, so there is only a short high level in the T2 clock cycle. Since the input of the trigger unit 530 is a low level at the rising edge of the clock signal in the T2 and T3 clock cycles, the output of the trigger unit 530 is always a low level. That is, the detection signal is always a low level.

[0093] Optionally, the timing margin detection device further includes a sampling unit, which is connected to the detected path and configured to receive a transmission signal, sample the transmission signal, and obtain a sampling result of the transmission signal.

[0094] exist Figure 3A , Figure 4A and Figure 5A In the relevant description, a sampling unit may be provided at the end point of the detected path, which is considered to be a part of the detected path. In another implementation, the sampling unit may also belong to the timing margin detection device. For example, the timing margin detection device includes a reference signal acquisition module, a detection signal acquisition module and a sampling unit. With this implementation, there is no need to consider the design of the timing margin detection device during the design process of the detected path or even the entire chip. After completing the design of the detected path or the entire chip, the timing margin detection device can be used to replace the originally designed sampling unit to achieve the insertion of the timing margin detection device.

[0095] Optionally, at least one of the first trigger unit, the second trigger unit and the third trigger unit is implemented by a trigger. For example, one or more of the trigger unit 310, the trigger unit 410 and the trigger unit 510 in the above figure are implemented by a trigger, such as a D trigger.

[0096] Optionally, the timing margin detection device provided according to at least one embodiment of the present disclosure also includes a detection module, which is connected to the reference signal acquisition module and the detection signal acquisition module and is configured to determine the timing margin of the detected path based on the reference signal and the detection signal.

[0097] Figure 6 A schematic diagram of a timing margin detection device provided according to an embodiment of the present disclosure is shown.

[0098] like Figure 6 As shown, the timing margin detection device 600 includes a reference signal acquisition module 610 , a detection signal acquisition module 620 , a detection module 630 and optionally a sampling unit 640 .

[0099] The sampling unit 640 is depicted with a dotted line frame to indicate that the sampling unit 640 is selectable as a part of the timing margin detection device 600 or as a part of the detected path. The detected path is connected to the sampling unit 640. The reference signal acquisition module 610 can be implemented by using the reference signal acquisition module 300 or the reference signal acquisition module 400. Figure 6 6 shows a connection mode corresponding to the reference signal acquisition module 400, that is, the reference signal acquisition module 610 is connected to the output end of the sampling unit 640. The detection signal acquisition module 620 can be implemented by the above-mentioned detection signal acquisition module 500. The detection signal acquisition module 620 is connected to the input end and the output end of the sampling unit 640. The detection module 630 is connected to the output end of the reference signal acquisition module 610 and the output end of the detection signal acquisition module 620.

[0100] The detection module 630 determines the timing margin of the detected path according to the reference signal and the detection signal.

[0101] For example, the detection module 630 performs timing analysis on the reference signal and the detection signal to determine whether the reference signal and the detection signal jump, wherein when the reference signal jumps and the detection signal jumps, it is determined that the timing margin of the detected path is sufficient; when the reference signal jumps and the detection signal does not jump, it is determined that the timing margin of the detected path is insufficient.

[0102] For another example, the detection module 630 performs a timing analysis on the reference signal and the detection signal to determine whether the reference signal and the detection signal are at a high level, wherein when the reference signal and the detection signal are at a high level at the same time, it is determined that the timing margin of the detected path is sufficient; when the reference signal is at a high level but the detection signal is at a low level, it is determined that the timing margin of the detected path is insufficient.

[0103] In this embodiment, when the detection module 630 performs timing analysis on the reference signal and the detection signal, it can determine whether the timing margin is sufficient based on the transition of the signal or whether the signal is high level or low level. The conditions for determining the timing margin can be flexibly selected according to actual needs.

[0104] Optionally, the timing margin detection device provided according to at least one embodiment of the present disclosure further includes: an adjustment module, connected to the detection module, and configured to adjust the operating voltage of the detected path in response to the timing margin of the detected path.

[0105] For example, Figure 6 The timing margin detection device 600 may further include an adjustment module (not shown in the figure). The adjustment module is connected to the output end of the detection module 630, and the adjustment module adjusts the working voltage of the detected path according to the timing margin of the detected path.

[0106] For example, the detection module 630 may output a detection result of the timing margin, for example, using a high level to indicate that the timing margin is sufficient, and using a low level to indicate that the timing margin is insufficient, and vice versa.

[0107] After receiving the detection result input by the detection module 630, the adjustment module increases the operating voltage in response to insufficient timing margin of the detected path; and reduces the operating voltage or maintains the operating voltage in response to sufficient timing margin of the detected path. For example, the adjustment module can increase or reduce the operating voltage according to the delay time of the delay unit, or can perform a single operating voltage adjustment according to a preset voltage value, such as increasing the operating voltage by 0.1V each time.

[0108] Fig. 7A A schematic diagram of another timing margin detection device provided according to an embodiment of the present disclosure is shown.

[0109] like Fig. 7A As shown, the timing margin detection device 700 includes a reference signal acquisition module 710 , a detection signal acquisition module 720 and optionally a sampling unit 730 .

[0110] The sampling unit 730 is depicted with a dotted line frame to indicate that the sampling unit 730 is selectable as a part of the timing margin detection device 700 or as a part of the detected path. The detected path is connected to the sampling unit 730. The reference signal acquisition module 710 can be implemented by using the reference signal acquisition module 300 or the reference signal acquisition module 400. Fig. 7A , the connection mode corresponding to the reference signal acquisition module 400 is shown, that is, the reference signal acquisition module 710 is connected to the output end of the sampling unit 730. The detection signal acquisition module 720 can be implemented by the above-mentioned detection signal acquisition module 500. The detection signal acquisition module 720 is connected to the input end and the output end of the sampling unit 730. The output end of the reference signal acquisition module 710 and the output end of the detection signal acquisition module 720 can be connected to an external module for timing analysis.

[0111] In the digital circuit design stage, there is no need to consider the design related to the timing margin detection device provided in the embodiment of the present application. Instead, after completing the layout and wiring and timing analysis at the back end, find the critical path (or other path that needs to be detected by timing margin) in the chip or circuit module, and use the replacement method to directly replace the sampling unit at the end of the critical path with the timing margin detection device. In practical applications, the paths of digital circuits are various, so the sampling units of multiple paths in the chip or circuit module can be replaced as needed to achieve monitoring of multiple paths. In addition, the level of the digital circuit does not change in every clock cycle. If the level of the detected path does not change, the corresponding timing detection function cannot be completed. Therefore, when the timing margin detection device is actually deployed, it is necessary to set it in combination with the actual situation of the path, and set the timing margin detection device corresponding to the detected path with a higher level reversal rate, so as to ensure the detection effect when the chip or circuit module is working.

[0112] Figure 7B A schematic diagram showing an implementation of a timing margin detection device 700 provided according to an embodiment of the present disclosure is shown.

[0113] exist Figure 7B In the embodiment, the timing margin detection device includes 4 D flip-flops, 1 delay unit D1 and 2 XOR gates X1 and X2. The 4 D flip-flops are DFF1 to DFF4. DFF1 is a sampling unit at the end point of the critical path P1, that is, the input D of DFF1 is the transmission signal, and the output Q of DFF1 is the sampling result of the transmission signal. X1, DFF2 and DFF3 constitute a reference signal acquisition module. DFF4, D1 and X2 constitute a detection signal acquisition module. The output S1 of DFF2 is a reference signal, and the output S2 of DFF4 is a detection signal.

[0114] When the delay of the delay unit D1 is adjustable, the delay of the delay unit D1 can be adjusted according to the control signal. When the delay of the delay unit D1 is a fixed value, the interface of the control signal can be omitted. Optionally, the control signal of the delay unit D1 is generated by a direct logic controller (DLC).

[0115] Figure 7C A schematic diagram showing another implementation of a timing margin detection device 700 provided according to an embodiment of the present disclosure is shown. Fig.7D Shown as Figure 7C The timing diagram of the timing margin detection device is shown.

[0116] exist Figure 7CIn the embodiment, the timing margin detection device includes three D flip-flops, one delay unit D1 and two XOR gates X1 and X2. The three D flip-flops are DFF1~DFF3. DFF1 is a sampling unit at the end point of the critical path P1, that is, the input of DFF1 is the transmission signal, and the output of DFF1 is the sampling result of the transmission signal. DFF2 and X1 form a reference signal acquisition module. DFF3, D1 and X2 form a detection signal acquisition module. The output of DFF2 is a reference signal, and the output of DFF3 is a detection signal. Figure 7B The timing margin detection device shown is different. Figure 7C The reference signal acquisition module of the timing margin detection device shown is implemented using only one D flip-flop.

[0117] When the circuit is working normally, the critical path P1 will transmit the signal to the input of DFF1, and then transmit it to the output of DFF1 after being sampled by DFF1. The trigger DFF2 is connected to the input D and output Q of DFF1 through the XOR gate X1. The function of DFF2 is to detect whether the input signal of DFF1 has a jump. Every time the input D of DFF1 changes, a pulse signal of one clock cycle can be generated at the output Q of DFF2. The timing situation is as follows Fig.7D As shown. The function of DFF2 is to generate a reference signal to indicate whether there is a level reversal on the critical path P1. It is a reference output. Only when the level on the critical path is reversed can the delay of the critical path be sampled and monitored.

[0118] The critical path P1 to DFF3 has an additional delay of the delay unit D1 compared to the timing path P1 to DFF2. Therefore, when the delay of the critical path P1 is close to one clock cycle, the critical path P1 to DFF3 will first have a timing violation due to the existence of the additional delay unit D1. When the timing cannot be met, the output of DFF3 cannot generate a transition detection pulse of one clock cycle, while DFF2, which serves as a reference, can output the transition detection result normally. Fig.7D As shown in the figure, when the delay of D1 is large enough, DFF3 cannot complete the jump detection output. In this way, there will be two situations, one is that DFF2 and DFF3 both produce jump detection results, and the other is that DFF3 cannot produce jump detection results. These two situations correspond to different situations of chip critical path delay.

[0119] like Fig.7D As shown in the timing, if the critical path P1 to DFF1 can work properly, the following conditions must be met:

[0120] T Q +T P1 +T setup < Tclk

[0121] Among them, T Q is the delay of the register from the rising edge of the clock to the output Q, T P1 is the delay of the critical path P1, T setup is the start time required for the trigger, T clk is a clock cycle.

[0122] The conditions for DFF2 to correctly detect the transition are:

[0123] T Q +T P1 +T setup < T clk

[0124] This condition is consistent with the condition for normal operation of the circuit.

[0125] DFF3 can correctly detect the transition conditions:

[0126] T Q +T P1 + T D1 +T setup < T clk

[0127] T D1 It is the additional delay added by the delay unit.

[0128] Due to T D1 When the temperature or voltage changes and the timing of the circuit deteriorates, the detection function of DFF3 is affected first. If the function of DFF3 happens to be abnormal, the delay of the circuit will deteriorate further. D1 Only then will the function of the normal circuit DFF1 be affected. D1 can be designed as a variable delay adjustment circuit, and the delay size can be adjusted within the required range. D1 It is the margin of circuit delay, that is, the timing margin. D1 The size of the circuit delay margin can be controlled, thereby more accurately controlling the minimum operating voltage required by the chip.

[0129] like Figure 7B and Figure 7CThe timing margin detection device shown outputs a reference signal and a detection signal, and these two signals can be input into the analysis and control module of the adaptive voltage and frequency adjustment for adaptive voltage and frequency adjustment. The timing margin detection device can be used as a supplementary solution to the adaptive voltage and frequency adjustment solution. On the basis of reducing costs, more paths can be subjected to timing margin detection, which helps to more accurately control the chip voltage, thereby achieving the purpose of improving the chip energy efficiency and performance. In addition, the timing margin detection device is independent of the chip design or the circuit module design and the corresponding process, and the timing margin detection device can be added without adjusting the chip design or the circuit module design process. For example, in the chip design process, a sampling unit must be set at the end of the path. As long as the sampling unit is replaced, the timing margin detection device can be added to the chip.

[0130] Figure 8 A flowchart of a timing margin detection method provided according to an embodiment of the present disclosure is shown.

[0131] exist Figure 8 In the method 800 for detecting the timing margin, the method 800 includes steps S801 and S802:

[0132] Step S801, obtaining a reference signal according to a transmission signal of a detected path, wherein the detected path is connected to a timing margin detection device, and the reference signal indicates whether a jump occurs in the transmission signal.

[0133] Step S802, in response to a jump in the transmission signal, obtaining a detection signal corresponding to the transmission signal, wherein the detection signal is obtained after delaying the transmission signal, wherein the reference signal and the detection signal are used to determine whether the timing margin of the detected path is sufficient.

[0134] The execution method of step S801 and step S802 can refer to the relevant description of the timing margin detection device, which will not be repeated here. For example, step S801 and step S802 can be executed by the timing margin detection device mentioned above, or by the following Fig. 9 The timing margin detection device is executed in the embodiment of the present invention.

[0135] For example, optionally, the detected path is a critical path in the chip.

[0136] At least one embodiment of the present disclosure further provides a timing margin detection device, including at least one processing device and a memory; wherein a computer program is stored in the memory, and when the computer program is executed by at least one processing device, the above-mentioned timing margin detection method is implemented.

[0137] Fig. 9 A schematic structural diagram of a timing margin detection device provided according to an embodiment of the present disclosure is shown.

[0138] like Fig. 9 As shown, the timing margin detection device 900 includes a processing device 910 and a memory 920. The processing device 910 and the memory 920 are connected. The memory 920 stores a computer program, and when the computer program is executed by the processing device 910, the timing margin detection method described above, such as the timing margin detection method 800, is implemented.

[0139] In this embodiment, the number of processing devices in the timing margin detection device 900 is greater than or equal to one. Fig. 9 Only the processing device 910 is shown, but the timing margin detection device 900 can also include multiple processing devices, and the multiple processing devices are connected to the memory 920. The computer program can also be executed by at least one of the multiple processing devices to implement the above-mentioned timing margin detection method. For example, the processing device can be a single chip microcomputer, also known as a microcontroller unit (MCU) or a single chip microcomputer.

[0140] Fig.10 A schematic diagram of a chip provided according to an embodiment of the present disclosure is shown.

[0141] exist Fig.10 In the embodiment, the chip 1000 includes multiple clock domains, namely clock domains 1001 to 100N, where N is an integer greater than or equal to 2. Each clock domain includes a critical path, namely critical paths 1010 to 10N0. Each critical path is connected to a timing margin detection device (which may also be a timing margin detection device), namely timing margin detection devices 1011 to 10NN.

[0142] The timing margin detection devices 1011~10NN (a total of N timing margin detection devices) detect whether the timing margin of the corresponding critical paths 1010~10N0 is sufficient, and obtain the detection results. In one implementation, the timing margin detection devices 1011~10NN can adjust the operating voltage of the corresponding critical paths 1010~10N0. In another implementation, a voltage adjustment module can be set for the chip 1000, connected to all the timing margin detection devices, and the operating voltage of the corresponding critical path can be adjusted according to the detection results. That is, a voltage adjustment module is used to adjust the operating voltage of all critical paths.

[0143] In a chip according to at least one embodiment of the present disclosure, optionally, the chip includes multiple clock domains, and the detected path is a critical path of the object clock domain.

[0144] At least one embodiment of the present disclosure further provides an electronic device, including the chip of any of the above embodiments. For example, the electronic device includes the chip 1000 .

[0145] Fig.11 A schematic diagram of an electronic device provided according to an embodiment of the present disclosure is shown.

[0146] For example, Fig.11 As shown, in some examples, the electronic device 1100 includes a processing device (e.g., a central processing unit, a graphics processor, etc.) 1101, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1102 or a program loaded from a storage device 1108 to a random access memory (RAM) 1103. For example, the processing device may include a timing margin detection device (e.g., a timing margin detection circuit) of any embodiment of the present disclosure. Various programs and data required for the operation of the computer system are also stored in RAM1103. The processor 1101, ROM 1102, and RAM1103 are connected to each other via a bus 1104. An input / output (I / O) interface 1105 is also connected to the bus 1104.

[0147] For example, the following components may be connected to the I / O interface 1105: an input device 1106 including, for example, a touch screen, a touch pad, a keyboard, a mouse, a camera, a microphone, an accelerometer, a gyroscope, etc.; an output device 707 including, for example, a liquid crystal display (LCD), a speaker, a vibrator, etc.; a storage device 1108 including, for example, a magnetic tape, a hard disk, etc.; and a communication device 1109 which may also include, for example, a network interface card such as a LAN card, a modem, etc. The communication device 1109 may allow the electronic device 1100 to communicate with other devices wirelessly or by wire to exchange data, and perform communication processing via a network such as the Internet. The drive 1110 is also connected to the I / O interface 1105 as needed. A removable medium 1111, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 1110 as needed, so that a computer program read therefrom is installed into the storage device 1108 as needed.

[0148] For example, the electronic device 1100 may further include a peripheral interface (not shown in the figure), etc. The peripheral interface may be various types of interfaces, such as a USB interface, a lightning interface, etc. The communication device 1109 may communicate with a network and other devices through wireless communication, such as the Internet, an intranet and / or a wireless network such as a cellular phone network, a wireless local area network (LAN) and / or a metropolitan area network (MAN). Wireless communication may use any of a variety of communication standards, protocols, and techniques, including, but not limited to, Global System for Mobile Communications (GSM), Enhanced Data GSM Environment (EDGE), Wideband Code Division Multiple Access (W-CDMA), Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Bluetooth, Wi-Fi (e.g., based on IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, and / or IEEE 802.11n standards), Voice over Internet Protocol (VoIP), Wi-MAX, protocols for email, instant messaging, and / or Short Message Service (SMS), or any other suitable communication protocol.

[0149] The electronic devices in the embodiments of the present disclosure may include, but are not limited to, mobile terminals such as chips, components of chips, mobile phones, laptop computers, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), vehicle-mounted terminals (such as vehicle-mounted navigation terminals), etc., and fixed terminals such as digital TVs, desktop computers, etc. Fig.11 The electronic device shown is only an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0150] For example, the electronic device 1100 can be any device such as a mobile phone, a tablet computer, a laptop computer, an e-book, a game console, a television, a digital photo frame, a navigator, a server, etc., or it can be any combination of data processing devices and hardware, and the embodiments of the present disclosure are not limited to this.

[0151] Optionally, at least one embodiment of the present disclosure further provides a computer-readable storage medium on which computer-executable instructions are stored, wherein when the instructions are executed by a processor, the above-mentioned timing margin detection method 800 is implemented.

[0152] It should be noted that the computer-readable medium of the present disclosure may be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium may be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In an embodiment of the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program, which may be used by or in combination with an instruction execution system, device or device. In an embodiment of the present disclosure, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, in which a computer-readable program code is carried. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. Computer readable signal media may also be any computer readable medium other than computer readable storage media, which may send, propagate or transmit a program for use by or in conjunction with an instruction execution system, apparatus or device. The program code contained on the computer readable medium may be transmitted using any appropriate medium, including but not limited to: wires, optical cables, RF (radio frequency), etc., or any suitable combination of the above.

[0153] The computer-readable medium may be included in the electronic device, or may exist independently without being incorporated into the electronic device.

[0154] The basic principles of the present application are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present application are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present application. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, not for limitation, and the above details do not limit the present application to being implemented by adopting the above specific details.

[0155] It is worth noting that the step flow charts and the above method descriptions in this application are only illustrative examples and are not intended to require or imply that the steps of each embodiment must be performed in the order given, and some steps can be performed in parallel, independently of each other, or in other appropriate orders. In addition, words such as "secondly", "then", "next", etc. are not intended to limit the order of the steps; these words are only used to guide the reader to read through the descriptions of these methods.

[0156] The block diagrams of devices, apparatuses, equipment, and systems involved in this application are only illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. It should also be noted that in the apparatus and method of this application, each component or each step can be decomposed and / or recombined. These decompositions and / or recombinations should be regarded as equivalent solutions of this application.

[0157] In addition to the above non-limiting disclosure, the present disclosure also has the following points to be explained:

[0158] (1) The drawings of the embodiments of the present disclosure only relate to the structures involved in the embodiments of the present disclosure. Other structures may refer to the general design.

[0159] (2) In the absence of conflict, the embodiments of the present disclosure and the features therein may be combined with each other to obtain new embodiments.

[0160] The above are only specific implementations of the present disclosure, but the protection scope of the present disclosure is not limited thereto, and the protection scope of the present disclosure shall be based on the protection scope of the claims.

Claims

1. A timing margin detection device, comprising: A reference signal acquisition module, configured to acquire a reference signal according to a transmission signal of a detected path, wherein the detected path is connected to the timing margin detection device, and the reference signal indicates whether a jump occurs in the transmission signal; a detection signal acquisition module, configured to acquire a detection signal corresponding to the transmission signal in response to a jump of the transmission signal, wherein the detection signal is obtained after delaying the transmission signal, The reference signal and the detection signal are used to determine whether the timing margin of the detected path is sufficient.

2. The timing margin detection device according to claim 1, wherein: The detected path is a critical path in the chip, and the critical path is a detected path with the largest delay among multiple detected paths in a clock domain of the chip.

3. The timing margin detection device according to claim 1, wherein: The reference signal acquisition module comprises: The first trigger unit is configured to output the reference signal according to rising edges of the transmission signal and the clock signal.

4. The timing margin detection device according to claim 3, wherein: The reference signal acquisition module also includes: The first XOR unit is connected to the detected path and is configured to perform an XOR operation on the transmission signal and a sampling result of the transmission signal to obtain a first XOR result, and input the first XOR result into the first trigger unit to obtain the reference signal.

5. The timing margin detection device according to claim 3, wherein: The reference signal acquisition module also includes: a second trigger unit, configured to output a trigger signal according to a sampling result of the transmission signal and a rising edge of the clock signal; and The second XOR unit is connected to the detected path and the second trigger unit, and is configured to perform an XOR operation on the sampling result of the transmission signal and the trigger signal to obtain a second XOR result, and input the second XOR result into the first trigger unit to obtain the reference signal.

6. The timing margin detection device according to claim 1, wherein: The detection signal acquisition module comprises: a delay unit, connected to the detected path, configured to receive the transmission signal, perform delay processing on the transmission signal, and obtain a delayed signal; a third XOR unit connected to the delay unit and configured to perform an XOR operation on the sampling result of the transmission signal and the delayed signal to obtain a third XOR result; and The third trigger unit is connected to the third XOR unit and is configured to output the detection signal according to the third XOR result and the rising edge of the clock signal.

7. The timing margin detection device according to any one of claims 1 to 6, further comprising: The sampling unit is connected to the detected path and is configured to receive the transmission signal, sample the transmission signal, and obtain a sampling result of the transmission signal.

8. The timing margin detection device according to any one of claims 3 to 6, wherein: At least one of the first trigger unit, the second trigger unit and the third trigger unit is implemented by a trigger.

9. The timing margin detection device according to claim 1, further comprising: The detection module is connected to the reference signal acquisition module and the detection signal acquisition module, and is configured to determine the timing margin of the detected path according to the reference signal and the detection signal.

10. The timing margin detection device according to claim 9, further comprising: The adjustment module is connected to the detection module and is configured to adjust the operating voltage of the detected path in response to the timing margin of the detected path.

11. The timing margin detection device according to claim 9, wherein: The detection module is configured to perform timing analysis on the reference signal and the detection signal to determine whether a jump occurs between the reference signal and the detection signal, wherein: When the reference signal jumps and the detection signal jumps, determining that the timing margin of the detected path is sufficient; When the reference signal changes and the detection signal does not change, it is determined that the timing margin of the detected path is insufficient.

12. The timing margin detection device according to claim 10, wherein: The adjustment module is configured to: In response to the timing margin of the detected path being insufficient, increasing the operating voltage; and In response to the timing margin of the detected path being sufficient, the operating voltage is reduced or maintained.

13. A timing margin detection method, comprising: Acquire a reference signal according to a transmission signal of a detected path, wherein the detected path is connected to a timing margin detection device, and the reference signal indicates whether a jump occurs in the transmission signal; In response to a jump in the transmission signal, a detection signal corresponding to the transmission signal is acquired, wherein the detection signal is obtained after delaying the transmission signal. The reference signal and the detection signal are used to determine whether the timing margin of the detected path is sufficient.

14. The method according to claim 13, wherein: The detected path is a critical path in the chip, and the critical path is a detected path with the largest delay among multiple detected paths in a clock domain of the chip.

15. A timing margin detection device, comprising: at least one processing device and memory; Wherein, a computer program is stored in the memory, and when the computer program is executed by the at least one processing device, the method described in claim 13 or 14 is implemented.

16. A chip, comprising: The timing margin detection device according to any one of claims 1 to 12 or 15, wherein: The timing margin detection device is connected to the detected path of the chip.

17. The chip according to claim 16, wherein: The chip includes multiple clock domains, and the detected path is a critical path in the object clock domain, wherein the critical path is a path with the largest delay among multiple paths in the object clock domain.

18. An electronic device comprising the chip according to claim 16 or 17.

19. A computer-readable storage medium having computer-executable instructions stored thereon, wherein: When the instructions are executed by a processor, the method described in claim 13 or 14 is implemented.

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