A clockless four-port multi-address wafer acceptance test structure and test method thereof

Abstract

The present invention discloses a clockless four-port multi-address wafer acceptance test structure and a test method thereof. The test structure, which is composed of four ports, N triggers and N layers of tree-like gating circuits, successfully breaks through the limitations of the traditional test structure without any changes to the existing WAT test machine and test pin card. Through the cooperation of the four ports of the signal port, the beat port, the power supply port and the ground port with the test machine, and the ingenious combination of the trigger and the tree-like gating circuit, it is possible to efficiently test a large number (tens, hundreds or even thousands) of test structures, completely avoiding the time waste and resource consumption caused by repeated testing of TestKey, and greatly improving the test efficiency and flexibility.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor manufacturing, and in particular relates to a clock-free four-port multi-address wafer acceptance test structure and a test method thereof. Background Art

[0002] In the semiconductor wafer production process, WAT (Wafer Acceptance Test) is a crucial step, which includes two main levels:

[0003] TestKey representativeness: The TestKey in the WAT test completes the manufacturing process together with the chips on the wafer, and these test structures are designed to be "typical", which means that their test results can represent the performance of the same type of devices on the chip. For example, the higher the saturation current obtained by the WAT test, the higher the saturation current of the transistor inside the chip, which infers that the chip has a higher speed.

[0004] Process Monitoring: TestKey’s test structures focus on capturing process fluctuations and potential risks on the production line without taking on functions beyond testing. They can be designed with minimum process windows or specific lessons learned to target test structures that are sensitive to specific process steps.

[0005] Traditional WAT tests usually use a 24-pin test pin card, where each pin corresponds to an aluminum pad Al Pad of the TestKey. The Al Pad is directly connected to an end point of the test structure through a metal trace. The benefit of this direct connection is that it reduces the interference of other factors on the test, and the test logic is simple and easy to operate.

[0006] Although there are technologies like SRAM address selection circuits that can select between multiple structures, these circuits need to be driven by clock signals. Since the machine used for WAT testing does not have the ability to send clock signals, WAT testing can only be performed on a single structure. This results in a very limited content that can be tested by a TestKey. If a test structure requires 4 test PINs and can share the VDD PIN, then a TestKey with 24 PINs can only hold 7 such test structures. The 23 free positions formed between the 24 PINs can only be idle, and the other 16 PINs cannot be fully utilized. In the empty space of the test structure, even if the test structure is relatively small, it can only be filled with dummy and cannot be used for other tests because there are not enough pads PINs available.

[0007] The present invention aims to solve the limitations of the existing WAT test, that is, without changing the existing WAT test machine and test pin card, through an innovative technical solution, to achieve the test of any number of test structures while keeping the number of PINs used for the test unchanged. Summary of the invention

[0008] The object of the present invention is to overcome the above-mentioned deficiencies of the prior art and to provide a clock-free four-port multi-address wafer acceptance test structure and a test method thereof.

[0009] The present invention is implemented as follows: In a first aspect, the present invention provides a clockless four-port multi-address wafer acceptance test structure, comprising: 4 ports, N triggers, and N layers of tree-like gating circuits;

[0010] The four ports include a signal port, a beat port, a power supply port, and a ground port;

[0011] Among the N flip-flops, the clock input terminal of the first flip-flop is connected to the beat port among the four ports, the data input terminal is connected to the signal port among the four ports, the output terminal is connected to the control terminal of the first tree-shaped gating circuit, and the GND terminal is connected to the ground port among the four ports; the clock input terminals of the other flip-flops are connected to the beat port among the four ports, the data input terminals are connected to the output terminals of the previous flip-flop, the output terminals are connected to the control terminal of the tree-shaped gating circuit of the corresponding layer, and the GND terminals are connected to the ground port among the four ports;

[0012] In the N-layer tree-shaped gating circuit, the i-th tree-shaped gating circuit includes multiplexers Mux, i∈[1,N]; in the first layer of tree-like gating circuits, the two output ends of each multiplexer Mux are respectively connected to the input ends of the two multiplexers Mux in the next tree-like gating circuit, and the input ends are connected to the power supply ports among the four ports; in the other layers of tree-like gating circuits, the two output ends of each multiplexer Mux are respectively connected to the input ends of the two multiplexers Mux in the next tree-like gating circuit, and the input ends are connected to an output end of one of the multiplexers Mux in the previous tree-like gating circuit.

[0013] Preferably, among the four ports, the signal port provides an input signal; the beat port provides a beat to the trigger by pulling up or down the voltage; and the power supply port provides a test voltage.

[0014] Preferably, the N triggers are of the same model. The trigger is a D trigger, a JK trigger, an RS trigger or a T trigger, and preferably a JK trigger.

[0015] In a second aspect, the present invention provides a four-port multi-address wafer acceptance test method, the method comprising:

[0016] The wafer containing the above test structure is placed on a wafer acceptance test probe station, and a standard wafer acceptance test needle card is used to complete the connection between the wafer acceptance test machine and the test structure; wherein one output terminal of each multiplexer Mux in the last layer of the tree-like gating circuit of the test structure is connected to a device to be tested;

[0017] The wafer acceptance tester controls the signal port and the beat port among the four ports, and provides the test voltage for the power supply port; the selected DUT is tested;

[0018] After completing the test of the current device under test, modify the voltage state setting of the trigger by controlling the signal port and the beat port among the four ports, thereby modifying the selection of the multiplexer Mux, connecting another device under test, and testing it; repeat the current step process to complete the test of all devices under test.

[0019] Preferably, the controlling of the signal port and the beat port among the four ports by the wafer acceptance tester specifically includes: setting voltage states for N triggers by the signal port and the beat port to realize gating of the multiplexer Mux;

[0020] Preferably, the voltage states output by the N trigger output terminals are in the opposite order to the voltage states provided by their own signal terminals.

[0021] The beneficial effects of the present invention include at least the following:

[0022] (1) The present invention can utilize the existing WAT test machine and pin card, and can detect a large number of test structures without repeated testing of TestKey, thereby greatly improving the test efficiency and resource utilization.

[0023] (2) The present invention gets rid of the dependence on clock signals, uses beat signals and trigger characteristics to achieve Mux gating, simplifies the test architecture, avoids clock-related problems, and improves stability.

[0024] (3) The present invention does not require a clock or oscillation circuit, which reduces the risk of process deviation and synchronization problems caused by complex circuits and enhances the reliability of the test structure.

[0025] (4) Compared with the traditional multi-PIN control Mux strategy, the present invention can complete the selection with only 4 PINs, which greatly saves pin resources. It is especially suitable for complex test structures and reduces costs and design difficulty. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the technical solution of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0027] Figure 1 It is a schematic diagram of a circuit of a four-port multi-address wafer acceptance test structure provided by an embodiment of the present invention.

[0028] Figure 2 It is a flow chart of a four-port multi-address wafer acceptance test method provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0029] As known from the background technology, the existing WAT test cannot implement testing of multiple different test contents at one time.

[0030] Therefore, the present invention proposes a clockless four-port multi-address wafer acceptance test structure and a test method thereof, which innovatively uses a test structure composed of 4 ports, N triggers and N layers of tree-like gating circuits, and successfully breaks through the limitations of the traditional test structure without any changes to the existing WAT test machine and test pin card. Through the well-designed signal port, beat port, power supply port and ground port, the four ports work in coordination with the test machine, and the ingenious combination of triggers and tree-like gating circuits, it is possible to extremely efficiently test a large number (tens, hundreds or even thousands) of test structures, completely avoiding the time waste and resource consumption caused by repeated testing of TestKey, greatly improving the test efficiency and flexibility, and providing strong technical support for large-scale semiconductor wafer testing.

[0031] The present invention also cleverly utilizes the inherent characteristics of the trigger that the state changes only on the rising edge of the clock and the output can be delayed by one beat, thereby abandoning the dependence of traditional testing on the clock signal. By pulling up or down the voltage of the beat port, the beat signal is accurately provided to the trigger, thereby completing the configuration process of the trigger in an orderly manner. On this basis, the trigger can reliably control the multiplexer Mux in the multi-layer tree-like gating circuit to achieve accurate address gating and ensure the stable operation of the test process. This clock-free driving mechanism not only simplifies the overall architecture of the test system and reduces the hardware requirements for the test machine, but also significantly reduces the interference and potential fault points introduced by the clock signal, greatly improving the accuracy and stability of the test.

[0032] In addition, unlike the traditional scheme of forming an internal clock by using an internal crystal oscillator, RC oscillator circuit or ring oscillator, the present invention does not need to set up a clock circuit or oscillation circuit. This design effectively avoids the risk of large deviation or even failure of the oscillation circuit due to process problems, and completely solves the complex problems that may be encountered during the internal and external communication synchronization process. By reducing the complexity of the circuit and potential unstable factors, the stable and reliable operation of the test structure under various process conditions is effectively guaranteed, the maintenance cost and technical difficulty are reduced, and the product yield and production efficiency are improved.

[0033] Compared with the traditional strategy of simply relying on multiple PINs to directly control Mux, the present invention combines triggers with tree-like gating circuits, and only needs 4 PINs to realize the gating operation of any number of test structures. The traditional multi-PIN direct control method needs to calculate ceil (log2N) PINs according to the number of test structures, where ceil is an upward rounding function. As the number of test structures increases, the advantages of the present invention in saving pin resources become more and more prominent. This efficient PIN utilization method not only reduces the design complexity and manufacturing cost of the test pin card, but also reserves more pin resources for other functional modules or test structures on the wafer, improves the overall utilization efficiency of the wafer, and has important economic value and technical significance in the field of semiconductor manufacturing testing.

[0034] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0035] In the production process of semiconductor wafers, the implementation of wafer acceptance test (WAT) plays a vital role in ensuring product quality and performance. This embodiment provides a clock-free four-port multi-address wafer acceptance test structure, including: 4 ports, N triggers, and N layers of tree-like gating circuits; N>1;

[0036] The four ports include a signal port (hereinafter described by the Signal terminal PIN), a beat port (hereinafter described by the Meter terminal PIN), a power supply port (hereinafter described by the Vcore terminal PIN), and a ground port (hereinafter described by the GND terminal PIN); specifically:

[0037] The Signal terminal PIN provides an input signal, which enters the D port of the first trigger, providing an initial signal basis for the subsequent test process. For example, in actual testing, the input signal may carry specific test instructions or data information, which will be accurately transmitted and processed under the coordinated work of subsequent triggers and gating circuits, thereby achieving effective testing of the device under test.

[0038] The Meter PIN provides a beat to N triggers by pulling up or down the voltage. During the test startup phase, the Meter PIN will perform operations such as pulling up the voltage to 1.2V or pulling down to 0V (or close to 0V), which is defined as a beat.

[0039] The Vcore PIN provides the test voltage and is connected to the input of the multiplexer Mux in the first tree-shaped selection circuit; the path selected by Mux is also the path of Vcore. During the entire test process, the path selected by Mux is the voltage supply path from the Vcore PIN, thereby providing stable power support for each device in the test structure and ensuring the normal progress of the test.

[0040] The GND terminal PIN is the ground of all devices and does not share the GND with the test structure to avoid interference in the test.

[0041] Among the N triggers, in terms of trigger settings, the models of the N triggers remain consistent, covering various types such as D triggers, JK triggers, RS triggers, and T triggers, among which the JK trigger is the preferred solution. The clock input terminal of the first trigger is connected to the Meter terminal PIN, the data input terminal is connected to the Signal terminal PIN, the output terminal is connected to the control terminal of the first tree-like gating circuit, and the ground terminal is connected to the GND terminal PIN; the clock input terminals of other triggers are connected to the Meter terminal PIN, the data input terminals are connected to the output terminals of the previous trigger, the output terminals are connected to the control terminals of the corresponding layer of the tree-like gating circuit, and the ground terminal is connected to the GND terminal PIN; this cascaded trigger connection method ensures that signals and states can be accurately and orderly transmitted between triggers, thereby realizing precise control of the tree-like gating circuit.

[0042] In the N-layer tree-shaped gating circuit, the i-th tree-shaped gating circuit includes Multiplexers Mux, i∈[1,N]; in the first layer of tree-like gating circuit, the two output ends of each multiplexer Mux are respectively connected to the input ends of the two multiplexers Mux in the next tree-like gating circuit, and the input ends are connected to the Vcore PIN port; in other layers of tree-like gating circuits, the two output ends of each multiplexer Mux are respectively connected to the input ends of the two multiplexers Mux in the next tree-like gating circuit, and the input ends are connected to an output end of one of the multiplexers Mux in the previous tree-like gating circuit. Through this layer-by-layer, closely connected structural design, the tree-like gating circuit can accurately select one of the output ends according to the high and low level states of the trigger output, and finally realize the precise gating of the multiplexer Mux where the device under test is located.

[0043] This embodiment also provides a four-port multi-address wafer acceptance test method, see Figure 2 , including the following steps:

[0044] Place the wafer containing the above WAT test structure on the WAT probe station, and use the standard WAT test needle card to complete the connection between the test machine and the test structure; in this process, it is necessary to ensure that one output end of each multiplexer Mux in the last tree-like selection circuit of the test structure is accurately connected to a device under test.

[0045] After the connection is completed, the WAT tester is used to precisely control the Signal PIN and the Meter PIN, and to provide a stable test voltage for the Vcore PIN. At the beginning of the test, the device under test after strobing is comprehensively and carefully tested according to the established test process and signal rules. For example, the tester may send a specific signal sequence to the Signal PIN according to different test requirements, and provide a corresponding beat signal through the Meter PIN to drive the trigger and strobe circuit to work, thereby realizing the test and data collection of various performance indicators of the device under test;

[0046] After completing the test of the current device under test, the tester accurately controls the Signal PIN and the Meter PIN again, and adjusts the mux gating by modifying the voltage state setting of the trigger. Specifically, according to the signal and beat control logic described above, the state combination of the input signal and the beat signal is changed, so that the output state of the trigger changes accordingly, thereby connecting another device under test and testing it according to the same test process and standards. This cycle is repeated until the test of all devices under test is completed, ensuring that each device under test on the wafer is strictly and accurately tested, providing a reliable basis for the quality assessment of semiconductor wafers and the optimization of production processes.

[0047] In the specific implementation of the present invention, the trigger state change and the signal transmission law play a key role, which contains a complex and subtle logical relationship and plays an indispensable guiding role in the precise control of the entire test process. See Table 1, taking the JK trigger as an example, the details are as follows:

[0048] It can be clearly observed from Table 1 that in the test scenario taking the JK trigger as an example, with the orderly advancement of the beats provided by the Meter-side PIN and the dynamic change of the signal level of the Signal-side PIN, the status of each trigger presents a highly ordered evolution pattern that follows specific rules.

[0049] In the initial stage, all triggers are in a random state, which provides an initial uncertainty basis for subsequent state changes. When the Meter PIN gives the first beat, if the Signal PIN is high, the first trigger will copy the high level state according to its working principle, marked as "H". This process is the starting point of the entire signal transmission and state update, and its importance lies in laying the foundation for the subsequent step-by-step transmission of the trigger state.

[0050] As the beats continue to increase, at the second beat, the first trigger outputs the state "H" at the output end (Q end), and the Signal end PIN remains unchanged. This shows that after a beat delay, the first trigger accurately transfers the input signal state to the output end according to its design characteristics, reflecting the key characteristics of the trigger changing the state at the rising edge of the clock and delaying the output by one beat.

[0051] When the third beat arrives, the Signal PIN still maintains a high level. The first trigger maintains its original state because it does not receive a new trigger condition, while the second trigger begins to copy the state "H" of the Q end of the first trigger. This link demonstrates the cascade mechanism of state transfer between triggers, that is, the latter trigger can accurately capture the output state of the previous trigger, and copy and update it under specific beat conditions.

[0052] In the fourth beat, the second trigger outputs the state "H" copied from the input end to the Q end, making the Q end change to the state "H". This further verifies the accuracy and stability of the trigger state transmission. After every two beats, the signal can successfully propagate one level between the triggers. This orderly propagation method ensures that the entire test structure can work according to the predetermined logic.

[0053] Starting from the fifth beat, the Signal PIN changes to a low level state ("L"). According to the rules established by the first four beats, during the fifth and sixth beats, the first trigger outputs the state "L" at the Q end, and the Q end state of the second trigger remains unchanged because it copies the state of the previous level before these two beats. During this period, the third trigger copies the state of the second trigger and outputs it to its own Q end. This series of changes shows that when the signal level changes, the trigger can still strictly follow the established rules to update and transmit the state, reflecting the robustness of the entire system.

[0054] In the seventh and eighth beats, the same mechanism continues to work. The first trigger copies the signal of the Signal PIN to the Q end, the second trigger copies the Q end of the first trigger and outputs it to its own Q end, and each subsequent trigger continues to copy the state of the previous trigger and outputs it to its own Q end. This progressive state transfer method enables the precise setting of the state of any trigger through the precise control of the Signal PIN and the Meter PIN during the entire test process, and then effectively controls the multiplexer Mux in the tree-like gating circuit through the trigger, and finally achieves accurate gating and testing of the device under test.

[0055] Table 1

[0056] Meter Signal D1 Q1 D2 Q2 D3 Q3 D4 Q4 1 H H 2 H H H 3 H H H H 4 H H H H H 5 L L H H H H 6 L L L H H H H 7 L L L L H H H H 8 L L L L L H H H H 9 H H L L L L H H H 10 H H H L L L L H H 11 L L H H L L L L H 12 L L L H H L L L L 13 H H L L H H L L L 14 H H H L L H H L L 15 L L H H L L H H L 16 L L L H H L L H H 17 H H L L H H L L H 18 H H H L L H H L L 19 L L H H L L H H L 20 L L L H H L L H H

[0057] In actual semiconductor wafer test applications, assuming that a specific circuit module needs to be tested, the module may require a specific trigger state combination to activate the corresponding test path. By referring to the rules revealed in Table 1, testers can accurately control the signals and beats of the Signal PIN and the Meter PIN to ensure that each trigger is set according to the expected state, thereby successfully selecting the multiplexer Mux corresponding to the circuit module and realizing accurate testing of the module. This control method based on the detailed trigger state change information provided in Table 1 greatly improves the accuracy and reliability of the test, reduces test errors and invalid tests caused by incorrect test paths or improper state settings, and provides strong technical support for high-quality testing of semiconductor wafers. For example, with Figure 1 Take a 4-layer tree-like gating circuit and 4 flip-flops as an example. If you want the Q-end states of the four flip-flops to be L, L, H, L, the order of the signals sent is L, H, L, L.

[0058] Through such signal interaction and trigger state change mechanism, orderly processing and transmission of input signals are achieved, laying the foundation for subsequent test structure selection.

[0059] The multiplexer Mux in each layer of the tree-like gating circuit selects one of the output terminals through the high and low level states output by the trigger Q terminal, and directly reaches the gating of the multiplexer Mux where the device under test is located.

[0060] In summary, the implementation mode of the present invention effectively verifies the feasibility and advantages of the test structure and method in realizing multi-device testing, precise gating and utilizing existing equipment resources through close collaboration and precise control of the various parts of the structure, and provides an innovative and effective experimental paradigm for semiconductor wafer acceptance testing.

[0061] The above is a preferred embodiment of the present invention. It should be pointed out that a person skilled in the art can make several improvements and modifications without departing from the principle of the present invention. These improvements and modifications are also considered to be within the scope of protection of the present invention.

Claims

1. A clockless four-port multi-address wafer acceptance test structure, characterized in that include: 4 ports, N triggers, N layers of tree-like gating circuits; N＞1； The four ports include a signal port, a beat port, a power supply port, and a ground port; Among the N flip-flops, the clock input terminal of the first flip-flop is connected to the beat port among the four ports, the data input terminal is connected to the signal port among the four ports, the output terminal is connected to the control terminal of the first tree-shaped gating circuit, and the GND terminal is connected to the ground port among the four ports; the clock input terminals of the other flip-flops are connected to the beat port among the four ports, the data input terminals are connected to the output terminals of the previous flip-flop, the output terminals are connected to the control terminal of the tree-shaped gating circuit of the corresponding layer, and the GND terminals are connected to the ground port among the four ports; In the N-layer tree-shaped gating circuit, the i-th tree-shaped gating circuit includes multiplexers, i∈[1,N]; in the first layer of the tree-shaped gating circuit, the two output ends of each multiplexer are respectively connected to the input ends of the two multiplexers in the next tree-shaped gating circuit, and the input ends are connected to the power supply port; In the tree-like gating circuits of other layers, the two output ends of each multiplexer are respectively connected to the input ends of the two multiplexers in the next tree-like gating circuit, and the input end is connected to an output end of one of the multiplexers in the previous tree-like gating circuit.

2. The test structure according to claim 1, characterized in that: Among the four ports, the signal port provides an input signal; the beat port provides a beat to the trigger by pulling up or down the voltage; and the power supply port provides a test voltage.

3. The test structure according to claim 1, characterized in that: The N flip-flops are of the same model.

4. The test structure according to claim 1 or 3, characterized in that: The trigger is a D trigger, a JK trigger, an RS trigger or a T trigger.

5. A four-port multi-address wafer acceptance test method, characterized in that: The method comprises: Placing a wafer containing the test structure according to any one of claims 1 to 4 on a wafer acceptance test probe station, and using a standard wafer acceptance test needle card to complete the connection between the wafer acceptance tester and the test structure; wherein one output terminal of each multiplexer in the last layer of the tree-like gating circuit of the test structure is connected to a device to be tested; The wafer acceptance tester controls the signal port and the beat port among the four ports, and provides the test voltage for the power supply port among the four ports; and tests the device under test after being selected; After completing the test of the current device under test, modify the voltage state setting of the trigger by controlling the signal port and the beat port among the four ports, thereby modifying the multiplexer selection, connecting another device under test, and testing it; repeat the current step process until the test of all devices under test is completed.

6. The method according to claim 5, characterized in that: The control of the signal port and the beat port among the four ports by the wafer acceptance tester specifically includes: setting voltage states for N triggers by the signal port and the beat port to realize the gating of the multiplexer.

7. The method according to claim 5, characterized in that: The voltage states output by the N trigger output terminals are in the opposite order to the voltage states provided by the N trigger signal terminals.

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