Sample and hold circuit

Abstract

The present invention provides a sampling and holding circuit. The sampling and holding circuit includes: a sampling and holding module, an error detection module and a current compensation module. When the power tube of the high-voltage non-isolated power supply chip is turned on, the sampling and holding module is used to maintain its own output voltage based on a holding capacitor. When the power tube is turned off, the error detection module and the current compensation module work together to charge or discharge the holding capacitor to accelerate the process in which the output voltage of the sampling and holding module follows the first feedback voltage. Such a configuration allows the holding capacitor to select a capacitor with a larger capacitance when selecting the holding capacitor, so that the voltage can be stabilized during the holding stage; and in the sampling stage, the holding capacitor can quickly follow the sampling signal through an additional compensation current, which has sensitivity. The sampling and holding circuit takes into account both the two design goals of high precision and fast response, and solves the problems existing in the prior art.

Description

Technical Field

[0001] The invention relates to the technical field of power chip design, and in particular to a sampling and holding circuit. Background Art

[0002] For high-voltage non-isolated power chips with floating structures, there will be both voltage loops and current loops inside the chip to control the loops. The voltage loop control requires sampling the output voltage. However, for floating structures, the control chip process often uses a low-voltage process due to cost control. When the power tube is turned on, the ground of the chip under the floating structure is not connected to the ground of the system, and the voltage of the chip is also raised synchronously. It is impossible to monitor the output voltage in real time like a conventional BUCK topology. The output voltage can only be sampled when the power tube is turned off. Therefore, in order to ensure the normal operation of the loop, the usual practice is to add a sample-and-hold circuit between the feedback voltage and the loop.

[0003] In the field of power chip design, the sample-and-hold circuit is an important circuit structure, and its main function is to sample and hold the input signal for subsequent circuit processing. The sample-and-hold circuit can be divided into an open-loop structure and a closed-loop structure, among which the closed-loop structure is widely used because of its better stability and precision. In the field of sample-and-hold circuit design, bipolar process and field-effect transistor process are two commonly used processes. Compared with field-effect transistors, the switching speed of transistors in bipolar process is slower, whether it is P-tube or N-tube. Therefore, for bipolar sample-and-hold circuits, it is more necessary to provide a high-precision, fast-response circuit structure. In the sampling process, due to the offset voltage of the operational amplifier, the output voltage of the final sample-and-hold circuit will have a certain nonlinear error with the sampling voltage. The existing sample-and-hold circuit usually adopts an open-loop structure, which has poor stability and precision and cannot meet the control requirements of high-voltage non-isolated power chips.

[0004] Please refer to Figure 1 , Figure 1 In the figure, A represents a buffer amplifier with high input impedance. When Vc is the sampling level, switch S is turned on, the analog signal Vi charges CH through S, and the output voltage Vo tracks the changes of the analog signal; when Vc is the holding level, switch S is turned off, and the output voltage Vo remains at the input signal value at the moment the analog switch is turned off. The function of the buffer amplifier with high input impedance is to isolate CH from the load, otherwise the charge on CH during the holding stage will be discharged through the load, and the holding function cannot be achieved.

[0005] In summary, in bipolar technology, the sample-and-hold circuit in the prior art cannot achieve both high precision and fast response. Summary of the invention

[0006] The object of the present invention is to provide a sample-and-hold circuit to simultaneously achieve the two design goals of high precision and fast response and solve the problems existing in the prior art.

[0007] In order to solve the above technical problems, the present invention provides a sample-and-hold circuit, which is applied to a high-voltage non-isolated power supply chip. The sample-and-hold circuit includes: a sample-and-hold module, an error detection module and a current compensation module.

[0008] When the power tube of the high-voltage non-isolated power chip is turned on, the sampling and holding module is used to maintain its own output voltage based on a holding capacitor, and the error detection module and the current compensation module do not work.

[0009] When the power tube is turned off, the sampling and holding module is used to collect the first feedback voltage and make its own output voltage follow the first feedback voltage; the error detection module is used to calculate the difference between the output voltage of the sampling and holding module and the first feedback voltage and output a difference signal; the current compensation module is used to charge or discharge the holding capacitor based on the difference signal to accelerate the process of the output voltage of the sampling and holding module following the first feedback voltage.

[0010] The first feedback voltage is used to reflect the output voltage of the high-voltage non-isolated power supply chip.

[0011] Optionally, the sampling and holding circuit further includes: a clock module, wherein the clock module is used to output a clock signal, and the waveform of the clock signal is consistent with the waveform of the control signal of the power tube.

[0012] The sampling and holding module includes a working state switching terminal, which is used to obtain the clock signal to realize the switching of its own acquisition / holding state; the error detection module includes an error detection enabling terminal, which is used to obtain the clock signal to start or stop its own work.

[0013] Optionally, the sampling and holding module includes a first signal acquisition unit, the holding capacitor and a second signal acquisition unit.

[0014] The first signal acquisition unit includes an acquisition enable terminal, which is configured as the working state switching terminal; the first signal acquisition unit is used to output the voltage of the input terminal to the output terminal, and when the state of the power tube corresponding to the clock signal is off, the output terminal of the first signal acquisition unit is connected to the first end of the holding capacitor; when the state of the power tube corresponding to the clock signal is on, the output terminal of the first signal acquisition unit is disconnected from the first end of the holding capacitor; the second end of the holding capacitor is grounded.

[0015] The second signal acquisition unit is used to output the voltage of the input end to the output end; the first end of the holding capacitor is also connected to the input end of the second signal acquisition unit; the output end of the second signal acquisition unit is configured as the output end of the sampling and holding module.

[0016] Optionally, the error detection module includes: a first transistor, a current mirror unit and a transconductance amplifier.

[0017] The first transistor is an NPN transistor, the base of the first transistor is configured as the error detection enable terminal, the collector of the first transistor is connected to the first end of the current mirror unit, and the emitter of the first transistor is used for grounding.

[0018] The current mirror unit is used to obtain a first bias current through a first terminal and provide a bias current to the transconductance amplifier through a second terminal.

[0019] The transconductance amplifier is used to calculate the difference between the output voltage of the sampling and holding module and the first feedback voltage and output a difference current, and the difference current is configured as the difference signal.

[0020] Optionally, the current mirror unit includes a second transistor and a third transistor; the transconductance amplifier includes a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a tenth transistor and an eleventh transistor.

[0021] The second transistor is an NPN transistor, the collector of the second transistor is configured as the first end of the current mirror unit, the collector of the second transistor is connected to its base, and the emitter of the second transistor is used for grounding.

[0022] The third transistor is an NPN transistor, the base of the third transistor is connected to the base of the second transistor, and the emitter of the third transistor is used for grounding.

[0023] The fourth transistor and the fifth transistor are both PNP transistors, the collectors of the fourth transistor and the fifth transistor are both connected to the collector of the third transistor, the base of the fourth transistor is used to obtain the first feedback voltage, and the base of the fifth transistor is used to obtain the output voltage of the sampling and holding module.

[0024] The sixth transistor and the seventh transistor are both PNP transistors, the emitters of the sixth transistor and the seventh transistor are both used to connect to a power supply, the base of the sixth transistor is connected to the base of the seventh transistor, the base of the sixth transistor is also connected to its own collector, and the collector of the sixth transistor is connected to the emitter of the fourth transistor.

[0025] The thirteenth transistor and the eleventh transistor are both PNP transistors, the emitters of the thirteenth transistor and the eleventh transistor are both used to connect to a power supply, the base of the thirteenth transistor is connected to the base of the eleventh transistor, the base of the eleventh transistor is also connected to its own collector, and the collector of the eleventh transistor is connected to the emitter of the fifth transistor.

[0026] The eighth transistor and the ninth transistor are both NPN transistors, the emitters of the eighth transistor and the ninth transistor are both used for grounding, the base of the eighth transistor is connected to the base of the ninth transistor, the base of the eighth transistor is also connected to its own collector, the collector of the eighth transistor is connected to the collector of the seventh transistor, and the collector of the ninth transistor is connected to the collector of the tenth transistor.

[0027] The collector of the triode is also configured as the output end of the error detection module.

[0028] Optionally, the current compensation module includes a compensation current calculation unit and a compensation current generation unit, the compensation current calculation unit is used to amplify and stabilize the difference signal, and the compensation current generation unit is used to output the charging and discharging current of the holding capacitor.

[0029] Optionally, the error detection module and the compensation current generating unit together form a dual transconductance amplifier differential structure to offset nonlinear factors.

[0030] Optionally, the compensation current calculation unit includes a twelfth transistor, a thirteenth transistor, a fourteenth transistor, a fifteenth transistor, a sixteenth transistor and a first resistor.

[0031] The twelfth transistor and the thirteenth transistor are both PNP transistors, the emitters of the twelfth transistor and the thirteenth transistor are both used to connect to a power supply, the base of the twelfth transistor is connected to the base of the thirteenth transistor; the base of the twelfth transistor is also connected to its own collector.

[0032] The fourteenth transistor is an NPN transistor, the collector of the fourteenth transistor is connected to the collector of the twelfth transistor, the emitter of the fourteenth transistor is used to be grounded through the first resistor, and the base of the fourteenth transistor is used to obtain a reference voltage.

[0033] The fifteenth transistor and the sixteenth transistor are both NPN transistors, the emitters of the fifteenth transistor and the sixteenth transistor are both used for grounding, the base of the fifteenth transistor is connected to the base of the sixteenth transistor, the base of the fifteenth transistor is also connected to its own collector, the collector of the fifteenth transistor is connected to the collector of the thirteenth transistor, and the collector of the sixteenth transistor is used to connect to the compensation current generating unit.

[0034] Optionally, the compensation current generating unit includes a seventeenth transistor, an eighteenth transistor, a nineteenth transistor, a twenty-third transistor, a twenty-first transistor, a twenty-second transistor, a twenty-third transistor, a second resistor and a third resistor.

[0035] The seventeenth transistor, the eighteenth transistor and the nineteenth transistor are all PNP transistors, and emitters of the seventeenth transistor, the eighteenth transistor and the nineteenth transistor are all used to connect to a power supply.

[0036] The collector of the seventeenth transistor is used to connect to the compensation current calculation unit and to output the charging and discharging current of the holding capacitor.

[0037] The base of the eighteenth transistor is connected to the base of the seventeenth transistor, and the base of the eighteenth transistor is also connected to its own collector.

[0038] The base of the nineteenth transistor is connected to its collector.

[0039] The twenty-third transistor and the twenty-first transistor are both NPN transistors, the base of the twenty-third transistor is used to obtain a reference voltage, the base of the twenty-third transistor is also connected to the first end of the second resistor, the collector of the twenty-third transistor is connected to the collector of the eighteenth transistor; the collector of the twenty-first transistor is connected to the collector of the nineteenth transistor, the base of the twenty-first transistor is connected to the second end of the second resistor, and the base of the twenty-first transistor is also used to be grounded through the third resistor; the emitter of the twenty-third transistor is connected to the emitter of the twenty-first transistor.

[0040] The 22nd triode and the 23rd triode are both NPN triodes, the emitters of the 22nd triode and the 23rd triode are both used for grounding, the base of the 22nd triode is connected to the base of the 23rd triode, the base of the 22nd triode is also connected to its own collector, the collector of the 23rd triode is connected to the emitter of the 21st triode, and the collector of the 22nd triode is used to obtain a second bias current.

[0041] Optionally, the high-voltage non-isolated power supply chip also includes a voltage loop control module and a current loop control module, the current loop control module is used to output a current adjustment signal to the voltage loop control module based on a second feedback voltage; the voltage loop control module outputs a control signal of the power tube based on the output signal of the sampling and holding circuit, a reference voltage and the current adjustment signal; the second feedback voltage is used to reflect the current flowing through the power tube.

[0042] Compared with the prior art, the present invention provides a sampling and holding circuit, wherein the sampling and holding circuit includes: a sampling and holding module, an error detection module and a current compensation module. When the power tube of the high-voltage non-isolated power supply chip is turned on, the sampling and holding module is used to maintain its own output voltage based on a holding capacitor. When the power tube is turned off, the sampling and holding module is used to collect the first feedback voltage and make its own output voltage follow the first feedback voltage. The error detection module and the current compensation module work together to charge or discharge the holding capacitor to accelerate the process in which the output voltage of the sampling and holding module follows the first feedback voltage. Such a configuration allows the holding capacitor to select a capacitor with a larger capacitance value when selecting the holding capacitor, so that the voltage can be stabilized during the holding stage; and in the sampling stage, the holding capacitor can quickly follow the sampling signal through an additional compensation current, which has both sensitivity. The sampling and holding circuit takes into account both the two design goals of high precision and fast response, and solves the problems existing in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.

[0044] Figure 1 The invention is a circuit diagram of a sampling and holding circuit in the prior art.

[0045] Figure 2 It is a connection diagram of a high-voltage non-isolated power supply chip according to an embodiment of the present invention.

[0046] Figure 3 It is a waveform diagram of a high-voltage non-isolated floating buck topology according to an embodiment of the present invention.

[0047] Figure 4 1 is a connection diagram of a sample-and-hold circuit according to an embodiment of the present invention.

[0048] Figure 5 4 is a circuit diagram of an error detection module and a current compensation module according to an embodiment of the present invention.

[0049] Figure 6 4 is a waveform diagram of a sample-and-hold circuit according to an embodiment of the present invention.

[0050] Figure 7 It is a waveform diagram of a high-voltage non-isolated power supply chip according to an embodiment of the present invention.

[0051] Figure 8 It is a waveform diagram of a high voltage non-isolated power supply chip in the prior art.

[0052] in:

[0053] 1-sampling and holding circuit; 2-voltage loop control module; 3-current loop control module; 4-power tube; 11-sampling and holding module; 12-error detection module; 13-current compensation module; 14-clock module; 111-first signal acquisition unit; 112-second signal acquisition unit; 131-compensation current calculation unit; 132-compensation current generation unit. DETAILED DESCRIPTION

[0054] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0055] As used in the present invention, the singular forms "one", "an" and "the" include plural objects, the term "or" is generally used to include the meaning of "and / or", the term "several" is generally used to include the meaning of "at least one", and the term "at least two" is generally used to include the meaning of "two or more". In addition, the terms "first", "second" and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second" and "third" may explicitly or implicitly include one or at least two of the features, "one end" and "the other end" and "the proximal end" and "the distal end" generally refer to two corresponding parts, which include not only the endpoints, and the terms "installed", "connected" and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral body; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. In addition, as used in the present invention, an element disposed on another element generally only indicates that there is a connection, coupling, cooperation or transmission relationship between the two elements, and the connection, coupling, cooperation or transmission between the two elements may be direct or indirect through an intermediate element, and cannot be understood as indicating or implying the spatial position relationship between the two elements, that is, one element may be in any orientation such as inside, outside, above, below or on one side of another element, unless otherwise clearly indicated in the content. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0056] The core idea of ​​the present invention is to provide a sample-and-hold circuit to simultaneously achieve the two design goals of high precision and fast response, and solve the problems existing in the prior art.

[0057] The following description is given with reference to the accompanying drawings.

[0058] In order to solve the above technical problems, this embodiment provides a sample-and-hold circuit, which is applied to a high-voltage non-isolated power supply chip. This embodiment is designed based on a bipolar process. Figure 2 , the high-voltage non-isolated power supply chip includes: the sampling and holding circuit 1, the voltage loop control module 2, the current loop control module 3, the power tube 4, and the current sampling resistor RCS. The sampling and holding circuit 1 includes: the sampling and holding module 11, the error detection module 12 and the current compensation module 13. When the high-voltage non-isolated power supply chip is working, it also needs external voltage divider resistors Ra and Rb, freewheeling inductor L1, voltage regulator D1, and filter capacitor COUT. The voltage at the connection between L1 and Cout is the output voltage VOUT of the high-voltage non-isolated power supply chip. Figure 2In the following figures, the triangular ground symbol represents the chip ground, and the three horizontal line ground symbol represents the actual ground (represented by VEE). When the distinction can be made without ambiguity in the context, the text description content uses the ground as the name.

[0059] The overall topology application is a high-voltage non-isolated floating structure. The ground of the chip will float as the power tube is turned on and off, so the sampled VOUT voltage is a square wave that switches between high and low. A sample-and-hold circuit needs to be added to ensure the normal operation of the loop. When the power tube is turned off, the sample-and-hold circuit samples the voltage at the FB end to ensure the normal operation of the subsequent voltage loop control module; when the power tube is turned on, the sample-and-hold module stops working and maintains the FB voltage sampled at the last moment of the previous cycle.

[0060] The sample-and-hold voltage VSH (i.e., the output voltage of the sample-and-hold circuit) is the input signal of the voltage loop control module, which includes error amplifier, comparator, driver and other modules, and outputs a square wave with a certain driving capability. The current loop control module adjusts the duty cycle of the loop PWM square wave by sampling the voltage drop of the current flowing through the resistor RCS of the power tube. L1, D1, and COUT form a conventional buck topology.

[0061] That is, the current loop control module is used to output a current adjustment signal to the voltage loop control module based on the second feedback voltage (i.e., the voltage drop of the resistor RCS); the voltage loop control module outputs the control signal of the power tube based on the output signal of the sampling and holding circuit, the reference voltage and the current adjustment signal; the second feedback voltage is used to reflect the current flowing through the power tube.

[0062] Please refer to Figure 3 , Figure 3 This is the waveform of an ideal high-voltage non-isolated floating buck topology system. The application environment is an input voltage of 120V, a reference voltage of 1.25V, an output voltage of 5V, and an output current of IO=0.5A. The reference ground of all voltages is the ground of the chip, and the earth is defined as VEE. The loop works normally, and VFB is a voltage that fluctuates around the reference voltage. However, due to the floating structure, the FB and VOUT voltages will float as the power tube is turned on and off. Due to the presence of an ESD diode between FB and the GND pin of the chip, the FB voltage will be clamped to -0.7V when the power tube is turned on, see Figure 3 VSH is the sampling and holding voltage that fluctuates around 1.25V. No sampling is performed when the power tube is turned on. VOUT-VEE is the output voltage, IL is the current flowing through the inductor L1, and IO is the load current.

[0063] The sampling and holding circuit works according to the following logic: when the power tube of the high-voltage non-isolated power chip is turned on, the sampling and holding module is used to maintain its own output voltage based on a holding capacitor, and the error detection module and the current compensation module do not work. The term "not working" here should be understood in a broad sense, that is, not outputting a signal, or outputting a signal but the signal is 0, which can be understood as not working.

[0064] When the power tube is turned off, the sampling and holding module is used to collect the first feedback voltage VFB and make its own output voltage VSH follow the first feedback voltage VFB, the error detection module is used to calculate the difference between the output voltage VSH of the sampling and holding module and the first feedback voltage VFB and output a difference signal; the current compensation module is used to charge or discharge the holding capacitor based on the difference signal to accelerate the process of the output voltage VSH of the sampling and holding module following the first feedback voltage. The specific form of the difference signal is not limited.

[0065] The first feedback voltage VFB is used to reflect the output voltage of the high-voltage non-isolated power supply chip.

[0066] Please refer to Figure 4 The sampling and holding circuit also includes: a clock module 14, which is used to output a clock signal, and the waveform of the clock signal is consistent with the waveform of the control signal of the power tube.

[0067] The sampling and holding module includes a working state switching terminal, which is used to obtain the clock signal to realize the switching of its own acquisition / holding state; the error detection module includes an error detection enabling terminal, which is used to obtain the clock signal to start or stop its own work.

[0068] The sampling and holding module includes a first signal acquisition unit 111 , the holding capacitor C1 and a second signal acquisition unit 112 .

[0069] The first signal acquisition unit 111 includes an acquisition enable terminal, which is configured as the working state switching terminal; the first signal acquisition unit 111 is used to output the voltage of the input terminal to the output terminal, and when the state of the power tube corresponding to the clock signal is off, the output terminal of the first signal acquisition unit 11 is connected to the first end of the holding capacitor C1; when the state of the power tube corresponding to the clock signal is on, the output terminal of the first signal acquisition unit 111 is disconnected from the first end of the holding capacitor C1; the second end of the holding capacitor C1 is grounded.

[0070] The second signal acquisition unit 112 is used to output the voltage of the input end to the output end; the first end of the holding capacitor C1 is also connected to the input end of the second signal acquisition unit 112; the output end of the second signal acquisition unit 112 is configured as the output end of the sampling and holding module.

[0071] In one embodiment, the first signal acquisition unit 111 and the second signal acquisition unit 112 are implemented based on a buffer amplifier with high input impedance.

[0072] In this embodiment, the holding capacitor C1 needs to track the changing sampling voltage. A smaller capacitance value will cause the circuit to discharge faster in the holding state, which increases the voltage reduction rate in the holding state, thereby affecting the sampling accuracy of the system. Therefore, the present invention designs a sampling and holding circuit to stabilize the holding voltage V1 and output voltage VSH of the capacitor, thereby improving the accuracy and reliability of the system. Taking advantage of the characteristics of the signal follower with large input resistance and small output resistance, the input and output ends of the circuit are respectively connected to the signal follower. This design can ensure that the capacitor can be charged faster in the sampling state, speed up the charging time, and slow down the system discharge speed in the holding state.

[0073] Please refer to Figure 5 The error detection module 12 includes: a first transistor Q1, a current mirror unit and a transconductance amplifier.

[0074] The first transistor is an NPN transistor, the base of the first transistor is configured as the error detection enable terminal, the collector of the first transistor is connected to the first end of the current mirror unit, and the emitter of the first transistor is used for grounding.

[0075] The current mirror unit is used to obtain a first bias current Ibias1 through a first terminal, and provide a bias current to the transconductance amplifier through a second terminal.

[0076] It can be understood that based on the above description, when the base of the first transistor is at a high level, the first transistor is turned on and directly pulls away the first bias current Ibias1. At this time, the current mirror unit has no current input and naturally cannot provide bias current for the transconductance amplifier, so the transconductance amplifier does not work.

[0077] When the transconductance amplifier receives the bias current, the transconductance amplifier is used to calculate the difference between the output voltage VSH of the sample and hold module and the first feedback voltage VFB and output a difference current, and the difference current is configured as the difference signal.

[0078] The current mirror unit includes a second transistor Q2 and a third transistor Q3; the transconductance amplifier includes a fourth transistor Q4, a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7, an eighth transistor Q8, a ninth transistor Q9, a tenth transistor Q10 and an eleventh transistor Q11.

[0079] The second transistor is an NPN transistor, the collector of the second transistor is configured as the first end of the current mirror unit, the collector of the second transistor is connected to its base, and the emitter of the second transistor is used for grounding.

[0080] The third transistor is an NPN transistor, the base of the third transistor is connected to the base of the second transistor, and the emitter of the third transistor is used for grounding.

[0081] The fourth transistor and the fifth transistor are both PNP transistors, the collectors of the fourth transistor and the fifth transistor are both connected to the collector of the third transistor, the base of the fourth transistor is used to obtain the first feedback voltage, and the base of the fifth transistor is used to obtain the output voltage of the sampling and holding module.

[0082] The sixth transistor and the seventh transistor are both PNP transistors, the emitters of the sixth transistor and the seventh transistor are both used to connect to a power supply, the base of the sixth transistor is connected to the base of the seventh transistor, the base of the sixth transistor is also connected to its own collector, and the collector of the sixth transistor is connected to the emitter of the fourth transistor.

[0083] The thirteenth transistor and the eleventh transistor are both PNP transistors, the emitters of the thirteenth transistor and the eleventh transistor are both used to connect to a power supply, the base of the thirteenth transistor is connected to the base of the eleventh transistor, the base of the eleventh transistor is also connected to its own collector, and the collector of the eleventh transistor is connected to the emitter of the fifth transistor.

[0084] The eighth transistor and the ninth transistor are both NPN transistors, the emitters of the eighth transistor and the ninth transistor are both used for grounding, the base of the eighth transistor is connected to the base of the ninth transistor, the base of the eighth transistor is also connected to its own collector, the collector of the eighth transistor is connected to the collector of the seventh transistor, and the collector of the ninth transistor is connected to the collector of the tenth transistor.

[0085] The collector of the triode is also configured as the output end of the error detection module. The collector of the triode outputs the difference signal, that is, I1.

[0086] The current compensation module includes a compensation current calculation unit 131 and a compensation current generation unit 132. The compensation current calculation unit 132 is used to amplify and stabilize the difference signal, and the compensation current generation unit is used to output the charge and discharge current of the holding capacitor.

[0087] Furthermore, the error detection module and the compensation current generating unit together form a dual transconductance amplifier differential structure to offset nonlinear factors.

[0088] The compensation current calculation unit includes a twelfth transistor Q12, a thirteenth transistor Q13, a fourteenth transistor Q14, a fifteenth transistor Q15, a sixteenth transistor Q16 and a first resistor R1.

[0089] The twelfth transistor and the thirteenth transistor are both PNP transistors, the emitters of the twelfth transistor and the thirteenth transistor are both used to connect to a power supply, the base of the twelfth transistor is connected to the base of the thirteenth transistor; the base of the twelfth transistor is also connected to its own collector.

[0090] The fourteenth transistor is an NPN transistor, the collector of the fourteenth transistor is connected to the collector of the twelfth transistor, the emitter of the fourteenth transistor is used to be grounded through the first resistor, and the base of the fourteenth transistor is used to obtain the reference voltage VREF.

[0091] The fifteenth transistor and the sixteenth transistor are both NPN transistors, the emitters of the fifteenth transistor and the sixteenth transistor are both used for grounding, the base of the fifteenth transistor is connected to the base of the sixteenth transistor, the base of the fifteenth transistor is also connected to its own collector, the collector of the fifteenth transistor is connected to the collector of the thirteenth transistor, and the collector of the sixteenth transistor is used to connect to the compensation current generating unit.

[0092] The compensation current generating unit includes a seventeenth transistor Q17, an eighteenth transistor Q18, a nineteenth transistor Q19, a twenty-third transistor Q20, a twenty-first transistor Q21, a twenty-second transistor Q22, a twenty-third transistor Q23, a second resistor R2 and a third resistor R3.

[0093] The seventeenth transistor, the eighteenth transistor and the nineteenth transistor are all PNP transistors, and emitters of the seventeenth transistor, the eighteenth transistor and the nineteenth transistor are all used to connect to a power supply.

[0094] The collector of the seventeenth transistor is used to connect to the compensation current calculation unit and to output the charging and discharging current of the holding capacitor.

[0095] The base of the eighteenth transistor is connected to the base of the seventeenth transistor, and the base of the eighteenth transistor is also connected to its own collector.

[0096] The base of the nineteenth transistor is connected to its collector.

[0097] The twenty-third transistor and the twenty-first transistor are both NPN transistors, the base of the twenty-third transistor is used to obtain the reference voltage VREF, the base of the twenty-third transistor is also connected to the first end of the second resistor, the collector of the twenty-third transistor is connected to the collector of the eighteenth transistor; the collector of the twenty-first transistor is connected to the collector of the nineteenth transistor, the base of the twenty-first transistor is connected to the second end of the second resistor, and the base of the twenty-first transistor is also used to be grounded through the third resistor; the emitter of the twenty-third transistor is connected to the emitter of the twenty-first transistor.

[0098] The twenty-second transistor and the twenty-third transistor are both NPN transistors, the emitters of the twenty-second transistor and the twenty-third transistor are both used for grounding, the base of the twenty-second transistor is connected to the base of the twenty-third transistor, the base of the twenty-second transistor is also connected to its own collector, the collector of the twenty-third transistor is connected to the emitter of the twenty-first transistor, and the collector of the twenty-second transistor is used to obtain the second bias current Ibias2.

[0099] Based on the above circuit structure, the working logic of the sampling and holding circuit is as follows: when the clock signal CLK is high, Q1 pulls Ibias1, and the error detection module does not work; when the clock signal CLK is low, I1=Gm1*(VFB-VSH). Wherein, Gm1 is the amplification factor of the transconductance amplifier.

[0100] The current flowing through Q14 is I2 = (VREF-Vbe) / R1, where Vbe is the diode junction voltage drop; the current flowing through Q12 is I3 = I2-I1. The ratio of the emitter junction area of ​​Q12 and Q13 is K1, and the ratio of the emitter junction area of ​​Q15 and Q16 is K2. Therefore, the current flowing through Q16 is I4 = K1*K2*I3 = K1*K2*((VREF-Vbe) / R1- Gm1*(VFB-VSH)).

[0101] The VREF voltage and resistor voltage divider generate the reference current IREF, which is the current flowing through Q17. Ibias2 is the reference current with a good temperature coefficient.

[0102] The current size IREF=Gm2*VREF*(R2 / (R2+R3)).

[0103] When the module is working, when VFB>VSH, I4<IREF,IOUT> 0, the module charges the external sampling capacitor; when VFB<VSH,I4> IREF, IOUT<0, the sampling capacitor discharges Q16; the charging current is IOUT1 and the discharging current is IOUT2.

[0104] The charging current IOUT1=IREF-I4, and the discharging current IOUT2=I4-IREF.

[0105] In summary, in order to ensure the linearity of the signal and further improve the accuracy of the module, the current compensation module composed of the compensation current calculation unit and the compensation current generation unit is introduced, and the differential structure of the dual OTA is used to offset the nonlinear factors, so that the relationship between the change of the sampling voltage and the change of the output current is more linear; suppressing the common mode signal, the dual OTA can ensure that the common mode noise is suppressed to a greater extent in the case of power supply noise interference. The compensation current calculation unit further amplifies the current after the error amplification of the detection VFB and VSH through the current mirror, and then compares it with the current IREF to obtain the required compensation current. This technology enhances the controllability of the charging current, and can flexibly adjust the maximum value of the charging current according to actual needs, improve the adaptability and flexibility of the module, and on the other hand, it also improves the performance and reliability of the circuit, meeting the requirements of the sampling and holding circuit for high precision and high stability.

[0106] Figure 6 is the compensation current result of the module. Combined with the voltage and current waveforms, the compensation amount is IOUT*△T / C1, △T is the power tube shutdown time, C1 is the sampling capacitor. VFB is the voltage to be sampled, VA is the voltage when the power tube is turned off at t1, and VB is the voltage when the power tube is turned off at t2. CLK is the time when the power tube is turned on when high, and CLK is the time when the power tube is turned off when low. VSH is the output voltage of the sample and hold circuit.

[0107] In the high-voltage non-isolated floating buck topology, the sample-and-hold circuit designed above can accurately capture the instantaneous voltage signal, ensuring that accurate feedback data is provided to the control system in a high-voltage, complex floating buck environment.

[0108] The error compensation and sampling and holding voltage of the system within a single cycle are as follows: Figure 7As shown. IO is the load current, and SW is the switching voltage waveform of the power tube. When the power tube is turned on at t3, the sampling and holding module does not sample VFB at this time. Due to the physical characteristics of the bipolar device itself, parasitic resistance and capacitor leakage, manufacturing process material defects, etc., the voltage of VSH will not stabilize at the VFB voltage before the power tube is turned on, but will gradually decrease. When the power tube is turned off again at t4, the sampling and holding module starts to sample the VFB voltage, and the internal compensation current IOUT of the module charges the sampling capacitor to ensure that the VSH voltage in the sampling stage quickly follows the VFB voltage, improve the high precision of the module and the stability of the system, and increase the system speed. The compensated sampling and holding voltage remains stable, avoiding errors caused by signal fluctuations, thereby achieving more accurate voltage adjustment in the high-voltage non-isolated system topology, improving power conversion efficiency, reducing output voltage ripple and electromagnetic interference caused by inaccurate sampling, optimizing system performance, and meeting application scenarios with high-precision power requirements.

[0109] Figure 8 The relevant waveforms of the high voltage non-isolated power chip in the prior art are shown. Comparing this embodiment with the prior art, it is found that in the prior art, when the power tube is turned on for the second time (relative to Figure 8 When VSH is turned off, the speed of VSH rising is slow and cannot reflect VFB in real time, which may lead to poor feedback control effect based on VSH design. Figure 8 It only shows one possible prior art. In other prior arts, the capacitance of the holding capacitor may not be large enough, which may cause the VSH to drop too fast when the power tube is turned off, resulting in a poor holding effect.

[0110] The beneficial effects of the technical solution are as follows: 1. The present invention adopts a bipolar process to provide a sampling and holding circuit for a high-voltage non-isolated power supply chip, introduces a closed-loop feedback structure, compares and adjusts the output signal with the input signal, reduces errors, and improves accuracy. This design effectively solves the problem of slow transistor switching speed in bipolar technology and provides a high-precision, fast-response circuit structure. 2. The present invention compares the input feedback FB voltage with the output holding voltage through an error detection circuit, generates a fixed current through a transconductance amplifier and compares the difference with the reference current, and finally adds the calculated difference current to the capacitor to compensate for the charging and discharging of the capacitor, achieving fast follow-up, compensation accuracy and speed. This design effectively improves the stability and accuracy of the sampling and holding circuit and meets the control requirements of the high-voltage non-isolated power supply chip. 3. The sampling and holding circuit of the present invention adopts a closed-loop structure, which has better stability and accuracy than the existing open-loop structure, and can better ensure the normal operation of the high-voltage non-isolated power supply chip. At the same time, the sampling and holding circuit of the present invention has a simple structure, is easy to implement, and has high practical value.

[0111] In summary, in a sampling and holding circuit provided in this embodiment, the sampling and holding circuit includes: a sampling and holding module, an error detection module and a current compensation module. When the power tube of the high-voltage non-isolated power supply chip is turned on, the sampling and holding module is used to maintain its own output voltage based on a holding capacitor. When the power tube is turned off, the sampling and holding module is used to collect the first feedback voltage and make its own output voltage follow the first feedback voltage. The error detection module and the current compensation module work together to charge or discharge the holding capacitor to accelerate the process of the output voltage of the sampling and holding module following the first feedback voltage. Such a configuration allows the holding capacitor to select a capacitor with a larger capacitance when selecting, so that the voltage can be stabilized in the holding stage; and in the sampling stage, the additional compensation current is used to enable the holding capacitor to quickly follow the sampling signal, which has both sensitivity. The sampling and holding circuit takes into account both the two design goals of high precision and fast response, and solves the problems existing in the prior art.

[0112] The above description is only a description of the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the technical solution of the present invention.

Claims

1. A sample-and-hold circuit, characterized in that: The sampling and holding circuit is applied to a high-voltage non-isolated power supply chip, and the sampling and holding circuit comprises: a sampling and holding module, an error detection module and a current compensation module; When the power tube of the high-voltage non-isolated power chip is turned on, the sampling and holding module is used to maintain its own output voltage based on a holding capacitor, and the error detection module and the current compensation module do not work; When the power tube is turned off, the sampling and holding module is used to collect the first feedback voltage and make its own output voltage follow the first feedback voltage; the error detection module is used to calculate the difference between the output voltage of the sampling and holding module and the first feedback voltage and output a difference signal; the current compensation module is used to charge or discharge the holding capacitor based on the difference signal to accelerate the process in which the output voltage of the sampling and holding module follows the first feedback voltage; The first feedback voltage is used to reflect the output voltage of the high-voltage non-isolated power supply chip; The sampling and holding circuit further includes: a clock module, the clock module is used to output a clock signal, the waveform of the clock signal is consistent with the waveform of the control signal of the power tube; The sampling and holding module includes a working state switching terminal, which is used to obtain the clock signal to realize the switching of its own acquisition / holding state; the error detection module includes an error detection enabling terminal, which is used to obtain the clock signal to start or stop its own work.

2. The sample-and-hold circuit according to claim 1, characterized in that: The sampling and holding module includes a first signal acquisition unit, the holding capacitor and a second signal acquisition unit; The first signal acquisition unit includes an acquisition enable terminal, which is configured as the working state switching terminal; the first signal acquisition unit is used to output the voltage of the input terminal to the output terminal, and when the state of the power tube corresponding to the clock signal is off, the output terminal of the first signal acquisition unit is connected to the first terminal of the holding capacitor; when the state of the power tube corresponding to the clock signal is on, the output terminal of the first signal acquisition unit is disconnected from the first terminal of the holding capacitor; the second terminal of the holding capacitor is grounded; The second signal acquisition unit is used to output the voltage of the input end to the output end; the first end of the holding capacitor is also connected to the input end of the second signal acquisition unit; the output end of the second signal acquisition unit is configured as the output end of the sampling and holding module.

3. The sample-and-hold circuit according to claim 1, characterized in that: The error detection module includes: a first triode, a current mirror unit and a transconductance amplifier; The first transistor is an NPN transistor, the base of the first transistor is configured as the error detection enable terminal, the collector of the first transistor is connected to the first end of the current mirror unit, and the emitter of the first transistor is used for grounding; The current mirror unit is used to obtain a first bias current through a first terminal and provide a bias current to the transconductance amplifier through a second terminal; The transconductance amplifier is used to calculate the difference between the output voltage of the sampling and holding module and the first feedback voltage and output a difference current, and the difference current is configured as the difference signal.

4. The sample-and-hold circuit according to claim 3, characterized in that: The current mirror unit includes a second triode and a third triode; the transconductance amplifier includes a fourth triode, a fifth triode, a sixth triode, a seventh triode, an eighth triode, a ninth triode, a tenth triode and an eleventh triode; The second transistor is an NPN transistor, the collector of the second transistor is configured as the first end of the current mirror unit, the collector of the second transistor is connected to its base, and the emitter of the second transistor is used for grounding; The third transistor is an NPN transistor, the base of the third transistor is connected to the base of the second transistor, and the emitter of the third transistor is used for grounding; The fourth transistor and the fifth transistor are both PNP transistors, the collectors of the fourth transistor and the fifth transistor are both connected to the collector of the third transistor, the base of the fourth transistor is used to obtain the first feedback voltage, and the base of the fifth transistor is used to obtain the output voltage of the sampling and holding module; The sixth triode and the seventh triode are both PNP triodes, the emitters of the sixth triode and the seventh triode are both used to connect to a power supply, the base of the sixth triode is connected to the base of the seventh triode, the base of the sixth triode is also connected to its own collector, and the collector of the sixth triode is connected to the emitter of the fourth triode; The thirteenth transistor and the eleventh transistor are both PNP transistors, the emitters of the thirteenth transistor and the eleventh transistor are both used to connect to a power supply, the base of the thirteenth transistor is connected to the base of the eleventh transistor, the base of the eleventh transistor is also connected to its own collector, and the collector of the eleventh transistor is connected to the emitter of the fifth transistor; The eighth transistor and the ninth transistor are both NPN transistors, the emitters of the eighth transistor and the ninth transistor are both grounded, the base of the eighth transistor is connected to the base of the ninth transistor, the base of the eighth transistor is also connected to its collector, the collector of the eighth transistor is connected to the collector of the seventh transistor, and the collector of the ninth transistor is connected to the collector of the tenth transistor; The collector of the triode is also configured as the output end of the error detection module.

5. The sample-and-hold circuit according to claim 1, characterized in that: The current compensation module includes a compensation current calculation unit and a compensation current generation unit. The compensation current calculation unit is used to amplify and stabilize the difference signal, and the compensation current generation unit is used to output the charging and discharging current of the holding capacitor.

6. The sample-and-hold circuit according to claim 5, characterized in that: The error detection module and the compensation current generating unit together form a dual transconductance amplifier differential structure to offset nonlinear factors.

7. The sample-and-hold circuit according to claim 5, characterized in that: The compensation current calculation unit includes a twelfth triode, a thirteenth triode, a fourteenth triode, a fifteenth triode, a sixteenth triode and a first resistor; The twelfth triode and the thirteenth triode are both PNP triodes, the emitters of the twelfth triode and the thirteenth triode are both used to connect to a power supply, the base of the twelfth triode is connected to the base of the thirteenth triode; the base of the twelfth triode is also connected to its own collector; The fourteenth transistor is an NPN transistor, the collector of the fourteenth transistor is connected to the collector of the twelfth transistor, the emitter of the fourteenth transistor is used to be grounded through the first resistor, and the base of the fourteenth transistor is used to obtain a reference voltage; The fifteenth transistor and the sixteenth transistor are both NPN transistors, the emitters of the fifteenth transistor and the sixteenth transistor are both used for grounding, the base of the fifteenth transistor is connected to the base of the sixteenth transistor, the base of the fifteenth transistor is also connected to its own collector, the collector of the fifteenth transistor is connected to the collector of the thirteenth transistor, and the collector of the sixteenth transistor is used to connect to the compensation current generating unit.

8. The sample-and-hold circuit according to claim 5, characterized in that: The compensation current generating unit includes a seventeenth triode, an eighteenth triode, a nineteenth triode, a twenty-third triode, a twenty-first triode, a twenty-second triode, a twenty-third triode, a second resistor and a third resistor; The seventeenth transistor, the eighteenth transistor and the nineteenth transistor are all PNP transistors, and the emitters of the seventeenth transistor, the eighteenth transistor and the nineteenth transistor are all used to connect to a power supply; The collector of the seventeenth transistor is used to connect to the compensation current calculation unit and to output the charge and discharge current of the holding capacitor; The base of the eighteenth transistor is connected to the base of the seventeenth transistor, and the base of the eighteenth transistor is also connected to its own collector; The base of the nineteenth transistor is connected to its collector; The twenty-third transistor and the twenty-first transistor are both NPN transistors, the base of the twenty-third transistor is used to obtain a reference voltage, the base of the twenty-third transistor is also connected to the first end of the second resistor, the collector of the twenty-third transistor is connected to the collector of the eighteenth transistor; the collector of the twenty-first transistor is connected to the collector of the nineteenth transistor, the base of the twenty-first transistor is connected to the second end of the second resistor, and the base of the twenty-first transistor is also used to be grounded through the third resistor; the emitter of the twenty-third transistor is connected to the emitter of the twenty-first transistor; The 22nd triode and the 23rd triode are both NPN triodes, the emitters of the 22nd triode and the 23rd triode are both used for grounding, the base of the 22nd triode is connected to the base of the 23rd triode, the base of the 22nd triode is also connected to its own collector, the collector of the 23rd triode is connected to the emitter of the 21st triode, and the collector of the 22nd triode is used to obtain a second bias current.

9. The sample-and-hold circuit according to claim 1, characterized in that: The high-voltage non-isolated power supply chip also includes a voltage loop control module and a current loop control module. The current loop control module is used to output a current adjustment signal to the voltage loop control module based on a second feedback voltage; the voltage loop control module outputs a control signal of the power tube based on the output signal of the sampling and holding circuit, a reference voltage and the current adjustment signal; the second feedback voltage is used to reflect the current flowing through the power tube.

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