A CMOS switch circuit

Abstract

The present application relates to a CMOS switch circuit, including a switch module and a terminal potential control module; the switch module includes first to fourth transistors; the types of the first and third transistors are complementary to the types of the second and fourth transistors; the output end of the switch module is electrically connected to the input end of the terminal potential control module and the circuit outside the switch module and the terminal potential control module; the multiple output ends of the terminal potential control module are electrically connected to the substrates of the first and third transistors, the substrates of the second and fourth transistors, the nodes between the first and second transistors, and the nodes between the third and fourth transistors respectively; the terminal potential control module is configured to electrically connect the output end of the switch module to the substrates of the first to fourth transistors when the second control signal is valid. The present application also relates to an electronic device. The CMOS switch circuit of the present application minimizes the main source of transistor leakage current and remains stable over the entire temperature range.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to a CMOS switch circuit. Background Art

[0002] The development of CMOS technology helps improve the performance of digital systems, such as speed increase, power saving, and size reduction. However, the widespread use of CMOS technology has brought many problems to analog circuit design, such as increased transistor leakage due to low threshold voltage and thin equivalent gate oxide layer. For circuits based on charge transfer, such as switched capacitor circuits, sample-and-hold circuits, high duty cycle circuits, or circuits that need to work at high temperatures, device current leakage must be minimized to maintain the integrity of the signal transmission of the entire circuit.

[0003] Over the years, people have conducted comprehensive analysis and modeling on the principles of transistor current leakage, and adopted various process technologies, such as halo ring implantation, high-K metal gate, triple-gate oxide layer, etc., in order to reduce the current leakage of transistors.

[0004] However, in many deep submicron process circuit designs, a high threshold voltage (V th ) devices are used in critical signal paths such as switches or amplifier inputs. While transistor leakage can be reduced by using a lower supply voltage, this solution sacrifices signal dynamic range and is not an ideal solution.

[0005] CMOS switches are very important circuit modules in all kinds of circuits, and play an important role in almost all analog circuits such as signal sampling, multi-channel gating, dynamic component matching, chopping, etc. Therefore, a continuous and stable low current leakage CMOS switch circuit is essential to support high-performance systems. Summary of the invention

[0006] In view of the technical problems existing in the prior art, the present application proposes a CMOS switch circuit, a CMOS switch circuit, comprising: a switch module and a terminal potential control module; wherein the switch module comprises: a first transistor, whose gate is configured to receive a first control signal, and whose source is electrically connected to the input end of the switch module; a second transistor, whose gate is configured to receive the first control signal, whose source is electrically connected to the drain of the first transistor, and whose drain is electrically connected to the output end of the switch module; a third transistor; whose gate is configured to receive a second control signal, and whose drain is electrically connected to the input end of the switch module; a fourth transistor, whose gate is configured to receive the second control signal, whose drain is electrically connected to the source of the third transistor, whose source is electrically connected to the output end of the switch module, and whose substrate is electrically connected to the substrate of the second transistor; wherein the types of the first transistor and the second transistor are the same as the types of the third transistor and the fourth transistor. types are complementary; and the first control signal is the inverse signal of the second control signal; wherein the output end of the switch module is electrically connected to the input end of the terminal potential control module and the circuit outside the switch module and the terminal potential control module, and the multiple output ends of the terminal potential control module are electrically connected to the substrate of the first transistor, the substrate of the third transistor, the substrate of the second transistor and the substrate of the fourth transistor, the node between the drain of the first transistor and the source of the second transistor, and the node between the source of the third transistor and the drain of the fourth transistor; wherein the terminal potential control module is configured to electrically connect the output end of the switch module to the substrates of the first transistor, the third transistor, the second transistor and the fourth transistor when the second control signal is valid.

[0007] In particular, the terminal potential control module is also configured to, when the first control signal is valid, electrically connect the output end of the switch module to the substrates of the second transistor and the fourth transistor, the node between the drain of the first transistor and the source of the second transistor, and the node between the source of the third transistor and the drain of the fourth transistor; electrically connect the substrate of the first transistor to a power supply; and ground the substrate of the third transistor.

[0008] In particular, the terminal potential control module comprises a buffer, an input end of which is electrically connected to an input end of the terminal potential control module, and an output end of which is electrically connected to substrates of the second transistor and the fourth transistor.

[0009] In particular, the terminal potential control module also includes a switching unit, whose input end is electrically connected to the output end of the buffer, and whose output end is electrically connected to the node between the drain of the first transistor and the source of the second transistor, and the node between the source of the third transistor and the drain of the fourth transistor.

[0010] In particular, the switching unit further includes: a fifth transistor, whose gate is configured to receive the second control signal, whose drain is electrically connected to the input end of the switching unit, whose source is electrically connected to the output end of the switching unit, and whose substrate is electrically connected to a power supply; a sixth transistor, whose gate is configured to receive the first control signal, whose source is electrically connected to the input end of the switching unit, whose drain is electrically connected to the output end of the switching unit, and whose substrate is grounded; wherein the type of the fifth transistor is consistent with the type of the first transistor and the second transistor; wherein the type of the sixth transistor is consistent with the type of the third transistor and the fourth transistor.

[0011] In particular, the terminal potential control module also includes: a first multiplexer, whose selection control end is configured to receive the second control signal, whose first input end is electrically connected to the output end of the buffer, whose second input end is grounded, and whose output end is electrically connected to the substrate of the third transistor.

[0012] In particular, the terminal potential control module also includes: a second multiplexer, whose selection control end is configured to receive the second control signal, whose first input end is electrically connected to the output end of the buffer, whose second input end is electrically connected to the power supply, and whose output end is electrically connected to the substrate of the first transistor.

[0013] The present application also proposes an electronic device, comprising the CMOS switch circuit as described above.

[0014] The CMOS switch circuit proposed in this application has lower current leakage characteristics compared with the existing CMOS switch circuit. No matter whether the switch module in the CMOS switch circuit is closed or open, the potential of each terminal of the transistor in the switch module can be controlled by the terminal potential control module, so that the two main sources of leakage current are minimized at the same time, and the current leakage characteristics remain stable in the entire temperature range, and the leakage current does not increase with the increase of temperature. At the same time, the CMOS switch circuit proposed in this application has a simple structure and low process dependence, and is easy to be widely used in the integrated circuit industry. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Below, the preferred embodiments of the present application will be further described in detail with reference to the accompanying drawings, wherein:

[0016] Figure 1It is a schematic circuit diagram of an existing CMOS switch circuit.

[0017] Figure 2 is a schematic diagram of transistor current leakage.

[0018] Figure 3 is a schematic circuit diagram of another existing CMOS switch circuit.

[0019] Figure 4 is a schematic circuit diagram of a CMOS switch circuit according to an embodiment of the present application.

[0020] Figure 5 yes Figure 1 , Figure 3 and Figure 4 The current leakage of the CMOS switch circuit shown is compared at different temperatures. DETAILED DESCRIPTION

[0021] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0022] In the following detailed description, reference may be made to the various specification drawings that are part of the present application and are used to illustrate specific embodiments of the present application. In the accompanying drawings, similar reference numerals describe substantially similar components in different figures. The various specific embodiments of the present application are described below in sufficient detail so that a person of ordinary skill in the art with relevant knowledge and skills in the art can implement the technical solutions of the present application. It should be understood that other embodiments may also be used or structural, logical or electrical changes may be made to the embodiments of the present application.

[0023] The technologies, methods and devices known to those skilled in the art may not be discussed in detail, but where appropriate, the technologies, methods and devices shall be considered as part of the specification. The lines between the units in the drawings are only for the convenience of explanation, indicating that at least the units at both ends of the lines are communicating with each other, and are not intended to limit the unconnected units from being unable to communicate. In addition, the number of lines between two units is intended to indicate at least the number of signals involved in the communication between the two units or at least the output terminals, and is not intended to limit the two units to only be able to communicate with each other through the signals shown in the figure.

[0024] A transistor may refer to a transistor of any structure, such as a field effect transistor (FET) or a bipolar junction transistor (BJT). When the transistor is a field effect transistor, it may be hydrogenated amorphous silicon, metal oxide, low temperature polysilicon, organic transistor, etc., depending on the channel material. Depending on whether the carrier is an electron or a hole, it can be divided into an N-type transistor and a P-type transistor, wherein the control electrode refers to the gate of the field effect transistor, the first electrode may be the drain or source of the field effect transistor, and the corresponding second electrode may be the source or drain of the field effect transistor; when the transistor is a bipolar transistor, the control electrode refers to the base of the bipolar transistor, the first electrode may be the collector or emitter of the bipolar transistor, and the corresponding second electrode may be the emitter or collector of the bipolar transistor. The transistor may be manufactured using amorphous silicon, polycrystalline silicon, oxide semiconductor, organic semiconductor, NMOS / PMOS process or CMOS process.

[0025] Figure 1 It is a schematic circuit diagram of an existing CMOS switch circuit.

[0026] Figure 1 The CMOS switch circuit 100 shown is composed of transistors of complementary types, that is, NMOS transistor MN1 and PMOS transistor MP1 are connected in parallel. When the control signal turns on transistor MN1 and transistor MP1 at the same time, the CMOS switch circuit 100 is in a "closed" state, and the input signal V in1 It can be transmitted from the input end to the output end, and the output signal V can be obtained from the output end out1 When the control signal causes the transistor MN1 and the transistor MP1 to be turned off at the same time, the CMOS switch circuit 100 is in an "off" state, and the signal path between the input terminal and the output terminal is cut off.

[0027] Figure 2 This is a schematic diagram of transistor current leakage, where G is the gate of the transistor, S is the source of the transistor, D is the drain of the transistor, and B is the substrate of the transistor.

[0028] Figure 2 It shows the various leakage currents existing in real transistors. SL is the subthreshold channel leakage current, I G is the gate leakage current, I PC is the source-drain punch-through current, I GIDL is the gate induced drain leakage current, I REV is the pn junction reverse bias current.

[0029] Among them, I SL It is the result of the transistor drain-induced barrier lowering (DIBL) effect that enhances the subthreshold conduction and is one of the main sources of transistor leakage current.gs Much smaller than the transistor threshold voltage V th When SL It can be expressed as:

[0030] (1)

[0031] Among them, V gs is the gate-source voltage of the transistor, V th is the threshold voltage of the transistor, V ds is the drain-source voltage of the transistor, W / L is the width-to-length ratio of the transistor, and I c is a unit width-to-length ratio (i.e. W / L = 1) and V gs =V th The subthreshold current of the transistor is is the thermal voltage, n is the subthreshold swing coefficient, and η is the DIBL coefficient introduced by the drain.

[0032] It can be seen from formula (1) that by reducing the gate-source voltage V gs , reduce the drain-source voltage V of the transistor ds , and increase the threshold voltage V th , which can be reduced exponentially SL .

[0033] Another major source of transistor leakage current is the drain-to-substrate leakage current I B , which is mainly composed of I REV and I GIDL Composition, I B It can be expressed as:

[0034] (2)

[0035] Among them, V db is the voltage between the transistor drain and substrate, V dg is the voltage between the drain and gate of the transistor, V ds is the drain-source voltage of the transistor, n is the subthreshold swing coefficient, is the thermal voltage, I S It is a function of the transistor drain diffusion area, transistor doping distribution and temperature. The leakage current I flowing out of the drain area REV ,I GIDL ,I PC Composition (where I PC with I REV and I GIDL The impact is relatively small and can be ignored), and I S Proportional to the cube of temperature T; I GIDL It has nothing to do with temperature, but has a complex relationship with the potential difference between the terminals of the transistor.

[0036] It can be seen from formula (2) that by minimizing the size of the transistor and reducing the potential difference between different terminals of the transistor, the leakage current I can be effectively reduced. B .

[0037] Figure 3 is a schematic circuit diagram of another existing CMOS switch circuit.

[0038] As mentioned above, reducing I SL The most direct way is to reduce the drain-source voltage V ds Therefore, the common solution to reduce the leakage current of CMOS switch circuits is as follows Figure 3 The stacked CMOS switch circuit 200 is shown.

[0039] The CMOS switch circuit 200 stacks two PMOS transistors MP21 and MP22, and two NMOS transistors MN21 and MN22. The stacking of transistors can reduce the DIBL effect by several to several dozen times, that is, reduce the DIBL coefficient η introduced by the drain in equation (1), so as to reduce I SL purpose.

[0040] However, the stacking of transistors will lead to a larger on-resistance. In order to keep the on-resistance basically unchanged, this stacked CMOS switch needs to be larger in size, which will cause a larger I REV , according to formula (2), increase I REV That is, I is increased B .

[0041] Therefore, this type of CMOS switch reduces I SL , but it leads to a greater I B , is not an ideal solution.

[0042] This application proposes a method that can simultaneously reduce I SL and I B CMOS switching circuit.

[0043] Figure 4 is a schematic circuit diagram of a CMOS switch circuit according to an embodiment of the present application.

[0044] According to one embodiment, Figure 4 The CMOS switch circuit 400 shown may include a switch module 401 .

[0045] According to one embodiment, the switch module 401 may include an input terminal IN 401 , configured to receive input signal V in401 .

[0046] According to one embodiment, the switch module 401 may include an output terminal OUT 401 , configured to output the output signal V of the switch module 401 when the switch module 401 is closed o401 .

[0047] According to one embodiment, Figure 5 The illustrated CMOS switch circuit 400 may include a terminal potential control module 402 .

[0048] According to one embodiment, the output terminal OUT of the switch module 401 401 Electrically connected to the input end of the terminal potential control module 402.

[0049] According to one embodiment, the output terminal OUT of the switch module 401 401 It is also electrically connected to a circuit (not shown) other than the switch module 401 and the terminal potential control module 402 .

[0050] According to one embodiment, the terminal potential control module 402 is configured to receive the output signal V of the switch module 401 when the switch module 401 is closed. o401 , and controls the potential of each terminal of the transistor in the switch module 401 to reduce the main source of the leakage current of the transistor I SL and I B Minimization purpose.

[0051] According to one embodiment, the terminal potential control module 402 is further configured to receive a signal from the output terminal OUT of the switch module 401 when the switch module 401 is disconnected. 401 The switch module 401 is electrically connected to the terminal potential control module 402 and controls the potential of each terminal of the transistor in the switch module 401 to reduce the leakage current of the transistor to the main source I SL and I B Minimization purpose.

[0052] According to one embodiment, the switch module 401 may include a PMOS transistor MP41, whose gate is configured to receive a control signal , whose source is electrically connected to the input terminal IN of the switch module 401 401 .

[0053] According to one embodiment, the switch module 401 may include a PMOS transistor MP42, whose gate is configured to receive a control signal , whose source is electrically connected to the drain of transistor MP41, and whose drain is electrically connected to the output terminal OUT of switch module 401 401 .

[0054] According to one embodiment, the switch module 401 may include an NMOS transistor MN41, whose gate is configured to receive the control signal φ and whose drain is electrically connected to the input terminal IN of the switch module 401. 401 .

[0055] According to one embodiment, the switch module 401 may include an NMOS transistor MN42, whose gate is configured to receive the control signal φ, whose drain is electrically connected to the source of the transistor MN41, and whose source is electrically connected to the output terminal OUT of the switch module 401. 401 , whose substrate is electrically connected to the substrate of transistor MP42.

[0056] According to one embodiment, the terminal potential control module 402 may include a buffer X1. According to one embodiment, the buffer X1 may include an input terminal IN X and output terminal OUT X , its input terminal IN X Electrically connected to the output terminal OUT of the switch module 401 401 , its output terminal OUT X Electrically connected to node C between the substrate of transistor MP42 and the substrate of transistor MN42 in switch module 401 .

[0057] According to one embodiment, the buffer X1 is configured to receive a signal from its input terminal IN when the switch module 401 is closed. X The output signal V of the receiving switch module 401 is o401 , and V o401 From its output terminal OUT X Output to the subsequent circuit in the terminal potential control module 402. In this process, the buffer X1 plays an isolation role, so that the interference signal including the transistor leakage current in the subsequent circuit of the terminal potential control module 402 will not affect V o401 have an impact.

[0058] According to one embodiment, the buffer X1 is further configured to receive a signal from its input terminal IN when the switch module 401 is disconnected. X Receives the output terminal OUT from the switch module 401 401 The switch module 401 and the terminal potential control module 402 are electrically connected to the circuit outside, and the signal is transmitted from the output terminal OUT X The output is sent to the subsequent circuit in the terminal potential control module 402. In this process, the buffer X1 plays an isolation role, so that the interference signal including the transistor leakage current in the subsequent circuit of the terminal potential control module 402 will not affect the output terminal OUT of the switch module 401. 401 The signals of the circuits other than the electrically connected switch module 401 and the terminal potential control module 402 are affected.

[0059] According to one embodiment, the terminal potential control module 402 may include a switch unit 403, whose input terminal IN 403 Electrically connected to the output terminal OUT of buffer X1 X , its output terminal OUT 403 The switch module 401 is electrically connected to a node A between the drain of the transistor MP41 and the source of the transistor MP42 and a node B between the source of the transistor MN41 and the drain of the transistor MN42 .

[0060] According to one embodiment, the switch unit 403 may include a PMOS transistor MP43, whose gate is configured to receive the control signal φ and whose drain is electrically connected to the input terminal IN of the switch unit 403. 403 , whose source is electrically connected to the output terminal OUT of the switch module 403 403 , whose substrate is configured to receive a power supply voltage V DD .

[0061] According to one embodiment, the switch unit 403 may include an NMOS transistor MN43, whose gate is configured to receive a control signal , whose source is electrically connected to the input terminal IN of the switch unit 403 403 , whose drain is electrically connected to the output terminal OUT of the switch unit 403 403 , whose substrate is configured to receive ground level V SS .

[0062] According to one embodiment, the terminal potential control module 402 may include a multiplexer MUX1, whose gate control terminal S1 is configured to receive the control signal φ; and whose input terminal A1 is electrically connected to the output terminal OUT of the buffer X1. X , and node C between the substrate of transistor MP42 and the substrate of transistor MN42 in switch module 401; its input terminal B1 is electrically connected to the substrate of transistor MN43 in switch unit 403; its output terminal OUT1 is electrically connected to the substrate of transistor MN41 in switch module 401.

[0063] According to one embodiment, the terminal potential control module 402 may include a multiplexer MUX2, whose strobe control terminal S2 is electrically connected to the strobe control terminal S1 of the multiplexer MUX1 and configured to receive the control signal φ; whose input terminal A2 is electrically connected to the input terminal A1 of the multiplexer MUX1, the output terminal OUT of the buffer X1, and the output terminal OUT2 of the buffer X2. X , and node C between the substrate of transistor MP42 and the substrate of transistor MN42 in switch module 401; its input terminal B2 is electrically connected to the substrate of transistor MP43 in switch unit 403; its output terminal OUT2 is electrically connected to the substrate of transistor MP41 in switch module 401.

[0064] According to one embodiment, when the switch module 401 is closed (ie, the control signal φ is valid), the switch unit 403 is opened, the output terminal OUT1 of the multiplexer MUX1 selects the input terminal A1, and the output terminal OUT2 of the multiplexer MUX2 selects the input terminal A2.

[0065] At this time, the input terminal IN of buffer X1 X The output signal V of the receiving switch module 401 is o401 , buffer X1 through its output terminal OUT X V o401 The signals are respectively output to the node C (i.e., the substrate of the transistor MP42 and the substrate of the transistor MN42), the input terminal A1 of the multiplexer MUX1, and the input terminal A2 of the multiplexer MUX2, and then respectively output from the output terminal OUT1 of the multiplexer MUX1 and the output terminal OUT2 of the multiplexer MUX2 to the substrate of the transistor MN41 and the substrate of MP41.

[0066] Therefore, the substrate potential V1 of the transistor MP41, the substrate potential V2 of the transistor MN41, and the substrate potential V4 of the transistors MP42 and MN42 are all equal to V o401 , there is no potential difference between the source, drain, and substrate of the four transistors in the switch module 401, that is, the V ds 、V db Both are 0.

[0067] V ds =0 Substituting into formula (1), we can get:

[0068] (3)

[0069] V ds =0, V db =0 Substituting into formula (2), we can get:

[0070] (4)

[0071] It can be seen from formula (3) and formula (4) that Figure 4 The CMOS switch circuit 400 shown in the figure greatly reduces the main source of leakage current I of each transistor when the switch module 401 is closed. SL and I B , and it can basically not change with temperature.

[0072] According to one embodiment, when the switch module 401 is disconnected (i.e., the control signal When the switch unit 403 is closed, the output terminal OUT1 of the multiplexer MUX1 selects the input terminal B1, and the output terminal OUT2 of the multiplexer MUX2 selects the input terminal B2.

[0073] At this time, although the switch module 401 is disconnected, the output terminal OUT of the switch module 401 is still 401 Still electrically connected to the circuit outside the switch module 401 and the terminal potential control module 402, in order to avoid the leakage current of the transistor in the switch module 401 to its output terminal OUT 401 The switch module 401 and the terminal potential control module 402 are electrically connected to each other, and the leakage current of the internal transistors must be kept at the lowest level even if the switch module 401 is disconnected. 401 The signal of the circuit other than the switch module 401 and the terminal potential control module 402 that are electrically connected is recorded as V a .

[0074] At this time, the input terminal IN of buffer X1 X Receive signal V a , buffer X1 through its output terminal OUT X V a The outputs are respectively output to the node C (ie, the substrate of the transistor MP42 and the substrate of the transistor MN42), and the input terminal IN of the switch unit 403. 403 , and then the output terminal OUT of the switch unit 403 403 output to nodes A and B respectively; at the same time, the output terminal OUT1 of the multiplexer MUX1 selects the input terminal B1, electrically connects the substrate of the transistor MN41 to the substrate of the transistor MN43, and receives the ground level V SS The output terminal OUT2 of the multiplexer MUX2 selects the input terminal B2, electrically connects the substrate of the transistor MP41 to the substrate of the transistor MP43, and receives the power supply voltage V DD .

[0075] Therefore, the substrate potential V1 of transistor MP41 = V DD , the substrate potential V2 of transistor MN41 = V SS , the potential V3 at the node A and the node B, and the substrate potential V4 of the transistor MP42 and the transistor MN42 are all equal to V a .

[0076] At this time, since the switch module 401 is turned off, the substrates of the transistors MP41 and MN41 receive the power supply voltage V DD and ground level V SS, and the transistor MP41 and the transistor MN41 are not electrically connected to the output terminal OUT of the switch module 401 401 The switch module 401 and the circuit other than the terminal potential control module 402 are directly connected, so the signal V a No longer has any impact.

[0077] The drain of transistor MP42 and the source of transistor MN42 are electrically connected to the output terminal OUT of switch module 401. 401 , and then electrically connected to the circuit outside the switch module 401 and the terminal potential control module 402, but as mentioned above, at this time V3 = V4 = V a , there is no potential difference between the source, drain, and substrate of transistor MP42 and transistor MN42, that is, V ds 、V db Both are 0.

[0078] V ds Substituting =0 into equation (1), we can also get equation (3).

[0079] V ds =0, V db Substituting =0 into formula (2), we can also get formula (4).

[0080] It can be seen from formula (3) and formula (4) that Figure 4 The CMOS switch circuit 400 shown in the figure still significantly reduces the main source of leakage current of the transistor MP42 and the transistor MN42 when the switch module 401 is disconnected. SL and I B , and it can basically not change with temperature.

[0081] According to other embodiments, the terminal potential control module may also have other circuit implementations different from the above, as long as the potential of each terminal of the transistor in the switch module can be controlled under different conditions of the switch module to achieve the main source of the leakage current of the transistor I SL and I B The purpose of minimization is sufficient and will not be elaborated here.

[0082] Figure 5 yes Figure 1 , Figure 3 and Figure 4 The current leakage of the CMOS switch circuit shown is compared at different temperatures. Figure 5 shows a common CMOS switch circuit (e.g. Figure 1 CMOS switch circuit 100 shown), stacked CMOS switch circuit (eg Figure 3CMOS switch circuit 200 shown in the figure), and the CMOS switch circuit proposed in the present application (for example Figure 4 The leakage current of the CMOS switch circuit 400 shown in FIG. 4 is between -45°C and 125°C.

[0083] Depend on Figure 5 It can be seen that the current leakage performance of the CMOS switch circuit proposed in the present application is very stable in the entire temperature range, and the leakage current will not increase with the increase of temperature whether in the low temperature range or the high temperature range.

[0084] In summary, the present application proposes a CMOS switch circuit, which has a lower current leakage characteristic than the existing CMOS switch circuit. No matter whether the switch module in the CMOS switch circuit is closed or open, the potential of each terminal of the transistor in the switch module can be controlled by the terminal potential control module, so that the potential difference between the two ends of the pn junction and along the channel is reduced to zero, thereby reducing the leakage current of the pn junction and along the channel, so that the two main sources of leakage current I SL and I B At the same time, the current leakage characteristic is minimized, and the current leakage characteristic remains stable in the entire temperature range, and the leakage current does not increase with the increase of temperature. At the same time, the CMOS switch circuit proposed in this application has a simple structure, low process dependence, and is easy to be widely used in the integrated circuit industry.

[0085] The present application also proposes an electronic device, which may include the CMOS switch circuit 400 as described above.

[0086] The above embodiments are only used to illustrate the present application, and are not intended to limit the present application. Ordinary technicians in the relevant technical field may make various changes and modifications without departing from the scope of the present application. Therefore, all equivalent technical solutions should also fall within the scope disclosed in the present application.

Claims

1. A CMOS switch circuit, comprising: Switch module and terminal potential control module; Wherein, the switch module comprises: a first transistor, whose gate is configured to receive a first control signal and whose source is electrically connected to an input terminal of the switch module, wherein the first transistor is a P-type transistor; a second transistor, whose gate is configured to receive the first control signal, whose source is electrically connected to the drain of the first transistor, and whose drain is electrically connected to the output terminal of the switch module, wherein the second transistor is a P-type; a third transistor; a gate of which is configured to receive a second control signal, and a drain of which is electrically connected to the input terminal of the switch module, wherein the third transistor is of N type; a fourth transistor, whose gate is configured to receive the second control signal, whose drain is electrically connected to the source of the third transistor, whose source is electrically connected to the output terminal of the switch module, and whose substrate is electrically connected to the substrate of the second transistor, wherein the fourth transistor is N-type; wherein the types of the first transistor and the second transistor are complementary to the types of the third transistor and the fourth transistor; and the first control signal is an inverse signal of the second control signal; The output end of the switch module is electrically connected to the input end of the terminal potential control module and circuits outside the switch module and the terminal potential control module, and the multiple output ends of the terminal potential control module are electrically connected to the substrate of the first transistor, the substrate of the third transistor, the node between the substrate of the second transistor and the substrate of the fourth transistor, the node between the drain of the first transistor and the source of the second transistor, and the node between the source of the third transistor and the drain of the fourth transistor respectively; The terminal potential control module is configured to electrically connect the output end of the switch module to the substrates of the first transistor, the second transistor, the third transistor and the fourth transistor when the second control signal is valid; Wherein, the terminal potential control module is also configured to, when the first control signal is valid, electrically connect the output end of the switch module to the substrates of the second transistor and the fourth transistor, the node between the drain of the first transistor and the source of the second transistor, and the node between the source of the third transistor and the drain of the fourth transistor; electrically connect the substrate of the first transistor to a power supply; and ground the substrate of the third transistor.

2. The CMOS switch circuit according to claim 1, wherein: The terminal potential control module includes a buffer, an input end of which is electrically connected to an input end of the terminal potential control module, and an output end of which is electrically connected to a node between a substrate of the second transistor and a substrate of the fourth transistor.

3. The CMOS switch circuit according to claim 2, wherein: The terminal potential control module also includes a switching unit, whose input end is electrically connected to the output end of the buffer, and whose output end is electrically connected to a node between the drain of the first transistor and the source of the second transistor, and a node between the source of the third transistor and the drain of the fourth transistor.

4. The CMOS switch circuit according to claim 3, wherein: The switch unit further comprises: a fifth transistor, whose gate is configured to receive the second control signal, whose drain is electrically connected to the input terminal of the switch unit, whose source is electrically connected to the output terminal of the switch unit, and whose substrate is electrically connected to a power supply; a sixth transistor, whose gate is configured to receive the first control signal, whose source is electrically connected to the input terminal of the switch unit, whose drain is electrically connected to the output terminal of the switch unit, and whose substrate is grounded; Wherein, the type of the fifth transistor is consistent with the type of the first transistor and the second transistor; The type of the sixth transistor is consistent with the types of the third transistor and the fourth transistor.

5. The CMOS switch circuit according to any one of claims 3 or 4, wherein: The terminal potential control module also includes: The first multiplexer has a gate control terminal configured to receive the second control signal, a first input terminal electrically connected to the output terminal of the buffer, a second input terminal grounded, and an output terminal electrically connected to the substrate of the third transistor.

6. The CMOS switch circuit according to claim 5, wherein: The terminal potential control module also includes: The second multiplexer has a selection control terminal configured to receive the second control signal, a first input terminal electrically connected to the output terminal of the buffer, a second input terminal electrically connected to a power supply, and an output terminal electrically connected to the substrate of the first transistor.

7. An electronic device comprising the CMOS switch circuit according to any one of claims 1 to 6.

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