Ultra-low-delay self-locking noise suppression level shift circuit

Abstract

The invention discloses a self-locking noise suppression level shift circuit with ultra-low delay, relates to the technical field of intelligent power driving, and aims to solve the problem that delay is increased when noise is filtered out through an RC filter circuit in the prior art. Comprising a high-voltage level shifting circuit, a common-mode noise elimination circuit, a differential-mode noise elimination circuit and an RS latch which are electrically connected, the common-mode noise elimination circuit is used for transmitting 1 / 2VDD voltage to the input end of the RS latch when common-mode noise exists, relatively low threshold voltage of the RS latch is designed, the 1 / 2VDD voltage is made to be high level for the RS latch, and therefore the 1 / 2VDD voltage is made to be low level for the RS latch. The state of the RS latch is kept unchanged, the differential mode noise elimination circuit is used for starting the differential mode noise elimination circuit through resistor voltage division when differential mode noise exists, and the input end of the RS latch is kept at a high level. The self-locking noise suppression level shift circuit provided by the invention is used for eliminating common-mode noise and differential-mode noise of dV / dt noise and has lower delay.

Description

Technical Field

[0001] The present invention relates to the field of intelligent power drive technology, and in particular to an ultra-low-delay self-locking noise suppression level shift circuit. Background Art

[0002] Intelligent power integrated circuits integrate high-voltage power devices and low-voltage control signal processing, protection, detection and other functions into one chip. It amplifies the power of the input signal and is mainly used in motor drive, automotive electronics, power management, daily lighting and other fields. It has the advantages of low power consumption, low cost, high efficiency and high reliability. Different topological structures of power devices correspond to different application scenarios, so the drive circuit is also divided into full-bridge drive circuit and half-bridge gate drive circuit. Among them, the half-bridge gate drive circuit is widely used due to its simple structure and strong driving capability.

[0003] The high-voltage side path in the half-bridge gate drive circuit is used to transfer the low-voltage signal to the high-voltage signal. During the signal transmission process, the floating ground potential of the high-voltage side path will change sharply, thereby generating dV / dt noise at the drain of the LDMOS tube in the high-voltage side path. The current caused by the dV / dt noise will cause an erroneous negative pulse, which may cause the RS latch to be in an unstable state.

[0004] The existing method is to introduce RC filtering and reasonably set the appropriate filter width to filter out the noise negative pulse and leave the correct pulse signal. However, the effect of eliminating noise by RC filtering depends on the filter width. When the filter width of RC filtering is small, the noise cannot be effectively filtered out, and when the filter width is large, the signal transmission will be delayed, which will restrict the maximum operating frequency of the half-bridge gate driver chip. Summary of the invention

[0005] The object of the present invention is to provide an ultra-low delay self-locking noise suppression level shift circuit, which is used to solve the problem that the existing RC filtering increases the delay while filtering out the noise.

[0006] In order to achieve the above object, the present invention provides the following technical solutions:

[0007] An ultra-low-delay self-locking noise suppression level shift circuit, comprising at least: a common-mode noise elimination circuit, a differential-mode noise elimination circuit, an RS latch, and a high-voltage level shift circuit, wherein the input end of the common-mode noise elimination circuit is connected to the output end of the high-voltage level shift circuit; the output end of the common-mode noise elimination circuit is connected to the input end of the RS latch; the input end of the differential-mode noise elimination circuit is connected to the output end of the high-voltage level shift circuit, and the output end of the differential-mode noise elimination circuit is connected to the input end of the RS latch;

[0008] The common mode noise elimination circuit is used to transmit 1 / 2VDD voltage to the input end of the RS latch when the negative noise pulse signal output by the high voltage level shift circuit has common mode noise, and the input end of the RS latch maintains a high level; VDD is the voltage difference between the power supply and the floating ground potential; the threshold voltage of the RS latch is less than 1 / 2VDD;

[0009] The differential mode noise elimination circuit is used to turn on the differential mode noise elimination circuit through resistor voltage division when the negative noise pulse signal output by the high voltage level shift circuit has differential mode noise, and the input end of the RS latch maintains a high level.

[0010] Compared with the prior art, the present application provides an ultra-low delay self-locking noise suppression level shift circuit comprising at least: a common-mode noise elimination circuit, a differential-mode noise elimination circuit, an RS latch and a high-voltage level shift circuit. When the negative pulse signal output by the high-voltage level shift circuit has common-mode noise, the common-mode noise elimination circuit transmits a 1 / 2VDD voltage to the input end of the RS latch. By designing a relatively low threshold voltage of the RS latch, the 1 / 2VDD voltage is a high level for the RS latch, so that the input end of the RS latch maintains a high level and the state of the RS latch remains unchanged, thereby eliminating the common-mode noise. When the high-voltage level shift circuit When there is differential-mode noise in the negative pulse signal output by the circuit, the differential-mode noise elimination circuit senses the noise through the resistor voltage divider and turns on the differential-mode noise elimination circuit, so that the input end of the RS latch maintains a high level and the state of the RS latch remains unchanged, thereby eliminating the differential-mode noise. Neither the common-mode noise elimination circuit nor the differential-mode noise elimination circuit of the present application uses an RC filtering circuit. While effectively removing the noise in the negative pulse signal in the high-voltage side channel, it has a lower delay characteristic, thereby enhancing the reliability and stability of the half-bridge drive circuit. In addition, the present application can solve problems related to process fluctuations and layout mismatch through a differential-mode noise elimination circuit, and can cope with various abnormal situations.

[0011] Optionally, the floating ground potential is the floating ground potential of the high-voltage side channel in the half-bridge gate drive circuit, and the common-mode noise elimination circuit includes a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, and a fourth NMOS tube;

[0012] The gate of the first PMOS tube is connected to the gate of the second PMOS tube, the gate of the first PMOS tube and the gate of the second PMOS tube are connected to the second output end of the high-voltage level shift circuit, the source of the first PMOS tube is connected to the power supply, the drain of the first PMOS tube is connected to the drain of the first NMOS tube, the source of the first NMOS tube is connected to the floating ground potential, the gate of the first NMOS tube is connected to the gate of the second NMOS tube, the gate of the first NMOS tube is connected to the drain of the first NMOS tube, the source of the second NMOS tube is connected to the floating ground potential, and the drain of the second NMOS tube is connected to the drain of the third PMOS tube; the gate of the third PMOS tube is connected to the gate of the fourth PMOS tube, the gate of the third PMOS tube is connected to the fourth PMOS tube, and the gate of the third PMOS tube is connected to the fourth PMOS tube. The gate of the S tube is connected to the first output end of the high-voltage level shift circuit, the source of the third PMOS tube is connected to the power supply, the drain of the second PMOS tube is connected to the drain of the third NMOS tube, the source of the second PMOS tube is connected to the power supply, the source of the third NMOS tube is connected to the floating ground potential, the gate of the third NMOS tube is connected to the gate of the fourth NMOS tube, the source of the fourth PMOS tube is connected to the power supply, the drain of the fourth PMOS tube is connected to the drain of the fourth NMOS tube, the drain of the fourth NMOS tube is connected to the gate of the fourth NMOS tube, the source of the fourth NMOS tube is connected to the floating ground potential, the drain of the second PMOS tube is connected to the set end of the RS latch, and the drain of the third PMOS tube is connected to the reset end of the RS latch.

[0013] Optionally, the differential mode noise elimination circuit includes: a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth PMOS transistor and a sixth PMOS transistor;

[0014] One end of the first resistor is connected to the first output end of the high-voltage level shift circuit, the other end of the first resistor is connected to one end of the third resistor, the other end of the first resistor is connected to the gate of the sixth PMOS tube, the other end of the third resistor is connected to the output end of the RS latch, one end of the second resistor is connected to the second output end of the high-voltage level shift circuit, the other end of the second resistor is connected to one end of the fourth resistor, the other end of the second resistor is connected to the gate of the fifth PMOS tube, and the other end of the fourth resistor is connected to the inverting output end of the RS latch; the drain of the fifth PMOS tube is connected to the reset end of the RS latch, the source of the fifth PMOS tube is connected to the power supply, the drain of the sixth PMOS tube is connected to the set end of the RS latch, and the source of the sixth PMOS tube is connected to the power supply.

[0015] Optionally, the high-voltage level shift circuit includes a first LDMOS transistor, a second LDMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a first zener diode and a second zener diode;

[0016] The gate of the first LDMOS tube is connected to an output end of a pulse signal generating circuit of a high-voltage side channel in a half-bridge gate driving circuit, the source of the first LDMOS tube is connected to the floating ground potential, the drain of the first LDMOS tube is respectively connected to the drain of the seventh PMOS tube, one end of the first resistor and the gate of the third PMOS tube, the gate of the seventh PMOS tube is connected to the drain of the seventh PMOS tube, the source of the seventh PMOS tube is connected to the power supply, the input end of the first voltage regulator diode is connected to the drain of the seventh PMOS tube, and the output end of the first voltage regulator diode is connected to the drain of the seventh PMOS tube. The gate of the second LDMOS tube is connected to the other output end of the pulse signal generating circuit, the source of the second LDMOS tube is connected to the floating ground potential, the drain of the second LDMOS tube is respectively connected to the drain of the eighth PMOS tube, one end of the second resistor, and the gate of the first PMOS tube, the gate of the eighth PMOS tube is connected to the drain of the eighth PMOS tube, the source of the eighth PMOS tube is connected to the power supply, the input end of the second zener diode is connected to the drain of the eighth PMOS tube, and the output end of the second zener diode is connected to the power supply.

[0017] Optionally, it is characterized in that when there is noise in the negative pulse signal output by the high-voltage level shift circuit, a voltage drop is generated at the drain of the first LDMOS tube and the drain of the second LDMOS tube, the first PMOS tube, the second PMOS tube, the third PMOS tube, and the fourth PMOS tube are turned on, and the voltage at the two input terminals of the RS latch is 1 / 2VDD; the gate voltage of the first PMOS tube and the gate voltage of the second PMOS tube are less than the power supply voltage, the first PMOS tube and the second PMOS tube are turned on, and the voltage at the input terminal of the RS latch is pulled up from 1 / 2VDD to VDD.

[0018] Optionally, the self-locking noise suppression level shift circuit further includes a fifth resistor, one end of the fifth resistor is connected to the power supply, and the other end of the fifth resistor is connected to the drain of the fourth PMOS tube.

[0019] Optionally, a ratio of the third resistor to the first resistor is equal to a ratio of the fourth resistor to the second resistor.

[0020] Optionally, the ratio of the width to length ratio of the first PMOS tube, the width to length ratio of the second PMOS tube, the width to length ratio of the third PMOS tube, and the width to length ratio of the fourth PMOS tube is 1:m:m:1; the ratio of the width to length ratio of the first NMOS tube, the width to length ratio of the second NMOS tube, the width to length ratio of the third NMOS tube, and the width to length ratio of the fourth NMOS tube is 1:m:m:1, and the value of m is 5-10.

[0021] Optionally, the width-to-length ratio of the fifth PMOS tube and the width-to-length ratio of the sixth PMOS tube are both greater than the width-to-length ratio of the first PMOS tube, the width-to-length ratio of the second PMOS tube, the width-to-length ratio of the third PMOS tube, and the width-to-length ratio of the fourth PMOS tube.

[0022] Optionally, the self-locking noise suppression level shift circuit also includes an output buffer circuit, which includes an output buffer stage, a ninth PMOS tube and a fifth NMOS tube, the input end of the output buffer stage is connected to the output end of the RS latch, the first output end of the output buffer stage is connected to the gate of the ninth PMOS tube, the drain of the ninth PMOS tube is connected to the power supply, the source of the ninth PMOS tube is connected to the output end of the high-voltage side channel, the second output end of the output buffer stage is connected to the gate of the fifth NMOS tube, the drain of the fifth NMOS tube is connected to the output end of the high-voltage side channel, and the source of the fifth NMOS tube is connected to the floating ground potential. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0024] Figure 1 It is a structural schematic diagram of a half-bridge gate drive circuit;

[0025] Figure 2 It is a structural schematic diagram of the high-pressure side channel in the prior art;

[0026] Figure 3 It is a schematic diagram of delay generated by filtering using an RC filter in the prior art;

[0027] Figure 4 A schematic diagram of the structure of an ultra-low-delay self-locking noise suppression level shifting circuit provided by the present invention;

[0028] Figure 5 A schematic diagram of the structure of the common-mode noise elimination circuit provided by the present invention;

[0029] Figure 6 A schematic diagram of simulation results of common mode noise provided by the present invention;

[0030] Figure 7 A schematic diagram of the differential mode simulation result of the circuit provided by the present invention, wherein the anti-noise capability of the circuit structure for eliminating the differential mode is adjusted to be very small;

[0031] Figure 8 A schematic diagram of differential mode simulation results of a noise self-locking circuit provided by the present invention, in which the anti-noise capability of the circuit structure for eliminating differential mode is restored to normal;

[0032] Fig. 9 A schematic diagram of simulation results of high-voltage side path delay of the self-locking noise suppression level shift circuit provided by the present invention;

[0033] Fig.10 A schematic diagram of delay simulation results of the level shift circuit provided by the present invention;

[0034] Fig.11 A schematic diagram of static current simulation results of VB and VDD provided by the present invention;

[0035] Fig.12 It is a schematic diagram of the simulation results of the negative VS tolerance of the circuit provided by the present invention.

[0036] Reference numerals:

[0037] 1-high-voltage level shift circuit, 2-common-mode noise elimination circuit, 3-differential-mode noise elimination circuit, 4-RS latch, 5-output buffer circuit, MP1-first PMOS tube, MP2-second PMOS tube, MP3-third PMOS tube, MP4-fourth PMOS tube, MP5-fifth PMOS tube, MP6-sixth PMOS tube, P1-seventh PMOS tube, P2-eighth PMOS tube, MP7-ninth PMOS tube, MN1-first NMOS tube, MN2-second NMOS tube, MN3-third NMOS tube, MN4-fourth NMOS tube, MN5-fifth NMOS tube, LD1-first LDMOS tube, LD2-second LDMOS tube, ZD1-first voltage regulator diode, ZD2-second voltage regulator diode, R1-first resistor, R2-second resistor, R3-third resistor, R4-fourth resistor, R5-fifth resistor. DETAILED DESCRIPTION

[0038] In order to clearly describe the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, words such as "first" and "second" are used to distinguish the same items or similar items with basically the same functions and effects. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and their order is not limited. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit them to be different.

[0039] It should be noted that, in the present invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0040] In the present invention, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b and c, where a, b, c can be single or multiple.

[0041] Figure 1 FIG. 4 shows a schematic diagram of a structure of a half-bridge gate drive circuit applied in a level shift circuit. Figure 1 As shown in the figure, there are two channels in the half-bridge gate drive circuit, namely the high-voltage side channel that transmits the signal from the high-voltage input terminal HIN to the high-voltage output terminal HO and the low-voltage side channel that transmits the signal from the low-voltage input terminal LIN to the low-voltage output terminal LO. VB is the power supply, and the VS port is the floating ground potential of the high-voltage side channel. The peripheral bootstrap circuit composed of the bootstrap diode Db and the capacitor Cb ensures that the fixed potential difference of VDD is maintained between the power supply VB and the floating ground potential VS. The voltage of the floating ground potential VS depends on the state of the two power devices T1 and T2. When the low-voltage output terminal LO is high, the power device T2 is turned on, at this time the high-voltage output terminal HO is low, the power device T1 is turned off, and the floating ground potential VS is the COM ground level; when the high-voltage output terminal HO is high, the power device T1 is turned on, at this time the low-voltage output terminal LO is low, the power device T2 is turned off, and VS is a high level of 600V. The high-voltage side channel transfers the low-voltage signal to the high-voltage signal, and is the most important module in the half-bridge gate drive circuit.

[0042] Figure 2 The schematic diagram of the structure of the high-pressure side channel in the prior art is shown as follows: Figure 2As shown in the figure, the traditional high-voltage side path consists of a pulse generation circuit, a high-voltage level shift circuit, an RC filter, an undervoltage protection, an RS latch, and an output buffer. The high-voltage level shift circuit consists of two LDMOS, LDM1 and LDM2, and a load resistor R a and R b The pulse generating circuit converts the square wave signal input by the input buffer circuit into two pulse signals to drive the Zener diodes LDM1 and LDM2 to conduct respectively. At this time, the corresponding branches are also turned on, and the current flows through the load resistor R a or R b , a negative pulse is generated at the drain of LDMOS. The RS latch restores the pulse signal to a square wave signal and transmits it to the high-voltage output terminal HO through the output buffer, so that the power device T1 is turned on, the floating ground potential VS is rapidly raised to 600V, and the potential of the power supply VB is also increased to 615V accordingly. The sharp voltage change will cause the drain-source parasitic capacitance C of LDMOS to P1 or C P2 The induced current I N1 or I N2 , can be entered into formula (1) as shown:

[0043]

[0044] Among them, I N1,2 is the induced current I N1 The current value or I N2 Current value, C P1,2 is the drain-source parasitic capacitance C P1 The capacitance value or C P2 Capacitance value.

[0045] Due to process fluctuations, the parasitic capacitance of LDMOS is not exactly the same, and the generated inductive noise is also different. The load resistance R generated by dV / dt noise a (R b ) The voltage drop across the drop1 (V drop2 ) is shown in formula (2):

[0046]

[0047] Among them, V drop1,2 Indicates voltage drop V drop1 and V drop2 , R a,b Represents the load resistance R a The resistance value and R b resistance value.

[0048] When the voltage drop is greater than VB-VS-V TH,RS (VTH,RS is the threshold voltage of the RS trigger), then the current caused by dV / dt noise will cause an erroneous negative pulse, which may cause the RS trigger to become unstable. Therefore, an RC filter is needed to filter. By setting the appropriate filter width reasonably, the negative pulse signal caused by the noise can be filtered out, leaving the correct signal pulse.

[0049] In the prior art, such as Figure 2 As shown in FIG. 1 , an RC filter is usually used to filter the drain end of the LDMOS tube, and the filtered signal is transmitted to the corresponding port of the RS trigger. The effect of eliminating noise using an RC filter depends on the filter width. Figure 3 As shown in the figure, S represents the signal output from the drain end of the LDMOS, SET represents the signal transmitted to the S port of the RS trigger after filtering by the RC filter, and HO represents the signal waveform output by the high-voltage side output port HO. When the filter width of the RC filter is small, the voltage at the input S end of the RS trigger in the noise area will still drop below the threshold, affecting the overall output of the chip. When the filter width is large, the SET end does not drop below the threshold in the noise area, the noise is effectively filtered out, and the high-voltage side output port HO outputs normally. However, when the effective signal is transmitted, additional delay is introduced. Therefore, the use of RC filtering to eliminate noise is affected by the filter width. If the filter width is too small, it is difficult to effectively filter out the noise. If the filter width is too large, the signal delay will increase.

[0050] In order to solve the above problems, the present invention provides a new noise elimination circuit for the high-voltage side channel, which processes the negative pulse signal in the high-voltage side channel to remove the noise signal and retain the valid signal. The ultra-low delay self-locking noise suppression level shift circuit provided by the present invention adopts a cleverly designed and fully functional construction scheme. While effectively removing the noise signal, it has a lower delay characteristic and enhances the reliability and stability of the half-bridge gate drive circuit. In addition, the present invention can also solve related problems such as process fluctuations and layout mismatches, and can cope with various abnormal situations.

[0051] Figure 4 A schematic diagram of the structure of an ultra-low delay self-locking noise suppression level shift circuit. This circuit is applied to the high-voltage side channel in a half-bridge gate drive circuit to eliminate the dV / dt noise generated at the drain end of the LDMOS due to the sharp change of the floating ground potential voltage. Figure 4As shown, an ultra-low delay self-locking noise suppression level shift circuit includes: a high-voltage level shift circuit 1, a noise self-locking circuit, an RS latch 4 and an output buffer circuit 5, wherein the noise self-locking circuit is composed of a common-mode noise elimination circuit 2 and a differential-mode noise elimination circuit 3; the input end of the common-mode noise elimination circuit 2 is connected to the output end of the high-voltage level shift circuit 1; the output end of the common-mode noise elimination circuit 2 is connected to the input end of the RS latch 4; the input end of the differential-mode noise elimination circuit 3 is connected to the output end of the high-voltage level shift circuit 1, and the output end of the differential-mode noise elimination circuit 3 is connected to the input end of the RS latch 4; the high-voltage level shift circuit 1 is a high-voltage level shift circuit in the high-voltage side channel of the half-bridge gate drive circuit;

[0052] The input end of the high-voltage level shift circuit 1 is connected to the output end of the pulse generating circuit of the high-voltage side channel, and the input end of the pulse generating circuit is connected to the output end of the input buffer circuit of the half-bridge gate drive circuit. After the input buffer circuit buffers the received square wave signal, it outputs a square wave buffer signal to the pulse generating circuit. The pulse generating circuit provides a corresponding pulse input signal to the high-voltage level shift circuit based on the square wave buffer signal. The high-voltage level shift circuit outputs a corresponding negative pulse signal based on the received pulse input signal. The common-mode noise elimination circuit 2 is used to transmit a 1 / 2VDD voltage to the input end of the RS latch 4 when there is common-mode noise in the negative pulse signal output by the high-voltage level shift circuit, and the input end of the RS latch 4 maintains a high level; VDD is the voltage difference between the power supply potential VB and the floating ground potential VS of the high-voltage side channel in the half-bridge gate drive circuit; the threshold voltage of the RS latch 4 is less than 1 / 2VDD;

[0053] The differential mode noise elimination circuit 3 is used to turn on the differential mode noise elimination circuit through resistor voltage division when the negative pulse signal output by the high voltage level shift circuit 1 has differential mode noise, so that the input end of the RS latch 4 maintains a high level.

[0054] In the above structure, the high-voltage level shift circuit 1 includes a first LDMOS transistor LD1, a second LDMOS transistor LD2, a seventh PMOS transistor P1, an eighth PMOS transistor P2, a first zener diode ZD1 and a second zener diode ZD2; the gate of the first LDMOS transistor LD1 is connected to the SET output end of the pulse signal generating circuit of the high-voltage side channel in the half-bridge gate drive circuit, the source of the first LDMOS transistor LD1 is connected to the floating ground potential VS, the drain of the first LDMOS transistor LD1 is respectively connected to the drain of the seventh PMOS transistor, one end of the first resistor R1 and the gate of the third PMOS transistor MP3, the gate of the seventh PMOS transistor P1 is connected to the drain of the seventh PMOS transistor P1, the source of the seventh PMOS transistor P1 is connected to the power supply VB, and the first The input end of the voltage stabilizing diode ZD1 is connected to the drain of the seventh PMOS tube P1, and the output end of the first voltage stabilizing diode ZD1 is connected to the power supply; the gate of the second LDMOS tube LD2 is connected to the RESET output end of the pulse signal generating circuit, the source of the second LDMOS tube LD2 is connected to the floating ground potential VS, the drain of the second LDMOS tube LD2 is respectively connected to the drain of the eighth PMOS tube P2, one end of the second resistor R2, and the gate of the first PMOS tube MP1, the gate of the eighth PMOS tube P2 is connected to the drain of the eighth PMOS tube P2, the source of the eighth PMOS tube P2 is connected to the power supply VB, the input end of the second voltage stabilizing diode ZD2 is connected to the drain of the eighth PMOS tube P2, and the output end of the second voltage stabilizing diode ZD2 is connected to the power supply VB. The two input ends of the high-voltage level shift circuit 1 are the gate of LD1 and the gate of LD2, respectively, the first output end of the high-voltage level shift circuit 1 is the drain of LD1, and the second output end of the high-voltage level shift circuit 1 is the drain of LD2. The high-voltage level shift circuit uses a PMOS tube to replace the resistor in the prior art. The gate and drain of the PMOS tube are connected to speed up the charging speed, thereby improving the signal transmission speed.

[0055] The common mode noise elimination circuit 2 in the above structure includes a first PMOS tube MP1, a second PMOS tube MP2, a third PMOS tube MP3, a fourth PMOS tube MP4, a first NMOS tube MN1, a second NMOS tube MN2, a third NMOS tube MN3, and a fourth NMOS tube MN4; the gate of the first PMOS tube MP1 is connected to the gate of the second PMOS tube MP2, and the gate of the first PMOS tube MP1 and the gate of the second PMOS tube MP2 are respectively connected to the second output end of the high voltage level shift circuit, that is, the gate of the first PMOS tube MP1 and the gate of the second PMOS tube MP2 are respectively connected to the second output end of the high voltage level shift circuit. The gates of the first PMOS tube MP1 are connected to the drain of the second LDMOS tube LD2, the source of the first PMOS tube MP1 is connected to the power supply VB, the drain of the first PMOS tube MP1 is connected to the drain of the first NMOS tube MN1, the source of the first NMOS tube MN1 is connected to the floating ground potential VS, the gate of the first NMOS tube MN1 is connected to the gate of the second NMOS tube MN2, the gate of the first NMOS tube MN1 is connected to the drain of the first NMOS tube MN1, the source of the second NMOS tube MN2 is connected to the floating ground potential VS, the drain of the second NMOS tube MN1 is connected to the drain of the third PMOS tube MP3. The gate of the third PMOS tube MP3 is connected to the gate of the fourth PMOS tube MP4, and the gate of the third PMOS tube MP3 and the gate of the fourth PMOS tube MP4 are respectively connected to the first output end of the high-voltage level shift circuit, that is, the gate of the third PMOS tube MP3 and the gate of the fourth PMOS tube MP4 are respectively connected to the drain of the first LDMOS tube LD1, the source of the third PMOS tube MP3 is connected to the power supply VB, the drain of the second PMOS tube MP2 is connected to the drain of the third NMOS tube MN3, the source of the second PMOS tube MP2 is connected to the power supply VB, and the third NMOS The source of the transistor MN3 is connected to the floating ground potential VS, the gate of the third NMOS transistor MN3 is connected to the gate of the fourth NMOS transistor MN4, the source of the fourth PMOS transistor MP4 is connected to the power supply VB, the drain of the fourth PMOS transistor MP4 is connected to the drain of the fourth NMOS transistor MN4, the drain of the fourth NMOS transistor MN4 is connected to the gate of the fourth NMOS transistor MN4, the source of the fourth NMOS transistor MN4 is connected to the floating ground potential VS, the drain of the second PMOS transistor MP2 is connected to the S set terminal of the RS latch, and the drain of the third PMOS transistor MP3 is connected to the R reset terminal of the RS latch. The two input terminals of the common mode noise elimination circuit 2: the gate connection of MP1 and MP2, the gate connection of MP3 and MP4, and the two output terminals of the common mode noise elimination circuit 2: the drain of MP3 and the drain of MP2.

[0056] Among them, the ratio of the width to length of the first PMOS tube MP1, the width to length of the second PMOS tube MP2, the width to length of the third PMOS tube MP3 and the width to length of the fourth PMOS tube MP4 is 1:m:m:1; the ratio of the width to length of the first NMOS tube MN1, the width to length of the second NMOS tube MN2, the width to length of the third NMOS tube MN3 and the width to length of the fourth NMOS tube MN4 is 1:m:m:1, wherein the optimal value of m is 5-10, such as 6, 7, 8, and m can also be 4.9, 4.8, etc. When the size of MN2 and MN3 is determined, the larger the value of m, the faster the charging speed of MN1 and MN4 will be, thereby making the transmission signal faster.

[0057] In the above structure, the differential mode noise elimination circuit 3 includes: a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5, wherein the ratio of the third resistor R3 to the first resistor R1 is equal to the ratio of the fourth resistor R4 to the second resistor R2; the ratio may be greater than or equal to 8, such as 9, 10, etc.; a fifth PMOS tube MP5 and a sixth PMOS tube MP6; one end of the first resistor R1 is connected to the first output end of the high voltage level shift circuit, that is, one end of the first resistor R1 is connected to the drain of the first LDMOS tube LD1, the other end of the first resistor R1 is respectively connected to one end of the third resistor R3 and the gate of the sixth PMOS tube MP6, the other end of the third resistor R3 is connected to the output end Q of the RS latch, and the second resistor R 2 is connected to the second output end of the high-voltage level shift circuit, that is, one end of the second resistor R2 is connected to the drain of the second LDMOS tube LD2, the other end of the second resistor R2 is respectively connected to one end of the fourth resistor R4 and the gate of the fifth PMOS tube MP5, and the other end of the fourth resistor R4 is connected to the inverting output end Q' of the RS latch; one end of the fifth resistor R5 is connected to the power supply VB, the other end of the fifth resistor R5 is connected to the drain of the fourth PMOS tube MP4, the drain of the fifth PMOS tube MP5 is connected to the R reset end of the RS latch, the source of the fifth PMOS tube MP5 is connected to the power supply VB, the drain of the sixth PMOS tube MP6 is connected to the S set end of the RS latch, and the source of the sixth PMOS tube MP6 is connected to the power supply VB. The input end of the differential mode noise elimination circuit 3 is one end of R1 and one end of R2, and the output end of the differential mode noise elimination circuit 3 is the drain of MP5 and the drain of MP6.

[0058] Among them, the resistance values ​​of the first resistor R1, the second resistor R2, the third resistor R3, and the fourth resistor R4 should be relatively large, for example, 100k ohms, 120k ohms, 200k ohms, etc., and the ratio of the third resistor to the first resistor is equal to the ratio of the fourth resistor to the second resistor; the two ratios of R3 / R1 and R4 / R2 are required to be relatively large, and are most preferably greater than or equal to 8, such as 8, 9, 10, etc., and can also be 11, 12, etc. The width-to-length ratio of the fifth PMOS tube and the width-to-length ratio of the sixth PMOS tube should be slightly larger than the width-to-length ratio of the first PMOS tube, the width-to-length ratio of the second PMOS tube, the width-to-length ratio of the third PMOS tube, and the width-to-length ratio of the fourth PMOS tube. For example, the width-to-length ratio of the fifth PMOS tube and the width-to-length ratio of the sixth PMOS tube is 10 (W / L), and the width-to-length ratio of other PMOS tubes is (W / L); to avoid the first PMOS tube, the second PMOS tube, the third PMOS tube, and the fourth PMOS tube from being turned on by mistake.

[0059] The output buffer circuit 5 in the above structure includes: an output buffer stage Driver-H, a ninth PMOS tube and a fifth NMOS tube, the input terminal IN of the output buffer stage is connected to the output terminal Q of the RS latch, the first output terminal OUT_DOWN of the output buffer stage is connected to the gate of the ninth PMOS tube MP7, the drain of the ninth PMOS tube MP7 is connected to the power supply VB, the source of the ninth PMOS tube MP7 is connected to the output terminal HO of the high-voltage side channel, the second output terminal OUT_UP of the output buffer stage is connected to the gate of the fifth NMOS tube, the drain of the fifth NMOS tube is connected to the output terminal of the high-voltage side channel, and the source of the fifth NMOS tube MN5 is connected to the floating ground potential VS. The input terminals of the RS latch are the S set terminal and the R reset terminal, and the output terminal of the RS latch is the Q output terminal.

[0060] The present application provides an ultra-low delay self-locking noise suppression level shift circuit, which includes at least a common-mode noise elimination circuit and a differential-mode noise elimination circuit. When common-mode noise exists in the negative pulse signal output by the high-voltage level shift circuit, a 1 / 2VDD voltage is transmitted to the input end of the RS latch through the common-mode noise elimination circuit, so that the input end of the RS latch is kept at a high level, and the state of the RS latch does not change, thereby eliminating the common-mode noise; when differential-mode noise exists in the negative pulse signal output by the high-voltage level shift circuit, the differential-mode noise elimination circuit keeps the input end of the RS latch at a high level through voltage division, and the state of the RS latch does not change, thereby eliminating the differential-mode noise. The common-mode noise elimination circuit and the differential-mode noise elimination circuit of the present application do not use an RC filter circuit. While effectively removing the noise in the negative pulse signal in the high-voltage side channel, they have lower delay characteristics, thereby enhancing the reliability and stability of the half-bridge drive circuit. In addition, the present application can solve related problems such as process fluctuations and layout mismatches through the differential-mode noise elimination circuit, and can cope with various abnormal situations.

[0061] Below Figure 5 Take the common mode noise elimination circuit process as an example to illustrate. Figure 5 As shown, when S is connected to the high-voltage side channel without dV / dt noise, the signal transmission is divided into the following cases:

[0062] 1. When Sa = "0", Ra = "1", MP1 and MP2 are turned on, MP3 and MP4 are turned off, the gate voltage of MN3 and MN4 increases and turns on, S_OUT = "0", R_OUT = "1", and the signal is transmitted normally;

[0063] 2. When Sa = "1", Ra = "0", MP1 and MP2 are turned off, MP3 and MP4 are turned on, the gate voltage of MN1 and MN2 increases and turns on, S_OUT = "1", R_OUT = "0", and the signal is transmitted normally;

[0064] 3. When Sa = "1", Ra = "1", the PMOS tube is turned off, and S_OUT and R_OUT both maintain the output of the previous state.

[0065] It can be understood that Sa and Ra are two input terminals of the common-mode noise elimination circuit, Sa is connected to the drain of LD2, Ra is connected to the drain of LD1, R_OUT and S_OUT are two output terminals of the common-mode noise elimination circuit, R_OUT is connected to the R terminal of the RS latch, and S_OUT is connected to the S terminal of the RS latch.

[0066] Therefore, when there is no dV / dt noise in the high-voltage side channel, the signal can be transmitted normally.

[0067] When the voltage of the floating ground potential VS of the high-voltage side channel rises sharply, dV / dt noise is likely to occur. When dV / dt noise occurs, the parasitic capacitance C DS The introduced noise current is shown in formula (3):

[0068]

[0069] Among them, I noise is the noise current, the noise current I noise When a transient voltage drop is generated across the seventh PMOS tube P1 and the eighth PMOS tube P2, it is assumed that the introduced voltage drops are the same. The voltage drop introduced by the seventh PMOS tube P1 turns on MP1, and introduces a noise current I1 under the action of the current mirrors MN1 and MN2. It is assumed that (W / L)MN2 / (W / L)MN1=m, where (W / L) is the width-to-length ratio. The noise current flowing through MN2 is shown in formula (4):

[0070]

[0071] Where I1 is the noise current flowing through MN2, μp is the electron mobility of the first PMOS tube MP1, and C ox is the gate oxide capacitance per unit area, V THP is the threshold voltage of the first PMOS tube MP1. The voltage drop introduced by the transient dVs / dt noise at P2 turns on MP3, generating a noise current I3, as shown in equation (5):

[0072]

[0073] When I1=I3, the size ratio of each tube can be obtained as shown in formula (6):

[0074]

[0075] dV / dt noise will make S and R "0" at the same time. At this time, all PMOS tubes are turned on, and all NMOS tubes are also turned on. Since the width-to-length ratio of MP1: the width-to-length ratio of MP2: the width-to-length ratio of MP3: the width-to-length ratio of MP4 is 1:m:m:1, and the width-to-length ratio of MN1: the width-to-length ratio of MN2: the width-to-length ratio of MN3: the width-to-length ratio of MN4 is 1:m:m:1, the charging capacity of the third PMOS tube at the R_OUT end is equal to the discharge capacity of the second N-type transistor MN3, and R_OUT outputs 1 / 2VDD voltage to the reset end of the RS latch, and the charging capacity of the second PMOS tube MP2 at the S_OUT end is equal to the discharge capacity of the third N-type transistor MN3, and S_OUT outputs 1 / 2VDD voltage to the S set end of the RS latch. Both input ends of the RS latch maintain a high level, thereby eliminating common-mode noise without introducing excessive delay. VDD=VB-VS.

[0076] Therefore, the common mode noise elimination circuit can eliminate the common mode noise in the dV / dt noise when the dV / dt noise appears in the high voltage side channel.

[0077] In the actual production process, due to the resistance and capacitance mismatch caused by the process, the parameters of the two tubes LD1 and LD2 will be different, which will cause differential mode noise. Therefore, the present invention designs a differential mode noise elimination circuit, which can eliminate the differential mode noise in the dV / dt noise when dV / dt noise appears in the high-voltage side channel. In the actual design, R3 / R1=10 is used for illustration. Figure 4, the working principle of differential mode noise elimination is: when the signal is transmitted normally, SET = "1", RESET = "0", MP1, MP2, MN3, MN4 are turned on, S = "1", R = "0", then the output of the RS latch Q = "1", Q` = "0", at this time HO = "1", the power tube is turned on. For the noise self-locking structure, since R3 / R1 = 10, the voltage difference of A1 relative to the voltage of VB is relatively large. At this time, MP5 is turned on and current is injected, making S become a high level faster, accelerating signal transmission and reducing delay. The same applies when SET = "0", RESET = "1".

[0078] When noise comes, the signal is R = "1", S = "1", the signal is maintained, A1 and A2 both become low level, and the state of the RS latch remains unchanged, so that noise will not change the output, achieving the purpose of eliminating noise.

[0079] Since the differential mode noise elimination circuit only includes a voltage dividing branch composed of a first resistor, a second resistor, a third resistor and a fourth resistor and two branches MP5 and MP6, the signal transmission can be fast. In addition, when the negative pulse signal output by the high-voltage level shift circuit has noise, the drain of the first LDMOS tube and the drain of the second LDMOS tube produce a voltage drop, the first PMOS tube, the second PMOS tube, the third PMOS tube and the fourth PMOS tube are turned on, and the voltage of the two input terminals of the RS latch is 1 / 2VDD; the gate voltage of the first PMOS tube and the gate voltage of the second PMOS tube are less than the power supply voltage, the first PMOS tube and the second PMOS tube are turned on, and the voltage of the input terminal of the RS latch is pulled up from 1 / 2VDD to VDD. The signal transmission speed can be accelerated.

[0080] The present application provides an ultra-low delay self-locking noise suppression level shift circuit. By designing a relatively low threshold voltage of the RS latch, a voltage of 1 / 2VDD is a high level for the RS latch, so that the input end of the RS latch maintains a high level and the state of the RS latch remains unchanged, thereby eliminating common-mode noise; when there is differential-mode noise in the negative pulse signal output by the high-voltage level shift circuit, the differential-mode noise elimination circuit senses the noise through the resistor voltage divider, turns on the differential-mode noise elimination circuit, so that the input end of the RS latch maintains a high level and the state of the RS latch remains unchanged, thereby eliminating differential-mode noise. Neither the common-mode noise elimination circuit nor the differential-mode noise elimination circuit of the present application uses an RC filtering circuit. While effectively removing the noise in the negative pulse signal in the high-voltage side channel, it has a lower delay characteristic, thereby enhancing the reliability and stability of the half-bridge drive circuit. In addition, the present application can solve related problems such as process fluctuations and layout mismatches through the differential-mode noise elimination circuit, and can cope with various abnormal situations.

[0081] Next, combine Figure 6-Figure 12 The simulation waveform further illustrates the noise elimination capability of the present application.

[0082] Figure 6-Figure 10 The simulation conditions are as follows: VB is connected to a 15V voltage source, the input frequency of the input terminals HIN and LIN is 500K, the input range is 0 to 15V, the rising time of the floating ground potential VS is controlled from 0 to 600V, and the voltage difference between the high-voltage side channel output terminal HO and the floating ground potential VS is observed.

[0083] like Figure 6 As shown, from top to bottom, each waveform represents the voltage of the power supply VB, the voltage of the floating ground potential VS, the voltage of the output terminal HO, and the voltage difference between the output terminal HO and the floating ground potential. The ordinate N of the first three waveforms represents the voltage amplitude, and the unit is V. The ordinate V of the fourth waveform represents the voltage amplitude, and the unit is uV (microvolt). The four waveforms share a horizontal axis time to represent time. When the voltage of VS rises rapidly and dV / dt reaches 100V / ns, noise pulses are generated at the drain of the first LDMOS tube LD1 and the drain of the second LDMOS tube LD2. At this time, the voltage difference between the output terminal HO and the floating ground potential is only 5.8584uV. The common-mode noise elimination circuit completely suppresses the transmission of the noise signal and does not cause the circuit to be turned on, indicating that the noise elimination ability of the common-mode noise elimination circuit is effective.

[0084] like Figure 7 As shown, MP5 and MP6 play the role of removing differential mode noise in the circuit. By reducing the width-to-length ratio of MP5 and MP6, and connecting a capacitor in parallel next to LD1, simulation is performed under the condition of differential mode noise, and it is found that false start-up is caused.

[0085] like Figure 8 As shown, the width-to-length ratio of MP5 and MP6 of the circuit is increased to 8 times, and the parallel capacitance is increased by 50 times. The simulation shows that the circuit does not cause false start-up, which shows that the circuit of the present invention has strong noise elimination ability, and can not only eliminate common mode noise, but also has strong ability to eliminate differential mode noise. Therefore, the delay characteristics of this structure overcome the shortcomings of the traditional transient noise suppression circuit and break the contradictory relationship between the delay and transient noise suppression ability of the traditional level shift circuit.

[0086] like Fig. 9 As shown, the delay of the entire path is less than 20ns. However, for traditional RC filtering technology, dV / dt noise greater than 50V / ns requires a filtering width greater than 70ns to eliminate it, so at least 70ns of delay is introduced.

[0087] like Fig.10As shown, the delay of the ultra-low delay self-locking noise suppression level shift circuit of the present invention is 1.647ns, which realizes ultra-low delay transmission of the transmission signal and meets the transmission delay requirement of the level shift circuit applied to the half-bridge gate driver chip.

[0088] Fig.11 The schematic diagram of the static current simulation results of VB and VDD provided by the present invention, static current simulation, static current refers to the current when the level shift circuit has no input signal, that is, the current consumed by the circuit itself when the circuit itself is not affected by external factors. The static current directly affects the reliability and power loss of the level shift circuit, so the static current is an important indicator of circuit design.

[0089] Simulation conditions: input HIN, LIN is 0V, VDD=15V, VB=15V, VS=0V, GND=0V, measure the current of VB and VDD.

[0090] like Fig.11 As shown, the static currents of VB and VDD are very small, both less than 10nA, meeting the design requirements of low power consumption.

[0091] Fig.12 The schematic diagram of the simulation result of the negative VS tolerance capability of the circuit provided by the present invention shows that in some traditional half-bridge drive circuit designs, an RC filter circuit is often used after the high-voltage level shift circuit to filter out dV / dt noise, so the switch threshold voltage of the first-stage inverter of the filter circuit is set relatively small. However, the switch threshold voltage of the inverter in the filter circuit is based on the floating ground potential VS terminal as the reference ground, so the threshold voltage will change with the VS terminal voltage. In order to ensure that the high-side drive circuit has a strong enough ability to withstand negative overshoot voltage, it is necessary to make the switch threshold voltage of the first-stage inverter of the filter circuit large enough. Even when VS generates a negative overshoot voltage, the subsequent circuit can normally receive the normal pulse signal output by the high-voltage level shift circuit. Therefore, there is a contradiction between the half-bridge drive circuit's ability to resist dV / dt noise and its immunity to negative overshoot.

[0092] In order to compare whether the circuit structure designed in the present invention is optimized in terms of its ability to withstand VS negative pressure, we used the same module to build a circuit that uses RC filtering to eliminate noise for comparison.

[0093] Simulation conditions: Simulation of VS negative voltage resistance: VIN is 0V to 15V, the period is 2us, and the pulse width is 1us. The square wave, where VB = (15-X)V, VS = (-X)V, increases the value of X until the output waveform is abnormal. When the simulation output is normal, the maximum value of X is the circuit's VS negative voltage resistance. The simulation shows that the circuit with RC filtering to eliminate noise has a VS negative voltage resistance of -6.9V. Figure 6As shown, the circuit of the present invention has a VS negative voltage tolerance of -12.9V, which is 6.9V better than the ordinary module. Cause analysis: The common mode module is a voltage-current-voltage (VIV) structure. The circuit first converts the input signal from a voltage signal to a current signal, and then restores the current signal to a voltage signal based on the VS voltage.

[0094] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0095] Although the present invention has been described in conjunction with specific features and embodiments thereof, it is apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the present invention. Accordingly, this specification and the accompanying drawings are merely exemplary illustrations of the present invention as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the present invention. Obviously, those skilled in the art may make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, the present invention is intended to include such modifications and variations if they fall within the scope of the claims of the present invention and their equivalents.

Claims

1. An ultra-low-latency self-locking noise suppression level shift circuit, characterized in that: At least: A common mode noise elimination circuit, a differential mode noise elimination circuit, an RS latch and a high voltage level shift circuit, wherein the input end of the common mode noise elimination circuit is connected to the output end of the high voltage level shift circuit; the output end of the common mode noise elimination circuit is connected to the input end of the RS latch; the input end of the differential mode noise elimination circuit is connected to the output end of the high voltage level shift circuit, and the output end of the differential mode noise elimination circuit is connected to the input end of the RS latch; The common mode noise elimination circuit is used to transmit 1 / 2VDD voltage to the input end of the RS latch when the negative noise pulse signal output by the high voltage level shift circuit has common mode noise, and the input end of the RS latch maintains a high level; VDD is the voltage difference between the power supply and the floating ground potential; the threshold voltage of the RS latch is less than 1 / 2VDD; The differential mode noise elimination circuit is used to turn on the differential mode noise elimination circuit through resistor voltage division when the negative noise pulse signal output by the high voltage level shift circuit has differential mode noise, and the input end of the RS latch maintains a high level.

2. The ultra-low-delay self-locking noise suppression level shift circuit according to claim 1, characterized in that: The floating ground potential is the floating ground potential of the high-voltage side channel in the half-bridge gate drive circuit, and the common-mode noise elimination circuit includes a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, and a fourth NMOS tube; The gate of the first PMOS tube is connected to the gate of the second PMOS tube, the gate of the first PMOS tube and the gate of the second PMOS tube are connected to the second output end of the high-voltage level shift circuit, the source of the first PMOS tube is connected to the power supply, the drain of the first PMOS tube is connected to the drain of the first NMOS tube, the source of the first NMOS tube is connected to the floating ground potential, the gate of the first NMOS tube is connected to the gate of the second NMOS tube, the gate of the first NMOS tube is connected to the drain of the first NMOS tube, the source of the second NMOS tube is connected to the floating ground potential, and the drain of the second NMOS tube is connected to the drain of the third PMOS tube; the gate of the third PMOS tube is connected to the gate of the fourth PMOS tube, the gate of the third PMOS tube is connected to the fourth PMOS tube, and the gate of the third PMOS tube is connected to the fourth PMOS tube. The gate of the S tube is connected to the first output end of the high-voltage level shift circuit, the source of the third PMOS tube is connected to the power supply, the drain of the second PMOS tube is connected to the drain of the third NMOS tube, the source of the second PMOS tube is connected to the power supply, the source of the third NMOS tube is connected to the floating ground potential, the gate of the third NMOS tube is connected to the gate of the fourth NMOS tube, the source of the fourth PMOS tube is connected to the power supply, the drain of the fourth PMOS tube is connected to the drain of the fourth NMOS tube, the drain of the fourth NMOS tube is connected to the gate of the fourth NMOS tube, the source of the fourth NMOS tube is connected to the floating ground potential, the drain of the second PMOS tube is connected to the set end of the RS latch, and the drain of the third PMOS tube is connected to the reset end of the RS latch.

3. The ultra-low-delay self-locking noise suppression level shift circuit according to claim 2, characterized in that: The differential mode noise elimination circuit comprises: a first resistor, a second resistor, a third resistor, a fourth resistor, a fifth PMOS transistor and a sixth PMOS transistor; One end of the first resistor is connected to the first output end of the high-voltage level shift circuit, the other end of the first resistor is connected to one end of the third resistor, the other end of the first resistor is connected to the gate of the sixth PMOS tube, the other end of the third resistor is connected to the output end of the RS latch, one end of the second resistor is connected to the second output end of the high-voltage level shift circuit, the other end of the second resistor is connected to one end of the fourth resistor, the other end of the second resistor is connected to the gate of the fifth PMOS tube, and the other end of the fourth resistor is connected to the inverting output end of the RS latch; the drain of the fifth PMOS tube is connected to the reset end of the RS latch, the source of the fifth PMOS tube is connected to the power supply, the drain of the sixth PMOS tube is connected to the set end of the RS latch, and the source of the sixth PMOS tube is connected to the power supply.

4. The ultra-low-delay self-locking noise suppression level shift circuit according to claim 3, characterized in that: The high-voltage level shift circuit includes a first LDMOS transistor, a second LDMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a first voltage stabilizing diode and a second voltage stabilizing diode; The gate of the first LDMOS tube is connected to an output end of a pulse signal generating circuit of a high-voltage side channel in a half-bridge gate driving circuit, the source of the first LDMOS tube is connected to the floating ground potential, the drain of the first LDMOS tube is respectively connected to the drain of the seventh PMOS tube, one end of the first resistor and the gate of the third PMOS tube, the gate of the seventh PMOS tube is connected to the drain of the seventh PMOS tube, the source of the seventh PMOS tube is connected to the power supply, the input end of the first voltage regulator diode is connected to the drain of the seventh PMOS tube, and the output end of the first voltage regulator diode is connected to the drain of the seventh PMOS tube. The gate of the second LDMOS tube is connected to the other output end of the pulse signal generating circuit, the source of the second LDMOS tube is connected to the floating ground potential, the drain of the second LDMOS tube is respectively connected to the drain of the eighth PMOS tube, one end of the second resistor, and the gate of the first PMOS tube, the gate of the eighth PMOS tube is connected to the drain of the eighth PMOS tube, the source of the eighth PMOS tube is connected to the power supply, the input end of the second zener diode is connected to the drain of the eighth PMOS tube, and the output end of the second zener diode is connected to the power supply.

5. The ultra-low-delay self-locking noise suppression level shift circuit according to claim 4, characterized in that: When the negative pulse signal output by the high-voltage level shift circuit has noise, a voltage drop is generated at the drain of the first LDMOS tube and the drain of the second LDMOS tube, the first PMOS tube, the second PMOS tube, the third PMOS tube, and the fourth PMOS tube are turned on, and the voltages at the two input terminals of the RS latch are 1 / 2VDD; the gate voltages of the first PMOS tube and the gate voltage of the second PMOS tube are less than the power supply voltage, the first PMOS tube and the second PMOS tube are turned on, and the voltage at the input terminal of the RS latch is pulled up from 1 / 2VDD to VDD.

6. The ultra-low-delay self-locking noise suppression level shift circuit according to claim 2, characterized in that: The self-locking noise suppression level shift circuit further includes a fifth resistor, one end of the fifth resistor is connected to the power supply, and the other end of the fifth resistor is connected to the drain of the fourth PMOS tube.

7. The ultra-low-delay self-locking noise suppression level shift circuit according to claim 3, characterized in that: The ratio of the third resistor to the first resistor is equal to the ratio of the fourth resistor to the second resistor.

8. The ultra-low-delay self-locking noise suppression level shift circuit according to claim 2, characterized in that: The ratio of the width to length ratio of the first PMOS tube, the width to length ratio of the second PMOS tube, the width to length ratio of the third PMOS tube, and the width to length ratio of the fourth PMOS tube is 1:m:m:1; the ratio of the width to length ratio of the first NMOS tube, the width to length ratio of the second NMOS tube, the width to length ratio of the third NMOS tube, and the width to length ratio of the fourth NMOS tube is 1:m:m:1, and the value of m is 5-10.

9. The ultra-low-delay self-locking noise suppression level shift circuit according to claim 3, characterized in that: The width-to-length ratios of the fifth PMOS tube and the sixth PMOS tube are both greater than the width-to-length ratios of the first PMOS tube, the second PMOS tube, the third PMOS tube, and the fourth PMOS tube.

10. The ultra-low-delay self-locking noise suppression level shift circuit according to claim 3, characterized in that: The self-locking noise suppression level shift circuit also includes an output buffer circuit, which includes an output buffer stage, a ninth PMOS tube and a fifth NMOS tube. The input end of the output buffer stage is connected to the output end of the RS latch, the first output end of the output buffer stage is connected to the gate of the ninth PMOS tube, the drain of the ninth PMOS tube is connected to the power supply, the source of the ninth PMOS tube is connected to the output end of the high-voltage side channel, the second output end of the output buffer stage is connected to the gate of the fifth NMOS tube, the drain of the fifth NMOS tube is connected to the output end of the high-voltage side channel, and the source of the fifth NMOS tube is connected to the floating ground potential.

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