A calibration system and method based on pure digital circuit

Abstract

The present invention belongs to the technical field of digital integrated circuits, and particularly relates to a calibration system based on a pure digital circuit and a method thereof. The system comprises: an SPI read-write module; a register module; a state control module, which generates a frequency calibration valid signal and an amplitude calibration valid signal according to the configuration value of the register module and the frequency calibration control signal and the amplitude calibration control signal sent by the frequency detector; a frequency calibration module, which generates a VCO core number and a tuning capacitance value under a corresponding state according to the initial values ​​of each module configured by the register module and the frequency calibration valid signal generated by the state control module; an amplitude calibration module, which generates an optimized amplitude setting under a corresponding state according to the initial values ​​of each module configured by the register module and the amplitude calibration valid signal generated by the state control module; the present invention can meet the amplitude and frequency calibration under different frequencies, that is, the output clock of the voltage-controlled oscillator can meet the needs of many high-precision application fields.

Description

Technical Field

[0001] The invention belongs to the technical field of digital integrated circuits, and in particular relates to a calibration system based on a pure digital circuit and a method thereof. Background Art

[0002] A phase-locked loop (PLL) is a structure that uses feedback technology to compare input and output clock signals to synchronize the output signal with the input signal. In this state, the phase difference between the input and output signals is zero or constant, and this state is called a locked state. When there is a phase error between the output and input signals, the error is minimized through the feedback loop, so that the loop enters the locked state again. The most basic phase-locked loop contains three basic modules: phase detector (PD, Phase Detector), loop filter (Loop Filter) and voltage-controlled oscillator (VCO, Voltage Controlled Oscillator). According to the characteristics of the negative feedback control system, the phase difference between the clock of the voltage-controlled oscillator after frequency division and the reference clock always fluctuates within a small range. The size of this range is crucial to the accuracy of the output clock frequency and phase of the voltage-controlled oscillator. We call the process of adjusting the output signal and the input signal to reach a locked state calibration. The quality of the calibration method directly affects whether the calibration state can be reached and the size of the final fluctuation range, so more and more research has begun to focus on how to design a more accurate calibration method. Summary of the invention

[0003] The purpose of the present invention is to overcome the above-mentioned shortcomings of the prior art. The present invention provides a calibration system and method based on a pure digital circuit, which can meet the amplitude and frequency calibration at different frequencies, that is, the output clock of the voltage-controlled oscillator can meet the needs of many high-precision application fields.

[0004] In order to solve the above technical problems, the present invention provides a calibration system based on a pure digital circuit, comprising:

[0005] SPI read / write module, which reads and writes the values ​​of all register modules in the calibration system according to the SPI protocol, thereby regulating the calibration process of the entire calibration system;

[0006] Register module, used to store the initial values ​​of each state and the output values ​​of each module required by the entire calibration system;

[0007] The state control module generates a frequency calibration valid signal and an amplitude calibration valid signal according to the configuration value of the register module and the frequency calibration control signal and the amplitude calibration control signal sent by the frequency detector and the phase detector; it also includes controlling the operating state of the entire calibration system, and different operating states correspond to different control signals; the operating states include an idle state IDLE, amplitude calibration states ACAL1, ACAL2 and ACAL3, a frequency calibration state FCAL and a calibration end state END;

[0008] The frequency calibration module generates the best VCO core number and tuning capacitance value under the corresponding state according to the initial values ​​of each module configured by the register module and the frequency calibration valid signal generated by the state control module, thereby realizing frequency calibration;

[0009] The amplitude calibration module generates an optimized amplitude setting under the corresponding state according to the initial values ​​of each module configured by the register module and the amplitude calibration valid signal generated by the state control module, thereby realizing amplitude calibration; the amplitude calibration module includes an amplitude calibration state one module, an amplitude calibration state two module and an amplitude calibration state three module; wherein the amplitude calibration state one module is used for waiting for the frequency calibration control signal to be valid during the first calibration, so as to smoothly switch to the frequency calibration mode; the amplitude calibration state two is used for the normal switching between the amplitude calibration process and the frequency calibration process; the amplitude calibration state three module is used for replacing the VCO core number when the tuning capacitor cannot meet the requirements during the frequency calibration process.

[0010] Preferably, the SPI read / write module completes the function of externally controlling the calibration system through the four ports of CS, SCLK, SDI and SDO, and controls the initial VCO core number, initial value of tuning capacitance and initial value of amplitude of the calibration system through the configuration register module. External designers can read and write the values ​​of registers in the calibration system according to the SPI protocol, so as to configure the corresponding state for the calibration system so that it can complete the calibration work normally; testers can also obtain the intermediate state values ​​of certain calibrations by reading the values ​​of corresponding registers, so as to judge whether the calibration system is operating normally or the cause of the error.

[0011] Preferably, the storage of the initial values ​​of each state required for the entire calibration system specifically includes: whether to force the selection of the VCO core and the corresponding selected VCO core number, the two delay time values ​​between starting the calibration system and starting the amplitude calibration, the delay time for starting the amplitude calibration again after each switching of the VCO core, the number corresponding to the initial VCO core and the total number, the initial value and maximum value of the tuning capacitor, the total number of optimized VCO core amplitude segments and the maximum amplitude, the optimized amplitude segments and amplitude values ​​of the VCO core corresponding to the initial state, the time corresponding to the frequency calibration control signal controlling the tuning capacitor to increase or decrease by one step, the time corresponding to the amplitude calibration control signal controlling the optimized amplitude to increase or decrease by one step, and the delay time between the end of the amplitude and frequency calibration and the end of the operation of the entire calibration system.

[0012] Preferably, the frequency calibration module, according to the corresponding configuration of the register module and under the control of the state control module, controls the tuning capacitor to increase or decrease from the initial value according to the configured time according to the different states of the frequency calibration control signal. If the tuning capacitor value exceeds the specified value, the VCO core will be changed, and the tuning capacitor will be traversed again in the new VCO core to select the most appropriate value; when the amplitude calibration control signal is valid or the VCO core has not found the most appropriate tuning capacitor after traversal, the frequency calibration process is terminated.

[0013] Preferably, the amplitude calibration state one module is a state entered when the calibration is started for the first time and after two delay times have expired. In this state, the calibration system will continue to perform the amplitude calibration process according to the amplitude calibration control signal until the frequency calibration control signal is valid or all amplitude values ​​of the optimized amplitude segment corresponding to the VCO core have been traversed. Only then will the amplitude calibration state one module be exited and the calibration state be ended.

[0014] Preferably, the amplitude calibration state two module is an amplitude calibration module corresponding to the second amplitude calibration after the first frequency calibration. The amplitude calibration state two module completes the normal frequency calibration function and enters the frequency calibration state after completion, or ends the calibration process because the traversal ends without reaching the specified state.

[0015] Preferably, the amplitude calibration state three module is a state entered when the tuning capacitor cannot meet the demand during the frequency calibration process and the VCO core number is replaced. In this state, amplitude calibration is not performed directly, and amplitude calibration is performed after a specified delay. The biggest difference from the amplitude calibration state two module is the delay time. This measure can ensure that after the VCO core is replaced, the calibration system reaches a relatively stable state again.

[0016] The present invention also provides a calibration method based on a pure digital circuit, comprising the following steps:

[0017] Step 1: After completing the configuration of the corresponding registers in the register module, start the calibration system. After the first two delay times of the configuration are over, the calibration system enters the amplitude calibration state ACAL1. In the amplitude calibration state ACAL1, the calibration system performs amplitude calibration according to different states of the amplitude calibration control signal a_con until the frequency calibration control signal is valid and enters the frequency calibration state FCAL, or when all the amplitude values ​​of the optimized amplitude segment corresponding to the VCO core are traversed, the frequency calibration control signal is still invalid, that is, f_con=0 and the optimal amplitude value is not found. At this time, it will directly enter the calibration end state END; when the frequency calibration control signal is valid, that is, f_con≠0, the calibration system will enter the frequency calibration state FCAL. In the frequency calibration state FCAL, the calibration system will perform frequency calibration according to different values ​​of the frequency calibration control signal f_con. When the tuning capacitance value exceeds the specified value, the VCO core will be changed. At this time, the calibration system enters the amplitude calibration state ACAL2. If the frequency calibration is performed normally, the frequency calibration control signal f_con becomes an invalid value, that is, f_con=0, and the calibration system will enter the amplitude calibration state ACAL2;

[0018] Step 2: In the amplitude calibration state ACAL2, the calibration system will perform amplitude calibration according to different states of the amplitude control signal a_con. If it is detected that the frequency control signal is valid, that is, f_con≠0, it will return to the frequency calibration state FCAL. After all the amplitude values ​​of the optimized amplitude segment corresponding to the VCO core are traversed, the frequency calibration control signal is still invalid, that is, f_con=0 and the optimal amplitude value is not found, or the amplitude calibration time reaches the specified time, the calibration system will directly enter the end state END; when the calibration system is in the amplitude calibration state ACAL3, the amplitude calibration state ACAL3 will delay for a certain time before starting the amplitude calibration process. If within the specified delay time, the frequency calibration control signal is valid, that is, f_con≠0, the calibration system will re-enter the frequency calibration state FCAL, and all the amplitude values ​​of the optimized amplitude segment corresponding to the VCO core are traversed and the optimal amplitude value is still not found, or the calibration system will enter the end state END after exceeding the specified time; when the calibration system is in the end state END, the entire calibration process will end after the specified time, and enter the idle state IDLE to wait for the next calibration process cycle.

[0019] Preferably, a frequency calibration process is also included, and the frequency calibration process specifically includes:

[0020] After the frequency calibration control signal is valid, the frequency calibration control signal f_con is checked every specified time to see if it is valid, that is, whether f_con is 0. If it is invalid, the frequency calibration process is terminated. If it is valid, the specific value of f_con is determined.

[0021] If f_con=2'b10, and the tuning capacitor has not reached the upper boundary value, the value of the tuning capacitor will increase by 1. However, when the tuning capacitor has reached the upper boundary value, it will be determined whether the VCO core number has reached the maximum value. When the VCO core number has not reached the maximum value, the VCO core number value will increase by 1, and then wait for the specified step delay time to enter the next cycle, otherwise the frequency calibration process ends.

[0022] If f_con=2'b01 or 2'b11, and the tuning capacitance has not reached the lower boundary value, the tuning capacitance value is reduced by 1, and then the specified step delay time is waited to enter the next cycle, otherwise the frequency calibration process is terminated.

[0023] Preferably, an amplitude calibration process is also included, and the amplitude calibration process specifically includes:

[0024] After the amplitude calibration signal is valid, wait for the specified step delay time and determine the value of the amplitude calibration control signal a_con;

[0025] When the value of a_con is 0, it is then determined whether the current amplitude value reaches the lower boundary value of the amplitude;

[0026] If the lower boundary value is reached and the number of amplitude segments reaches the lower boundary value, the amplitude calibration process will end;

[0027] If the lower boundary value is reached and the number of amplitude segments has not reached the lower boundary value, the number of amplitude segments decreases by 1 and the amplitude returns to the maximum value;

[0028] If the lower boundary value is not reached, the current amplitude value will be reduced by 1, and then the frequency calibration control signal f_con will be judged whether it is valid. If it is not valid, it will wait for the specified step delay time to enter the next cycle. If it is valid, the amplitude calibration process will end;

[0029] When a_con=1'b1, it is then determined whether the current amplitude value reaches the upper boundary value of the amplitude value. If it reaches the upper boundary value and the number of amplitude segments reaches the upper boundary value, the amplitude calibration process will end;

[0030] If the upper boundary value is reached and the number of amplitude segments does not reach the upper boundary value, the amplitude segment number increases by 1 and the amplitude returns to the minimum value;

[0031] If the upper boundary value is not reached, the current amplitude value will increase by 1, and then determine whether the frequency calibration control signal f_con is valid. If not, wait for the specified step delay time before entering the next cycle. If valid, end the amplitude calibration process.

[0032] Compared with the prior art, the present invention has the following beneficial effects:

[0033] The calibration system of the present invention mainly includes an SPI read-write module, a register module, a state control module, a frequency calibration module and an amplitude calibration module. The state control module mainly controls the operating state of the entire calibration circuit according to the initial values ​​of various calibration circuits transmitted by the register module, the amplitude control signal and the frequency control signal transmitted by the frequency detector and phase detector. Different operating states correspond to different control signals. These control signals can drive the frequency calibration module and the amplitude calibration module to perform corresponding frequency calibration and amplitude calibration on the entire circuit to adjust the output of the voltage-controlled oscillator to be consistent with the reference voltage, thereby achieving the purpose of calibration.

[0034] The state control module of the present invention can control the entire calibration circuit to first perform amplitude calibration and then frequency calibration according to the different states of the configuration value of the register module, the amplitude calibration control signal and the frequency calibration control signal, and then perform amplitude calibration, and the process is repeated to ensure the accuracy of the output signal. Moreover, the frequency calibration module can adjust the entire frequency calibration circuit according to the frequency calibration control signal, the configuration value of the register and the frequency calibration effective signal generated by the state conversion module, and generate the best VCO core number and tuning capacitance value suitable for the current state, thereby ensuring the accuracy of the frequency of the output signal. The frequency calibration module can realize the regulation of multiple voltage-controlled oscillators, greatly enhancing the range of frequency calibration, so that the circuit can meet the needs of more high-precision application fields.

[0035] The present invention can adjust the entire amplitude calibration circuit according to the amplitude calibration control signal, the configuration value of the register and the amplitude calibration effective signal generated by the state conversion module through the amplitude calibration module, generate the best amplitude value suitable for the current state, etc., thereby ensuring the accuracy of the amplitude of the output signal. In addition, the amplitude calibration module optimizes the amplitude of the VCO core in sections, and can realize the calibration of signals with a wider amplitude range. The amplitude calibration module is composed of a plurality of modules corresponding to different amplitude calibration states, and can realize flexible configuration of the amplitude calibration signal generated under different conditions, so that the circuit can meet the needs of more complex fields. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 The figure is a structural block diagram of a calibration system based on a pure digital circuit according to the present invention.

[0037] Figure 2 It is a flow chart of state conversion of the state control module of the present invention.

[0038] Figure 3 It is a flow chart of the frequency calibration module of the present invention.

[0039] Figure 4 It is a flow chart of the amplitude calibration module of the present invention. DETAILED DESCRIPTION

[0040] The present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the accompanying drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0041] like Figure 1 As shown, an embodiment of the present invention provides a calibration system based on a pure digital circuit, wherein the dotted line portion is a specific implementation structure designed by the embodiment of the present invention, including an SPI read-write module, a register module, a state control module, a frequency calibration module and an amplitude calibration module; wherein the SPI read-write module mainly completes the data exchange between the calibration system and the outside world; the register module is mainly used to store various initial values ​​required for calibration, as well as the real-time output of each module during the calibration process. The state control module mainly controls the operating state of the entire calibration system according to the configuration of the relevant registers and the amplitude and frequency control signals, thereby controlling the subsequent amplitude calibration and frequency calibration modules. The frequency calibration module mainly selects the corresponding VCO core and tuning capacitor according to the different states of the frequency calibration signal, thereby completing the frequency calibration process; the amplitude calibration module mainly selects the optimized amplitude setting corresponding to the corresponding VCO core according to the different states of the amplitude calibration signal.

[0042] The SPI read-write module mainly completes the function of externally controlling the calibration system through the four ports of CS, SCLK, SDI and SDO. By configuring the registers therein, the initial VCO core number, initial value of tuning capacitance and initial value of amplitude of the calibration system can be controlled, and the entire calibration process can be externally regulated, which greatly enhances the controllability of the entire calibration process.

[0043] The register module mainly stores the initial values ​​of various states required for calibration, including whether to force the selection of the VCO core and the corresponding selected VCO core number, the two delay time values ​​between starting the calibration system and starting the amplitude calibration, etc. All registers in this module can be read by the SPI read-write module, and the relevant registers involving the initial values ​​of the calibration state can be written with corresponding values ​​by the SPI read-write module; this module can also pass the various initial values ​​required for calibration to the state control module, and at the same time receive the real-time output values ​​of each module in the calibration process passed by the state control module, so that the outside can read the real-time output values ​​of each module in the calibration system through the SPI read-write module, thereby monitoring the operating status of the calibration system, which can not only detect the calibration process in real time and increase the reliability of the calibration circuit, but also promptly discover the module with errors in the circuit and correct the errors in time.

[0044] The state control module mainly controls the operating state of the entire calibration system according to the initial values ​​of various calibration systems transmitted by the register module, the amplitude control signal and the frequency control signal transmitted by the frequency detector and phase detector. Different operating states correspond to different control signals. These control signals can drive the frequency calibration module and the amplitude calibration module to perform corresponding frequency calibration and amplitude calibration on the entire circuit to adjust the output of the voltage-controlled oscillator to be consistent with the reference voltage, thereby achieving the purpose of calibration. Specifically, the state control module can control the entire calibration circuit to perform amplitude calibration first and then frequency calibration, and then amplitude calibration according to the different states of the configuration value of the register module, the amplitude calibration control signal and the frequency calibration control signal, and repeat the process to ensure the accuracy of the output signal.

[0045] like Figure 2 As shown in the figure, the operating states of the state control module are mainly divided into six states: IDLE, ACAL1, FCAL, ACAL2, ACAL3 and END. The idle state IDLE indicates that the calibration is not started, ACAL1, ACAL2 and ACAL3 control three amplitude calibration modules respectively, FCAL controls the frequency calibration module, and the end state END indicates the end of calibration. After the specified delay time, the entire circuit will end the calibration process and return to the idle IDLE state.

[0046] The state transition process is as follows: After the corresponding registers are configured, the calibration system is started. After the first two delay times of the configuration are over, the circuit enters the amplitude calibration ACAL1 state. In this state, the circuit performs amplitude calibration according to the different states of the amplitude control signal a_con until the frequency calibration signal is valid and enters the frequency calibration FCAL state, or when all the amplitude values ​​of the optimized amplitude segment corresponding to the VCO core are traversed, the frequency control signal is still invalid (f_con=0) and the optimal amplitude value is not found, then the circuit directly enters the end state END; when the frequency control signal is valid (f_con≠0), the circuit enters the frequency calibration state FCAL, in which the circuit performs frequency calibration according to different values ​​of the frequency control signal f_con, and when the tuning capacitor value exceeds the specified value, the VCO core will be changed, and then the circuit enters the amplitude calibration state ACAL2. If the frequency calibration is performed normally, the frequency control signal f_con becomes an invalid value (f_con=0), and the circuit enters the amplitude calibration state ACAL2.

[0047] In the ACAL2 state, the circuit will perform amplitude calibration according to the different states of the amplitude control signal a_con. If it is detected that the frequency control signal is valid (f_con≠0), it will return to the frequency calibration state FCAL. After all the amplitude values ​​of the optimized amplitude segment corresponding to the VCO core are traversed, the frequency control signal is still invalid (f_con=0) and the optimal amplitude value is not found, or the amplitude calibration time reaches the specified time, the circuit will directly enter the end state END at this time; when the circuit is in the ACAL3 state, due to the replacement of the VCO core, the circuit needs a certain time to reach a stable state again, so this state will delay for a certain time before starting the amplitude calibration process. If within the specified delay time, the frequency control signal is valid (f_con≠0), the circuit will re-enter the frequency calibration state FCAL, all the amplitude values ​​of the optimized amplitude segment corresponding to the VCO core are traversed and the optimal amplitude value is still not found, or the circuit will enter the end state END after exceeding the specified time; when the circuit is in the end state END, the entire calibration process will end after the specified time, and enter the idle state to wait for the next calibration cycle.

[0048] The frequency calibration module mainly controls the tuning capacitor to increase or decrease from the initial value to the most appropriate value according to the configuration of the corresponding register and the different states of the frequency control signal, and also includes the continuous transformation of the VCO core, so as to ensure the accuracy of the frequency of the output signal. In addition, the frequency calibration module can realize the regulation of multiple voltage-controlled oscillators, which greatly enhances the range of frequency calibration and enables the circuit to meet the needs of more high-precision application fields. The flowchart of the frequency calibration module is as follows Figure 3 As shown, after the frequency calibration control signal is valid, the frequency control signal f_con is detected once every specified time to see if it is valid, that is, whether f_con is 0. If it is invalid, the frequency calibration process is terminated. If it is valid, the specific value of f_con is determined. If f_con=2'b10, and the tuning capacitor has not reached the upper boundary value, the value of the tuning capacitor will be increased by 1. However, after the tuning capacitor value reaches the upper boundary, it is determined whether the VCO core number has reached the maximum value. When the VCO core number has not reached the maximum value, the VCO core number value will be increased by 1, and then wait for the specified step delay time to enter the next cycle, otherwise the frequency calibration process is terminated. If f_con=2'b01 or 2'b11, and the tuning capacitor has not reached the lower boundary value, the tuning capacitor value is reduced by 1, and then wait for the specified step delay time to enter the next cycle, otherwise the frequency calibration process is terminated.

[0049] The amplitude calibration module optimizes the amplitude of the VCO core in segments, which can realize the calibration of signals with a wider amplitude range. The amplitude calibration module is composed of multiple modules corresponding to different amplitude calibration states, which can realize flexible configuration of amplitude calibration signals generated under different conditions, so that the circuit can meet the needs of more complex fields. The amplitude calibration state 1, amplitude calibration state 2 and amplitude calibration state 3 modules contained in the amplitude calibration module are all based on the register configuration and the different states of the amplitude control signal. The control calibration system continuously traverses the amplitude value of the corresponding VCO core after optimization until the optimal amplitude value is found or the frequency control signal is valid, thereby ensuring the accuracy of the amplitude of the output signal. The amplitude calibration state 1 module focuses on the first calibration, waiting for the frequency control signal to be valid, and then it can smoothly switch to the frequency calibration mode. The amplitude calibration state 2 module focuses on the normal switching between the amplitude calibration process and the frequency calibration process. The amplitude calibration state 3 module focuses on the replacement of the VCO core number when the tuning capacitor cannot meet the requirements during frequency calibration.

[0050] like Figure 4 As shown, the amplitude calibration process is similar to the frequency calibration process. After the amplitude calibration signal is valid, wait for the specified step delay time, and judge the value of the amplitude control signal a_con. When it is 0, then judge whether the current amplitude value reaches the lower boundary value of the amplitude. If it reaches the lower boundary value, and the number of amplitude segments reaches the lower boundary value, the amplitude calibration process will end; if it reaches the lower boundary value, and the number of amplitude segments does not reach the lower boundary value, the number of amplitude segments will be reduced by 1 and the amplitude will return to the maximum value; if it does not reach the lower boundary value, the current amplitude value will be reduced by 1, and then judge whether the frequency control signal f_con is valid. If it is invalid, wait for the specified step delay time to enter the next cycle. If it is valid, the amplitude calibration process will end. When a_con=1'b1, then determine whether the current amplitude value reaches the upper boundary value of the amplitude value. If it reaches the upper boundary value and the number of amplitude segments reaches the upper boundary value, the amplitude calibration process will end; if it reaches the upper boundary value and the number of amplitude segments does not reach the upper boundary value, the amplitude segment number will increase by 1 and the amplitude will return to the minimum value; if it does not reach the upper boundary value, the current amplitude value will increase by 1, and then determine whether the frequency control signal f_con is valid. If it is invalid, wait for the specified step delay time before entering the next cycle. If it is valid, the amplitude calibration process will end.

[0051] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A calibration system based on pure digital circuits, characterized in that: include: SPI read-write module, which reads and writes the values ​​of all register modules in the calibration system according to the SPI protocol, so as to regulate the calibration process of the entire calibration system; Register module, used to store the initial values ​​of each state and the output values ​​of each module required by the entire calibration system; The state control module generates a frequency calibration valid signal and an amplitude calibration valid signal according to the configuration value of the register module and the frequency calibration control signal and the amplitude calibration control signal sent by the frequency detector and the phase detector; it also includes controlling the operating state of the entire calibration system, and different operating states correspond to different control signals; the operating states include an idle state IDLE, amplitude calibration states ACAL1, ACAL2 and ACAL3, a frequency calibration state FCAL and a calibration end state END; The frequency calibration module generates the VCO core number and tuning capacitance value required in the corresponding state according to the initial values ​​of each module configured by the register module and the frequency calibration valid signal generated by the state control module, thereby realizing frequency calibration; The amplitude calibration module generates an optimized amplitude setting under the corresponding state according to the initial values ​​of each module configured by the register module and the amplitude calibration valid signal generated by the state control module, thereby realizing amplitude calibration; the amplitude calibration module includes an amplitude calibration state 1 module, an amplitude calibration state 2 module and an amplitude calibration state 3 module; wherein the amplitude calibration state 1 module is used to wait for the frequency calibration control signal to be valid when performing calibration for the first time, so as to smoothly switch to the frequency calibration mode; the amplitude calibration state 2 module is used for the normal switching between the amplitude calibration process and the frequency calibration process; The amplitude calibration state three modules are used to replace the VCO core number when the tuning capacitor cannot meet the demand during the frequency calibration process.

2. A calibration system based on a pure digital circuit as claimed in claim 1, characterized in that: The SPI read / write module completes the function of externally controlling the calibration system through the four ports of CS, SCLK, SDI and SDO, and controls the initial VCO core number, the initial value of the tuning capacitance and the initial value of the amplitude of the calibration system through the configuration register module.

3. A calibration system based on a pure digital circuit as claimed in claim 1, characterized in that: The storage of the initial values ​​of each state required for the entire calibration system specifically includes: whether to force the selection of the VCO core and the corresponding selected VCO core number, the two delay time values ​​between starting the calibration system and starting the amplitude calibration, the delay time for starting the amplitude calibration again after each VCO core switch, the number corresponding to the initial VCO core and the total number, the initial value and maximum value of the tuning capacitor, the total number of optimized VCO core amplitude segments and the maximum amplitude, the optimized amplitude segments and amplitude values ​​corresponding to the VCO core in the initial state, the time corresponding to the frequency calibration control signal controlling the tuning capacitor to increase or decrease by one step, the time corresponding to the amplitude calibration control signal controlling the optimized amplitude to increase or decrease by one step, and the delay time between the end of the amplitude and frequency calibration and the end of the operation of the entire calibration system.

4. A calibration system based on a pure digital circuit as claimed in claim 1, characterized in that: The frequency calibration module controls the tuning capacitance to increase or decrease from the initial value according to the configured time according to the different states of the frequency calibration control signal according to the corresponding configuration of the register module and under the control of the state control module. If the tuning capacitance value exceeds the specified value, the VCO core is changed, and the tuning capacitance is traversed again in the new VCO core to select the required value; The frequency calibration process ends when the amplitude calibration control signal is valid or the VCO core fails to find the required tuning capacitor after one traversal.

5. A calibration system based on a pure digital circuit as claimed in claim 1, characterized in that: The amplitude calibration state one module is the state entered after the first calibration is started and two delay times have expired. In this state, the calibration system will continue to perform the amplitude calibration process according to the amplitude calibration control signal until the frequency calibration control signal is valid or all amplitude values ​​of the optimized amplitude segment corresponding to the VCO core have been traversed. Only then will the amplitude calibration state one module be exited and the calibration state be ended.

6. A calibration system based on pure digital circuits as claimed in claim 1, characterized in that: The amplitude calibration state two module is an amplitude calibration module corresponding to the second amplitude calibration after the first frequency calibration. The amplitude calibration state two module completes the normal frequency calibration function and enters the frequency calibration state after completion, or ends the calibration process because the traversal ends without reaching the specified state.

7. A calibration system based on pure digital circuits as claimed in claim 1, characterized in that: The amplitude calibration state three module is a state entered when the tuning capacitor cannot meet the requirements during the frequency calibration process and the VCO core number is changed. In this state, the amplitude calibration is not performed directly, but is performed after a specified delay.

8. A calibration method based on a pure digital circuit, using a calibration system based on a pure digital circuit as claimed in any one of claims 1 to 7, characterized in that: The steps include: Step 1: After completing the configuration of the corresponding registers in the register module, start the calibration system. After the first two delay times of the configuration are over, the calibration system enters the amplitude calibration state ACAL1. In the amplitude calibration state ACAL1, the calibration system performs amplitude calibration according to different states of the amplitude calibration control signal a_con until the frequency calibration control signal is valid and enters the frequency calibration state FCAL, or when all the amplitude values ​​of the optimized amplitude segment corresponding to the VCO core are traversed, the frequency calibration control signal is still invalid, that is, f_con=0 and the required amplitude value is not found, then the calibration end state END will be directly entered; when the frequency calibration control signal is valid, that is, f_con≠0, the calibration system will enter the frequency calibration state FCAL, in which the calibration system will perform frequency calibration according to different values ​​of the frequency calibration control signal f_con, when the tuning capacitance value exceeds the specified value, the VCO core will be changed, then the calibration system enters the amplitude calibration state ACAL2, if the frequency calibration is performed normally, the frequency calibration control signal f_con becomes an invalid value, that is, f_con=0, then the calibration system will enter the amplitude calibration state ACAL2; Step 2: In the amplitude calibration state ACAL2, the calibration system will perform amplitude calibration according to different states of the amplitude control signal a_con. If it is detected that the frequency control signal is valid, that is, f_con≠0, it will return to the frequency calibration state FCAL. After all the amplitude values ​​of the optimized amplitude segment corresponding to the VCO core are traversed, the frequency calibration control signal is still invalid, that is, f_con=0 and the required amplitude value is not found, or the amplitude calibration time reaches the specified time, the calibration system will directly enter the end state END; when the calibration system is in the amplitude calibration state ACAL3, the amplitude calibration state ACAL3 will delay for a period of time before starting the amplitude calibration process. If within the specified delay time, the frequency calibration control signal is valid, that is, f_con≠0, the calibration system will re-enter the frequency calibration state FCAL, and all the amplitude values ​​of the optimized amplitude segment corresponding to the VCO core are traversed and the required amplitude value is still not found, or the calibration system will enter the end state END after exceeding the specified time; When the calibration system is in the end state END, the entire calibration process will end after a specified time and enter the idle state IDLE to wait for the next calibration process cycle.

9. A calibration method based on a pure digital circuit as claimed in claim 8, characterized in that: It also includes a frequency calibration process, which specifically includes: After the frequency calibration control signal is valid, the frequency calibration control signal f_con is checked every specified time to see if it is valid, that is, whether f_con is 0. If it is invalid, the frequency calibration process is terminated. If it is valid, the specific value of f_con is determined. If f_con=2'b10, and the tuning capacitor has not reached the upper boundary value, the value of the tuning capacitor will increase by 1. However, when the tuning capacitor has reached the upper boundary value, it will be determined whether the VCO core number has reached the maximum value. When the VCO core number has not reached the maximum value, the VCO core number value will increase by 1, and then wait for the specified step delay time to enter the next cycle, otherwise the frequency calibration process ends. If f_con=2'b01 or 2'b11, and the tuning capacitance has not reached the lower boundary value, the tuning capacitance value is reduced by 1, and then the specified step delay time is waited to enter the next cycle, otherwise the frequency calibration process is terminated.

10. A calibration method based on a pure digital circuit as claimed in claim 8, characterized in that: The amplitude calibration process is also included, and the amplitude calibration process specifically includes: After the amplitude calibration signal is valid, wait for the specified step delay time and determine the value of the amplitude calibration control signal a_con; When the value of a_con is 0, it is then determined whether the current amplitude value reaches the lower boundary value of the amplitude; If the lower boundary value is reached and the number of amplitude segments reaches the lower boundary value, the amplitude calibration process will end; If the lower boundary value is reached and the number of amplitude segments has not reached the lower boundary value, the number of amplitude segments decreases by 1 and the amplitude returns to the maximum value; If the lower boundary value is not reached, the current amplitude value will be reduced by 1, and then the frequency calibration control signal f_con will be judged whether it is valid. If it is not valid, it will wait for the specified step delay time to enter the next cycle. If it is valid, the amplitude calibration process will end; When a_con=1'b1, it is then determined whether the current amplitude value reaches the upper boundary value of the amplitude value. If it reaches the upper boundary value and the number of amplitude segments reaches the upper boundary value, the amplitude calibration process will end; If the upper boundary value is reached and the number of amplitude segments does not reach the upper boundary value, the amplitude segment number increases by 1 and the amplitude returns to the minimum value; If the upper boundary value is not reached, the current amplitude value will increase by 1, and then determine whether the frequency calibration control signal f_con is valid. If not, wait for the specified step delay time before entering the next cycle. If valid, end the amplitude calibration process.

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