A broadband multi-level three-dimensional vertical interconnection structure based on HTCC technology

Abstract

The present invention discloses a broadband multi-level three-dimensional vertical interconnection structure based on HTCC technology, which belongs to the field of radio frequency front-end system integration. The structure includes a PCB motherboard, a ball grid array and a SiP module arranged in sequence from bottom to top; in the SiP module, the chips are distributed between different levels, and the connection mode of the chips between different levels is set; the radio frequency signal is transmitted upward through the PCB motherboard, and after flowing through the lower layer bare chip, it is orderly transmitted upward through the strip line and signal via inside the HTCC, and finally transmitted to the surface chip, forming a complete and efficient vertical interconnection signal transmission system. The present invention improves the flexibility of the layout of the interconnection lines between chips, reduces the routing crosstalk between chips, greatly broadens the three-dimensional integration scene of bare chips in HTCC, realizes high-density SiP packaging, and can meet the stringent technical requirements for radio frequency signal transmission, processing and chip interconnection under complex circuit architecture.

Description

Technical Field

[0001] The invention belongs to the field of radio frequency front-end system integration and relates to a broadband multi-level three-dimensional vertical interconnection structure based on HTCC technology. Background Art

[0002] With the rapid development and widespread application of modern communication and navigation systems, radar, satellite and other technologies, coupled with the urgent needs of military and civilian fields, the market has put forward new demands on electronic equipment, driving microwave circuits and systems towards small size, light weight, high reliability, low power consumption and high integration. However, the traditional two-dimensional integration method faces limitations in size reduction, routing interconnection, etc. Therefore, circuit integration technology is turning to three-dimensional integration.

[0003] Three-dimensional integration technology can break through limitations in microsystems and highly integrated environments, achieve higher integration, more compact packaging size, and improve system performance and reliability, while reducing energy consumption and manufacturing costs. High-temperature co-fired ceramic (HTCC) is a multi-layer 3D packaging technology. Common vertical interconnection and signal transmission between HTCC layers are mostly based on the transition of ball grid array (BGA) and via vertical technology. In HTCC packaging technology, when multiple chips need to be packaged together, multiple chips are placed on the same layer, which will cause routing crosstalk and low flexibility. At the same time, the length of the interconnection line between the chip and other circuit components increases, which not only increases the delay of signal transmission, but also may increase signal loss. In addition, the concentration of chips on the same layer will cause local overheating, affecting the stability and reliability of the circuit. Therefore, it is necessary to study a circuit wiring with higher density and more compact packaging technology. Summary of the invention

[0004] In view of the problems existing in the prior art, the present invention provides a broadband multi-level three-dimensional vertical interconnection structure based on HTCC technology. The structure distributes chips between different layers, improves the flexibility of interconnection line layout between chips, reduces the crosstalk between chip routing, and thus reduces signal transmission delay and transmission loss.

[0005] The specific technical solution adopted by the present invention is as follows:

[0006] A broadband multi-level three-dimensional vertical interconnection structure based on HTCC technology includes a PCB motherboard, a ball grid array and a SiP (system-in-package) module arranged in sequence from bottom to top.

[0007] The PCB motherboard includes a dielectric substrate, a grounding layer arranged on its lower surface, and a coplanar waveguide arranged on its upper surface;

[0008] The ball grid array includes a signal solder ball and a plurality of shielding solder balls; the lower end of the signal solder ball is welded to the output end of the coplanar waveguide, and the other end is welded to the lower signal via of the SiP module; the shielding solder ball is arranged at the periphery of the signal solder ball to prevent energy leakage of the signal solder ball;

[0009] The SiP module includes a lower ground plate, an upper ground plate, a plurality of ceramic dielectric plates, an upper chip, a lower chip, an upper signal via, a lower signal via, a strip line, a microstrip line, and a shielded via array;

[0010] A plurality of ceramic dielectric plates are arranged between the lower ground plate and the upper ground plate, and a plurality of ceramic dielectric plates are arranged above the upper ground plate;

[0011] The lower signal via passes through the multilayer ceramic dielectric plate and the isolation circular hole arranged on the lower ground plate, and is connected to the input end of the strip line;

[0012] The lower chip is arranged in the middle of the strip line;

[0013] The output end of the strip line is connected to the upper signal via;

[0014] The upper signal via passes through the multilayer ceramic dielectric plate and the isolation circular hole arranged on the upper ground plate, and is connected to the input end of the microstrip line;

[0015] The upper chip is arranged in the middle of the microstrip line;

[0016] The output end of the microstrip line serves as a signal output end.

[0017] Preferably, when the SiP module further includes N middle-layer chips, N is an integer greater than 1; then N middle-layer ground plates are further arranged between the lower ground plate and the upper ground plate, and multiple layers of ceramic dielectric plates and a middle-layer chip are arranged between adjacent ground plates;

[0018] The middle-layer chip is arranged in the middle layer of the multi-layer ceramic dielectric board and is connected with the upper and lower chips through strip lines and signal vias.

[0019] Preferably, a shielding array consisting of a plurality of metal vias is arranged around the periphery of the upper signal via and the lower signal via to prevent external radiation of the signal and interference of external signals.

[0020] Preferably, a metal grounding hole array is provided at the periphery of the coplanar waveguide to enable the coplanar waveguide to achieve good signal transmission performance.

[0021] Preferably, the upper chip is connected to the strip line through a flip-chip process or a gold wire bonding process; and the lower chip is connected to the microstrip line through a flip-chip process or a gold wire bonding process.

[0022] In the present invention, efficient input of RF signals is achieved by coplanar waveguides arranged on the upper surface of the PCB motherboard. During the signal transmission process, the RF signal is accurately transmitted to the stripline portion of the HTCC (high temperature co-fired ceramic) middle layer through the BGA signal solder balls and signal vias. Based on the flip-chip process or the gold wire bonding process, a stable interconnection channel between the stripline and the integrated bare chip is constructed to ensure stable signal interaction. After the signal flows smoothly through the lower bare chip, it is orderly transmitted upward through the stripline and signal vias inside the HTCC, and finally transmitted to the microstrip line structure on the surface of the HTCC. The HTCC surface microstrip line is also adapted to the flip-chip process or the gold wire bonding process, so as to achieve reliable interconnection with the bare chip arranged on the surface of the HTCC, forming a complete and efficient vertical interconnection signal transmission system. The present invention greatly broadens the three-dimensional integration scenario of bare chips in HTCC, realizes high-density SiP packaging, and can meet the stringent technical requirements for RF signal transmission, processing and chip interconnection under complex circuit architecture. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 This is an overall structural view of the broadband multi-level three-dimensional vertical interconnection structure of this embodiment.

[0024] Figure 2 This is a diagram of an application scenario of the broadband multi-level three-dimensional vertical interconnect structure combined with a bare chip in this embodiment.

[0025] Figure 3 It is an exploded diagram of the overall structure of the broadband multi-level three-dimensional vertical interconnection structure of this embodiment.

[0026] Figure 4 This is a structural view of the solder ball array and PCB motherboard of the broadband multi-level three-dimensional vertical interconnect structure of this embodiment.

[0027] Figure 5 It is a top view of the solder ball array and PCB motherboard of the broadband multi-level three-dimensional vertical interconnection structure of this embodiment.

[0028] Figure 6 1 is an exploded view of the SiP module of the broadband multi-level three-dimensional vertical interconnection structure of this embodiment.

[0029] Figure 7 It is a top view of the strip lines, vias and solder ball arrays of the broadband multi-level three-dimensional vertical interconnect structure of this embodiment.

[0030] Figure 8 It is a top view of the microstrip lines, isolation holes and via arrays of the broadband multi-level three-dimensional vertical interconnection structure of this embodiment.

[0031] Fig. 9This is a back-to-back structural view of the broadband multi-level three-dimensional vertical interconnection structure of this embodiment.

[0032] Fig.10 This is a test result diagram of the broadband multi-level three-dimensional vertical interconnect structure of this embodiment. DETAILED DESCRIPTION

[0033] The present invention is further described in detail below with reference to the accompanying drawings and embodiments.

[0034] This embodiment provides a broadband multi-level three-dimensional vertical interconnection structure operating at 2GHz-18GHz, which solves the problem of low flexibility and density of interconnection line layout between chips when chips are concentrated on the same layer in common HTCC packaging technology, leaving space for chips and their connections, and reducing mutual crosstalk between lines. Compared with the common vertical interconnection structure, the present invention realizes the multi-layer layout of middle-layer bare chips and surface-layer bare chips, expands the scope of HTCC technology in bare chip three-dimensional integration application, and achieves the goal of high-density SiP packaging.

[0035] In this embodiment, a broadband multi-level three-dimensional vertical interconnection structure based on HTCC technology is provided. Figure 1-8 As shown, it includes a PCB motherboard (1), a ball grid array (2) and a SiP (system-in-package) module (3) arranged in sequence from bottom to top.

[0036] The PCB motherboard (1) has a size of 10 mm×10 mm×0.254 mm, and comprises a dielectric substrate (120) and a grounding layer (110) arranged on its lower surface, and a coplanar waveguide (130) arranged on its upper surface; a metal grounding hole array (121) is arranged on the periphery of the coplanar waveguide (130) to enable the coplanar waveguide to achieve good signal transmission performance.

[0037] The ball grid array (2) comprises a signal solder ball (210) and 15 shielding solder balls (220), the radius of the solder ball is 0.3 mm, the height is 0.4 mm, and each solder ball is provided with a solder pad (230) above and below; the lower end of the signal solder ball (210) is welded to the output end of the coplanar waveguide, and the other end is welded to the lower signal via of the SiP module; the shielding solder balls (220) are arranged in a circle with equal spacing around the signal solder ball (210), and four shielding solder balls are symmetrically placed around the signal solder ball to prevent energy leakage of the signal solder ball.

[0038] The SiP module has a size of 8 mm×8 mm×1.145 mm and comprises a lower ground plane (310), an upper ground plane (360), 11 layers of ceramic dielectric plates (320), an upper chip (390), a lower chip (391), an upper signal via (370), a lower signal via (330), a strip line (350), a microstrip line (380), and a shielded via array (340).

[0039] Eight layers of ceramic dielectric plates are arranged between the lower grounding plate (310) and the upper grounding plate (360), and three layers of ceramic dielectric plates are arranged above the upper grounding plate (360), with each layer of ceramic dielectric plates having a thickness of 0.1 mm.

[0040] Chip slots are provided in the third and fourth ceramic dielectric plates from bottom to top for accommodating lower chips, and the upper surface of the lower chip is flush with the upper surface of the fourth ceramic dielectric plate; chip slots are provided in the top two ceramic dielectric plates for accommodating upper chips, and the upper surface of the upper chip is flush with the upper surface of the top ceramic dielectric plate.

[0041] The lower signal via (330) passes through four layers of ceramic dielectric plates and an isolation circular hole (311) arranged on the lower ground plate, and is connected to the input end of the strip line (350).

[0042] The lower layer chip (391) is arranged in the middle of the strip line (350) and is connected to the strip line through a flip chip process or a gold wire bonding process.

[0043] The output end of the stripline (350) is connected to an upper layer signal via (370).

[0044] The upper signal via (370) passes through four layers of ceramic dielectric plates and an isolation circular hole (361) arranged on the upper ground plate, and is connected to the input end of the microstrip line (380).

[0045] The upper chip (390) is arranged in the middle of the microstrip line (380) and is connected to the microstrip line through a flip-chip welding process or a gold wire bonding process.

[0046] The output end of the microstrip line (380) serves as a signal output end.

[0047] A shielding array (340) consisting of 31 metal vias is arranged around the upper signal via (370) and the lower signal via (330) to prevent external radiation of the signal and interference from external signals.

[0048] The input radio frequency signal is transmitted to the HTCC middle layer strip line (350) through the coplanar waveguide (130) on the PCB motherboard via the signal solder ball (210) and the signal via hole (330). The middle layer strip line (350) can be interconnected with the bare chip of the HTCC middle layer through the process of flip-chip welding or gold wire bonding. After passing through the bare chip of the middle layer, the signal can continue to be transmitted to the HTCC surface layer microstrip line (380) through the HTCC middle layer strip line (350) and the signal via hole (370). The surface layer microstrip line (380) can also be interconnected with the HTCC surface layer bare chip through the process of flip-chip welding or gold wire bonding.

[0049] The lower grounding layer (110) and the grounding hole (121) of the PCB motherboard of the vertical interconnection structure are used to provide good grounding, which helps to reduce electromagnetic interference in the circuit, and can also increase the mechanical stability of the board and improve its structural strength. The coplanar waveguide (130) on the upper surface of the PCB motherboard has good broadband transmission performance, which is used to realize broadband and low-loss signal transmission of the structure, and has good anti-interference performance. The signal solder ball (210) in the ball grid array (BGA) realizes the vertical interconnection between the coplanar waveguide (130) and the system-level packaging (SiP) module, realizing the initial transition of the vertical interconnection structure; the shielding solder ball (220) is used to reduce signal leakage, shield the interference of the external electromagnetic field on the internal signal, and can further improve the stability of the structure. The signal via (330) in the system-level package (SiP) module is connected to the signal solder ball (210) to realize the vertical interconnection between the coplanar waveguide (CP W) (130) and the HTCC middle layer strip line (350); the signal via (370) is used to realize the vertical interconnection between the middle layer strip line (210) and the surface layer microstrip line (380); and for the final physical processing, the connection between the transmission line and the signal via (350, 380) is circularized; the shielding via (340) can effectively reduce the electromagnetic radiation at the signal via, prevent the external radiation of the signal and the interference of the external signal, and improve the electromagnetic compatibility of the circuit.

[0050] In order to facilitate testing, the vertical interconnection structure in the embodiment is set to a back-to-back structure, such as Fig. 9 shown by Fig.10 The test results show that in the range of 2-18 GHz, the insertion loss of the structure of this embodiment is less than 0.5 dB, and the return loss is less than 11.6 dB, which meets the requirements of radio frequency signal transmission.

Claims

1. A broadband multi-level three-dimensional vertical interconnection structure based on HTCC technology, characterized in that: It includes a PCB motherboard, a ball grid array and a SiP module arranged in sequence from bottom to top; The PCB motherboard includes a dielectric substrate, a grounding layer arranged on its lower surface, and a coplanar waveguide arranged on its upper surface; The ball grid array includes a signal solder ball and a plurality of shielding solder balls; the lower end of the signal solder ball is welded to the output end of the coplanar waveguide, and the other end is welded to the lower signal via of the SiP module; the shielding solder ball is arranged at the periphery of the signal solder ball to prevent energy leakage of the signal solder ball; The SiP module includes a lower ground plate, an upper ground plate, a plurality of ceramic dielectric plates, an upper chip, a lower chip, an upper signal via, a lower signal via, a strip line, a microstrip line, and a shielded via array; A plurality of ceramic dielectric plates are arranged between the lower ground plate and the upper ground plate, and a plurality of ceramic dielectric plates are arranged above the upper ground plate; The lower signal via passes through the multilayer ceramic dielectric plate and the isolation circular hole arranged on the lower ground plate, and is connected to the input end of the strip line; The lower chip is arranged in the middle of the strip line; The output end of the strip line is connected to the upper signal via; The upper signal via passes through the multilayer ceramic dielectric plate and the isolation circular hole arranged on the upper ground plate, and is connected to the input end of the microstrip line; The upper chip is arranged in the middle of the microstrip line; The output end of the microstrip line serves as a signal output end.

2. A broadband multi-level three-dimensional vertical interconnect structure based on HTCC technology as claimed in claim 1, characterized in that: When the SiP module further includes N middle-layer chips, N is an integer greater than 1; then N middle-layer ground plates are further arranged between the lower ground plate and the upper ground plate, and multiple layers of ceramic dielectric plates and a middle-layer chip are arranged between adjacent ground plates; The middle-layer chip is arranged in the middle layer of the multi-layer ceramic dielectric board and is connected with the upper and lower chips through strip lines and signal vias.

3. A broadband multi-level three-dimensional vertical interconnect structure based on HTCC technology as claimed in claim 1 or 2, characterized in that: A shielding array consisting of a plurality of metal vias is arranged around the upper signal via and the lower signal via to prevent external radiation of the signal and interference of external signals.

4. A broadband multi-level three-dimensional vertical interconnect structure based on HTCC technology as claimed in claim 3, characterized in that: A metal grounding hole array is arranged at the periphery of the coplanar waveguide to enable the coplanar waveguide to achieve good signal transmission performance.

5. A broadband multi-level three-dimensional vertical interconnect structure based on HTCC technology as claimed in claim 4, characterized in that: The upper chip is connected to the strip line through a flip-chip process or a gold wire bonding process; the lower chip is connected to the microstrip line through a flip-chip process or a gold wire bonding process.

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