Memory block and method of manufacturing the same

Abstract

The application provides a memory block and a manufacturing method thereof. The memory block comprises: each memory subarray layer in a memory array comprises a laminated drain region, channel and source region semiconductor layer; the drain region, channel and source region semiconductor layer respectively comprises a plurality of drain region, channel and source region semiconductor strips distributed along a row direction and extended along a column direction; a column of drain region, channel and source region semiconductor strips in the multi-layer memory subarray layer is a column of semiconductor strip-shaped structures; a drain / source lead-out area is provided with a plurality of drain / source connection end units spaced apart along the row and column directions, respectively; and a drain / source connection end in each of the drain / source connection end units is connected to a layer of drain region / source region semiconductor strip in the corresponding column of semiconductor strip-shaped structures. The memory block can avoid a bridging condition of two adjacent drain / source connection ends along the column direction in the same drain / source connection end unit.

Description

[0001] Cross-reference to related applications

[0002] This application is a further improvement based on Chinese Patent Application No. 2022113607924, filed on November 1, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0003] This invention relates to the field of semiconductor device technology, and in particular to a memory block and its manufacturing process. Background Technology

[0004] Two-dimensional (2D) memory blocks are ubiquitous in electronic devices and can include, for example, NOR flash memory arrays, NAND flash memory arrays, and dynamic random-access memory (DRAM) arrays. However, 2D memory arrays have reached their scaling limits, and their storage density cannot be further increased.

[0005] Furthermore, in non-(NOR) flash memory blocks, the source region, which serves as the bitline (BL), and the drain region, which serves as the senseline (SL), are typically led out via interconnects and then connected to the connection pads of the memory block for signal transmission. However, bridging can easily occur between adjacent interconnects in existing memory blocks, leading to short circuits. Summary of the Invention

[0006] The storage block and its manufacturing process provided in this application aim to solve the problems that existing 2D storage arrays are approaching their scaling limits and storage density cannot be further increased, as well as the problem that bridging between two adjacent connection lines can easily occur, leading to short circuits in the connection lines.

[0007] To solve the above-mentioned technical problems, one technical solution adopted in this application is to provide a storage block. The storage block includes:

[0008] Substrate;

[0009] A memory array, disposed on the substrate, includes multiple memory cells arranged in a three-dimensional array. The memory array comprises multiple memory subarray layers stacked sequentially along the height direction. Each memory subarray layer includes a drain semiconductor layer, a channel semiconductor layer, and a source semiconductor layer stacked along the height direction. Each drain semiconductor layer, channel semiconductor layer, and source semiconductor layer in each memory subarray layer includes multiple drain semiconductor strips, channel semiconductor strips, and source semiconductor strips distributed along the row direction. Each drain semiconductor strip, channel semiconductor strip, and source semiconductor strip extends along the column direction. A column of drain semiconductor strips, channel semiconductor strips, and source semiconductor strips in the multiple memory subarray layers is defined as a column of semiconductor strip structures.

[0010] At least one drain / source lead-out region, wherein the drain / source lead-out region is provided with a plurality of drain / source connection terminal units, the plurality of drain / source connection terminal units are respectively spaced apart along the row direction and the column direction; wherein the drain / source connection terminal in each drain / source connection terminal unit is connected to a layer of drain / source region semiconductor strip in the corresponding column of the semiconductor strip structure.

[0011] In the drain / source lead-out area, the drain / source connection terminals of several drain / source connection terminal units in the same row are connected to the drain / source semiconductor strips of the same layer in multiple columns of the semiconductor strip structure, and the drain / source connection terminals of several drain / source connection terminal units in the same column are connected to multiple drain / source semiconductor strips of different layers in a corresponding column of the semiconductor strip structure.

[0012] Each drain / source connection unit includes a first drain / source connection and a second drain / source connection distributed along the row direction; the first drain / source connection and the second drain / source connection are respectively connected to the drain / source semiconductor strips of the same layer of two adjacent columns of the semiconductor strip structure.

[0013] In the drain / source lead-out region, each column of the non-edge semiconductor strip structure corresponds to two columns of drain / source connection terminal units; wherein, the second drain / source connection terminal in one column of drain / source connection terminal units connects to the drain / source semiconductor strips of the odd-numbered layers in the non-edge semiconductor strip structure, and the first drain / source connection terminal in the other column of drain / source connection terminal units connects to the drain / source semiconductor strips of the even-numbered layers in the non-edge semiconductor strip structure.

[0014] In this configuration, the two columns of drain / source connection units corresponding to each column of the non-edge semiconductor strip structure are staggered.

[0015] In each of the drain / source connection units, the first drain / source connection terminal and the second drain / source connection terminal share the same drain / source isolation hole; wherein, the drain / source isolation hole is used to remove the portion of the channel semiconductor strip in two adjacent columns of the semiconductor strip structure that is close to the drain / source isolation hole; the drain / source isolation hole and the removal area of ​​the channel semiconductor strip are filled with a first insulating material;

[0016] In each column of semiconductor strips located in the region of each drain / source connection unit, adjacent drain / source semiconductor strips in different layers are isolated from each other by the first insulating material.

[0017] In the region where each drain / source connection terminal unit is located, an outgoing hole is provided on both sides of the drain / source isolation hole, and each outgoing hole corresponds to exposing one of the drain / source semiconductor strips in a row of semiconductor strip structures;

[0018] Among them, the drain / source connection terminal units in the same row and the lead-out holes in the same row respectively expose the drain / source semiconductor strips in the same layer of the semiconductor strip structure in multiple columns;

[0019] The drain / source connection terminal units in the same column and the corresponding lead-out holes in the same column expose the drain / source semiconductor strips in different layers of the semiconductor strip structure in the same column.

[0020] The hole is provided with a drain / source lead-out structure, and the drain / source connection terminal is connected to the drain / source semiconductor strip in the semiconductor strip structure through the drain / source lead-out structure.

[0021] The sidewalls and bottom walls of the lead-out hole are partially covered with an insulating layer to expose only one corresponding drain / source semiconductor strip in the semiconductor strip structure.

[0022] The drain / source lead-out structure includes a semiconductor interconnect layer and a connectivity improvement layer extending along the height direction; wherein the semiconductor interconnect layer contacts the corresponding exposed semiconductor strips of the drain / source regions, and the connectivity improvement layer is disposed on the semiconductor interconnect layer and contacts the corresponding drain / source connection terminals.

[0023] The semiconductor interconnect layer includes a polysilicon interconnect layer, and the interconnection improvement layer includes a metal silicide interconnection improvement layer.

[0024] The drain / source lead-out structure includes a connection improvement layer and a metal connection layer extending along the height direction; wherein the connection improvement layer contacts the corresponding exposed drain / source semiconductor strip, and the metal connection layer is disposed on the connection improvement layer and contacts the corresponding drain / source connection terminal.

[0025] Wherein, the connectivity improvement layer includes a metal silicide connectivity improvement layer; and / or

[0026] The metal connection layer and the drain / source connection terminal are made of the same metal.

[0027] The drain / source lead-out region includes a high drain / source lead-out sub-region and a low drain / source lead-out sub-region. The drain / source connection terminal in the high drain / source lead-out sub-region is used to connect to the drain / source semiconductor strip in the high region of the semiconductor strip structure. The drain / source connection terminal in the low drain / source lead-out sub-region is used to connect to the drain / source semiconductor strip in the low region of the semiconductor strip structure.

[0028] The drain / source connection terminals corresponding to the drain / source semiconductor strips in the high region of each layer, and the drain / source connection terminals corresponding to the drain / source semiconductor strips in the matching layer of the drain / source semiconductor strips in the low region, are formed in the same process.

[0029] The storage block includes a plurality of drain / source lead-out regions, which are spaced apart in the column direction.

[0030] To solve the above-mentioned technical problems, another technical solution adopted in this application is: providing a process method for manufacturing a memory block. The method includes: providing a semiconductor substrate, wherein the semiconductor substrate includes a substrate and a plurality of memory subarray layers disposed on the substrate and sequentially stacked along a height direction, each memory subarray layer including a drain semiconductor layer, a channel semiconductor layer, and a source semiconductor layer stacked along the height direction; the drain semiconductor layer, channel semiconductor layer, and source semiconductor layer in each memory subarray layer respectively include a plurality of drain semiconductor strips, channel semiconductor strips, and source semiconductor strips distributed along a row direction; each drain semiconductor strip, channel semiconductor strip, and source semiconductor strip extends along a column direction; a column of drain semiconductor strips, channel semiconductor strips, and source semiconductor strips in the multiple memory subarray layers is defined as a column semiconductor strip structure;

[0031] In at least one drain / source lead-out region of the semiconductor substrate, a plurality of drain / source connection terminal units are provided, and the plurality of drain / source connection terminal units are respectively spaced apart along the row direction and the column direction; wherein, the drain / source connection terminal in each drain / source connection terminal unit is connected to a layer of drain / source region semiconductor strip in the corresponding column of the semiconductor strip structure.

[0032] In the drain / source lead-out area, the drain / source connection terminals of several drain / source connection terminal units in the same row are connected to the drain / source semiconductor strips of the same layer in multiple columns of the semiconductor strip structure, and the drain / source connection terminals of several drain / source connection terminal units in the same column are connected to multiple drain / source semiconductor strips of different layers in a corresponding column of the semiconductor strip structure.

[0033] Wherein, the provision of a plurality of drain / source connection terminal units in at least one drain / source lead-out region of the semiconductor substrate includes:

[0034] Multiple drain / source isolation holes are provided in the drain / source outlet area;

[0035] The portion of the channel semiconductor strip near the drain / source lead-out region in two adjacent columns of the semiconductor strip structure is removed through the drain / source isolation hole, and a first insulating material is filled in the removal area of ​​the drain / source isolation hole and the channel semiconductor strip.

[0036] A lead-out hole of a preset depth is opened on both sides of the drain / source isolation hole, and each lead-out hole exposes one layer of the drain / source semiconductor strip in the semiconductor strip structure.

[0037] A drain / source lead-out structure is formed in the lead-out hole, and a drain / source connection end is formed on the drain / source lead-out structure.

[0038] The step of opening outlet holes of a predetermined depth on both sides of the drain / source isolation hole includes:

[0039] A first removal operation is performed to create a first lead-out hole on each side of a portion of the drain / source isolation holes; each of the first lead-out holes exposes the drain / source semiconductor strip of the a layer in each column of the semiconductor strip structure;

[0040] A second removal operation is performed to create a b-th lead-out hole on each side of a portion of the drain / source isolation holes; each b-th lead-out hole exposes the drain / source semiconductor strip of the b-th layer in each column of the semiconductor strip structure; and so on, until the drain / source semiconductor strip of the last layer in each column of the semiconductor strip structure is exposed; wherein a and b are natural numbers greater than or equal to 1 and less than or equal to the number of layers of the memory subarray.

[0041] The step of opening outlet holes of a predetermined depth on both sides of the drain / source isolation hole includes:

[0042] Rows of corresponding depth of lead-out holes are sequentially opened on both sides of the drain / source isolation holes in each row. The m-th lead-out holes opened on both sides of the m-th drain / source isolation holes expose the drain / source semiconductor strip of the m-th layer in each column of semiconductor strip structure, where m is a natural number greater than or equal to 1 and less than or equal to the number of layers of the memory subarray.

[0043] The step of sequentially creating a row of outlet holes of corresponding depth on both sides of each row of drain / source isolation holes includes:

[0044] First lead-out holes are respectively opened on both sides of the drain / source isolation holes in the first row, and each first lead-out hole exposes the drain / source semiconductor strip of the first layer in each column of the semiconductor strip structure;

[0045] Second lead-out holes are respectively opened on both sides of the drain / source isolation holes in the second row, and each second lead-out hole exposes the drain / source semiconductor strip of the second layer in each column of the semiconductor strip structure; and so on, until the drain / source semiconductor strip of the last layer in each column of the semiconductor strip structure is exposed.

[0046] The step of opening outlet holes of a predetermined depth on both sides of the drain / source isolation hole includes:

[0047] A lead-out hole of a preset depth is opened on both sides of each drain / source isolation hole. Each lead-out hole of the preset depth is removed at least once. After n removal operations, the lead-out hole of the preset depth exposes the drain / source semiconductor strip of the nth layer in the corresponding column of semiconductor strip structure. n is a natural number that is greater than or equal to 1 and less than or equal to the number of layers of the memory subarray.

[0048] The step of creating outlet holes of a preset depth on both sides of each of the drain / source isolation holes, and subjecting each outlet hole of the preset depth to at least one removal operation, includes:

[0049] A first lead-out hole is opened on both sides of each drain / source isolation hole by a first removal operation, wherein the lead-out hole after the first removal operation exposes the drain / source semiconductor strip of the first layer in each column of semiconductor strip structure.

[0050] Except for the first lead-out hole with a preset depth of a first depth, the other first lead-out holes are subjected to a second removal operation to form second lead-out holes, wherein the second lead-out holes expose the drain / source semiconductor strips of the second layer in each column of the semiconductor strip structure;

[0051] Except for the second lead-out hole with a preset depth of the second depth, a third removal operation is performed on the other second lead-out holes to form third lead-out holes, wherein the third lead-out holes expose the drain / source semiconductor strips of the third layer in each column of the semiconductor strip structure; and so on, until the drain / source semiconductor strips of the last layer in each column of the semiconductor strip structure are exposed.

[0052] The step of creating outlet holes of a preset depth on both sides of each of the drain / source isolation holes, and subjecting each outlet hole of the preset depth to at least one removal operation, includes:

[0053] A first removal operation is performed to create first lead-out holes on both sides of a portion of the drain / source isolation holes; a second removal operation is performed to create (K / 2+1)th lead-out holes on both sides of the remaining drain / source isolation holes; wherein each first lead-out hole exposes the drain / source semiconductor strip of the first layer in the corresponding column of the semiconductor strip structure; each (K / 2+1)th lead-out hole exposes the drain / source semiconductor strip of the (K / 2+1)th layer in the corresponding column of the semiconductor strip structure; K is the total number of drain / source semiconductor strips in a column of the semiconductor strip structure;

[0054] Except for the lead-out holes with preset depths of the first depth and the (K / 2+1)th depth, the other first lead-out holes and the (K / 2+1)th lead-out holes are respectively subjected to a third removal operation to form the second lead-out hole and the (K / 2+2)th lead-out hole respectively.

[0055] Except for the lead-out holes with preset depths of the second depth and the (K / 2+2)th depth, the other second lead-out holes and the (K / 2+2)th lead-out holes are subjected to a fourth removal operation to form the third lead-out hole and the (K / 2+3)th lead-out hole respectively; and so on, until the drain / source semiconductor strip of the last layer in each column of semiconductor strip structure is exposed.

[0056] The step of forming a drain / source lead-out structure in the lead-out hole and forming the drain / source connection end on the drain / source lead-out structure includes:

[0057] An insulating layer is deposited on the sidewalls and bottom wall of the outlet hole;

[0058] At least a portion of the insulating isolation layer on the bottom wall of the lead-out hole is removed to expose the drain / source semiconductor strip of the corresponding layer in a row of semiconductor strip structures corresponding to the lead-out hole;

[0059] A semiconductor interconnect layer extending along the height direction is formed in the lead-out hole where the insulating isolation layer is deposited on the sidewall;

[0060] A connectivity improvement layer is formed on the semiconductor interconnect layer;

[0061] The drain / source connection is formed on the side of the connectivity improvement layer opposite to the semiconductor connectivity layer.

[0062] The semiconductor interconnect layer includes a polysilicon interconnect layer, and the interconnection improvement layer includes a metal silicide interconnection improvement layer.

[0063] The step of forming a drain / source lead-out structure in the lead-out hole and forming the drain / source connection end on the drain / source lead-out structure includes:

[0064] An insulating layer is deposited on the sidewalls and bottom wall of the outlet hole;

[0065] At least a portion of the insulating isolation layer on the bottom wall of the lead-out hole is removed to expose the drain / source semiconductor strip of the corresponding layer in a row of semiconductor strip structures corresponding to the lead-out hole;

[0066] A connection improvement layer is formed in the lead-out hole in which the insulating isolation layer is deposited on the sidewall;

[0067] A metal connection layer extending along the height direction is formed on the connection improvement layer;

[0068] The drain / source connection is formed on the side surface of the metal connection layer opposite to the connection improvement layer.

[0069] Wherein, the connectivity improvement layer includes a metal silicide connectivity improvement layer; and / or

[0070] The metal connection layer and the drain / source connection terminal are made of the same metal.

[0071] Wherein, the provision of a plurality of drain / source connection terminal units in at least one drain / source lead-out region of the semiconductor substrate includes:

[0072] In each of the plurality of drain / source lead-out regions of the semiconductor substrate, a plurality of drain / source connection terminal units are respectively provided.

[0073] The beneficial effects of this application, which differ from the prior art, are as follows: The memory block provided in the embodiments of this application includes a substrate, a memory array, and at least one drain / source lead-out region. The memory array includes multiple memory cells distributed in a three-dimensional array. The memory array includes multiple memory sub-array layers stacked sequentially along the height direction. Each memory sub-array layer includes a drain semiconductor layer, a channel semiconductor layer, and a source semiconductor layer stacked along the height direction. The drain semiconductor layer, channel semiconductor layer, and source semiconductor layer in each memory sub-array layer respectively include multiple drain semiconductor strips, channel semiconductor strips, and source semiconductor strips distributed along the row direction. Each drain semiconductor strip, channel semiconductor strip, and source semiconductor strip extends along the column direction. A column of drain semiconductor strips, channel semiconductor strips, and source semiconductor strips in the multilayer memory sub-array layer is defined as a column of semiconductor strip structure. Meanwhile, the drain / source lead-out area is provided with multiple drain / source connection terminal units, which are spaced apart along the row and column directions respectively. In the drain / source lead-out area, the drain / source connection terminal in each drain / source connection terminal unit in the same drain / source lead-out area is connected to one layer of drain / source semiconductor strip in the corresponding column semiconductor strip structure. Compared with the drain / source connection terminal in each drain / source connection terminal unit being connected to multiple layers of drain / source semiconductor strip in the corresponding column semiconductor strip structure, it can avoid bridging between two adjacent drain / source connection terminals along the column direction in the same drain / source connection terminal unit, which could lead to a short circuit. Attached Figure Description

[0074] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0075] Figure 1 A schematic diagram of a structure where the drain / source connection hole has been excessively etched.

[0076] Figure 2a A top view of a storage block provided in another embodiment of this application;

[0077] Figure 2b A partial top view of a storage block provided in an embodiment of this application;

[0078] Figure 3 for Figure 2a A vertical cross-sectional view along the row direction at point A of the storage block shown;

[0079] Figure 4 for Figure 2a The vertical cross-sectional view along the row direction at point B of the storage block shown.

[0080] Figure 5 A schematic diagram of a planar structure forming an outgoing via on a semiconductor substrate;

[0081] Figure 6 for Figure 5 A vertical cross-sectional view along the row direction at point C of the semiconductor substrate shown.

[0082] Figure 7 for Figure 5 A vertical cross-sectional view along the row direction at point D of the semiconductor substrate shown.

[0083] Figure 8 for Figure 5 Another vertical cross-sectional view of the semiconductor substrate shown along the row direction;

[0084] Figure 9 for Figure 2a Another vertical cross-sectional view along the row direction at point A of the storage block shown;

[0085] Figure 10 for Figure 2a Another vertical cross-sectional view along the row direction at point B of the storage block shown;

[0086] Figure 11 Another flowchart illustrating a method for manufacturing a memory block according to an embodiment of this application;

[0087] Figure 12 This is a planar schematic diagram of another semiconductor structure provided in an embodiment of this application;

[0088] Figures 13-30 for Figure 11 The diagram shows the structural schematic corresponding to the specific process flow of the manufacturing method for the memory block.

[0089] Explanation of reference numerals in the attached figures

[0090] Memory block 10 / 10'; Memory array 1; Memory subarray layer 1a; Drain semiconductor strip 11; Channel semiconductor strip 12; Source semiconductor strip 13; A row of semiconductor strip structures 1b; Isolation wall 3; Word line via 4; Substrate 81; Drain semiconductor layer 11c; Channel semiconductor layer 12c; Source semiconductor layer 13c; First drain / source connection group 92a; Second drain / source connection group 92b; Drain / source connection plug 94; First insulating material 95a; Filler 95b; Insulating layer 95c; Drain / source via 96; Drain / source connection via 98;

[0091] Drain / source connection unit 21; Drain / source connection terminal 211; Through hole 22; First through hole 22a; Second through hole 22b; Third through hole 22c; Sixth through hole 22d; (K / 2+1)th through hole 22e; (K / 2+2)th through hole 22f; (K / 2+3)th through hole 22g; Drain / source through structure 23; Semiconductor connection layer 231; Connection improvement layer 232; Metal connection layer 233; Insulating isolation layer 24; Drain / source isolation through hole 25. Detailed Implementation

[0092] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0093] The terms "first," "second," and "third" in this application are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first," "second," or "third" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified. All directional indications (such as up, down, left, right, front, back, etc.) in the embodiments of this application are only used to explain the relative positional relationships and movements between components in a specific orientation (as shown in the figures). If the specific orientation changes, the directional indications also change accordingly. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or devices.

[0094] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0095] The present application will now be described in detail with reference to the accompanying drawings and embodiments.

[0096] This document incorporates all contents from the "Detailed Description" of Chinese Patent Application 2022113607924. Figures 43-46 and their corresponding text in Chinese Patent Application 2022113607924 illustrate that each first drain / source connection group 92a or second drain / source connection group 92b includes multiple drain / source connections 91a / 91b. Furthermore, Figures 59 and 60, and the relevant textual descriptions of steps S435 and S436 in Chinese Patent Application 2022113607924 also describe that during step S436, the source / drain voltage recovery region is used as a cutoff layer for the drain / source connection hole 98 (referred to as a drain / source isolation hole in this application) using an insulating layer 95c, and then filled with a polysilicon filler 95b. Then, utilizing the high selectivity of polysilicon to the insulating layer 95c, the multiple drain / source connection holes 98 can remain on steps of different heights. However, in conjunction with the appendix of this application… Figure 1 , Figure 1 This is a schematic diagram of a drain / source connection hole 98 that has been excessively etched. During the formation of multiple drain / source connection holes 98, when the height difference between two steps is large, the drain / source connection hole 98 corresponding to the higher step may remain etched for an extended period. This causes the bottom of the drain / source connection hole 98 corresponding to the higher step to gradually increase in size, resulting in a gradual decrease in the spacing between the two drain / source connection holes 98 corresponding to adjacent steps, or even direct connection. This allows conductive material to be filled into these two drain / source connection holes 98 to form a drain / source connection plug 94 (see Chinese Patent Application 2022113607924). Figure 4 After that, it may cause bridging of the drain / source connection plug 94 (referred to as drain / source lead-out structure in this application embodiment), resulting in risks such as short circuits.

[0097] To address the aforementioned issues, this embodiment provides an alternative memory block and its manufacturing process, which can prevent bridging between two adjacent drain / source connection plugs 94, thus avoiding risks such as short circuits; and can also reduce process complexity and improve manufacturing efficiency.

[0098] See Figures 2a to 4 , Figure 2a A top view of a storage block provided in another embodiment of this application; Figure 3 for Figure 2a A vertical cross-sectional view along the row direction at point A of the storage block shown; Figure 4 for Figure 2a The image shows a vertical cross-sectional view along the row direction at point B of the memory block. In this embodiment, another memory block 10' is provided, including a substrate 81 and a memory array 1.

[0099] For details regarding the specific structure and function of the substrate 81 and the memory array 1, please refer to Chinese Patent Application 2022113607924, its appendix. Figures 2a to 3 Appendix Figure 18 The corresponding text describes the specific structure and function of the memory array 1 and the substrate 81, as well as the specific method for forming the memory array 1 on the substrate 81. Specifically, Chinese patent application 2022113607924 describes the substrate 81 as a single-crystal substrate; the memory array 1 is disposed on the substrate 81. The memory array 1 includes multiple memory cells arranged in a three-dimensional array. As its... Figure 2a As shown, the memory array 1 includes multiple memory subarray layers 1a stacked sequentially along the height direction Z. Each memory subarray layer 1a includes a drain semiconductor layer 11c, a channel semiconductor layer 12c, and a source semiconductor layer 13c stacked along the height direction Z. The drain semiconductor layer 11c, the channel semiconductor layer 12c, and the source semiconductor layer 13c can be single-crystal semiconductor layers grown epitaxially. The height direction Z is perpendicular to the substrate (e.g., ...). Figure 9 The orientation of the substrate 81). "Layered sequentially" indicates that the layers are arranged sequentially from bottom to top on the substrate, while "layered" simply means arrangement and does not explicitly indicate or imply the structure or the vertical relationship between layers. In each memory subarray layer 1a, the drain semiconductor layer (D) includes multiple drain semiconductor strips 11 spaced apart along the row direction X, each drain semiconductor strip 11 extending along the column direction Y; the channel semiconductor layer (CH) includes multiple channel semiconductor strips 12 spaced apart along the row direction X, each channel semiconductor strip 12 extending along the column direction Y. The source semiconductor layer (S) includes multiple source semiconductor strips 13 spaced apart along the row direction X, each source semiconductor strip 13 extending along the column direction Y. Each drain semiconductor strip 11, channel semiconductor strip 12, and source semiconductor strip 13 is a single-crystal semiconductor strip. Those skilled in the art will understand that each drain semiconductor strip 11, channel semiconductor strip 12, and source semiconductor strip 13 can be a single-crystal semiconductor strip formed by processing the drain semiconductor layer, channel semiconductor layer, and source semiconductor layer formed epitaxially. For example, as in Chinese patent application 2022113607924... Figure 2a-3 As shown, for ease of description, it is defined that a row of drain semiconductor strips 11, channel semiconductor strips 12 and source semiconductor strips 13 in each memory subarray layer 1a constitute a semiconductor strip structure 1b.

[0100] The storage block 10' provided in this application differs from the storage block 10 provided in Chinese patent application 2022113607924 in that: the storage block 10' includes: at least one drain / source lead-out area, wherein a drain / source lead-out area is provided with a plurality of drain / source connection terminal units 21, and the plurality of drain / source connection terminal units 21 are respectively spaced along the row direction X and the column direction Y; that is, a plurality of drain / source connection terminal units 21 are respectively distributed along the row direction X and the column direction Y. In the drain / source lead-out region, the drain / source connection terminal 211 (CT) in each drain / source connection terminal unit 21 in the same drain / source lead-out region is connected to a layer of drain / source region semiconductor strip 11 / 13 in the corresponding column semiconductor strip structure 1b; compared with the drain / source connection terminal 211 in each drain / source connection terminal unit 21 being connected to a multilayer drain / source region semiconductor strip 11 / 13 in the corresponding column semiconductor strip structure 1b, it can avoid bridging between two adjacent drain / source connection terminals 211 in the same drain / source connection terminal unit 21 along the column direction Y, which could lead to a short circuit.

[0101] Specifically, the drain / source connection terminals 211 (CT) in several drain / source connection terminal units 21 in the same row are connected to the drain / source semiconductor strips 11 / 13 in the same layer of the multi-column semiconductor strip structure 1b, and the drain / source connection terminals 211 in several drain / source connection terminal units 21 in the same column are connected to multiple drain / source semiconductor strips 11 / 13 in different layers of a corresponding semiconductor strip structure 1b.

[0102] Each drain / source connection unit 21 may include one drain / source connection terminal 211 or two drain / source connection terminals 211 distributed along the row direction X. When each drain / source connection unit 21 includes one drain / source connection terminal 211, the drain / source connection terminal 211 is connected to the corresponding drain / source semiconductor strip 11 / 13. Each drain / source connection unit 21 includes two drain / source connection terminals 211, which are respectively connected to two adjacent columns of semiconductor strip structures 1b. That is, one column of semiconductor strip structures 1b corresponds to one drain / source connection terminal 211 in one drain / source connection unit 21. Compared to the scheme where one column of semiconductor strip structures 1b corresponds to multiple drain / source connection terminals 211 in one drain / source connection unit 21, and multiple drain / source connection terminals 211 are connected to the drain / source region semiconductor strips 11 / 13 of different layers of the column of semiconductor strip structures 1b, this scheme can avoid bridging between two adjacent drain / source connection terminals 211 along the column direction Y in the same drain / source connection unit 21, which could lead to a short circuit. At the same time, each drain / source connection terminal 211 extends to the side of the memory array 1 away from the substrate 81, that is, the drain / source connection terminals 211 all fall on the top of the memory block 10', which can reduce the difficulty of the fabrication process of the memory block 10'.

[0103] In some embodiments, combined with Figures 2a to 4 Each drain / source connection unit 21 includes a first drain / source connection 211 and a second drain / source connection 211 distributed along the row direction X; the first drain / source connection 211 and the second drain / source connection 211 are respectively connected to the drain / source semiconductor strips 11 / 13 of the same layer of two adjacent columns of semiconductor strip structures 1b.

[0104] In this embodiment, combined with Figure 2a Each semiconductor strip structure 1b is connected to one of the drain / source connection terminals 211 in the same row of multiple drain / source connection terminal units 21; that is, in the multiple drain / source connection terminal units 21 in the same row, there are two columns of semiconductor strip structures 1b between each two adjacent drain / source connection terminal units 21.

[0105] Of course, in other embodiments, see Figure 2b , Figure 2b This is a partial top view of a memory block provided in an embodiment of this application; along the row direction X, a row of semiconductor strip structures 1b may also be provided between every two adjacent drain / source connection terminal units 21. Two drain / source connection terminals 211 that are close to each other in these two drain / source connection terminal units 21 are respectively connected to the drain / source region semiconductor strips 11 / 13 of the same layer of the semiconductor strip structure 1b located between them. This is so that when the drain / source connection terminal 211 of one drain / source connection terminal unit 21 is damaged and cannot transmit signals, the drain / source connection terminal 211 of the other adjacent drain / source connection terminal unit 21 can be used to ensure the normal lead-out of the corresponding layer's drain / source region semiconductor strips 11 / 13. For example, combined with... Figure 2b The second column of semiconductor strip structures 1b shown from left to right is connected to the right drain / source connection terminal 211 of the first drain / source connection terminal unit 21 from left to right, and to the left drain / source connection terminal 211 of the second drain / source connection terminal unit 21.

[0106] The following embodiments of this application are all based on Figure 2a The corresponding solutions will be explained.

[0107] The following definition defines the two outermost columns of semiconductor strip structures 1b along the row direction X as edge semiconductor strip structures 1b; and the other columns of semiconductor strip structures 1b located between the two edge columns of semiconductor strip structures 1b as non-edge semiconductor strip structures 1b.

[0108] Please continue reading. Figure 2aIn the drain / source lead-out region, each column of non-edge semiconductor strip structure 1b is respectively connected to two columns of drain / source connection terminal units 21; wherein, the second drain / source connection terminal 211 in one column of drain / source connection terminal units 21 is connected to the drain / source region semiconductor strips 11 / 13 of the odd-numbered layers in the non-edge semiconductor strip structure 1b, and the first drain / source connection terminal 211 in the other column of drain / source connection terminal units 21 is connected to the drain / source region semiconductor strips 11 / 13 of the even-numbered layers in the non-edge semiconductor strip structure 1b. In this way, the spacing between two adjacent drain / source connection terminal units 21 along the column direction Y can be increased, avoiding bridging of the drain / source connection terminals 211 in two adjacent drain / source connection terminal units 21 along the column direction Y.

[0109] Of course, in other embodiments, the second drain / source connection terminal 211 in one row of drain / source connection terminal units 21 can be connected to the multilayer drain / source semiconductor strip 11 / 13 in the high region F2 of the non-edge semiconductor strip structure 1b, and the first drain / source connection terminal 211 in another row of drain / source connection terminal units 21 can be connected to the multilayer drain / source semiconductor strip 11 / 13 in the low region F1 of the non-edge semiconductor strip structure 1b. Alternatively, the second drain / source connection terminal 211 in one column of drain / source connection terminal units 21 can be connected to any few layers of drain / source semiconductor strips 11 / 13 in the non-edge semiconductor strip structure 1b, and the first drain / source connection terminal 211 in another column of drain / source connection terminal units 21 can be connected to the remaining few layers of drain / source semiconductor strips 11 / 13 in the non-edge semiconductor strip structure 1b. This application does not limit this, as long as these two columns of drain / source connection terminal units 21 lead out the corresponding multilayer drain / source semiconductor strips 11 / 13 of the non-edge semiconductor strip structure 1b respectively.

[0110] Among them, the first drain / source connection terminal 211 and the second drain / source connection terminal 211 in the same drain / source connection terminal unit 21 can connect the drain / source semiconductor strips 11 / 13 of the same layer of two adjacent columns of semiconductor strip structures 1b; or connect the drain / source semiconductor strips 11 / 13 of different layers of two adjacent columns of semiconductor strip structures 1b.

[0111] It is understandable that the connection principle between the drain / source connection unit 21 and the semiconductor strip structure 1b described above also applies to the edge semiconductor strip structure 1b.

[0112] Combination Figure 2aIn each non-edge column of semiconductor strip structure 1b, the two columns of drain / source connection units 21 are staggered along the row direction X. Thus, even with the fabrication of each row of drain / source connection units 21, while ensuring the drain / source lead-out region is within a preset size range along the column direction Y, the spacing between adjacent drain / source connection units 21 in the same column is maximized, reducing the probability of bridging between the drain / source connections 211 in the two drain / source connection units 21.

[0113] Please continue reading. Figures 2a-4 The first drain / source connection 211 and the second drain / source connection 211 in each drain / source connection unit 21 share the same drain / source isolation hole 25 (see below). Figure 13 The drain / source isolation via 25, in conjunction with the word line via 4 and the isolation wall 3, separates two adjacent rows of semiconductor strip structures 1b. The word line via 4 and the isolation wall 3 can be referenced in Chinese Patent Application 2022113607924, which includes... Figure 4 and Figure 2a The corresponding text section describes the letter line hole 4 and the isolation wall 3.

[0114] The drain / source isolation via 25 is used to remove the portion of the channel semiconductor strip 12 in two adjacent columns of semiconductor strip structures 1b that is close to the drain / source isolation via 25; the removed areas of the drain / source isolation via 25 and the channel semiconductor strip 12 are filled with a first insulating material 95a. Two adjacent drain / source semiconductor strips 11 / 13 in different layers of each column of semiconductor strip structure 1b in the region of each drain / source connection unit 21 are isolated from each other by the first insulating material 95a. This "isolation from each other" means preventing short circuits when two adjacent drain / source semiconductor strips 11 / 13 are led out. The structure, function, and opening method of the drain / source isolation via 25 are the same as or similar to the structure, function, and opening method of the drain / source via 96 described above, as detailed above. For the filling method of the first insulating material 95a, please refer to the relevant description of the filling method of the first insulating material 95a in Chinese Patent Application 2022113607924.

[0115] In some embodiments, see Figure 5 and Figure 6 , Figure 5 A schematic diagram of a planar structure forming an outgoing via on a semiconductor substrate; Figure 6 for Figure 5 A vertical cross-sectional view along the row direction at point C of the semiconductor substrate shown. Figure 7 for Figure 5The diagram shows a vertical cross-sectional view of the semiconductor substrate at point D along the row direction. Along the row direction X, in the region where each drain / source connection unit 21 is located, drain / source isolation vias 25 are respectively provided on both sides of the via 22. Each via 22 exposes a layer of drain / source semiconductor strips 11 / 13 in a row of semiconductor strip structures 1b. It can be understood that each drain / source isolation via 25 has one via 22 on each side along the row direction X; one of the two vias 22 exposes a layer of drain / source semiconductor strips 11 / 13 in one of the corresponding two adjacent rows of semiconductor strip structures 1b; the other via 22 exposes a layer of drain / source semiconductor strips 11 / 13 in the other of the corresponding two adjacent rows of semiconductor strip structures 1b.

[0116] Among them, comparison Figure 5 and Figure 6 As shown, the drain / source connection terminal units 21 in the same row, corresponding to the lead-out holes 22 in the same row, respectively expose the drain / source semiconductor strips 11 / 13 of the same layer in the multi-column semiconductor strip structure 1b. (Comparison) Figure 5 and Figure 7 As shown, the drain / source connection terminal units 21 in the same column and the corresponding lead-out holes 22 in the same column expose the drain / source semiconductor strips 11 / 13 of different layers in the same semiconductor strip structure 1b, so as to lead out the multilayer drain / source semiconductor strips 11 / 13 in the corresponding column of semiconductor strip structure 1b.

[0117] Combination Figure 3 or Figure 4 A drain / source lead-out structure 23 is provided in the lead-out hole 22, and the drain / source connection terminal 211 is connected to the drain / source region semiconductor strip 11 / 13 in the semiconductor strip structure 1b through the drain / source lead-out structure 23.

[0118] In some embodiments, combined with Figure 3 and Figure 8 As shown, Figure 8 for Figure 5 Another vertical cross-sectional view of the semiconductor substrate along the X-direction is shown. The sidewalls and bottom walls of the lead-out holes 22 are covered with an insulating layer 24, exposing only one corresponding drain / source semiconductor strip 11 / 13 in the semiconductor strip structure 1b. This ensures that the corresponding drain / source lead-out structure 23 is electrically connected only to the corresponding drain / source semiconductor strip 11 / 13, and is insulated from drain / source semiconductor strips 11 / 13 in other layers. The insulating layer 24 may be made of silicon oxide or silicon nitride.

[0119] In some embodiments, such as Figure 3 or Figure 4As shown, the drain / source lead-out structure 23 includes a semiconductor interconnect layer 231 and a connectivity improvement layer 232 extending along the height direction Z; wherein, the semiconductor interconnect layer 231 is in direct contact with the corresponding exposed drain / source semiconductor strips 11 / 13. Since polysilicon has good filling properties, the semiconductor interconnect layer 231 may include a polysilicon interconnect layer. The connectivity improvement layer 232 is disposed on the side of the semiconductor interconnect layer 231 facing away from the substrate 81 and is in contact with the corresponding drain / source connection terminal 211. The conductivity of the connectivity improvement layer 232 is superior to that of the semiconductor interconnect layer 231. Specifically, the connectivity improvement layer 232 includes a metal silicide connectivity improvement layer 232 to ensure effective contact and electrical connection between the connectivity improvement layer 232 and the corresponding drain / source connection terminal 211. The semiconductor interconnect layer 231 extends along the height direction Z to a port near the end of the lead-out hole 22 facing away from the substrate 81; the surface of the connection improvement layer 232 facing away from the semiconductor interconnect layer 231 may be flush with the surface of the memory array 1 facing away from the substrate 81. The drain / source interconnect 211 is made of metal.

[0120] In another embodiment, see Figures 9-10 , Figure 9 for Figure 2a Another vertical cross-sectional view along the row direction at point A of the storage block shown; Figure 10 for Figure 2a Another vertical cross-sectional view along the row direction at point B of the shown memory block. The drain / source lead-out structure 23 includes a connection improvement layer 232 and a metal connection layer 233 extending along the height direction Z. The connection improvement layer 232 is in direct contact and electrically connected to the corresponding exposed drain / source semiconductor strips 11 / 13. The connection improvement layer 232 includes a metal silicide connection improvement layer 232. The metal connection layer 233 is disposed on the side surface of the connection improvement layer 232 facing away from the substrate 81 and extends along the height direction Z to the side surface of the memory array 1 facing away from the substrate 81, and contacts the corresponding drain / source connection terminal 211. The conductivity of the metal connection layer 233 is better than that of the connection improvement layer 232. The dimension of the metal connection layer 233 along the height direction Z is much larger than that of the connection improvement layer 232 along the height direction Z, and the side surface of the metal connection layer 233 facing away from the connection improvement layer 232 can be flush with the side surface of the memory array 1 facing away from the substrate 81. In some embodiments, the metal interconnect layer 233 and the drain / source connection 211 are made of the same metal, such as tungsten, copper, or silver.

[0121] In some embodiments, please refer back to Chinese Patent Application 2022113607924, where Figures 46, 54-60 and the corresponding text describe an example of forming connection ends connected to the drain / source semiconductor strips 11 / 13 of the corresponding layer by dividing the area into a high region F2 and a low region F1 and simultaneously etching them. The embodiments provided below in this application can also adopt a similar approach. For example, if the current semiconductor strip structure 1b corresponds to six drain / source semiconductor strips 11 / 13, then the drain / source semiconductor strips 11 / 13 in the lower region F1 of the semiconductor strip structure 1b refer to the multi-layer drain / source semiconductor strips 11 / 13 from the fourth drain / source semiconductor strip 11 / 13 to the sixth drain / source semiconductor strip 11 / 13 from top to bottom, and the drain / source semiconductor strips 11 / 13 in the higher region F2 of the semiconductor strip structure 1b refer to the multi-layer drain / source semiconductor strips 11 / 13 from the first drain / source semiconductor strip 11 / 13 to the third drain / source semiconductor strip 11 / 13 from top to bottom.

[0122] Specifically, each drain / source lead-out region includes a high drain / source lead-out sub-region and a low drain / source lead-out sub-region. The drain / source connection terminal 211 in the high drain / source lead-out sub-region is used to connect to the drain / source semiconductor strips 11 / 13 of the high region F2 in the semiconductor strip structure 1b; the drain / source connection terminal 211 in the low drain / source lead-out sub-region is used to connect to the drain / source semiconductor strips 11 / 13 of the low region F1 in the semiconductor strip structure 1b. The drain / source connection terminal 211 corresponding to the drain / source semiconductor strips 11 / 13 of each high region F2 layer, the drain / source semiconductor strips 11 / 13 of the matching layer of the drain / source semiconductor strips 11 / 13 of the low region F1, and the drain / source lead-out structure 23 can be formed in the same process; this simplifies the process and reduces process difficulty. For specific process methods, please refer to the relevant description in the process method section below.

[0123] In some embodiments, storage block 10' may include a plurality of drain / source lead-out regions, which are spaced apart in the column direction Y. Thus, in each column of semiconductor strip structure 1b, the same drain / source region semiconductor strip 11 / 13 can be connected to the corresponding drain / source connection terminal 211 in the corresponding drain / source connection terminal unit 21 in multiple drain / source lead-out regions. That is, the same drain / source region semiconductor strip 11 / 13 can be connected to multiple drain / source connection terminals 211 along the column direction Y. This allows the portion of the same drain / source region semiconductor strip 11 / 13 located between two adjacent drain / source connection terminals 211 along the column direction Y to directly transmit signals through the corresponding drain / source connection terminal 211, performing read (RD), program (PGM) and other operations. Compared to the existing method of leading out the tail of each drain / source region semiconductor strip 11 / 13 (i.e., the edge of the memory block 10'10) through a connecting line to perform related operations on the entire drain / source region semiconductor strip 11 / 13, the resistance can be reduced, signal transmission can be facilitated, and the speed of read (RD), program (PGM) and other operations of the memory block 10'10 can be improved.

[0124] The memory block 10' provided in this embodiment includes a substrate 81, a memory array 1, and at least one drain / source lead-out region. The memory array 1 includes multiple memory cells distributed in a three-dimensional array. The memory array 1 includes multiple memory sub-array layers 1a stacked sequentially along the height direction Z. Each memory sub-array layer 1a includes a drain semiconductor layer 11c, a channel semiconductor layer 12c, and a source semiconductor layer 13c stacked along the height direction Z. The drain semiconductor layer 11c, channel semiconductor layer 12c, and source semiconductor layer 13c in each memory sub-array layer 1a respectively include multiple drain semiconductor strips 11, channel semiconductor strips 12, and source semiconductor strips 13 distributed along the row direction X. Each drain semiconductor strip 11, channel semiconductor strip 12, and source semiconductor strip 13 extends along the column direction Y. A column of drain semiconductor strips 11, channel semiconductor strips 12, and source semiconductor strips 13 in the multilayer memory sub-array layer 1a is defined as a column of semiconductor strip structure 1b. Simultaneously, the drain / source lead-out region is provided with multiple drain / source connection terminal units 21, which are spaced apart along the row direction X and column direction Y respectively; in the drain / source lead-out region, the drain / source connection terminal 211 in each drain / source connection terminal unit 21 in the same drain / source lead-out region is connected to a layer of drain / source region semiconductor strip 11 / 13 in the corresponding column semiconductor strip structure 1b; compared to the drain / source connection terminal 211 in each drain / source connection terminal unit 21 connecting to the corresponding column semiconductor strip... The multilayer drain / source semiconductor strips 11 / 13 in structure 1b can prevent bridging between two adjacent drain / source connection terminals 211 along the column direction Y in the same drain / source connection terminal unit 21, which would lead to a short circuit. At the same time, by extending each drain / source connection terminal 211 to the side of the memory array 1 away from the substrate 81, that is, by having all drain / source connection terminals 211 fall on the top of the memory block 10', the fabrication process of the memory block 10' can be simplified. The memory block 10' has a high storage density.

[0125] The above Figures 2a-10 The storage block 10' shown can be specifically manufactured using the following storage block manufacturing process.

[0126] See Figures 11 to 12 , Figure 11 Another flowchart illustrating a method for manufacturing a memory block according to an embodiment of this application; Figure 12 This is a planar schematic diagram of another semiconductor substrate provided in an embodiment of this application; in this embodiment, a method for manufacturing a memory block is provided, the method specifically including:

[0127] Step S51: Provide a semiconductor substrate.

[0128] For details on the specific structure and function of the semiconductor substrate, please refer to the relevant description of the semiconductor substrate provided in step S41 of Chinese patent application 2022113607924.

[0129] Step S52: In at least one drain / source lead-out region of the semiconductor substrate, a plurality of drain / source connection terminal units are provided.

[0130] It should be noted that the drain / source lead-out region can refer to the entire semiconductor substrate, or a portion of the semiconductor substrate with a certain length along the column direction Y; the drain / source lead-out region is actually an artificially defined virtual region, not a physically existing area on the semiconductor substrate; it can correspond to any part of the semiconductor substrate along the column direction Y according to actual needs. For example... Figure 12 The portion of the semiconductor substrate shown can be divided into a drain / source lead-out region.

[0131] The semiconductor substrate may include one or more drain / source lead-out regions; step S52 specifically involves setting multiple drain / source connection terminal units 21 in each drain / source lead-out region. When the semiconductor substrate includes one drain / source lead-out region, this region may correspond to a non-end region along the column direction Y of the semiconductor substrate, that is, a region along the column direction Y of the semiconductor substrate that is distinct from the beginning and end. Compared to a scheme where the drain / source lead-out region is the end region along the column direction Y of the semiconductor substrate, this reduces resistance, facilitates signal transmission, and improves the speed of read (RD), program (PGM), and other operations of the memory block 10'10.

[0132] When a semiconductor substrate includes multiple drain / source lead-out regions, the multiple drain / source lead-out regions are spaced apart in the column direction Y; the multiple drain / source lead-out regions can be simultaneously set with their respective multiple drain / source connection terminal units 21 using the same process to simplify the process.

[0133] The following describes the specific implementation of step S52 using the example of setting multiple drain / source connection terminal units 21 in a drain / source lead-out area.

[0134] In this configuration, multiple drain / source connection units 21 are spaced apart along the row direction X and the column direction Y. In the drain / source lead-out region, the drain / source connection terminal 211 (CT) in each drain / source connection unit 21 in the same drain / source lead-out region is connected to a layer of drain / source region semiconductor strip 11 / 13 in the corresponding column semiconductor strip structure 1b. Compared to the drain / source connection terminal 211 in each drain / source connection unit 21 being connected to multiple layers of drain / source region semiconductor strip 11 / 13 in the corresponding column semiconductor strip structure 1b, this configuration avoids bridging between two adjacent drain / source connection terminals 211 along the column direction Y in the same drain / source connection unit 21, which could lead to a short circuit.

[0135] Specifically, the drain / source connection terminals 211 (CT) in several drain / source connection terminal units 21 in the same row are connected to the drain / source semiconductor strips 11 / 13 in the same layer of the multi-column semiconductor strip structure 1b. The drain / source connection terminals 211 in several drain / source connection terminal units 21 in the same column are connected to multiple drain / source semiconductor strips 11 / 13 in different layers of a corresponding semiconductor strip structure 1b. See the above for details. Figures 2a-10 The relevant description of the drain / source connection terminal unit 21.

[0136] In one specific implementation, combined with Figures 13 to 14 , Figure 13 for Figure 12 The diagram shows a product structure with multiple drain / source isolation vias on a semiconductor substrate. Figure 14 A schematic diagram of the product plan after filling the removed areas of the drain / source isolation vias and channel semiconductor strips with the first insulating material; step S52 specifically includes:

[0137] Step S521: Set multiple drain / source isolation holes 25 in the drain / source lead-out area.

[0138] Among them, such as Figure 13 As shown, drain / source isolation holes 25 are spaced apart along the row direction X and column direction Y, and each drain / source isolation hole 25 extends to the substrate 81 along the height direction Z.

[0139] Step S522: Remove the portion of the channel semiconductor strip 12 near the drain / source lead-out region in the two adjacent columns of semiconductor strip structures 1b through the drain / source isolation hole 25, and fill the removed area of ​​the drain / source isolation hole 25 and the channel semiconductor strip 12 with the first insulating material 95a.

[0140] The specific implementation of steps S521 and S522 is the same as or similar to the specific implementation of steps S42 and S43 above, which involve opening multiple drain / source holes 96, removing part of the channel semiconductor strip 12 in the semiconductor strip structure 1b through the drain / source holes 96, and filling the first insulating material 95a. For details, please refer to the relevant description above.

[0141] The vertical cross-sectional view of the product after removing the portion of the channel semiconductor strip 12 near the drain / source lead-out region in two adjacent rows of semiconductor strip structures 1b through the drain / source isolation hole 25 is similar to the structure shown in Figure 52 of Chinese Patent Application 2022113607924, which illustrates the structure after removing the portion of the channel semiconductor strip 12 near the drain / source lead-out region in two adjacent rows of semiconductor strip structures 1b through the drain / source hole 96.

[0142] Step S523: Open out holes 22 of preset depth on both sides of the drain / source isolation hole 25, and each out hole 22 exposes a layer of drain / source semiconductor strip 11 / 13 in a row of semiconductor strip structure 1b.

[0143] Combination Figures 5 to 8 Etching can be used to create lead-out holes 22 on both sides of the drain / source isolation hole 25. Specifically, a lead-out hole 22 with a preset depth of a first depth is defined as a first lead-out hole 22a, used to expose the first layer of drain / source semiconductor strips 11 / 13 in the corresponding column of semiconductor strip structure 1b; a lead-out hole 22 with a preset depth of a second depth is defined as a second lead-out hole 22b, used to expose the second layer of drain / source semiconductor strips 11 / 13 in the corresponding column of semiconductor strip structure 1b; a lead-out hole 22 with a preset depth of a third depth is defined as a third lead-out hole 22c, used to expose the third layer of drain / source semiconductor strips 11 / 13 in the corresponding column of semiconductor strip structure 1b, and so on. Step S523 can be implemented in the following three ways.

[0144] In the first implementation method, step S523 specifically includes:

[0145] Step A: A first removal operation is performed to open a first lead-out hole on both sides of the partial drain / source isolation hole; each a lead-out hole exposes the drain / source semiconductor strip 11 / 13 of the a layer in each column of semiconductor strip structure 1b.

[0146] Where a can be 1, 2, 3... or Q; Q is the total number of storage subarray layers 1a. That is, the first removal operation can be used to create a first lead-out hole; or a second lead-out hole; or a lead-out hole 22 of other depths.

[0147] Step B: By performing the second removal operation, the b-th lead-out holes are respectively opened on both sides of the partial drain / source isolation holes; each b-th lead-out hole exposes the drain / source semiconductor strip 11 / 13 of the b-th layer in each column of semiconductor strip structure 1b; and so on, until the drain / source semiconductor strip 11 / 13 of the last layer in each column of semiconductor strip structure 1b is exposed; where a and b are natural numbers greater than or equal to 1 and less than or equal to the number of layers of the memory subarray.

[0148] Where b can be any natural number different from a and less than or equal to Q. That is, the second removal operation can also be used to create an outlet hole 22 of any depth different from the a-th outlet hole. In this embodiment, the order in which outlet holes 22 of each depth are formed is not limited, as long as each removal operation forms an outlet hole 22 of the same depth, to prevent adjacent outlet holes 22 formed in the same removal operation from becoming connected.

[0149] In one specific embodiment, a row of lead-out holes 22 of corresponding depth are sequentially opened on both sides of each row of drain / source isolation holes 25, wherein the m-th lead-out holes opened on both sides of the m-th row of drain / source isolation holes expose the drain / source semiconductor strips 11 / 14 of the m-th layer in each column of semiconductor strip structure 1b.

[0150] In this process, a mask can be used to etch both sides of the drain / source isolation hole 25 in the m-th row to form the m-th lead-out hole.

[0151] It should be noted that line m in this application does not refer to a specific line; it can refer to any row of drain / source isolation vias 25 on the semiconductor substrate; m is a natural number greater than or equal to 1 and less than or equal to the number of layers in the memory subarray layer 1a. For example, the first line could be... Figure 15 The top row along the column direction Y can also be the bottom row along the column direction Y, or any other row between the top and bottom; the second row can be... Figure 15 The top row or the bottom row along the column direction Y. The following embodiments of this application are for illustrative purposes, such as... Figure 15 For example, the row along the column direction Y from top to bottom is the first row, the second row, ... the mth row.

[0152] The steps of sequentially opening a row of corresponding outlet holes 22 on both sides of each row of drain / source isolation holes 25 include steps f1-h1.

[0153] Combination Figures 6 to 8 as well as Figures 15-18 ; Figure 15 for Figure 14 The product shown is a schematic diagram of the product after processing in step Sf1; Step f1: First lead-out holes 22a are opened on both sides of the drain / source isolation hole 25 in the first row, and each first lead-out hole 22a exposes the drain / source semiconductor strip 11 / 13 of the first layer in each column of semiconductor strip structure 1b.

[0154] Combination Figure 7 and Figure 16 , Figure 16 for Figure 15 The diagram shows a structure with second lead-out holes on both sides of the drain / source isolation vias in the second row. Step g1: Second lead-out holes 22b are formed on both sides of the drain / source isolation vias 25 in the second row, each second lead-out hole 22b exposing the drain / source semiconductor strips 11 / 13 of the second layer in each column of semiconductor strip structures 1b. This process is repeated until the drain / source semiconductor strips 11 / 13 of the last layer in each column of semiconductor strip structures 1b are exposed.

[0155] For example, in a row of semiconductor strip structures 1b, the total number of drain / source semiconductor strips 11 / 13 is six. See also Figure 17 and Figure 18 , Figure 17 for Figure 16 The diagram shows a structure with third outlet holes on both sides of the drain / source isolation hole in the third row. Figure 18 for Figure 17 The structure shown is a vertical cross-sectional view at the third lead-out hole; after step g1, it also includes: step h1: third lead-out holes 22c are opened on both sides of the drain / source isolation hole 25 in the third row, and each third lead-out hole 22c exposes the drain / source semiconductor strip 11 / 13 of the third layer in each column of semiconductor strip structure 1b.

[0156] Subsequently, using a mask, lead-out holes 22 of corresponding depths are sequentially opened on both sides of the drain / source isolation holes 25 in the fourth, fifth, and sixth rows, exposing the drain / source semiconductor strips 11 / 13 of the corresponding layers; thereby exposing the drain / source semiconductor strips 11 / 13 of all layers.

[0157] The aforementioned lead-out holes 22 of the same preset depth are formed in the same row, and the corresponding mask has a simple structure, small area, and is easy to process. Of course, in other specific embodiments, by changing the mask, the lead-out holes 22a of the preset depth formed for each removal operation can also be located in different rows; or, some can be located in the same row and some in different rows; this application does not limit this.

[0158] In the first embodiment described above, different etching processes are used to form the lead-out holes 22 at different depths. That is, each etching process etches only lead-out holes 22 at the same depth (dimension along the height direction Z). The etching time for each lead-out hole 22 in that etching process is the same, meaning that all lead-out holes 22 reach the preset depth simultaneously without any time difference. This prevents situations where some lead-out holes 22 reach the preset depth, but others do not, and are continued to be etched. Consequently, the bottom of lead-out holes 22 that have already reached the preset depth gradually enlarges due to the extended etching time, leading to communication with adjacent lead-out holes 22. This ultimately causes bridging of the drain / source lead-out structures 23 within the corresponding lead-out hole 22, resulting in risks such as short circuits. This is a more preferred solution for semiconductor substrates with a large number of layers in the memory subarray layer 1a.

[0159] In the second embodiment, step S523 specifically includes: forming lead-out holes 22 of a preset depth on both sides of each drain / source isolation hole 25. Each lead-out hole 22 of the preset depth is formed by at least one removal operation. After n removal operations, the lead-out holes 22 of the preset depth expose the drain / source semiconductor strips 11 / 13 of the nth layer in the corresponding column of semiconductor strip structures 1b, where n is a natural number greater than or equal to 1 and less than or equal to the number of layers in the memory subarray layer 1a. The removal operation can be an etching operation.

[0160] In one specific implementation, combined with Figures 19 to 21 On both sides of each drain / source isolation hole 25, an outlet hole 22 of a preset depth is opened. Each outlet hole 22 of the preset depth is subjected to at least one removal operation, specifically including the following steps f2-i2.

[0161] like Figure 5 and Figure 6 As shown, in step f2: by performing a first removal operation, first lead-out holes 22a are opened on both sides of each drain / source isolation hole 25, wherein the lead-out holes 22 after the first removal operation expose the drain / source semiconductor strips 11 / 13 of the first layer in each row of semiconductor strip structures 1b.

[0162] In this second embodiment, the lead-out hole 22 formed by the nth removal operation can be referred to as the nth lead-out hole, and the nth lead-out hole exposes the drain / source semiconductor strip 11 / 13 of the nth layer in the corresponding column of semiconductor strip structure 1b. For example, the lead-out hole 22 formed by the first removal operation can be referred to as the first lead-out hole 22a. The vertical cross-sectional views of the first lead-out holes 22a on both sides of each drain / source isolation hole 25 are as follows. Figure 6 As shown.

[0163] See Figure 19 , Figure 19 In order to be in Figure 5 A schematic diagram of the structure in which the second drain / source connection terminal 211 is formed on the product shown;

[0164] Step g2: Except for the first lead-out hole 22a with a preset depth of the first depth, perform a second removal operation on the other first lead-out holes 22a to form second lead-out holes 22b, wherein the second lead-out holes 22b expose the drain / source semiconductor strips 11 / 13 of the second layer in each column of semiconductor strip structure 1b.

[0165] It is understood that the second outlet hole 22b formed by the second removal operation has a preset depth of the second depth for a portion of it, and a preset depth of the remaining portion of it is the third depth, or the fourth depth, or the fifth depth, ... or the Nth depth; that is to say, the remaining portion of the second outlet hole 22b needs to undergo further removal operations to reach the corresponding preset depth.

[0166] In this second embodiment, the example is taken as a row arrangement of lead-out holes 22 with a preset depth of Q. For example, a row arrangement of first lead-out holes 22a with a preset depth of a first depth; in this embodiment, step g2 means that a second removal operation is performed on all rows of first lead-out holes 22a except for one row of first lead-out holes 22a to form second lead-out holes 22b; each second lead-out hole 22b exposes the drain / source semiconductor strips 11 / 13 of the second layer in each column of semiconductor strip structure 1b.

[0167] Specifically, a mask can be used to cover one row of the first exit holes 22a in a plurality of rows, while exposing all other first exit holes 22a, to perform step g2; the vertical cross-sectional view of the second exit holes 22b on both sides of each drain / source isolation hole 25 after step g2 is as follows. Figure 7 As shown. The first exit hole 22a of the covered row can be the first exit hole 22a of the first row, or it can be the first exit hole 22a of the second row, the third row, or other rows. This application takes the covering of the first exit hole 22a of the first row as an example.

[0168] See Figure 20 , Figure 20 In order to be in Figure 19 The diagram shows a structure with a third lead-out hole formed on the product. Step h2: Except for the second lead-out hole 22b with a preset depth of the second depth, a third removal operation is performed on the other second lead-out holes 22b to form a third lead-out hole 22c. The third lead-out hole 22c exposes the drain / source semiconductor strips 11 / 13 of the third layer in each column of semiconductor strip structure 1b. This process is repeated until the drain / source semiconductor strips 11 / 13 of the last layer in each column of semiconductor strip structure 1b are exposed.

[0169] For example, a third removal operation is performed on all the second exit holes 22b in all rows except one row of second exit holes 22b to form a third exit hole 22c; each third exit hole 22c exposes the drain / source semiconductor strip 11 / 13 of the third layer in each column of semiconductor strip structure 1b.

[0170] As described above, a mask can be used to cover the first outlet hole 22a with a preset depth of a first depth and the second outlet hole 22b with a preset depth of a second depth, while exposing all other second outlet holes 22b, to execute step h2; the vertical cross-sectional views of the third outlet holes 22c on both sides of each drain / source isolation hole 25 after processing in step h2 are as follows. Figure 18 As shown. The second exit hole 22b of the covered row can be the second exit hole 22b of the first row, or it can be the second exit hole 22b of the second row, the third row, or other rows. This application uses the example of covering the second exit hole 22b of the first row.

[0171] For example, in a row of semiconductor strip structures 1b, the total number of drain / source semiconductor strips 11 / 13 is six. After step h2, the method further includes using a mask to sequentially open corresponding lead-out holes 22 on both sides of the drain / source isolation holes 25 in the fourth and fifth rows, exposing the drain / source semiconductor strips 11 / 13 of the corresponding layers, and step i2.

[0172] See Figure 2a , Figure 2b and Figure 21 , Figure 21 A schematic diagram of the product structure for forming the sixth lead-out hole; Step i2: Except for the lead-out holes 22 with preset depths from the first depth to the fifth depth, the other fifth lead-out holes are subjected to a sixth removal operation to form the sixth lead-out hole 22d, wherein the sixth lead-out hole 22d exposes the drain / source semiconductor strips 11 / 13 of the sixth layer in each column of semiconductor strip structure 1b.

[0173] For example, except for the fifth lead-out hole in one row, a sixth removal operation is performed on the fifth lead-out hole in another row to form a sixth drain / source lead-out hole 22d; each sixth lead-out hole 22d exposes the drain / source semiconductor strip 11 / 13 of the sixth layer in the multi-column semiconductor strip structure 1b; thus exposing the drain / source semiconductor strip 11 / 13 of all layers.

[0174] Of course, it is understandable that the exit holes 22 with a preset depth of Q can also be located in different rows; or some can be located in the same row and some in different rows. For example, some of the exit holes 22 with a preset depth of Q are located in the first row, some in the second row, and the rest in the fourth row. In this specific embodiment, after step g2 specifically covers the first exit hole 22a with a preset depth of the first depth, a second removal operation is performed on the other first exit holes 22a; steps h2 and i2 are similar.

[0175] In the second embodiment described above, since each etching process etches to the same layer of the semiconductor substrate, the depth of the etched holes is the same. The etching time for each lead-out hole 22 corresponding to this etching process is the same, meaning that each lead-out hole 22 reaches the preset depth simultaneously without any time difference. This prevents the situation where some lead-out holes 22 reach the preset depth, but others do not reach the preset depth and are etched further, causing the bottom of the lead-out holes 22 that have reached the preset depth to gradually enlarge due to the extended etching time. In other words, when it is necessary to etch a lead-out hole 22 with a greater depth, other lead-out holes 22 with a smaller depth will not continue to be etched. Therefore, this effectively avoids the risk of some lead-out holes 22 gradually enlarging at the bottom due to different etching times, which could lead to communication with other adjacent lead-out holes 22, causing bridging of the drain / source lead-out structures 23 within the corresponding lead-out hole 22 and resulting in short circuits. This is a better solution for semiconductor substrates with a large number of layers in the storage subarray layer 1a.

[0176] The third implementation method differs from the third embodiment described above in that step S523 specifically includes steps f3-h3.

[0177] See Figure 22 , Figure 22 This is a side view along the column direction of a semiconductor substrate provided in an embodiment of this application after processing in step f3; Step f3: First lead-out holes 22a are formed on both sides of a portion of the drain / source isolation holes 25 by a first removal operation; (K / 2+1)th lead-out holes 22e are formed on both sides of the remaining drain / source isolation holes 25 by a second removal operation; wherein, each first lead-out hole 22a exposes the drain / source semiconductor strip 11 / 13 of the first layer in the corresponding column of the semiconductor strip structure 1b; each (K / 2+1)th lead-out hole 22e exposes the drain / source semiconductor strip 11 / 13 of the (K / 2+1)th layer in the corresponding column of the semiconductor strip structure 1b; K is the total number of drain / source semiconductor strips 11 / 13 in a column of semiconductor strip structure 1b. For example, if K is six, then each fourth lead-out hole 22d exposes the drain / source semiconductor strip 11 / 13 of the fourth layer in the corresponding column of the semiconductor strip structure 1b.

[0178] Specifically, first exit holes 22a can be opened on both sides of the drain / source isolation holes 25 in multiple adjacent rows; or, first exit holes 22a can be opened on both sides of the drain / source isolation holes 25 in any few rows (such as the first row, the third row, and the fourth row); and then (K / 2+1)th exit holes 22e can be opened on both sides of the drain / source isolation holes 25 in the remaining rows.

[0179] In specific implementation, multiple first lead-out holes 22a can be formed using the same etching process with a mask; multiple (K / 2+1)th lead-out holes 22e can be formed using a different etching process with a mask. Of course, in other implementations, as in step f2, first lead-out holes 22a can be formed on both sides of each drain / source isolation hole 25 through a first removal operation, exposing the drain / source semiconductor strips 11 / 13 of the first layer in each row of semiconductor strip structures 1b; then, a second removal operation is performed on all other first lead-out holes 22a except for the first lead-out holes 22a with a preset depth of the first depth to form (K / 2+1)th drain / source lead-out holes 22e; each (K / 2+1)th lead-out hole 22e exposes the drain / source semiconductor strips 11 / 13 of the (K / 2+1)th layer in each row of semiconductor strip structures 1b.

[0180] See Figure 23 , Figure 23 A side view along the column direction of a semiconductor substrate provided in an embodiment of this application after being processed by step g3; Step g3: Except for the lead-out holes 22 with a preset depth of first depth and (K / 2+1) depth, a third removal operation is performed on all other first lead-out holes 22a and (K / 2+1) lead-out holes 22e to form second lead-out holes 22b and (K / 2+2) lead-out holes 22f respectively.

[0181] Specifically, a third removal operation is performed on all first outlet holes 22a except for the first outlet hole 22a with a preset depth of a first depth, to form a second outlet hole 22b; and a third removal operation is performed on all (K / 2+1) outlet holes 22e except for the preset depth of a (K / 2+1) depth, to form a (K / 2+2) outlet hole 22f.

[0182] In this embodiment, the first outlet holes 22 with a preset depth of a first depth can be located in the same row; the (K / 2+1)th outlet holes 22 with a preset depth of (K / 2+1)th depth can also be located in the same row. In this embodiment, a third removal operation can be performed on all first outlet holes 22 in all rows except one row of first outlet holes 22a; a third removal operation can be performed on all (K / 2+1)th outlet holes 22e in all rows except one row of (K / 2+1)th outlet holes 22e, so as to form an outlet hole 22f with a depth of (K / 2+2).

[0183] It is understood that the second lead-out hole 22b and the (K / 2+2)th lead-out hole 22f in step g3 are formed by the same removal operation; for example, they are formed simultaneously using the same etching process with a mask; thus, the process can be simplified and the process efficiency improved. Specifically, the second lead-out hole 22b exposes the drain / source semiconductor strips 11 / 13 of the second layer in each row of semiconductor strip structures 1b; the (K / 2+2)th lead-out hole 22f exposes the drain / source semiconductor strips 11 / 13 of the (K / 2+2)th layer in each row of semiconductor strip structures 1b.

[0184] See Figure 24 , Figure 24 A side view along the column direction of a semiconductor substrate provided in an embodiment of this application after being processed in step h3; Step h3: Except for the lead-out holes 22 at the second depth and the (K / 2+2) depth, a fourth removal operation is performed on the other second lead-out holes 22b and the (K / 2+2) lead-out holes 22f to form the third lead-out holes 22c and the (K / 2+3) lead-out holes 22g; and so on, until the drain / source semiconductor strips 11 / 13 of the last layer in each column of semiconductor strip structure 1b are exposed.

[0185] Similarly, the lead-out holes 22 with preset depths of the first depth, second depth, (K / 2+1) depth, or (K / 2+2) depth can be located in the same row. In this embodiment, a fourth removal operation can be performed on all second lead-out holes 22b in all rows except one row to form a third lead-out hole 22c; a fourth removal operation can be performed on the lead-out holes with a depth of (K / 2+2) opened on both sides of the drain / source isolation holes 25 in all rows except one row of (K / 2+2) lead-out holes 22f to form a (K / 2+3) lead-out hole 22g. This process continues until the drain / source semiconductor strips 11 / 13 of the last layer in each column of semiconductor strip structure 1b are exposed.

[0186] It is understood that the third lead-out hole 22c and the (K / 2+3)th lead-out hole 22g in step h3 are formed by the same removal operation; this simplifies the process and improves process efficiency. Specifically, the third lead-out hole 22c exposes the drain / source semiconductor strips 11 / 13 of the third layer in each row of semiconductor strip structures 1b; the (K / 2+3)th lead-out hole 22g exposes the drain / source semiconductor strips 11 / 13 of the (K / 2+3)th layer in multiple rows of semiconductor strip structures 1b.

[0187] Compared to the first and second embodiments, the third implementation method described above simplifies the process and improves process efficiency. For example, when the total number of drain / source semiconductor strips 11 / 13 in a row of semiconductor strip structures 1b is six, the first and second embodiments require a total of six removal operations to expose all drain semiconductor strips 11 and source semiconductor strips 13; while the third embodiment only requires four removal operations to expose all drain semiconductor strips 11 and source semiconductor strips 13, saving two removal operations, simplifying the process and increasing efficiency.

[0188] Step S524: Form a drain / source lead-out structure 23 in the lead-out hole 22, and form a drain / source connection end 211 on the drain / source lead-out structure 23.

[0189] Step S524 can be implemented in the following two ways.

[0190] The first implementation method, see [link to implementation method]. Figures 25 to 28 This is a structural diagram corresponding to a specific implementation process of step S524; Figure 25 This is a schematic diagram of the structure after covering the sidewalls and bottomwalls of the outlet hole 22 with insulating isolation layers 24; step S524 includes:

[0191] Step k1: Deposit an insulating layer 24 on the sidewalls and bottomwalls of the lead-out hole 22.

[0192] Step k2: Remove at least a portion of the insulating isolation layer 24 on the bottom wall of the lead-out hole 22 to expose the drain / source semiconductor strips 11 / 13 of the corresponding layer in the row of semiconductor strip structures 1b corresponding to the lead-out hole 22.

[0193] The above method ensures that the corresponding drain / source lead-out structure 23 formed later is only electrically connected to the corresponding drain / source semiconductor strip 11 / 13, and is insulated from the drain / source semiconductor strip 11 / 13 of other layers.

[0194] like Figure 2a , Figure 2b As shown, a portion of the insulating layer 24 on the bottom wall of the lead-out hole 22 can be removed.

[0195] Step k3: A semiconductor interconnect layer 231 extending along the height direction Z is formed in each lead-out hole 22 where an insulating isolation layer 24 is deposited on the sidewall.

[0196] Specifically, such as Figure 26 As shown, a semiconductor interconnect layer 231 is deposited in each lead-out hole 22 and on the surface of the memory array 1 facing away from the substrate 81; then, as Figure 27As shown, the semiconductor interconnect layer 231 on the side surface of the memory array 1 facing away from the substrate 81 is removed to form a semiconductor interconnect layer 231 in each lead-out hole 22. The semiconductor layer on the side surface of the memory array 1 facing away from the substrate 81 can be removed by chemical mechanical polishing (CMP).

[0197] The semiconductor interconnect layer 231 includes a polysilicon interconnect layer.

[0198] Step k4: Form a connectivity improvement layer 232 on the semiconductor interconnect layer 231.

[0199] like Figure 28 As shown, a connection improvement layer 232 is formed on the side of the semiconductor connection layer 231 facing away from the substrate 81, and is used to improve the contact resistance between the drain / source lead-out structure 23 and the drain / source connection terminal 211. The connection improvement layer 232 specifically includes a metal silicide connection improvement layer to ensure effective contact and electrical connection between the connection improvement layer 232 and the corresponding drain / source connection terminal 211 formed later. In some embodiments, the connection improvement layer 232 may be omitted.

[0200] Step k5: Form a drain / source connection terminal 211 on the side surface of the connection improvement layer 232 that is away from the semiconductor connection layer 231.

[0201] like Figure 3 As shown, the drain / source connection terminals 211 all fall on the side surface of the memory array 1 facing away from the substrate 81, that is, on the top of the memory block 10'. In this case, the gate connection terminal, drain / source connection terminal 211, and substrate 81 connection terminal of the memory block 10' can all fall on the top of the memory block 10', reducing the process difficulty.

[0202] Combination Figure 3 The orthographic projection of the drain / source connection terminal 211 onto the memory array 1 covers the connection improvement layer 232 to ensure sufficient contact between the drain / source connection terminal 211 and the corresponding connection improvement layer 232, thereby ensuring an effective electrical connection between the two. The drain / source connection terminal 211 is made of metal.

[0203] As described above, the corresponding connectivity improvement layer 232 can be formed simultaneously on each semiconductor interconnect layer 231 using the same process; and the corresponding drain / source connection terminal 211 can be formed simultaneously on each connectivity improvement layer 232 using the same process, thereby improving fabrication efficiency. Of course, the connectivity improvement layer 232 and drain / source connection terminal 211 corresponding to each semiconductor interconnect layer 231 can also be formed separately using multiple processes, and this application does not limit this.

[0204] For the second implementation method, see [link / reference] Figures 29 to 30 This is a structural diagram corresponding to another specific implementation process of step S524; step S524 specifically includes:

[0205] Step j1: Deposit an insulating layer 24 on the sidewalls and bottomwalls of the lead-out hole 22.

[0206] Step j2: Remove at least a portion of the insulating isolation layer 24 on the bottom wall of the lead-out hole 22 to expose the drain / source semiconductor strips 11 / 13 of the corresponding layer in the row of semiconductor strip structures 1b corresponding to the lead-out hole 22.

[0207] The specific implementation methods of steps j1 and j2 are similar to those of steps k1 and k2 described above.

[0208] Step j3: Form a connection improvement layer 232 in the lead-out hole 22.

[0209] like Figure 29 As shown, a connection improvement layer 232 is formed on the bottom wall of the lead-out hole 22 and contacts the corresponding drain / source semiconductor strip 11 / 13 to improve the contact resistance between the drain / source lead-out structure 23 and the drain / source semiconductor strip 11 / 13. The connection improvement layer 232 includes a metal silicide connection improvement layer 232.

[0210] Step j4: Form a metal connection layer 233 extending along the height direction Z on the connection improvement layer 232.

[0211] like Figure 30 As shown, metal material can be filled into the lead-out hole 22 to form a metal connection layer 233. The metal connection layer 233 can be a tungsten layer; the dimension of the metal connection layer 233 along the height direction Z is much larger than the dimension of the connection improvement layer 232 along the height direction Z.

[0212] Step j5: Form a drain / source connection terminal 211 on the side surface of the metal connection layer 233 opposite to the connection improvement layer 232.

[0213] Combination Figure 10 The specific implementation process of step j5 is the same as or similar to that of step k5. The metal connection layer 233 and the drain / source connection terminal 211 can be made of the same metal.

[0214] In some implementations, if the metal material filled in step j4 overflows from the lead-out hole 22 during execution, the metal material outside the lead-out hole 22 can be removed by CMP grinding; then step j5 is executed. Of course, the metal material outside the lead-out hole 22 can also be left unremoved, and step j5 can be executed directly; in this case, it can be understood that the metal material outside the lead-out hole 22 serves as part of the corresponding drain / source connection terminal 211, and the metal material inside the lead-out hole 22 serves as the metal connection layer 233.

[0215] like Figure 10As shown, at this time, the drain / source connection terminals 211 all fall on the side surface of the memory array 1 facing away from the substrate 81, that is, on the top of the memory block 10', and are connected to the metal interconnect layer 233 in the lead-out hole 22. In this case, the gate connection terminal, drain / source connection terminal 211, and substrate 81 connection terminal of the memory block 10' can all fall on the top of the memory block 10', reducing the process difficulty.

[0216] The process method for manufacturing a memory block provided in this embodiment involves setting multiple drain / source connection units 21 in at least one drain / source lead-out region of a semiconductor substrate. These multiple drain / source connection units 21 are spaced apart along the row direction X and column direction Y. In the drain / source lead-out region, drain / source connection terminals 211 (CT) in several drain / source connection units 21 in the same row connect to drain / source semiconductor strips 11 / 13 in the same layer of a multi-column semiconductor strip structure 1b. Drain / source connection terminals 211 in several drain / source connection units 21 in the same column connect to multiple drain / source semiconductor strips 11 / 13 in different layers of a corresponding semiconductor strip structure 1b. That is, in each drain / source connection unit 21 in the same drain / source lead-out region... The drain / source connection terminal 211 is connected to a layer of drain / source semiconductor strip 11 / 13 in the corresponding column semiconductor strip structure 1b. Compared with the drain / source connection terminal 211 in each drain / source connection terminal unit 21 being connected to multiple layers of drain / source semiconductor strip 11 / 13 in the corresponding column semiconductor strip structure 1b, it can avoid bridging between two adjacent drain / source connection terminals 211 in the same drain / source connection terminal unit 21 along the column direction Y, which would lead to a short circuit. At the same time, by extending each drain / source connection terminal 211 to the side of the memory array 1 away from the substrate 81, that is, the drain / source connection terminals 211 all fall on the top of the memory block 10', the fabrication process of the memory block 10' can be reduced. The memory block 10' has a high storage density.

[0217] The above are merely embodiments of this application and do not limit the scope of this patent application. Any equivalent structural or procedural changes made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A memory block, characterized by The application relates to a memory block, comprising: a substrate; a memory array arranged on the substrate and comprising a plurality of memory cells arranged in a three-dimensional array, wherein the memory array comprises a plurality of memory subarray layers stacked in a height direction, each of the memory subarray layers comprising a drain semiconductor layer, a channel semiconductor layer and a source semiconductor layer stacked in the height direction; the drain semiconductor layer, the channel semiconductor layer and the source semiconductor layer in each of the memory subarray layers respectively comprise a plurality of drain semiconductor strips, channel semiconductor strips and source semiconductor strips arranged in a row direction, each of the drain semiconductor strips, the channel semiconductor strips and the source semiconductor strips extending in a column direction; a column of the drain semiconductor strips, the channel semiconductor strips and the source semiconductor strips in a plurality of the memory subarray layers define a column of semiconductor strip-shaped structures; at least one drain / source lead-out region, wherein the drain / source lead-out region is provided with a plurality of drain / source connection end units, the plurality of drain / source connection end units are arranged in the row direction and the column direction respectively; wherein the drain / source connection end in each of the drain / source connection end units is connected to a drain / source semiconductor strip in a corresponding column of the semiconductor strip-shaped structures.

2. The memory block of claim 1, wherein in the drain / source lead-out region, the drain / source connection end in a plurality of the drain / source connection end units in the same row is connected to a plurality of the drain / source semiconductor strips in the same layer of the semiconductor strip-shaped structures in a plurality of columns, and the drain / source connection end in a plurality of the drain / source connection end units in the same column is connected to a plurality of the drain / source semiconductor strips in different layers of the corresponding semiconductor strip-shaped structures in a column.

3. The memory block of claim 1, wherein each of the drain / source connection end units comprises a first drain / source connection end and a second drain / source connection end arranged in the row direction; the first drain / source connection end and the second drain / source connection end are respectively connected to the drain / source semiconductor strips in the same layer of two columns of the semiconductor strip-shaped structures adjacent to each other.

4. The memory block of claim 3, wherein in the drain / source lead-out region, each column of the semiconductor strip-shaped structures other than edge columns corresponds to two columns of the drain / source connection end units; wherein the second drain / source connection end in one column of the drain / source connection end units is connected to the drain / source semiconductor strips in odd layers of the semiconductor strip-shaped structures other than the edge columns, and the first drain / source connection end in the other column of the drain / source connection end units is connected to the drain / source semiconductor strips in even layers of the semiconductor strip-shaped structures other than the edge columns.

5. The memory block of claim 4, wherein the two columns of the drain / source connection end units corresponding to each column of the semiconductor strip-shaped structures other than the edge columns are staggered with each other.

6. The memory block of claim 3, wherein The first drain / source connection end and the second drain / source connection end in each of the drain / source connection end units share a same drain / source isolation hole; wherein the drain / source isolation hole is used to remove a part of a channel semiconductor strip in two adjacent columns of the semiconductor strip structures close to the drain / source isolation hole; and the drain / source isolation hole and a removed region of the channel semiconductor strip are filled with a first insulating material; Two adjacent drain / source semiconductor strips of different layers in each column of the semiconductor strip structures in a region where each of the drain / source connection end units is located are isolated from each other by the first insulating material.

7. The memory block of claim 6, wherein, In the region where each of the drain / source connection end units is located, two sides of the drain / source isolation hole are respectively provided with lead-out holes, and each of the lead-out holes respectively exposes one drain / source semiconductor strip in one column of the semiconductor strip structures; wherein the same row of the drain / source connection end units correspond to the same row of the lead-out holes which respectively expose the drain / source semiconductor strips of the same layer in multiple columns of the semiconductor strip structures; the same column of the drain / source connection end units correspond to the same column of the lead-out holes which respectively expose the drain / source semiconductor strips of different layers in the same column of the semiconductor strip structures.

8. The memory block of claim 7, wherein, the lead-out holes are provided with drain / source lead-out structures, and the drain / source connection end connects the drain / source semiconductor strip in the semiconductor strip structure through the drain / source lead-out structure.

9. The memory block of claim 7, wherein, a part of a side wall and a bottom wall of the lead-out hole is covered with an insulating isolation layer to expose only one corresponding drain / source semiconductor strip in the semiconductor strip structure.

10. The memory block of claim 8, wherein, the drain / source lead-out structure comprises a semiconductor connection layer and a connection improvement layer extending along the height direction; wherein the semiconductor connection layer is in contact with the corresponding exposed drain / source semiconductor strip, and the connection improvement layer is arranged on the semiconductor connection layer and in contact with the corresponding drain / source connection end.

11. The memory block of claim 10, wherein, the semiconductor connection layer comprises a polysilicon connection layer, and the connection improvement layer comprises a metal silicide connection improvement layer.

12. The memory block of claim 8, wherein, the drain / source lead-out structure comprises a connection improvement layer and a metal connection layer extending along the height direction; wherein the connection improvement layer is in contact with the corresponding exposed drain / source semiconductor strip, and the metal connection layer is arranged on the connection improvement layer and in contact with the corresponding drain / source connection end.

13. The memory block of claim 12, wherein, the connection improvement layer comprises a metal silicide connection improvement layer; and / or the metal connection layer is made of the same metal as the drain / source connection end.

14. The memory block of claim 1, wherein, The drain / source lead-out area includes a drain / source high lead-out sub-area and a drain / source low lead-out sub-area, wherein the drain / source connection end in the drain / source high lead-out sub-area is used to connect the drain region / source region semiconductor strip in the high region of the semiconductor strip structure; the drain / source connection end in the drain / source low lead-out sub-area is used to connect the drain region / source region semiconductor strip in the low region of the semiconductor strip structure; The drain / source connection end corresponding to the drain region / source region semiconductor strip in each layer of the high region is formed in the same process as the drain / source connection end corresponding to the drain region / source region semiconductor strip matched with the drain region / source region semiconductor strip in the same layer of the low region.

15. The memory block of claim 1, wherein: The memory block includes a plurality of drain / source lead-out areas, and the plurality of drain / source lead-out areas are arranged at intervals in the column direction.

16. A process method of a memory block, comprising: providing a semiconductor substrate, wherein the semiconductor substrate includes a substrate and a plurality of memory sub-array layers arranged on the substrate and stacked in a height direction, each of the memory sub-array layers includes a drain region semiconductor layer, a channel semiconductor layer and a source region semiconductor layer stacked in the height direction, each of the drain region semiconductor layer, the channel semiconductor layer and the source region semiconductor layer in each of the memory sub-array layers includes a plurality of drain region semiconductor strips, channel semiconductor strips and source region semiconductor strips distributed in a row direction, each of the drain region semiconductor strips, the channel semiconductor strips and the source region semiconductor strips extends in a column direction, and a column of the drain region semiconductor strips, the channel semiconductor strips and the source region semiconductor strips in a plurality of the memory sub-array layers defines a column of semiconductor strip structures; in at least one drain / source lead-out area of the semiconductor substrate, a plurality of drain / source connection end units are arranged, and the plurality of drain / source connection end units are arranged at intervals in the row direction and the column direction, respectively, wherein a drain / source connection end in each of the drain / source connection end units is connected to a layer of drain region / source region semiconductor strips in a corresponding column of the semiconductor strip structures.

17. The process method of claim 16, wherein: in the drain / source lead-out area, a drain / source connection end in each of a plurality of the drain / source connection end units in a same row is connected to a layer of drain region / source region semiconductor strips in a plurality of corresponding columns of the semiconductor strip structures, and a drain / source connection end in each of a plurality of the drain / source connection end units in a same column is connected to a plurality of layers of the drain region / source region semiconductor strips in a corresponding column of the semiconductor strip structures.

18. The process of claim 16, wherein, The step of arranging a plurality of drain / source connection end units in at least one drain / source lead-out area of the semiconductor substrate includes: arranging a plurality of drain / source isolation holes in the drain / source lead-out area; removing a portion of the channel semiconductor strips in two adjacent columns of the semiconductor strip structures close to the drain / source lead-out area through the drain / source isolation holes, and filling a first insulating material in the drain / source isolation holes and the removed region of the channel semiconductor strips; and A plurality of lead-out holes with a preset depth are formed on both sides of the drain / source isolation hole, each of the lead-out holes corresponding to a layer of the drain / source semiconductor strips in each column of the semiconductor strip structure; A drain / source lead-out structure is formed in the lead-out hole, and the drain / source connection end is formed on the drain / source lead-out structure.

19. The process method of claim 18, wherein, The step of forming the plurality of lead-out holes with a preset depth on both sides of the drain / source isolation hole comprises: a first removal operation is performed to form a plurality of first lead-out holes on both sides of the drain / source isolation hole, each of the first lead-out holes exposing a first layer of the drain / source semiconductor strips in each column of the semiconductor strip structure; a second removal operation is performed to form a plurality of second lead-out holes on both sides of the drain / source isolation hole, each of the second lead-out holes exposing a second layer of the drain / source semiconductor strips in each column of the semiconductor strip structure; and the process is repeated until a last layer of the drain / source semiconductor strips in each column of the semiconductor strip structure is exposed, wherein a and b are natural numbers greater than or equal to 1 and less than or equal to the number of layers of the storage subarray.

20. The process method of claim 19, wherein, The step of forming the plurality of lead-out holes with a preset depth on both sides of the drain / source isolation hole comprises: a plurality of lead-out holes with a corresponding depth are formed on both sides of each row of the drain / source isolation hole, wherein a mth lead-out hole formed on both sides of an mth row of the drain / source isolation hole exposes an mth layer of the drain / source semiconductor strips in each column of the semiconductor strip structure, and m is a natural number greater than or equal to 1 and less than or equal to the number of layers of the storage subarray.

21. The process method of claim 20, wherein, The step of forming the plurality of lead-out holes with a corresponding depth on both sides of each row of the drain / source isolation hole comprises: a first lead-out hole is formed on both sides of a first row of the drain / source isolation hole, each of the first lead-out holes exposing a first layer of the drain / source semiconductor strips in each column of the semiconductor strip structure; a second lead-out hole is formed on both sides of a second row of the drain / source isolation hole, each of the second lead-out holes exposing a second layer of the drain / source semiconductor strips in each column of the semiconductor strip structure; and the process is repeated until a last layer of the drain / source semiconductor strips in each column of the semiconductor strip structure is exposed.

22. The process method of claim 18, wherein, The step of forming the plurality of lead-out holes with a preset depth on both sides of the drain / source isolation hole comprises: A plurality of drain / source isolation holes are formed in the semiconductor substrate, each of the drain / source isolation holes is formed to expose a plurality of semiconductor strips of a drain region / source region in a corresponding column of semiconductor strip structures, and each of the drain / source isolation holes is formed to have a preset depth.

23. The method of claim 22, wherein: the step of forming the plurality of drain / source isolation holes in the semiconductor substrate, each of the drain / source isolation holes being formed to expose a plurality of semiconductor strips of a drain region / source region in a corresponding column of semiconductor strip structures, and each of the drain / source isolation holes being formed to have a preset depth, comprises: forming a first drain / source isolation hole in each of the drain / source isolation holes by a first removing operation, wherein the first drain / source isolation hole exposes a first layer of the semiconductor strips of the drain region / source region in each column of the semiconductor strip structures; performing a second removing operation on the first drain / source isolation hole to form a second drain / source isolation hole, wherein the second drain / source isolation hole exposes a second layer of the semiconductor strips of the drain region / source region in each column of the semiconductor strip structures; performing a third removing operation on the second drain / source isolation hole to form a third drain / source isolation hole, wherein the third drain / source isolation hole exposes a third layer of the semiconductor strips of the drain region / source region in each column of the semiconductor strip structures; and 24. The method of claim 22, wherein: the step of forming the plurality of drain / source isolation holes in the semiconductor substrate, each of the drain / source isolation holes being formed to expose a plurality of semiconductor strips of a drain region / source region in a corresponding column of semiconductor strip structures, and each of the drain / source isolation holes being formed to have a preset depth, comprises: forming a first drain / source isolation hole in each of the drain / source isolation holes by a first removing operation; and forming a (K / 2+1)th drain / source isolation hole in each of the remaining drain / source isolation holes by a second removing operation, wherein each of the first drain / source isolation hole exposes a first layer of the semiconductor strips of the drain region / source region in a corresponding column of the semiconductor strip structures, each of the (K / 2+1)th drain / source isolation hole exposes a (K / 2+1)th layer of the semiconductor strips of the drain region / source region in a corresponding column of the semiconductor strip structures, and K is a total number of layers of the semiconductor strips of the drain region / source region in a column of the semiconductor strip structures; performing a third removing operation on each of the first drain / source isolation hole and the (K / 2+1)th drain / source isolation hole to form a second drain / source isolation hole and a (K / 2+2)th drain / source isolation hole, respectively; and performing a fourth removing operation on each of the second drain / source isolation hole and the (K / 2+2)th drain / source isolation hole to form a third drain / source isolation hole and a (K / 2+3)th drain / source isolation hole, respectively. In addition to the lead-out holes with the preset depths of the second depth and the (K / 2+2)th depth, fourth removing operations are performed on the other second lead-out holes and the (K / 2+2)th lead-out holes respectively to form third lead-out holes and (K / 2+3)th lead-out holes respectively; and the operations are sequentially repeated until the drain / source semiconductor strips of the last layer in each column of the semiconductor strip structure are exposed.

25. The process of claim 18, wherein, the step of forming the drain / source lead-out structure in the lead-out hole and forming the drain / source connecting terminal on the drain / source lead-out structure comprises: depositing an insulating isolation layer on the sidewall and the bottom wall of the lead-out hole; removing at least part of the insulating isolation layer on the bottom wall of the lead-out hole to expose the drain / source semiconductor strips of the corresponding layer in the column of semiconductor strip structure corresponding to the lead-out hole; forming a semiconductor connecting layer extending in the height direction in the lead-out hole with the insulating isolation layer deposited on the sidewall; forming a connecting improvement layer on the semiconductor connecting layer; forming the drain / source connecting terminal on the side of the connecting improvement layer away from the semiconductor connecting layer.

26. The process of claim 25, wherein, the semiconductor connecting layer comprises a polysilicon connecting layer, and the connecting improvement layer comprises a metal silicide connecting improvement layer.

27. The process of claim 18, wherein, the step of forming the drain / source lead-out structure in the lead-out hole and forming the drain / source connecting terminal on the drain / source lead-out structure comprises: depositing an insulating isolation layer on the sidewall and the bottom wall of the lead-out hole; removing at least part of the insulating isolation layer on the bottom wall of the lead-out hole to expose the drain / source semiconductor strips of the corresponding layer in the column of semiconductor strip structure corresponding to the lead-out hole; forming a connecting improvement layer in the lead-out hole with the insulating isolation layer deposited on the sidewall; forming a metal connecting layer extending in the height direction on the connecting improvement layer; forming the drain / source connecting terminal on the side surface of the metal connecting layer away from the connecting improvement layer.

28. The process of claim 27, wherein, the connecting improvement layer comprises a metal silicide connecting improvement layer; and / or the metal connecting layer and the drain / source connecting terminal are made of the same metal.

29. The process of any one of claims 18-28, wherein, the step of disposing a plurality of drain / source connecting terminal units in at least one drain / source lead-out region of the semiconductor substrate comprises: disposing a plurality of drain / source connecting terminal units in each of the plurality of drain / source lead-out regions of the semiconductor substrate respectively.

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