Semiconductor device

Abstract

A semiconductor device includes a first gate structure in a cell region of a substrate, where the substrate includes a peripheral circuit region; a bit line structure on the cell region of the substrate; a cell capacitor structure on the bit line structure; a decoupling capacitor structure on the peripheral circuit region of the substrate; and a second gate structure on the decoupling capacitor structure.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0116109 filed in the Korean Intellectual Property Office on September 1, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Example embodiments of the present disclosure relate to a semiconductor device. More particularly, example embodiments of the present disclosure relate to a DRAM device. Background Art

[0004] In a DRAM device, a cell capacitor may be formed in a cell region, and a decoupling capacitor and a peripheral circuit transistor may be formed in a peripheral circuit region. Since DRAM is highly integrated, the space for forming the decoupling capacitor and the peripheral circuit transistor may be insufficient. Summary of the invention

[0005] Example embodiments provide a semiconductor device having improved electrical characteristics.

[0006] According to an example embodiment of the present disclosure, a semiconductor device is provided. The semiconductor device may include a first gate structure located in a cell region of a substrate, wherein the substrate includes a peripheral circuit region, a bit line structure located on the cell region of the substrate, a cell capacitor structure located on the bit line structure, a decoupling capacitor structure located on the peripheral circuit region of the substrate, and a second gate structure located on the decoupling capacitor structure.

[0007] According to an example embodiment of the present disclosure, a semiconductor device is provided. The semiconductor device may include: a first gate structure located in a cell region of a first substrate, wherein the first substrate includes a peripheral circuit region; a bit line structure located on the cell region of the first substrate; a cell capacitor structure located on the bit line structure; a decoupling capacitor structure located at least partially in the peripheral circuit region of the first substrate; and a second gate structure located on the peripheral circuit region of the first substrate, wherein the second gate structure is a first distance from an upper surface of the first substrate, wherein the cell capacitor structure is a second distance from an upper surface of the first substrate, and wherein the first distance is greater than the second distance.

[0008] According to an example embodiment of the present disclosure, a semiconductor device is provided. The semiconductor device may include: a first substrate, which includes a first cell region and a first peripheral circuit region; a first gate structure, which is located in the first cell region of the first substrate; a bit line structure, which is located on the first cell region of the first substrate; a cell capacitor structure, which is located on the bit line structure; a decoupling capacitor structure, which is located on the first peripheral circuit region of the first substrate; a second substrate, which is located on the cell capacitor structure and the decoupling capacitor structure, wherein the second substrate includes a second cell region and a second peripheral circuit region corresponding to the first cell region of the first substrate and the first peripheral circuit region of the first substrate, respectively; a second gate structure, which is located on the second cell region of the second substrate; a third gate structure, which is located on the second peripheral circuit region of the second substrate; and a through-piece, which extends into the second substrate, wherein some of the through-pieces are electrically connected to the cell capacitor structure and the decoupling capacitor structure.

[0009] A semiconductor device according to example embodiments may have sufficient space for a peripheral circuit transistor and a decoupling capacitor, and thus may have enhanced electrical characteristics. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a cross-sectional view illustrating a semiconductor device according to example embodiments.

[0011] Figure 2 , Figure 3 , Figure 4 , Figure 5 , Figure 6 , Figure 7 and Figure 8 is a cross-sectional view illustrating a semiconductor device according to example embodiments.

[0012] Fig. 9 , Fig.10 , Fig.11 , Fig.12 , Fig.13 and Fig.14 is a cross-sectional view illustrating a semiconductor device according to example embodiments.

[0013] Fig.15 , Fig.16 , Fig.17 , Fig.18 , Fig.19 , Fig. 20 , Fig.21 and Fig. 22 is a cross-sectional view illustrating a semiconductor device according to example embodiments.

[0014] Fig.23 , Fig.24 , Fig.25 , Fig.26 , Fig. 27 , Fig.28 , Fig.29 , Fig.30 , Fig.31 , Fig.32 , Fig.33 , Fig.34 , Fig.35 , Fig.36 , Fig.37 , Fig.38 , Fig.39 , Fig.40 , Fig.41 , Fig.42 , Fig.43 , Fig.44 , Fig.45 , Fig.46 , Fig.47 , Fig.48 , Fig.49 , Fig.50 , Fig.51 , Fig.52 , Fig.53 , Fig.54 , Fig.55 , Fig.56 , Fig.57 , Fig.58 , Fig.59 , Fig.60 , Fig.61 , Fig.62 , Fig.63 , Fig.64 and Fig.65 are plan views and cross-sectional views illustrating a method of manufacturing a semiconductor device according to example embodiments. DETAILED DESCRIPTION

[0015] The above and other aspects and features of the decoupling capacitor structure and its formation method according to the example embodiment, and the semiconductor device including the decoupling capacitor structure and its manufacturing method will become easy to understand from the following detailed description with reference to the accompanying drawings. It will be understood that although the terms "first", "second" and / or "third" can be used to describe various elements, components, regions, layers and / or parts in this article, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, first component, first area, first layer or first part discussed below may be referred to as the second element, second component, second area, second layer or second part or the third element, third component, third area, third layer or third part.

[0016] In order to make the present disclosure clear, parts not related to the description will be omitted, and the same elements or equivalents are represented by the same reference numerals throughout the specification. In addition, since the sizes and thicknesses of the constituent members shown in the drawings are arbitrarily given for better understanding and ease of description, the present disclosure is not limited to the sizes and thicknesses shown. In the drawings, the thicknesses of layers, films, panels, regions, etc. are exaggerated for clarity. In the drawings, the thicknesses of some layers and regions are excessively shown for better understanding and ease of description.

[0017] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements.

[0018] For ease of description, spatially relative terms such as "below," "below," "down," "above," "upper," etc. may be used herein to describe the relationship of one element or feature to another (or more) element or feature shown in the accompanying drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, the elements described as being "below" or "below" other elements or features will be oriented as being "above" the other elements or features. Thus, the term "below" may encompass both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein may be interpreted accordingly.

[0019] In addition, unless explicitly described to the contrary, the word "include" and variations such as "include" or "contain" will be understood to imply that the elements are included but no other elements are excluded. As used herein, the phrase "at least one of A, B, and C" refers to the logic (A OR B OR C) using a non-exclusive logic or (OR), and should not be interpreted as meaning "at least one of A, at least one of B, and at least one of C". As used herein, unless the context clearly indicates otherwise, the singular forms "one", "one", and "the" are also intended to include plural forms. It will also be understood that the terms "include", "include" and / or "contain" specify the presence of stated features, steps, operations, elements, and / or components when used herein, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups thereof. The term "and / or" includes any and all combinations of one or more related listed items. The term "connection" can be used herein to refer to physical connections and / or electrical connections, and can refer to direct or indirect physical connections and / or electrical connections. Components or layers described with reference to “overlapping” in a specific direction may be at least partially blocked by each other when viewed along a line extending in the specific direction or in a plane perpendicular to the specific direction.

[0020] Figure 1 is a cross-sectional view illustrating a semiconductor device according to example embodiments.

[0021] Reference Figure 1 The semiconductor device may include a first substrate 10, a first gate structure 15 in the first substrate 10, a bit line structure 20a on the first substrate 10, a unit capacitor structure 40a, a first decoupling capacitor structure 40b, a second substrate 70, and a third gate structure 80a and a fourth gate structure 80b under the second substrate 70.

[0022] The semiconductor device may also include a second gate structure 20b, a first contact plug 31, a landing pad 32, a conductive pad 35, a first capacitor connection structure to a third capacitor connection structure 51, 52 and 54, a first bonding pattern to a third bonding pattern 61, 62 and 64, a second contact plug to a fourth contact plug 91, 92 and 94, a first wiring to a third wiring 93, 96 and 98, a first insulating interlayer to a third insulating interlayer 30, 50 and 90, and a bonding layer 60.

[0023] Each of the first substrate 10 and the second substrate 70 may include a first region I and a second region II. In example embodiments, the first region I of each of the first substrate 10 and the second substrate 70 may be a cell region in which a memory cell is formed, and the second region II of each of the first substrate 10 and the second substrate 70 may be a peripheral circuit region in which a peripheral circuit pattern for driving the memory cell is formed.

[0024] Hereinafter, in some cases, the first region I and the second region II may be defined not only as being inside each of the first substrate 10 and the second substrate 70, but also as being in a space overlapping with the inside of each of the first substrate 10 and the second substrate 70 in a vertical direction substantially perpendicular to the upper surface of the first substrate 10 or the lower surface of the second substrate 70.

[0025] Each of the first substrate 10 and the second substrate 70 may include a semiconductor material (e.g., silicon, germanium, silicon germanium, etc.) or a II IV group compound semiconductor (e.g., GaP, GaAs, GaSb, etc.). In example embodiments, each of the first substrate 10 and the second substrate 70 may be a silicon on insulator (SOI) substrate or a germanium on insulator (GOI) substrate.

[0026] In example embodiments, the first gate structures 15 may be buried in the first region I of the first substrate 10, and a plurality of the first gate structures 15 may be spaced apart from each other in a horizontal direction substantially parallel to an upper surface of the first substrate 10. Alternatively, the first gate structures 15 may be formed on the first substrate 10. Each of the first gate structures 15 may operate as a word line of the semiconductor device.

[0027] The first gate structure 15 may include a first gate electrode 14 , a first gate insulating pattern 12 on a lower surface and sidewalls of the first gate electrode 14 , and a first gate mask 16 on the first gate insulating pattern 12 and the first gate electrode 14 .

[0028] In example embodiments, a plurality of bit line structures 20a may be spaced apart from each other in a horizontal direction on the first region I of the first substrate 10, and each of the bit line structures 20a may include a conductive structure 21 and an insulating structure 23 sequentially stacked in a vertical direction.

[0029] The second gate structure 20b may be formed on the second region II of the first substrate 10, and may include a second gate insulating pattern 22, a second gate electrode 24, and a second gate mask 26 sequentially stacked in a vertical direction. In example embodiments, the second gate structure 20b may be disposed at substantially the same height as the bit line structure 20a from the upper surface of the first substrate 10. That is, the bit line structure 20a and the second gate structure 20b may extend from the first substrate 10 by substantially the same distance.

[0030] The second gate insulation pattern 22 may include an oxide (e.g., silicon oxide), each of the conductive structure 21 and the second gate electrode 24 may include, for example, doped polysilicon, metal, metal silicon nitride, metal silicide, etc., and each of the insulating structure 23 and the second gate mask 26 may include an insulating nitride (e.g., silicon nitride).

[0031] The first insulating interlayer 30 may be formed on the first substrate 10 , and may cover or overlap the bit line structure 20 a and the second gate structure 20 b .

[0032] The first contact plugs 31 and the landing pads 32 may extend through the first insulating interlayer 30 on the first region I of the first substrate 10, and may be stacked in a vertical direction on the upper surface of the first substrate 10. A plurality of first contact plugs 31 may be spaced apart from each other in a horizontal direction, and a plurality of landing pads 32 may be spaced apart from each other in the horizontal direction.

[0033] The conductive pad 35 may extend through an upper portion of the first insulating interlayer 30 on the second region II of the first substrate 10. In example embodiments, the conductive pad 35 may be disposed at substantially the same height as the landing pad 32 and may include substantially the same material. In example embodiments, a plurality of conductive pads 35 may be spaced apart from each other in a horizontal direction.

[0034] Each of the first contact plug 31 , the landing pad 32 , and the conductive pad 35 may include, for example, doped polysilicon, metal nitride, metal silicide, or the like.

[0035] The unit capacitor structure 40a may be formed on the first insulating interlayer 30 on the first region I of the first substrate 10, and may contact the upper surface of the landing pad 32. The unit capacitor structure 40a may include a first capacitor electrode 41, a first dielectric pattern 43, a second capacitor electrode 45, and a third capacitor electrode 47. In example embodiments, the unit capacitor structure 40a may include a plurality of first capacitor electrodes 41 that are spaced apart from each other in a horizontal direction and respectively contact the upper surface of the landing pad 32. Each of the first capacitor electrodes 41 may have a shape of a column or a hollow cylinder extending in a vertical direction, and the first capacitor electrodes 41 may be arranged in a honeycomb pattern or a lattice pattern in a plan view.

[0036] The first dielectric pattern 43 , the second capacitor electrode 45 , and the third capacitor electrode 47 may be sequentially stacked on a surface of the first capacitor electrode 41 (eg, an upper surface and side surfaces of the first capacitor electrode 41 ) and on an upper surface of the first insulating interlayer 30 .

[0037] In example embodiments, a plurality of unit capacitor structures 40 a may be spaced apart from each other in a horizontal direction on the first region I of the first substrate 10 .

[0038] The first decoupling capacitor structure 40b may be formed on the conductive pad 35 on the second region II of the first substrate 10, and may include a fourth capacitor electrode 42, a second dielectric pattern 44, a fifth capacitor electrode 46, and a sixth capacitor electrode 48. In example embodiments, the first decoupling capacitor structure 40b may include a plurality of fourth capacitor electrodes 42 spaced apart from each other in a horizontal direction on the second region II of the first substrate 10. Each of the fourth capacitor electrodes 42 may have a shape of a column or a hollow cylinder extending in a vertical direction, and the fourth capacitor electrodes 42 may be arranged in a honeycomb pattern or a lattice pattern in a plan view.

[0039] The second dielectric pattern 44 , the fifth capacitor electrode 46 , and the sixth capacitor electrode 48 may be sequentially stacked on a surface of the fourth capacitor electrode 42 and an upper surface of the conductive pad 35 .

[0040] In example embodiments, a plurality of first decoupling capacitor structures 40b may be spaced apart from each other in a horizontal direction on the second region II of the first substrate 10 and may respectively contact the conductive pads 35. The first decoupling capacitor structures 40b may also be referred to as power capacitor structures.

[0041] Each of the first capacitor electrode 41, the second capacitor electrode 45, the fourth capacitor electrode 42, and the fifth capacitor electrode 46 may include a conductive material (e.g., metal, metal nitride, etc.), and each of the first dielectric pattern 43 and the second dielectric pattern 44 may include a high-k dielectric material (such as a metal oxide, e.g., hafnium oxide, zirconium oxide, etc.). Each of the third capacitor electrode 47 and the sixth capacitor electrode 48 may include, for example, doped silicon germanium.

[0042] The first capacitor connection structure 51 may be formed on the unit capacitor structure 40a and may contact the upper surface of the third capacitor electrode 47 to be electrically connected to the third capacitor electrode 47, the second capacitor connection structure 52 may be formed on the first decoupling capacitor structure 40b and may contact the upper surface of the sixth capacitor electrode 48 to be electrically connected to the sixth capacitor electrode 48, and the third capacitor connection structure 54 may contact the upper surface of the conductive pad 35 to be electrically connected to the conductive pad 35.

[0043] In the drawings, each of the first capacitor connection structure 51 and the second capacitor connection structure 52 includes an upper portion having a planar shape and a vertical portion extending in a vertical direction, and the third capacitor connection structure 54 includes a lower portion having a relatively small width and an upper portion having a relatively large width. However, the present disclosure may not be limited thereto.

[0044] The second insulating interlayer 50 may be formed on the first insulating interlayer 30 and may cover the side walls of the unit capacitor structure 40a, the first decoupling capacitor structure 40b, and the first capacitor connection structure to the third capacitor connection structure 51, 52 and 54, or overlap with the side walls of the unit capacitor structure 40a, the first decoupling capacitor structure 40b, and the first capacitor connection structure to the third capacitor connection structure 51, 52 and 54.

[0045] The bonding layer 60 may be formed on the second insulating interlayer 50 and the first to third capacitor connection structures 51, 52, and 54, and the first to third bonding patterns 61, 62, and 64 may extend through the bonding layer 60 to respectively contact the upper surfaces of the first to third capacitor connection structures 51, 52, and 54. The bonding layer 60 may include an insulating material (e.g., silicon carbon nitride (SiCN) or silicon oxide), and the first to third bonding patterns 61, 62, and 64 may include a metal (e.g., copper).

[0046] The third insulating interlayer 90 may be formed on the bonding layer 60 and the first to third bonding patterns 61, 62, and 64, and may cover the side walls of the third gate structure 80a and the fourth gate structure 80b, the second to fourth contact plugs 91, 92, and 94, and the first to third wirings 93, 96, and 98, or overlap with the side walls of the third gate structure 80a and the fourth gate structure 80b, the second to fourth contact plugs 91, 92, and 94, and the first to third wirings 93, 96, and 98.

[0047] The third gate structure 80a may include a third gate insulating pattern 81, a third gate electrode 83, and a third gate mask 85 sequentially stacked in the vertical direction from the lower surface of the first region I of the second substrate 70. The fourth gate structure 80b may include a fourth gate insulating pattern 82, a fourth gate electrode 84, and a fourth gate mask 86 sequentially stacked in the vertical direction from the lower surface of the second region II of the second substrate 70.

[0048] The third gate structure 80a and the first source / drain region adjacent to the third gate structure 80a at the lower portion of the first region I of the second substrate 70 may form a first peripheral circuit transistor, for example, a core transistor. The fourth gate structure 80b and the second source / drain region adjacent to the fourth gate structure 80b at the lower portion of the second region II of the second substrate 70 may form a second peripheral circuit transistor, for example, a peripheral transistor.

[0049] The second contact plug 91 and the first wiring 93 may be sequentially stacked in the vertical direction from the lower surface of the first region I of the second substrate 70 to contact the upper surface of the first bonding pattern 61. The third contact plug 92 and the second wiring 96 may be sequentially stacked in the vertical direction from the lower surface of the second region II of the second substrate 70 to contact the upper surface of the second bonding pattern 62. The fourth contact plug 94 and the third wiring 98 may be sequentially stacked in the vertical direction from the lower surface of the second region II of the second substrate 70 to contact the upper surface of the third bonding pattern 64.

[0050] In example embodiments, the second contact plug 91 may contact the first source / drain region of the first peripheral circuit transistor to be electrically connected to the first source / drain region of the first peripheral circuit transistor, and each of the third contact plug 92 and the fourth contact plug 94 may contact the second source / drain region of the second peripheral circuit transistor to be electrically connected to the second source / drain region of the second peripheral circuit transistor.

[0051] Each of the first gate insulating pattern 12, the third gate insulating pattern 81, and the fourth gate insulating pattern 82 may include an oxide, for example, silicon oxide. Each of the first gate electrode 14, the third gate electrode 83, and the fourth gate electrode 84 may include, for example, a metal, a metal nitride, a metal silicide, etc. Each of the first gate mask 16, the third gate mask 85, and the fourth gate mask 86 may include an insulating nitride, for example, silicon nitride.

[0052] Each of the first capacitor connection structure 51 and the second capacitor connection structure 52, the second to fourth contact plugs 91, 92 and 94, and the first to third wirings 93, 96 and 98 may include, for example, a metal, a metal nitride, a metal silicide, etc., and each of the first to third insulating interlayers 30, 50 and 90 may include an oxide (e.g., silicon oxide), an insulating nitride (e.g., silicon nitride) or a low-k dielectric material.

[0053] The semiconductor device may include a first substrate 10 and a second substrate 70 sequentially stacked in a vertical direction. Transistors, word lines, bit lines, and wiring structures may be disposed on the first substrate 10 and below the second substrate 70 to be electrically connected to the first substrate 10 and the second substrate 70 through the first to third bonding patterns 61, 62, and 64 in the bonding layer 60.

[0054] In example embodiments, the first peripheral circuit transistor and the second peripheral circuit transistor may be respectively disposed under the first region I and the second region II of the second substrate 70. Therefore, when compared to an embodiment in which the first peripheral circuit transistor and the second peripheral circuit transistor are disposed on the second region II of the first substrate 10, sufficient space may be provided on the second region II of the first substrate 10, and additional space may be provided under the second substrate 70.

[0055] Therefore, space for forming, for example, an additional first decoupling capacitor structure 40b may be provided on the second region II of the first substrate 10, and space for forming additional first and second peripheral circuit transistors may be provided under the first and second regions I and II of the second substrate 70, respectively.

[0056] As a result, the semiconductor device can have an additional space for forming, for example, a transistor, a capacitor, etc., so as to have enhanced electrical characteristics.

[0057] Figures 2 to 8 are cross-sectional views showing semiconductor devices according to example embodiments. Figure 1 The semiconductor devices are substantially the same or similar, and thus repeated descriptions are omitted herein.

[0058] Reference Figure 2 , the second gate structure 20 b may not be disposed on the second region II of the first substrate 10 , and the conductive pad 35 under the first decoupling capacitor structure 40 b may contact the upper surface of the second region II of the first substrate 10 .

[0059] Reference Figure 3 Since the first peripheral circuit transistor and the second peripheral circuit transistor are not disposed on the second region II of the first substrate 10 , the additional first decoupling capacitor structure 40 b may be disposed in a space on the second region II of the first substrate 10 .

[0060] Second and third capacitor connecting structures 52 and 54 , second and third bonding patterns 62 and 64 , second and third wirings 96 and 98 , and third and fourth contact plugs 92 and 94 may be additionally formed to be electrically connected to an additional first decoupling capacitor structure 40 b .

[0061] Reference Figure 4 When an additional second substrate 70 is disposed above the first substrate 10, an additional second peripheral circuit transistor including a fourth gate structure 80b may be disposed in a space below the first region I and the second region II of the second substrate 70, specifically, in a space below the second region II of the second substrate 70.

[0062] Reference Figure 5 Since the first peripheral circuit transistor and the second peripheral circuit transistor are not disposed on the second region II of the first substrate 10 , the third peripheral circuit transistor may be additionally disposed in a space on the second region II of the first substrate 10 .

[0063] In example embodiments, the third peripheral circuit transistor may be a transistor of a different type from the first peripheral circuit transistor and the second peripheral circuit transistor. The third peripheral circuit transistor may include a fifth gate structure 29 on the second region II of the first substrate 10 and a third source / drain region at an upper portion of the second region II of the first substrate 10. The fifth gate structure 29 may include a fifth gate insulating pattern 25, a fifth gate electrode 27, and a fifth gate mask 28 sequentially stacked.

[0064] A fifth contact plug 33 and a fourth wiring 34 electrically connected to the third peripheral circuit transistor may be formed in the first insulating interlayer 30 , and a sixth contact plug 56 extending through the second insulating interlayer 50 to contact the third bonding pattern 64 may be formed on the fourth wiring 34 .

[0065] Reference Figure 6 , a second decoupling capacitor structure 40 c may be formed in the first substrate 10 instead of the first decoupling capacitor structure 40 b in the second insulating interlayer 50 .

[0066] The fourth capacitor electrode 42 included in the second decoupling capacitor structure 40c may include a lower portion and a vertical portion, the lower portion may have a planar shape, the vertical portion may extend in a vertical direction on the lower portion and be spaced apart from each other in a horizontal direction. The second dielectric pattern 44, the fifth capacitor electrode 46, and the sixth capacitor electrode 48 may be sequentially stacked on the fourth capacitor electrode 42.

[0067] In example embodiments, the second capacitor connection structure 52 may contact an upper surface of the sixth capacitor electrode 48 , and the third capacitor connection structure 54 may contact an upper surface of the fourth capacitor electrode 42 .

[0068] Reference Figure 7 , a third decoupling capacitor structure 40d may be formed instead of the first decoupling capacitor structure 40b.

[0069] In example embodiments, each of the fourth capacitor electrode 42 and the fifth capacitor electrode 46 included in the third decoupling capacitor structure 40d in the second insulating interlayer 50 may have a planar shape extending in a horizontal direction, and the fourth capacitor electrode 42 and the fifth capacitor electrode 46 may at least partially overlap each other. A portion of the second insulating interlayer 50 between the fourth capacitor electrode 42 and the fifth capacitor electrode 46 may serve as a dielectric pattern. Alternatively, the second dielectric pattern 44 includes a material different from that of the second insulating interlayer 50. That is, a high-k dielectric material may be formed between the fourth capacitor electrode 42 and the fifth capacitor electrode 46.

[0070] Fourth and fifth capacitor connecting structures 58 and 59 that may respectively contact upper surfaces of fourth and fifth capacitor electrodes 42 and 46 and lower surfaces of second and third bonding patterns 62 and 64 may be formed in the second insulating interlayer 50 .

[0071] Figure 8 is a cross-sectional view showing a semiconductor device according to an example embodiment. Except for not including a bonding pattern, the semiconductor device may be Figure 1 The semiconductor devices are substantially the same or similar, and thus repeated descriptions are omitted herein.

[0072] Reference Figure 8 ,and Figure 1 Unlike the semiconductor device shown, the semiconductor device may not include the first to third bonding patterns 61 , 62 , and 64 in the bonding layer 60 , but may include the first to third conductive connection patterns 67 , 68 , and 69 .

[0073] Therefore, the first to third capacitor connection structures 51, 52, and 54 may respectively contact the first to third conductive connection patterns 67, 68, and 69 to be respectively electrically connected to the first to third wirings 93, 96, and 98. Each of the first to third conductive connection patterns 67, 68, and 69 may include a conductive material, for example, a metal, a metal nitride, a metal silicide, or the like.

[0074] Figures 2 to 7 Each of the semiconductor devices shown in 400 may further include first to third conductive connection patterns 67 , 68 , and 69 instead of the first to third bonding patterns 61 , 62 , and 64 .

[0075] Figures 9 to 14 1 is a cross-sectional view showing a semiconductor device according to an example embodiment. In addition to the positions of the structures disposed above or below the first substrate and the second substrate, the semiconductor devices may be Figure 1 or Figure 8 The semiconductor devices are substantially the same or similar, and thus repeated descriptions are omitted herein.

[0076] Reference Fig. 9 ,and Figure 1 Differently, the first substrate 10 , the first insulating interlayer 30 , and the second insulating interlayer 50 may be sequentially stacked downwardly below the bonding layer 60 in a vertical direction.

[0077] The first insulating pattern 11 may extend through the first substrate 10, and the first capacitor connection structure 51 and the second capacitor connection structure 52 may be electrically connected to the first bonding pattern 61 and the second bonding pattern 62 respectively through the first through-piece 95 and the second through-piece 97, and the first through-piece 95 and the second through-piece 97 may extend through the first insulating pattern 11 and the first insulating interlayer 30 and the second insulating interlayer 50.

[0078] The conductive pad 35 may be electrically connected to the third bonding pattern 64 through the third via 99 instead of the third capacitor connection structure 54 , wherein the third via 99 may extend through the first insulating pattern 11 and the first insulating interlayer 30 .

[0079] Reference Fig.10 ,exist Fig. 9 In the semiconductor device of FIG. 1 , the first to third conductive connection patterns 67 , 68 , and 69 instead of the first to third bonding patterns 61 , 62 , and 64 may be formed in the bonding layer 60 .

[0080] Therefore, the first to third vias 95 , 97 , and 99 may contact the first to third conductive connection patterns 67 , 68 , and 69 , respectively, to be electrically connected to the first to third wirings 93 , 96 , and 98 , respectively.

[0081] Reference Fig.11 ,and Figure 1 Unlike the semiconductor device of FIG. 1 , the second substrate 70 and the third insulating interlayer 90 may be sequentially stacked on the bonding layer 60 and the first to third bonding patterns 61 , 62 , and 64 in a vertical direction upward (eg, away from the first substrate 10 ).

[0082] Therefore, the first peripheral circuit transistor including the third gate structure 80 a and the fourth gate structure 80 b , respectively, may be formed on the first region I and the second region II of the second substrate 70 , respectively.

[0083] The second insulating pattern 71 may extend through the second substrate 70, and first to third vias 95, 97, and 99 may be formed instead of the second to fourth contact plugs 91, 92, and 94, which may extend through the second insulating pattern 71 and a lower portion of the third insulating interlayer 90. Therefore, the first to third capacitor connection structures 51, 52, and 54 may be electrically connected to the first to third wirings 93, 96, and 98 through the first to third bonding patterns 61, 62, and 64 and the first to third vias 95, 97, and 99, respectively.

[0084] In example embodiments, each of the first to third through-vias 95, 97, and 99 may extend through a corresponding one of the first and second source / drain regions included in the first and second peripheral circuit transistors to be electrically connected to the corresponding one of the first and second source / drain regions.

[0085] Reference Fig.12 ,exist Fig.11 In the semiconductor device of the present invention, the first to third conductive connection patterns 67, 68, and 69 instead of the first to third bonding patterns 61, 62, and 64 may be formed in the bonding layer 60. Therefore, the first to third vias 95, 97, and 99 may contact the first to third conductive connection patterns 67, 68, and 69, respectively, to be electrically connected to the first to third capacitor connection structures 51, 52, and 54, respectively.

[0086] Reference Fig.13 ,and Figure 1 Unlike the semiconductor device of FIG. 1 , the second insulating interlayer 50 , the first insulating interlayer 30 , the first substrate 10 , the bonding layer 60 , the second substrate 70 , and the third insulating interlayer 90 may be sequentially stacked upward in a vertical direction.

[0087] Therefore, the first peripheral circuit transistor including the third gate structure 80 a and the fourth gate structure 80 b , respectively, may be formed on the first region I and the second region II of the second substrate 70 , respectively.

[0088] The first insulating pattern 11 and the second insulating pattern 71 may extend through the first substrate 10 and the second substrate 70, respectively. The first through-pieces 95a and 95b may contact the first capacitor connection structure 51, the first bonding pattern 61, and the first wiring 93 to be electrically connected to the first capacitor connection structure 51, the first bonding pattern 61, and the first wiring 93. The second through-pieces 97a and 97b may contact the second capacitor connection structure 52, the second bonding pattern 62, and the second wiring 96 to be electrically connected to the second capacitor connection structure 52, the second bonding pattern 62, and the second wiring 96, and the third through-pieces 99a and 99b may contact the conductive pad 35, the third bonding pattern 64, and the third wiring 98 to be electrically connected to the conductive pad 35, the third bonding pattern 64, and the third wiring 98.

[0089] Reference Fig.14 ,exist Fig.13 In the semiconductor device of FIG. 1 , the first to third conductive connection patterns 67 , 68 , and 69 instead of the first to third bonding patterns 61 , 62 , and 64 may be formed in the bonding layer 60 .

[0090] The semiconductor device may have a periphery-on-cell (POC) structure including a second substrate 70, and first and second peripheral circuit transistors having third and fourth gate structures 80a and 80b, respectively, over a first substrate 10, a cell capacitor structure 40a, and a first decoupling capacitor structure 40b. However, the present disclosure may not be limited thereto, and the semiconductor device may have a cell-on-periphery (COP) structure as described in further detail below.

[0091] Figures 15 to 22 1 is a cross-sectional view showing a semiconductor device according to an example embodiment. Except for the positions of the first substrate and the second substrate and the structures disposed on or under the first substrate and the second substrate, these semiconductor devices may be Figure 1 or Figure 8 The semiconductor devices are substantially the same or similar, and thus repeated descriptions are omitted herein.

[0092] Reference Fig.15 , Figure 1 The orientation of the semiconductor device can be flipped so that the relative positions of the first substrate 10 and the second substrate 70 can be changed, and the third insulating interlayer 90, the bonding layer 60, the second insulating interlayer 50, the first insulating interlayer 30 and the first substrate 10 can be stacked sequentially upward in the vertical direction.

[0093] Therefore, the first and second peripheral circuit transistors may be disposed on the first and second regions I and II of the second substrate 70 , respectively, and the unit capacitor structure 40 a and the first decoupling capacitor structure 40 b may be disposed under the first and second regions I and II of the first substrate 10 , respectively.

[0094] Reference Fig.16 ,exist Fig.15 In the semiconductor device of FIG. 1 , the first to third conductive connection patterns 67 , 68 , and 69 instead of the first to third bonding patterns 61 , 62 , and 64 may be formed in the bonding layer 60 .

[0095] Reference Fig.17 ,and Fig.15 Unlike the embodiment of the present invention, the second substrate 70 and the third insulating interlayer 90 may be sequentially stacked below the bonding layer 60 in a vertical direction downward (eg, away from the first substrate 10 ).

[0096] The second insulating pattern 71 may extend through the second substrate 70, and each of the first to third vias 95, 97, and 99 may extend through the second insulating pattern 71 and an upper portion of the third insulating interlayer 90. The first to third capacitor connecting structures 51, 52, and 54 may be electrically connected to the first to third wirings 93, 96, and 98, respectively, through the first to third bonding patterns 61, 62, and 64 and the first to third vias 95, 97, and 99, respectively.

[0097] Reference Fig.18 ,exist Fig.17 In the semiconductor device of the present invention, the first to third conductive connection patterns 67, 68, and 69 instead of the first to third bonding patterns 61, 62, and 64 may be formed in the bonding layer 60. Therefore, the first to third capacitor connection structures 51, 52, and 54 may contact the first to third conductive connection patterns 67, 68, and 69, respectively, to be electrically connected to the first to third through-holes 95, 97, and 99 and the first to third wirings 93, 96, and 98, respectively.

[0098] Reference Fig.19 ,and Fig.15 Unlike the embodiment of the present invention, the first substrate 10 , the first insulating interlayer 30 , and the second insulating interlayer 50 may be sequentially stacked on the bonding layer 60 in a vertical direction upward, and the first insulating pattern 11 may extend through the first substrate 10 .

[0099] The first to third through-pieces 95, 97 and 99 can extend through the lower portions of the first insulating pattern 11, the first insulating interlayer 30 and the second insulating interlayer 50 to contact the first to third capacitor connecting structures 51, 52 and 54, respectively, and can be electrically connected to the first to third capacitor connecting structures 51, 52 and 54.

[0100] Reference Fig. 20 ,exist Fig.19 In the semiconductor device of FIG. 1 , the first to third conductive connection patterns 67 , 68 , and 69 instead of the first to third bonding patterns 61 , 62 , and 64 may be formed in the bonding layer 60 .

[0101] Reference Fig.21 ,and Fig.15 Unlike the embodiment of the present invention, the second substrate 70 and the third insulating interlayer 90 may be sequentially stacked downwardly below the bonding layer 60 in a vertical direction.

[0102] Therefore, the first peripheral circuit transistor and the second peripheral circuit transistor including the third gate structure 80 a and the fourth gate structure 80 b , respectively, may be formed under the first region I and the second region II of the second substrate 70 , respectively.

[0103] The first insulating pattern 11 and the second insulating pattern 71 may extend through the first substrate 10 and the second substrate 70, respectively. The first through-pieces 95a and 95b may contact the first capacitor connection structure 51, the first bonding pattern 61, and the first wiring 93 to be electrically connected to the first capacitor connection structure 51, the first bonding pattern 61, and the first wiring 93. The second through-pieces 97a and 97b may contact the second capacitor connection structure 52, the second bonding pattern 62, and the second wiring 96 to be electrically connected to the second capacitor connection structure 52, the second bonding pattern 62, and the second wiring 96. The third through-pieces 99a and 99b may contact the conductive pad 35, the third bonding pattern 64, and the third wiring 98 to be electrically connected to the conductive pad 35, the third bonding pattern 64, and the third wiring 98.

[0104] Reference Fig. 22 ,exist Fig.21 In the semiconductor device of FIG. 1 , the first to third conductive connection patterns 67 , 68 , and 69 instead of the first to third bonding patterns 61 , 62 , and 64 may be formed in the bonding layer 60 .

[0105] Figures 9 to 22 Each of the semiconductor devices shown in the figure can be applied to Figures 2 to 7 semiconductor devices and Figure 1 and Figure 8 semiconductor device.

[0106] Figure 23 to Figure 651 is a plan view and a cross-sectional view showing a method of manufacturing a semiconductor device according to an example embodiment. Specifically, Fig.23 , Fig.26 , Fig.31 , Fig.35 , Fig.42 , Fig.46 , Fig.51 and Fig.57 It is a floor plan. Fig.24 , Fig. 27 , Fig.29 , Fig.32 , Fig.34 , Fig.36 , Fig.38 , Fig.40 , Fig.43 , Figure 47 to Figure 48 , Fig.52 , Fig.58 , Fig.61 and Fig.63 It is a cross-sectional view taken along the line AA' of the corresponding plan view. Fig.25 , Fig.28 , Fig.30 , Fig.33 , Fig.37 , Fig.39 , Fig.41 , Figure 44 to Figure 45 , Fig.49 , Fig.53 , Fig.55 , Fig.59 and Fig.64 including cross-sectional views taken along lines BB' and CC' of the corresponding plan views, and Fig.50 , Fig.54 , Fig.56 , Fig.60 , Fig.62 and Fig.65 It is a cross-sectional view taken along the line DD' of the corresponding plan view.

[0107] exist Fig.57 In order to avoid complexity of the drawings, some structures, such as the sixth wiring to the eighth wiring 741, 742 and 744, are not shown.

[0108] The method may include implementing Figure 1 A more specific process of the present disclosure of a semiconductor device, and Figures 2 to 22 The semiconductor device of the present disclosure may also be implemented by processes substantially the same as or similar to these processes.

[0109] Hereinafter, in the specification (and not necessarily in the claims), two directions substantially parallel to the upper surface of the first substrate 100 and substantially perpendicular to each other may be referred to as a first direction D1 and a second direction D2, respectively, and a direction substantially parallel to the upper surface of the first substrate 100 and forming an acute angle with respect to the first direction D1 and the second direction D2 may be referred to as a third direction D3. In addition, a direction substantially perpendicular to the upper surface of the first substrate 100 may be referred to as a vertical direction.

[0110] Reference Figure 23 to Figure 25 , a first active pattern 103 and a second active pattern 105 may be formed on a first substrate 100 including a first region I and a second region II, and an isolation pattern structure 110 may be formed to cover or overlap sidewalls of the first active pattern 103 and the second active pattern 105 .

[0111] The first region I of the first substrate 100 may be a cell region on which memory cells are formed, and the second region II of the first substrate 100 may be a peripheral circuit region on which peripheral circuit patterns for driving the memory cells are formed.

[0112] The first active pattern 103 and the second active pattern 105 may be formed by removing the upper portion of the first substrate 100 to form a first concave portion. The first active pattern 103 may extend in the third direction D3, and a plurality of first active patterns 103 may be spaced apart from each other in each of the first direction D1 and the second direction D2. In addition, a plurality of second active patterns 105 may be spaced apart from each other in each of the first direction D1 and the second direction D2, and Fig.23 Some second active patterns 105 are shown.

[0113] In example embodiments, the isolation pattern structure 110 may include first to third isolation patterns 112, 114, and 116 sequentially stacked on the inner wall of the first recess. A portion of the first recess in the first region I of the first substrate 100 may have a relatively small width, and thus, only the first isolation pattern 112 may be formed in the portion of the first recess. However, a portion of the first recess in the second region II or a portion between the first region I and the second region II of the first substrate 100 may have a relatively large width, and thus, all of the first to third isolation patterns 112, 114, and 116 may be formed in the portion of the first recess.

[0114] The first isolation pattern 112 and the third isolation pattern 116 may have an oxide (eg, silicon oxide), and the second isolation pattern 114 may include a nitride (eg, silicon nitride).

[0115] The first active pattern 103 and the isolation pattern structure 110 in the first region I of the first substrate 100 may be partially removed to form a second recess extending in the first direction D1.

[0116] A first gate structure 170 may be formed in the second recess. In example embodiments, the first gate structure 170 may include a first gate insulating pattern 120 on a bottom and sidewalls of the second recess, a first barrier pattern 130 on a portion of the first gate insulating pattern 120 on a bottom and lower sidewalls of the second recess, a first conductive pattern 140 on the first barrier pattern 130 and filling a lower portion of the second recess or in the lower portion of the second recess, a second conductive pattern 150 on the first barrier pattern 130 and the first conductive pattern 140, and a first gate mask 160 on an upper surface of the second conductive pattern 150 and an upper inner sidewall of the first gate insulating pattern 120 and filling an upper portion of the second recess or in the upper portion of the second recess. The first barrier pattern 130, the first conductive pattern 140, and the second conductive pattern 150 may form a first gate electrode.

[0117] The first barrier pattern 130 may include metal nitride, for example, titanium nitride, tantalum nitride, etc. The first conductive pattern 140 may include metal, metal nitride, metal silicide, doped polysilicon, etc., and the second conductive pattern 150 may include doped polysilicon.

[0118] In example embodiments, the first gate structures 170 may extend in the first direction D1 on the first region I of the first substrate 100, and a plurality of first gate structures 170 may be spaced apart from each other in the second direction D2. Ends of the first gate structures 170 in the first direction D1 may be aligned with each other in the second direction D2.

[0119] Reference Figure 26 to Figure 28 , an insulating layer structure 210 may be formed on the first region I and the second region II of the first substrate 100. A portion of the insulating layer structure 210 on the second region II of the first substrate 100 may be removed, and a thermal oxidation process may be performed on the second active pattern 105 on the second region II of the first substrate 100 to form a second gate insulating layer 220.

[0120] The insulating layer structure 210 may include sequentially stacked first to third insulating layers 180, 190, and 200. The first and third insulating layers 180 and 200 may include oxide (eg, silicon oxide), and the second insulating layer 190 may include nitride (eg, silicon nitride).

[0121] Alternatively, the second insulating layer 190 and the third insulating layer 200 on the second region II of the first substrate 100 among the insulating layer structure 210 may be removed, and the first insulating layer 180 remaining on the second region II of the first substrate 100 may be used as the second gate insulating layer 220. In this embodiment, the second gate insulating layer 220 may be formed not only on the second active pattern 105 but also on the isolation pattern structure 110 on the second region II of the first substrate 100.

[0122] The insulating layer structure 210 may be patterned, and the first active pattern 103, the isolation pattern structure 110, and the first gate mask 160 of the first gate structure 170 may be partially etched using the patterned insulating layer structure 210 as an etching mask to form a first opening 230. In example embodiments, the patterned insulating layer structure 210 may have a circular or elliptical shape in a plan view, and a plurality of insulating layer structures 210 may be spaced apart from each other along the first direction D1 and the second direction D2 on the first region I of the first substrate 100. Each of the insulating layer structures 210 may overlap with opposite ends of the first active pattern 103 in the third direction D3 in a vertical direction.

[0123] Reference Fig.29 and Fig.30 A third conductive layer 240, a second barrier layer 250, a fourth conductive layer 260, and a first mask layer 270 may be sequentially stacked on the insulating layer structure 210, the first active pattern 103, the isolation pattern structure 110 and the first gate structure 170 exposed by the first opening 230 on the first region I of the first substrate 100, and the second gate insulating layer 220 and the isolation pattern structure 110 on the second region II of the first substrate 100, and these layers may form a conductive structure layer. The third conductive layer 240 may fill the first opening 230 or be in the first opening 230.

[0124] The third conductive layer 240 may include doped polysilicon, the second barrier layer 250 may include metal silicon nitride (eg, titanium silicon nitride), the fourth conductive layer 260 may include metal (eg, tungsten), and the first mask layer 270 may include nitride (eg, silicon nitride).

[0125] Reference Figure 31 to Figure 33 , the conductive structure layer and the second gate insulating layer 220 may be patterned to form a second gate structure 330 on the second region II of the first substrate 100 .

[0126] The second gate structure 330 may include a second gate insulating pattern 280, a third conductive pattern 290, a second barrier pattern 300, a fourth conductive pattern 310 and a second gate mask 320 sequentially stacked in a vertical direction, and the third conductive pattern 290, the second barrier pattern 300 and the fourth conductive pattern 310 may form a second gate electrode.

[0127] The second gate structure 330 may partially overlap the second active pattern 105 in a vertical direction on the second region II of the first substrate 100 . Fig.31 Four second gate structures 330 are shown, and each of the four second gate structures 330 may extend in the first direction D1 and be spaced apart from each other in the second direction D2. However, the present disclosure may not be limited thereto.

[0128] A portion of the conductive structure layer on the edge portion of the first region I of the first substrate 100 adjacent to the second region II of the first substrate 100 can also be removed, and thus, the insulating layer structure 210, the upper surface of the first active pattern 103, the isolation pattern structure 110 and the first gate structure 170 exposed by the first opening 230 can also be partially exposed.

[0129] A first gate spacer structure may be formed on the sidewalls of the second gate structure 330, and a second gate spacer structure may be formed on the sidewalls of the conductive structure layer remaining on the first region I of the first substrate 100. The first gate spacer structure may include a first spacer 340 and a third spacer 350 stacked on the sidewalls of the second gate structure 330 in a horizontal direction substantially parallel to the upper surface of the first substrate 100, and the second gate spacer structure may include a second spacer 345 and a fourth spacer 355 stacked on the sidewalls of the conductive structure layer in a horizontal direction.

[0130] The first spacer 340 and the second spacer 345 may be formed by forming a first spacer layer on the first substrate 100 to cover or overlap the conductive structure layer and the second gate structure 330 and anisotropically etching the first spacer layer. The third spacer 350 and the fourth spacer 355 may be formed by forming a second spacer layer on the first substrate 100 to cover or overlap the conductive structure layer, the second gate structure 330, and the first spacer 340 and the second spacer 345 and anisotropically etching the second spacer layer.

[0131] The first spacer 340 and the second spacer 345 may include nitride (eg, silicon nitride), and the third spacer 350 and the fourth spacer 355 may include oxide (eg, silicon oxide).

[0132] However, the structures of the first and second gate spacer structures may not be limited thereto, and each of the first and second gate spacer structures may include a single spacer or more than two spacers sequentially stacked.

[0133] In example embodiments, impurities may be implanted into an upper portion of the second active pattern 105 adjacent to the second gate structure 330 to form a source / drain layer, and the second gate structure 330 and the source / drain layer may form a transistor. However, impurities may not be implanted into an upper portion of the second active pattern 105 adjacent to one or more of the second gate structures 330, and one or more of the second gate structures 330 may be a dummy gate structure that does not operate as a gate of a transistor. Fig.31 Only the dummy gate structure is shown.

[0134] A first etch stop layer 360 may be formed on the first substrate 100 to cover or overlap the conductive structure layer, the second gate structure 330, the first and second gate spacer structures, and the isolation pattern structure 110. The first etch stop layer 360 may include a nitride, for example, silicon nitride.

[0135] Reference Fig.34 , a fourth insulating interlayer 370 may be formed on the first etch stop layer 360 to have a sufficient height, and may be planarized until an upper surface of the second gate structure 330 and an upper surface of a portion of the first etch stop layer 360 on the conductive structure layer are exposed.

[0136] Therefore, the fourth insulating interlayer 370 may fill or be located in the space between the first gate spacer structures on the sidewalls of the second gate structure 330 and in the space between the first gate spacer structures on the sidewalls of the second gate structure 330 and the second gate spacer structures on the sidewalls of the conductive structure layer.

[0137] The fourth insulating interlayer 370 may include oxide (eg, silicon oxide), and the first capping layer 380 may include nitride (eg, silicon nitride).

[0138] Reference Figure 35 to Figure 37 , a portion of the first capping layer 380 on the first region I of the first substrate 100 can be etched to form a first capping pattern 385, and the first etch stop layer 360, the first mask layer 270, the fourth conductive layer 260, the second barrier layer 250 and the third conductive layer 240 can be sequentially etched using the first capping pattern 385 as an etching mask.

[0139] In example embodiments, the first capping pattern 385 may extend in the second direction D2 on the first region I of the first substrate 100 , and a plurality of first capping patterns 385 may be formed to be spaced apart from each other in the first direction D1 . The first capping layer 380 may remain on the second region II of the first substrate 100 .

[0140] Through the etching process, on the first region I of the first substrate 100, the fifth conductive pattern 245, the third barrier pattern 255, the sixth conductive pattern 265, the first mask 275, the first etch stop pattern 365, and the first capping pattern 385 may be sequentially stacked on the first opening 230. The third insulating pattern 205, the fifth conductive pattern 245, the third barrier pattern 255, the sixth conductive pattern 265, the first mask 275, the first etch stop pattern 365, and the first capping pattern 385 may be sequentially stacked on the second insulating layer 190 of the insulating layer structure 210 outside the first opening 230.

[0141] Hereinafter, the fifth conductive pattern 245, the third barrier pattern 255, the sixth conductive pattern 265, the first mask 275, the first etch stop pattern 365, and the first capping pattern 385, which are sequentially stacked, may be referred to as a bit line structure 395. The fifth conductive pattern 245, the third barrier pattern 255, and the sixth conductive pattern 265, which are sequentially stacked, may collectively form a conductive structure, and the first mask 275, the first etch stop pattern 365, and the first capping pattern 385, which are sequentially stacked, may collectively form an insulating structure. In example embodiments, the bit line structure 395 may extend in the second direction D2 on the first region I of the first substrate 100, and a plurality of the bit line structures 395 may be spaced apart from each other in the first direction D1.

[0142] A dummy bit line structure including a seventh conductive pattern 247, a fourth barrier pattern 257, an eighth conductive pattern 267, and a second mask 277 sequentially stacked and extending along the second direction D2 may be formed on a portion of the first region I of the first substrate 100 adjacent to the second region II of the first substrate 100 in the first direction D1, and a first etch stop layer 360 may remain on the second gate structure 330, the dummy bit line structure, the first gate spacer structure and the second gate spacer structure, a portion of the insulating layer structure 210, and the isolation pattern structure 110. In addition, a first capping layer 380 may remain on a portion of the first etch stop layer 360 on the upper surfaces of the second gate structure 330 and the dummy bit line structure, and the fourth insulating interlayer 370.

[0143] Reference Fig.38 and Fig.39A fifth spacer layer may be formed on the first substrate 100 to cover or overlap the bit line structure 395, the dummy bit line structure, and the first capping layer 380, and a fourth insulating layer and a fifth insulating layer may be sequentially formed on the fifth spacer layer.

[0144] The fifth spacer layer may also cover or overlap sidewalls of the third insulation pattern 205 between the second insulation layer 190 and the bit line structure 395 , and the fifth insulation layer may fill the first opening 230 .

[0145] The fifth spacer layer may include a nitride (eg, silicon nitride), the fourth insulating layer may include an oxide (eg, silicon oxide), and the fifth insulating layer may include a nitride (eg, silicon nitride).

[0146] The fourth insulating layer and the fifth insulating layer may be etched by an etching process. In example embodiments, the etching process may be performed by a wet etching process using an etching solution including phosphorous acid (H 3 PO 4 ), SC1, hydrogen fluoride (HF), and the fourth and fifth insulating layers except for the portions in the first opening 230 may be removed. Thus, most of the entire surface of the fifth spacer layer (i.e., the entire surface except for the portion thereof in the first opening 230) may be exposed, and the portions of the fourth and fifth insulating layers remaining in the first opening 230 may form the fourth insulating pattern 410 and the fifth insulating pattern 420, respectively.

[0147] A sixth spacer layer may be formed on the exposed surfaces of the fifth spacer layer and the fourth and fifth insulating patterns 410 and 420 in the first opening 230, and the sixth spacer layer may be anisotropically etched to form sixth spacers 430 on the surfaces of the fifth spacer layer and the fourth and fifth insulating patterns 410 and 420 to cover or overlap the sidewalls of the bit line structure 395. The sixth spacer layer may also be formed on the sidewalls of the dummy bit line structure. The sixth spacer layer may include an oxide, for example, silicon oxide.

[0148] A dry etching process may be performed using the first capping pattern 385 and the sixth spacer 430 as an etching mask to form a second opening 440 exposing an upper surface of the first active pattern 103. An upper surface of the first isolation pattern 112 of the isolation pattern structure 110 and an upper surface of the first gate mask 160 may also be exposed through the second opening 440.

[0149] Through the dry etching process, portions of the fifth spacer layer on the upper surfaces of the first capping pattern 385, the second insulating layer 190, and the first capping layer may be removed, and thus a fifth spacer 400 may be formed that covers or overlaps a sidewall of the bit line structure 395. The fifth spacer 400 may also cover or overlap a sidewall of the dummy bit line structure.

[0150] In addition, during the dry etching process, the first insulating layer 180 and the second insulating layer 190 may be partially removed so that the first insulating pattern 185 and the second insulating pattern 195 remain under the bit line structure 395. The first to third insulating patterns 185, 195, and 205 sequentially stacked under the bit line structure 395 may form an insulating pattern structure 215.

[0151] Reference Fig.40 and Fig.41 A seventh spacer layer may be formed on an upper surface of the first capping pattern 385, an upper surface of the first capping layer 380, an outer sidewall of the sixth spacer 430, portions of upper surfaces of the fourth and fifth insulating patterns 410 and 420, an upper surface of the first active pattern 103, the first isolation pattern 112, and the first gate mask 160 exposed by the second opening 440. The seventh spacer layer may be anisotropically etched to form a seventh spacer 450 covering or overlapping a sidewall of the bit line structure 395. The seventh spacer may include a nitride, for example, silicon nitride.

[0152] The fifth to seventh spacers 400 , 430 , and 450 sequentially stacked in a horizontal direction from the sidewall of the bit line structure 395 on the first region I of the first substrate 100 may be referred to as a bit line spacer structure 460 .

[0153] The second capping pattern 480 may be formed on the first region I of the first substrate 100 to fill or in the second opening 440 , and may be planarized until upper surfaces of the first capping pattern 385 and the first capping layer 380 are exposed.

[0154] In example embodiments, the second capping pattern 480 may extend in the second direction D2, and a plurality of second capping patterns 480 may be spaced apart from each other in the first direction D1 by the bit line structure 395. The second capping pattern 480 may include, for example, doped polysilicon.

[0155] Reference Figure 42 to Figure 44A third mask having a third opening may be formed on the first capping pattern 385, the first capping layer 380, and the second capping pattern 480, each of which may extend along the first direction D1 and be spaced apart from each other along the second direction D2 on the first region I of the first substrate 100. An etching process may be performed on the second capping pattern 480 using the third mask as an etching mask.

[0156] In example embodiments, each of the third openings may overlap in a vertical direction with a region between the first gate structures 170 on the first region I of the first substrate 100. When the etching process is performed, the fourth opening may be formed to expose the upper surface of the first active pattern 103 between the bit line structures 395 on the first region I of the first substrate 100.

[0157] After removing the third mask, a lower contact plug 475 may be formed on the first region I of the first substrate 100 to fill the fourth opening or in the fourth opening. The lower contact plug 475 may include, for example, doped polysilicon. In example embodiments, the lower contact plug 475 may extend along the first direction D1 between the bit line structures 395, and a plurality of lower contact plugs 475 may be spaced apart from each other along the second direction D2 by the second capping pattern 480.

[0158] Reference Fig.45 , an upper portion of the lower contact plug 475 may be removed to expose an upper portion of the bit line spacer structure 460 on a sidewall of the bit line structure 395 , and upper portions of the sixth and seventh spacers 430 and 450 of the exposed bit line spacer structure 460 may be removed.

[0159] An etch-back process may be further performed to remove an upper portion of the lower contact plug 475. Therefore, an upper surface of the lower contact plug 475 may be lower than uppermost surfaces of the sixth spacer 430 and the seventh spacer 450 (e.g., a distance between an uppermost surface of the first substrate 100 and an upper surface of the lower contact plug 475 is smaller than a distance between an uppermost surface of the sixth spacer 430 and an uppermost surface of the first substrate and a distance between an uppermost surface of the seventh spacer 450 and an uppermost surface of the first substrate 100).

[0160] An eighth spacer layer may be formed on the bit line structure 395, the bit line spacer structure 460, the second capping pattern 480, the first capping layer 380, and the lower contact plug 475. The eighth spacer layer may be anisotropically etched so that the eighth spacer 490 may be formed to cover or overlap an upper portion of the bit line spacer structure 460 on each opposing sidewall of the bit line structure 395 in the first direction D1, and so that an upper surface of the lower contact plug 475 is exposed and not covered by or overlapped with the eighth spacer 490.

[0161] A metal silicide pattern 500 may be formed on the exposed upper surface of the lower contact plug 475. In example embodiments, the metal silicide pattern 500 may be formed by forming a metal layer on the first and second capping patterns 385 and 480, the first capping layer 380, the eighth spacer 490, and the lower contact plug 475, heat-treating the metal layer, and removing an unreacted portion of the metal layer. The metal silicide pattern 500 may include, for example, cobalt silicide, nickel silicide, titanium silicide, or the like.

[0162] Reference Fig.46 and Fig.47 A first sacrificial layer may be formed on the first and second capping patterns 385 and 480, the eighth spacer 490, the metal silicide pattern 500, and the lower contact plug 475, and an upper portion of the first sacrificial layer may be planarized until the first and second capping patterns 385 and 480 and an upper surface of the first capping layer 380 are exposed.

[0163] The first sacrificial layer may include, for example, SOH, ACL, or the like.

[0164] The fifth opening 520 may be formed to extend through a portion of the first capping layer 380 at a boundary between the first region I and the second region II of the first substrate 100. The fifth opening 520 may extend through the fourth insulating interlayer 370, the first etch stop layer 360, the insulating layer structure 210, the first gate mask 160, the second conductive pattern 150, and the isolation pattern structure 110 located below a portion of the first capping layer 380 to expose the first conductive pattern 140. The fifth opening 520 may also expose the first barrier pattern 130 and the first gate insulating pattern 120 on the sidewalls of the first conductive pattern 140.

[0165] In addition, a sixth opening (not shown) may also be formed to extend through a portion of the first capping layer 380 on the second region II of the first substrate 100, the fourth insulating interlayer 370 below the portion of the first capping layer 380, and the first etch stop layer 360 to expose the upper surface of the second active pattern 105 between the second gate structures 330. However, the sixth opening may expose the upper surface of the source / drain layer at the upper portion of the second active pattern 105 between the second gate structures 330 operating as the gates of the transistors, and may not be formed between the second gate structures 330, which may be dummy gate structures.

[0166] Reference Figures 48 to 50, the first sacrificial layer may be removed by, for example, an ashing process and / or a stripping process, and a fifth barrier layer 530 may be formed on the first capping pattern 385 and the second capping pattern 480, the eighth spacer 490, the metal silicide pattern 500, and the lower contact plug 475 on the first region I of the first substrate 100. The fifth barrier layer 530 may also be located on the first capping layer 380, the sidewall of the fifth opening 520, the first conductive pattern 140, the first barrier pattern 130, the first gate insulating pattern 120, and the isolation pattern structure 110 exposed by the fifth opening 520, and the source / drain layer exposed by the sixth opening. A second metal layer 540 may be formed on the fifth barrier layer 530 to fill the space between the bit line structure 395, the fifth opening 520, and the sixth opening or be located in the space.

[0167] The fifth barrier layer 530 may include a metal nitride (eg, titanium nitride, tantalum nitride, etc.), and the second metal layer 540 may include a metal (eg, tungsten).

[0168] A planarization process may also be performed on an upper portion of the second metal layer 540. The planarization process may include a CMP process and / or an etch-back process.

[0169] Reference Figure 51 to Figure 54 , the second metal layer 540 and the fifth barrier layer 530 may be patterned.

[0170] Therefore, an upper contact plug 549 may be formed on the first region I of the first substrate 100, a fifth wiring 600 may be formed on a boundary between the first region I and the second region II of the first substrate 100, a first conductive pad 605 may be formed on the second region II of the first substrate 100, and a second conductive pad 607 may be formed on a portion of the first region I adjacent to the second region II of the first substrate 100 along the first direction D1. A seventh opening 547 may be formed between the upper contact plug 549, the fifth wiring 600, the first conductive pad 605, and the second conductive pad 607. An upper portion of the upper contact plug 549 may serve as a landing pad for a unit capacitor structure that may be formed subsequently.

[0171] The seventh opening 547 can be formed by removing not only the second metal layer 540 and the fifth barrier layer 530, but also the first capping pattern 385 and the second capping pattern 480, the first capping layer 380, the bit line spacer structure 460, the eighth spacer 490, the first etch stop layer 360, the first etch stop pattern 365, the first mask 275, the second gate mask 320, and the first gate spacer structure and the second gate spacer structure.

[0172] When the seventh opening 547 is formed, the second metal layer 540 and the fifth barrier layer 530 may be transformed into a first metal pattern 545 and a fifth barrier pattern 535 covering or overlapping a lower surface of the first metal pattern 545, respectively, and the first metal pattern 545 and the fifth barrier pattern 535 may form an upper contact plug 549 on the first region I of the first substrate 100. In example embodiments, a plurality of upper contact plugs 549 may be formed to be spaced apart from each other in each of the first direction D1 and the second direction D2, and may be arranged in a honeycomb pattern or a lattice pattern in a plan view. Each of the upper contact plugs 549 may have a circular, elliptical, or polygonal shape in a plan view.

[0173] The lower contact plug 475 , the metal silicide pattern 500 , and the upper contact plug 549 sequentially stacked on the first region I of the first substrate 100 may form a contact plug structure.

[0174] The fifth wiring 600 may include a fourth metal pattern 590 and an eighth barrier pattern 580 covering or overlapping a lower surface of the fourth metal pattern 590, and the first conductive pad 605 may include a fifth metal pattern 595 and a ninth barrier pattern 585 covering or overlapping a lower surface of the fifth metal pattern 595. A seventh contact plug 570 including a second metal pattern 560 and a sixth barrier pattern 550 may be formed in the fifth opening 520, and an eighth contact plug including a third metal pattern and a seventh barrier pattern may be formed in the sixth opening. The second conductive pad 607 may include a sixth metal pattern 597 and a tenth barrier pattern 587 covering or overlapping a lower surface of the sixth metal pattern 597.

[0175] In example embodiments, the fifth wiring 600 may extend from a boundary between the first region I and the second region II of the first substrate 100 toward the second region II of the first substrate 100 along the first direction D1, and a plurality of fifth wirings 600 may be spaced apart from each other along the second direction D2. In example embodiments, the fifth wiring 600 may overlap the fifth opening 520 in the vertical direction, and at least one of the fifth wirings 600 may overlap the sixth opening in the vertical direction.

[0176] Therefore, the fifth wiring 600 may be connected to the first conductive pattern 140 through the seventh contact plug 570 and may apply an electrical signal to the first gate structure 170. In addition, the fifth wiring 600 may be connected to the source / drain layer of the upper portion of the second active pattern 105 through the eighth contact plug and may apply an electrical signal to the source / drain layer.

[0177] In example embodiments, two adjacent or neighboring first conductive pads 605 on a portion of the second region II of the first substrate 100 may form a pair of first conductive pads 605, and a plurality of pairs of first conductive pads 605 may be spaced apart from each other in each of the first and second directions D1 and D2. Fig.54 A pair of first conductive pads 605 are shown spaced apart from each other in the first direction D1 by the seventh opening 547 extending in the second direction D2 , however, the present disclosure is not limited thereto.

[0178] The second conductive pad 607 may overlap the dummy bit line structure in a vertical direction.

[0179] In some embodiments, the exposed sixth spacer 430 may be removed to form an air gap connected to the seventh opening 547. The sixth spacer 430 may be removed by, for example, a wet etching process.

[0180] Reference Fig.55 and Fig.56 The sixth insulating layer 620 may be formed to fill the seventh opening 547 or in the seventh opening 547 , and a second etch stop layer 630 may be formed on the sixth insulating layer 620 , the upper contact plug 549 , the fifth wiring 600 , and the first and second conductive pads 605 and 607 .

[0181] The sixth insulating layer 620 may include nitride (eg, silicon nitride), and the second etch stop layer 630 may include nitride (eg, silicon boronitride, silicon carbonitride, etc.).

[0182] If an air gap connected to the seventh opening 547 is formed, the sixth insulating layer 620 may be formed to include a material having a low gap filling property, and thus the air gap may not be filled by or include the sixth insulating layer 620 but remain. The air gap may be referred to as an air spacer.

[0183] Reference Figures 57 to 60 A mold layer may be formed on the second etch stop layer 630, and a portion of the mold layer and a portion of the second etch stop layer 630 thereunder may be etched to form an eighth opening and a ninth opening that partially expose the upper contact plug 549 and the first conductive pad 605, respectively.

[0184] Since the plurality of upper contact plugs 549 are spaced apart from each other in each of the first direction D1 and the second direction D2 in a honeycomb pattern or a lattice pattern in a plan view, the plurality of eighth openings respectively exposing the plurality of upper contact plugs 549 may be spaced apart from each other in each of the first direction D1 and the second direction D2 in a honeycomb pattern or a lattice pattern in a plan view.

[0185] In example embodiments, in plan view, the ninth openings may be arranged in a honeycomb pattern or a lattice pattern on each of the first conductive pads 605. Each of the ninth openings may have a shape, for example, a circle, an ellipse, or a polygon.

[0186] A first capacitor electrode layer may be formed on the sidewalls of the eighth and ninth openings, the upper surfaces of the upper contact plug 549 and the first conductive pad 605, and the mold layer. A second sacrificial layer may be formed on the first capacitor electrode layer to fill the remaining portions of the eighth and ninth openings or in the remaining portions of the eighth and ninth openings, and the first capacitor electrode layer and the second sacrificial layer may be planarized until the upper surface of the mold layer is exposed to divide the first capacitor electrode layer into a plurality of portions. Thus, a first capacitor electrode 660 and a fourth capacitor electrode 665 having a columnar shape may be formed in the eighth and ninth openings, respectively.

[0187] The second sacrificial layer and the mold layer may be removed through a wet etching process using an etching solution including, for example, LAL.

[0188] A dielectric layer may be formed on the surfaces of the first capacitor electrode 660 and the fourth capacitor electrode 665 and the upper surface of the second etch stop layer 630, and a second capacitor electrode layer and a third capacitor electrode layer may be sequentially formed on the dielectric layer. The second capacitor electrode layer and the third capacitor electrode layer and the dielectric layer may be patterned, and the second etch stop layer 630 may be exposed.

[0189] Thus, a unit capacitor structure including a first capacitor electrode 660, a first dielectric pattern 670, a second capacitor electrode 680, and a third capacitor electrode 690 may be formed on the first region I of the first substrate 100, and each of the first capacitor electrodes 660 and corresponding portions of the first dielectric pattern 670, the second capacitor electrode 680, and the third capacitor electrode 690 may collectively form a unit capacitor 700. Thus, the first capacitor structure may include a plurality of unit capacitors 700 spaced apart from each other in the first direction D1 and the second direction D2 on the first region I of the first substrate 100.

[0190] In addition, a first decoupling capacitor structure including a fourth capacitor electrode 665, a second dielectric pattern 675, a fifth capacitor electrode 685, and a sixth capacitor electrode 695 may be formed on the second region II of the first substrate 100, and each of the fourth capacitor electrodes 665 and corresponding portions of the second dielectric pattern 675, the fifth capacitor electrode 685, and the sixth capacitor electrode 695 may collectively form a decoupling capacitor 705. Therefore, the first decoupling capacitor structure may include a plurality of decoupling capacitors 705 spaced apart from each other in the first direction D1 and the second direction D2 on the second region II of the first substrate 100.

[0191] In example embodiments, a plurality of first decoupling capacitor structures may be spaced apart from each other on the second region II of the first substrate 100. In example embodiments, a plurality of decoupling capacitors 705 may be formed on each of the first conductive pads 605, and the decoupling capacitors 705 on a pair of first conductive pads 605 may share the second dielectric pattern 675, the fifth capacitor electrode 685, and the sixth capacitor electrode 695.

[0192] A fifth insulating interlayer 710 may be formed on the cell capacitor structure, the first decoupling capacitor structure, and the second etch stop layer 630 on the first region I and the second region II of the first substrate 100. Ninth to eleventh contact plugs 721, 722, and 724 may be formed through the fifth insulating interlayer 710 to contact the upper surfaces of the pair of first conductive pads 605. A sixth insulating interlayer 730 may be formed on the fifth insulating interlayer 710 and the ninth to eleventh contact plugs 721, 722, and 724, and sixth to eighth wirings 741, 742, and 744 may be formed through the sixth insulating interlayer 730 to contact the upper surfaces of the ninth to eleventh contact plugs 721, 722, and 724, respectively.

[0193] The ninth contact plug 721 and the sixth wiring 741 may collectively form a first capacitor connection structure, the tenth contact plug 722 and the seventh wiring 742 may collectively form a second capacitor connection structure, and the eleventh contact plug 724 and the eighth wiring 744 may collectively form a third capacitor connection structure.

[0194] Reference Fig.61 and Fig.62 , a third gate structure 841 and a fourth gate structure 842 may be formed on the first region I and the second region II of the second substrate 800, respectively. A third gate spacer 851 and a fourth gate spacer 852 may be formed on the sidewalls of the third gate structure 841 and the fourth gate structure 842, respectively. A first source / drain region 802 and a second source / drain region 804 may be formed on upper portions of the first region I and the second region II of the second substrate 800, respectively adjacent to the third gate structure 841 and the fourth gate structure 842, respectively. A seventh insulating interlayer 860 may be formed on the second substrate 800 to cover the third gate structure 841 and the fourth gate structure 842 and the third gate spacer 851 and the fourth gate spacer 852 or overlap the third gate structure 841 and the fourth gate structure 842 and the third gate spacer 851 and the fourth gate spacer 852.

[0195] The third gate structure 841 may include a third gate insulating pattern 811 , a third gate electrode 821 , and a third gate mask 831 sequentially stacked, and the fourth gate structure 842 may include a fourth gate insulating pattern 812 , a fourth gate electrode 822 , and a fourth gate mask 832 sequentially stacked.

[0196] Twelfth and thirteenth contact plugs 871 and 872 may be formed through the seventh insulating interlayer 860 to contact upper surfaces of the first and second source / drain regions 802 and 804 , respectively, and a fourteenth contact plug 874 may be formed to contact an upper surface of the second region II of the second substrate 800 .

[0197] The eighth insulating interlayer 880 may be formed on the seventh insulating interlayer 860 and the twelfth to fourteenth contact plugs 871, 872 and 874, and the ninth to eleventh wirings 891, 892 and 894 may be formed to pass through the eighth insulating interlayer 880 to contact the upper surfaces of the twelfth to fourteenth contact plugs 871, 872 and 874, respectively.

[0198] Reference Figure 63 to Figure 65 , a bonding layer 900 may be formed on the eighth insulating interlayer 880, and first to third bonding patterns 911, 912, and 914 may be formed to pass through the bonding layer 900 to contact upper surfaces of ninth to eleventh wirings 891, 892, and 894, respectively.

[0199] After flipping the orientation of the second substrate 800 , the second substrate 800 can be bonded to the first substrate 100 so that the first to third bonding patterns 911 , 912 , and 914 can contact upper surfaces of the sixth to eighth wirings 741 , 742 , and 744 , respectively, thereby completing the manufacture of the semiconductor device.

[0200] While the present disclosure has been shown and described with reference to example embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure as defined by the claims.

Claims

1. A semiconductor device comprising: A first gate structure, which is located in a cell region of a substrate, wherein the substrate includes a peripheral circuit region; A bit line structure located on the cell region of the substrate; a cell capacitor structure located on the bit line structure; a decoupling capacitor structure located on the peripheral circuit region of the substrate; and A second gate structure is located on the decoupling capacitor structure.

2. The semiconductor device according to claim 1, further comprising a plurality of second gate structures, the plurality of second gate structures including the second gate structure, wherein: The plurality of second gate structures are spaced apart from one another along a horizontal direction parallel to an upper surface of the substrate on the peripheral circuit region of the substrate. 3 . The semiconductor device of claim 1 , further comprising a third gate structure located on the cell capacitor structure.

4. The semiconductor device of claim 1 , further comprising a plurality of decoupling capacitor structures, the plurality of decoupling capacitor structures including the decoupling capacitor structure, wherein: The plurality of decoupling capacitor structures are spaced apart from one another on the peripheral circuit region of the substrate along a horizontal direction parallel to an upper surface of the substrate.

5. The semiconductor device according to claim 1, further comprising a third gate structure located on the peripheral circuit region of the substrate, wherein: The third gate structure is spaced apart from the decoupling capacitor structure.

6. The semiconductor device according to claim 1, wherein: The decoupling capacitor structure comprises: first capacitor electrodes spaced apart from each other in a horizontal direction parallel to an upper surface of the substrate, wherein each of the first capacitor electrodes extends in a vertical direction perpendicular to the upper surface of the substrate; a dielectric pattern located on the upper surface and the side surface of the first capacitor electrode; a second capacitor electrode located on the dielectric pattern; and A third capacitor electrode is located on the second capacitor electrode. 7 . The semiconductor device according to claim 6 , further comprising a conductive pad electrically connected to a lower surface of the first capacitor electrode.

8. The semiconductor device according to claim 1, wherein: The decoupling capacitor structure comprises: a first capacitor electrode having a planar shape extending in a horizontal direction parallel to an upper surface of the substrate; a second capacitor electrode having a planar shape extending in the horizontal direction and at least partially overlapping the first capacitor electrode in a vertical direction perpendicular to an upper surface of the substrate; and A dielectric pattern is located between the first capacitor electrode and the second capacitor electrode.

9. The semiconductor device according to claim 1, wherein: The decoupling capacitor structure is a first distance from an upper surface of the substrate, wherein the cell capacitor structure is a second distance from the upper surface of the substrate, and wherein the first distance is less than the second distance.

10. The semiconductor device according to claim 1, wherein At least a portion of the decoupling capacitor structure is located in the substrate.

11. The semiconductor device according to claim 1, wherein: The decoupling capacitor structure and the cell capacitor structure are separated from an upper surface of the substrate by a same distance.

12. A semiconductor device comprising: A first gate structure, which is located in a cell region of a first substrate, wherein the first substrate includes a peripheral circuit region; A bit line structure located on the cell region of the first substrate; a cell capacitor structure located on the bit line structure; a decoupling capacitor structure located at least partially in the peripheral circuit region of the first substrate; and A second gate structure is located on the peripheral circuit region of the first substrate, wherein the second gate structure is a first distance from the upper surface of the first substrate, wherein the unit capacitor structure is a second distance from the upper surface of the first substrate, and wherein the first distance is greater than the second distance.

13. The semiconductor device according to claim 12, further comprising a plurality of second gate structures, the plurality of second gate structures including the second gate structure, wherein: The plurality of second gate structures are spaced apart from one another on the peripheral circuit region of the first substrate along a horizontal direction parallel to an upper surface of the first substrate.

14. The semiconductor device of claim 12, further comprising a third gate structure located on the cell capacitor structure.

15. The semiconductor device according to claim 12, further comprising a second substrate located on the first substrate, wherein The lower surface of the second substrate is located on the second gate structure.

16. The semiconductor device according to claim 12, further comprising a second substrate located on the first substrate, wherein: The second gate structure is located on the upper surface of the second substrate.

17. A semiconductor device comprising: A first substrate including a first unit region and a first peripheral circuit region; a first gate structure located in the first cell region of the first substrate; A bit line structure located on the first cell region of the first substrate; a cell capacitor structure located on the bit line structure; a decoupling capacitor structure located on the first peripheral circuit region of the first substrate; a second substrate located on the unit capacitor structure and the decoupling capacitor structure, wherein the second substrate comprises a second unit region and a second peripheral circuit region corresponding to the first unit region of the first substrate and the first peripheral circuit region of the first substrate, respectively; a second gate structure located on the second cell region of the second substrate; A third gate structure is located on the second peripheral circuit region of the second substrate; and Vias extend into the second substrate, wherein some of the vias are electrically connected to the cell capacitor structure and the decoupling capacitor structure.

18. The semiconductor device according to claim 17, further comprising a plurality of third gate structures, the plurality of third gate structures including the third gate structure, wherein: The plurality of third gate structures are spaced apart from one another on the second peripheral circuit region of the second substrate along a horizontal direction parallel to an upper surface of the second substrate.

19. The semiconductor device of claim 17, further comprising a plurality of decoupling capacitor structures, the plurality of decoupling capacitor structures including the decoupling capacitor structure, wherein: The plurality of decoupling capacitor structures are spaced apart from one another on the first peripheral circuit region of the first substrate along a horizontal direction parallel to an upper surface of the first substrate.

20. The semiconductor device according to claim 17, further comprising a fourth gate structure located on the first peripheral circuit region of the first substrate, wherein: The fourth gate structure is spaced apart from the decoupling capacitor structure.

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