Integrated assembly

Abstract

Some embodiments include an integrated assembly having a semiconductor die with a memory array region and one or more regions around the memory array region. A stack of alternating insulation levels and conductive levels extends across the memory array region and into at least one of the peripheral regions. The stack generates a bending stress on the die. At least one stress relief region extends through the stack and is configured to mitigate the bending stress.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application of the invention patent application with the application date of September 21, 2020, application number "202010993539.7", and invention name "Integrated Assembly". Technical Field

[0003] Integrated assembly, integrated memory, integrated die configuration. Background Art

[0004] Memory provides data storage for electronic systems. Flash memory is a type of memory and has many uses in modern computers and devices. For example, a modern personal computer may have a BIOS stored on a flash memory chip. As another example, it is becoming increasingly common for computers and other devices to utilize flash memory in solid-state drives to replace conventional hard disk drives. As yet another example, flash memory is popular in wireless electronic devices because it enables manufacturers to support new communication protocols as they are standardized and provides the ability to remotely upgrade the device to enhance features.

[0005] NAND may be the basic architecture of flash memory, and may be configured to include vertically stacked memory cells (memory structure).

[0006] Before describing NAND specifically, it may be helpful to more generally describe the relationship of a memory array within an integrated arrangement. Figure 1A block diagram of a prior art device 1000 is shown, which includes a memory array 1002 having a plurality of memory cells 1003 arranged in rows and columns along with access lines 1004 (e.g., word lines for conducting signals WL0 to WLm) and first data lines 1006 (e.g., bit lines for conducting signals BL0 to BLn). The access lines 1004 and first data lines 1006 may be used to transfer information to and from the memory cells 1003. A row decoder 1007 and a column decoder 1008 decode address signals A0 to AX on address lines 1009 to determine which memory cells 1003 are to be accessed. Sense amplifier circuits 1015 operate to determine the value of information read from the memory cells 1003. I / O circuits 1017 transfer the value of information between the memory array 1002 and input / output (I / O) lines 1005. The signals DQ0 to DQN on the I / O line 1005 may represent the value of information to be read from or written to the memory cell 1003. Other devices may communicate with the device 1000 through the I / O line 1005, the address line 1009, or the control line 1020. The memory control unit 1018 is used to control the memory operation to be performed on the memory cell 1003 and utilizes the signal on the control line 1020. The device 1000 may receive the power supply voltage signals Vcc and Vss on the first power supply line 1030 and the second power supply line 1032, respectively. The device 1000 includes a selection circuit 1040 and an input / output (I / O) circuit 1017. The selection circuit 1040 may respond to the signals CSEL1 to CSELn via the I / O circuit 1017 to select the signals on the first data line 1006 and the second data line 1013 that may represent the value of information to be read from or programmed into the memory cell 1003. Column decoder 1008 may selectively activate CSEL1-CSELn signals based on A0-AX address signals on address line 1009. Selection circuit 1040 may select signals on first data line 1006 and second data line 1013 to provide communication between memory array 1002 and I / O circuit 1017 during read and program operations.

[0007] Figure 1 The memory array 1002 may be a NAND memory array, and Figure 2 Display can be used Figure 1Schematic diagram of a three-dimensional NAND memory device 200 of a memory array 1002 of FIG. 1 . The device 200 includes a plurality of strings of charge storage devices. In a first direction (Z-Z'), each string of charge storage devices may include, for example, thirty-two charge storage devices stacked on top of each other, wherein each charge storage device corresponds to, for example, one of thirty levels (e.g., level 0 to level 31). The charge storage devices of the respective strings may share a common channel region, such as a channel region formed in a respective pillar of semiconductor material (e.g., polysilicon) around which the string of charge storage devices is formed. In a second direction (XX'), each of, for example, sixteen first groups of the plurality of strings may include, for example, eight strings that share a plurality (e.g., thirty-two) access lines (i.e., "global control gate (CG) lines," also referred to as word lines WL). Each of the access lines may couple a charge storage device within a level. When each charge storage device includes a cell capable of storing two bits of information, the charge storage devices coupled by the same access line (and therefore corresponding to the same level) can be logically grouped into, for example, two pages, such as P0 / P32, P1 / P33, P2 / P34, etc. In the third direction (Y-Y'), each second group of, for example, eight second groups of a plurality of strings can include sixteen strings coupled by corresponding ones of eight data lines. The size of the memory block can include 1,024 pages and a total of approximately 16MB (e.g., 16 WLs x 32 levels x 2 bits = 1,024 pages / block, block size = 1,024 pages x 16KB / page = 16MB). The number of strings, levels, access lines, data lines, first groups, second groups, and / or pages can be greater or less than Figure 2 The number shown in .

[0008] Figure 3 exhibit Figure 2 A cross-sectional view of a memory block 300 of a 3D NAND memory device 200 in the XX′ direction, including a cross-sectional view of a memory block 300 in the XX′ direction relative to Figure 2 The fifteen charge storage device strings in one of the sixteen first groups of strings are described. The plurality of strings of the memory block 300 may be grouped into a plurality of subsets 310, 320, 330 (eg, tile columns), such as tile columns. I , Tile Column J and tile rows K, where each subset (e.g., tile column) includes a "partial block" (sub-block) of the memory block 300. A global drain-side select gate (SGD) line 340 may be coupled to the SGD of multiple strings. For example, the global SGD line 340 may be coupled to multiple (e.g., three) sub-SGD lines 342, 344, 346 via corresponding ones of multiple (e.g., three) sub-SGD drivers 332, 334, 336, where each sub-SGD line corresponds to a respective subset (e.g., tile column). Each of the sub-SGD drivers 332, 334, 336 may simultaneously couple or cut off the SGD of the strings of the corresponding partial block (e.g., tile column) independently of the SGD of the strings of the other partial blocks. A global source-side select gate (SGS) line 360 ​​may be coupled to the SGS of multiple strings. For example, the global SGS line 360 ​​may be coupled to a plurality of sub-SGS lines 362, 364, 366 via a corresponding one of the plurality of sub-SGD drivers 332, 334, 336, wherein each sub-SGS line corresponds to a corresponding subset (e.g., a tile column). Each of the sub-SGS drivers 322, 324, 326 may simultaneously couple or cut off the SGS of a string of a corresponding partial block (e.g., a tile column) independently of the SGS of a string of other partial blocks. The global access line (e.g., a global CG line) 350 may couple a charge storage device of a corresponding level corresponding to each of the plurality of strings. Each global CG line (e.g., a global CG line 350) may be coupled to a plurality of sub-access lines (e.g., sub-CG lines) 352, 354, 356 via a corresponding one of the plurality of sub-string drivers 312, 314, and 316. Each of the sub-string drivers may simultaneously couple or cut off the charge storage device corresponding to a corresponding partial block and / or level independently of the charge storage devices of other partial blocks and / or other levels. The charge storage devices corresponding to respective subsets (e.g., partial blocks) and respective levels may comprise a "partial level" (e.g., a single "tile") of charge storage devices. The strings corresponding to respective subsets (e.g., partial blocks) may be coupled to respective ones of sub-sources 372, 374, and 376 (e.g., "tile sources"), with each sub-source being coupled to a respective power source.

[0009] Alternatively, refer to Figure 4 The NAND memory device 200 is described with reference to a schematic illustration of FIG.

[0010] The memory array 200 includes word lines 2021 to 202 N and bit lines 2281 to 228 M .

[0011] Memory array 200 also includes NAND strings 2061 to 206 M Each NAND string includes charge storage transistors 2081 to 208 NThe charge storage transistor may use a floating gate material (eg, polysilicon) to store charge, or may use a charge trapping material (such as, for example, silicon nitride, metal nanodots, etc.) to store charge.

[0012] The charge storage transistor 208 is located at the intersection of the word line 202 and the string 206. The charge storage transistor 208 represents a non-volatile memory cell for storing data. The charge storage transistor 208 of each NAND string 206 is connected in series from source to drain between a source select device (e.g., source side select gate, SGS) 210 and a drain select device (e.g., drain side select gate, SGD) 212. Each source select device 210 is located at the intersection of the string 206 and the source select line 214, and each drain select device 212 is located at the intersection of the string 206 and the drain select line 215. The select devices 210 and 212 can be any suitable access devices, and in Figure 4 The box is used to summarize the description.

[0013] The source of each source select device 210 is connected to the common source line 216. The drain of each source select device 210 is connected to the source of the first charge storage transistor 208 of the corresponding NAND string 206. For example, the drain of source select device 2101 is connected to the source of the charge storage transistor 2081 of the corresponding NAND string 2061. The source select devices 210 are connected to the source select line 214.

[0014] The drain of each drain select device 212 is connected to the bit line (i.e., digit line) 228 at the drain contact. For example, the drain of drain select device 2121 is connected to bit line 2281. The source of each drain select device 212 is connected to the drain of the last charge storage transistor 208 of the corresponding NAND string 206. For example, the source of drain select device 2121 is connected to the charge storage transistor 208 of the corresponding NAND string 2061. N of the drain.

[0015] The charge storage transistor 208 includes a source 230, a drain 232, a charge storage region 234, and a control gate 236. The charge storage transistor 208 has its control gate 236 coupled to the word line 202. The columns of charge storage transistors 208 are those transistors within the NAND string 206 that are coupled to a given bit line 228. The rows of charge storage transistors 208 are those transistors that are coupled in common to a given word line 202.

[0016] Memory arrays (memory devices) may be fabricated on semiconductor dies. Figure 5-10 A region of an example integrated assembly 10 associated with a conventional die including a conventional memory device is illustrated. Figure 5The top view of shows that the integrated assembly 10 includes a pair of memory device tiles (or tile regions) 12 and 14, wherein the tiles are separated from each other by an inter-tile region 16.

[0017] The tile 12 includes a first memory device sub-block (or block area) 18 and a second memory device sub-block (or block area) 20 ; wherein the sub-blocks 18 and 20 are separated from each other by an intervening inter-block area 22 .

[0018] Block 12 also includes an interconnect region (e.g., a step region) 24 for establishing connections with individual conductive levels of a word line stack (discussed below). The illustrated interconnect region 24 includes a pair of spaced trenches 26 and 28 for establishing connections with different sets of conductive levels, and includes a region 30 between the spaced trenches.

[0019] In addition, block 12 includes memory array regions 32 and 34 within sub-blocks 18 and 20, respectively; and includes an intervening region 36 between interconnect region 24 and memory array regions 32 and 34. Channel material pillars 38 are within memory array regions 32 and 34 and pass through the conductive level stack (discussed below); and support structures 40 are within intervening region 36 and also pass through the conductive level stack. It should be noted that channel material pillars 38 are formed to be more densely packed than support structures 40. Specifically, there are more channel material pillars 38 per unit area than support structures 40 per unit area. Channel material pillars 38 are shown as circular, while support structures 40 are shown as square. This difference in shape of the channel material pillars relative to the support structures is used to emphasize that the support structures include a different configuration than the channel material pillars. It should be understood that the channel material pillars and the support structures may include any suitable shapes, and may or may not be different shapes relative to each other.

[0020] A gap is provided between interposing area 36 and memory array areas 32 and 34 to indicate that there may be a distance between the memory array area and interposing area 36 , and also to indicate that there may be additional components between the memory array area and interposing area 36 .

[0021] Routing region 42 extends through memory array regions 32 and 34. The routing region may provide access to bit lines and / or other components.

[0022] Block 14 includes features similar to those described above with reference to block 12. Specifically, block 14 includes a first memory device sub-block (or block region) 48 and a second memory device sub-block (or block region) 50; wherein sub-blocks 48 and 50 are separated from each other by an intervening inter-block region 52. Block 14 includes an interconnect region (e.g., a step region) 54 having a pair of separation trenches 56 and 58, and includes a region 60 between the separation trenches. Block 14 also includes memory array regions 62 and 64 within sub-blocks 48 and 50, respectively; and includes an intervening region 66 between interconnect region 54 and memory array regions 62 and 64. Channel material pillars 38 are within memory array regions 62 and 64, and support structures 40 are within intervening region 66. A wiring region 68 extends through memory array regions 62 and 64, wherein such wiring regions are similar to wiring region 42 discussed above.

[0023] A periphery (peripheral region) 70 is along the sides of tiles 12 and 14. The peripheral region is not shown as extending along intervening regions 36 and 66 or along interconnect regions 24 and 54, but may extend along one or more of such regions in some applications.

[0024] Inter-tile region 16 and inter-tile regions 22 and 52 may be considered to include slits filled with insulating material 72. Such slits may extend along the sides of tiles 12 and 14, as shown;

[0025] Memory array regions 32 and 34 may be considered to have a first side 35 adjacent to interposing region 36, and to have additional sides 37 and 39 adjacent to peripheral region 70. Similarly, memory array regions 62 and 64 may be considered to include a first side 65 adjacent to interposing region 66, and to include second sides 67 and 69 adjacent to peripheral region 70.

[0026] Figure 6-10 Show respectively along Figure 5 Cross-sectional view of lines AA, BB, CC, DD and EE.

[0027] refer to Figure 6 , cross-sectional view AA extends across inter-block region 22 and across portions of memory blocks 18 and 20. The illustrated region includes a stack 74 of alternating conductive 76 and insulating 78 levels.

[0028] Conductive level 76 includes conductive material 80 , and insulating level 78 includes insulating material 82 .

[0029] Conductive material 80 may include any suitable composition(s); and in some embodiments may include a metal-containing material (e.g., tungsten). In some applications, conductive material 80 may include a tungsten core at least partially surrounded by a liner including a metal nitride (e.g., titanium nitride).

[0030] Insulating material 82 may comprise any suitable composition(s); and in some applications may comprise, consist essentially of, or consist of silicon dioxide.

[0031] The channel material column 38 extends through the stack 74 and includes a channel material 84. The channel material 84 may, for example, include, consist essentially of, or consist of appropriately doped silicon. The channel material column 38 is shown as a ring surrounding an insulating material 86. This configuration of the channel material column may be considered to correspond to a "hollow" channel configuration, in which the dielectric material 86 is disposed within the hollow of the channel material column. In other applications, the channel material may be configured as a solid column rather than as the illustrated hollow column.

[0032] The channel material pillar 38 is separated from the conductive level 76 of the stack 74 by an intervening region 88. Region 88 may include tunneling materials, charge storage materials, charge blocking materials, and dielectric barrier materials. The tunneling material (also referred to as a gate dielectric material) may include one or more of silicon dioxide, aluminum oxide, hafnium oxide, zirconium oxide, etc. The charge storage material may include a charge trapping material (e.g., one or more of silicon nitride, silicon oxynitride, conductive nanodots, etc.). The charge blocking material may include one or more of silicon dioxide, aluminum oxide, hafnium oxide, zirconium oxide, etc. The dielectric barrier material may include one or more of aluminum oxide, hafnium oxide, zirconium oxide, etc.

[0033] Memory cells (e.g., NAND memory cells) 90 (only some of which are labeled) are located along the channel material pillar 38. The memory cells 90 include regions of the conductive level 76 (specifically, the control gate region), portions of the channel material 84, and portions of the tunneling material, charge storage material, charge blocking material, and dielectric barrier material within the intervening region 88. The memory cells 90 are stacked vertically on top of each other. In some embodiments, the assembly 10 may be viewed as including the same as described above with reference to FIG. Figure 2 The described configuration is similar to a three-dimensional NAND configuration (three-dimensional memory device).

[0034] Conductive level 76 may be referred to as a word line / control gate level because it includes the word lines and control gates associated with the vertically stacked memory cells 90 of the NAND string. The number of memory cell levels in an individual string may be determined by the number of conductive levels 76. A NAND string may include any suitable number of memory cell levels. For example, a NAND string may have 8 memory cell levels, 16 memory cell levels, 32 memory cell levels, 64 memory cell levels, 512 memory cell levels, 1024 memory cell levels, etc.

[0035] One or more of the lower conductive levels 76 may be incorporated into a source side select gate (SGS).

[0036] The stack 74 is shown supported over a source structure 92. This source structure may be similar to the source structure 216 discussed above.

[0037] The source structure 92 is supported by a semiconductor base 15. The base 15 may include a semiconductor material; and may, for example, include, consist essentially of, or consist of single crystal silicon. The base 15 may be referred to as a semiconductor substrate. The term "semiconductor substrate" refers to any structure including a semiconducting material, including but not limited to bulk semiconducting material, such as a semiconducting wafer (alone or in an assembly including other materials), and a layer of semiconducting material (alone or in an assembly including other materials). The term "substrate" refers to any supporting structure, including but not limited to the semiconductor substrate described above. In some applications, the base 15 may correspond to a semiconductor substrate containing one or more materials associated with integrated circuit manufacturing. Such materials may include, for example, one or more of refractory metal materials, barrier materials, diffusion materials, insulator materials, etc.

[0038] A gap is disposed between substrate 15 and source structure 92 to indicate that there may be other components, materials, etc. disposed between substrate 15 and structure 92 .

[0039] Substrate 15 may be considered to represent a portion of a semiconductor die; and the integrated circuit die may be considered to include stack 74 together with substrate 15 .

[0040] refer to Figure 7 , cross-sectional view BB extends across intervening region 66 and across a pair of support structures 40. Support structures 40 pass through stack 74 of alternating levels 76 and 78. Conductive structures 92 are Figure 7 Not shown, but understood, the support structure 40 may pass through the stack 74 to the upper surface of this conductive structure.

[0041] Support structure 40 includes conductive material 94 .

[0042] Insulating material 96 separates conductive material 94 from levels 76 and 78 of stack 74 .

[0043] Conductive material 94 may include any suitable composition(s); such as, for example, one or more of tungsten, titanium nitride, tantalum nitride, etc.

[0044] Insulating material 96 may include any suitable composition(s); such as, for example, silicon dioxide.

[0045] The support structure may be "live," meaning that it is electrically coupled to active circuitry, or may be "dummy," meaning that it is not electrically coupled to active circuitry. In some applications, some support structures are live, while other support structures are dummy.

[0046] refer to Figure 8 , cross-sectional view CC extends across interconnect region (step region) 24. First trench 26 enables connection 97 to be made from first series of conductive levels 76 to circuit 98, and second trench 28 enables connection 100 to be made from second series of conductive levels 76 to circuit 98. In some embodiments, circuit 98 may be a driver circuit (e.g., a word line driver circuit). Connection 100 may extend to the same driver circuit 98 as connection 97 (as shown), or may extend to a different driver circuit than connection 97.

[0047] Insulating material 77 is over interconnect region 24, and trenches 26 and 28 extend into this insulating material. Insulating material 77 may comprise any suitable composition(s); and in some embodiments may comprise, consist essentially of, or consist of silicon dioxide.

[0048] refer to Fig. 9 , cross-sectional view DD extends across peripheral region 70. Stack 74 enters peripheral region 70. Fig. 9 Conductive structure 92 is not shown in FIG. Conductive structure 92 may or may not be present within the illustrated portion of peripheral region 70.

[0049] refer to Fig.10 , cross-sectional view DD extends across one of wiring regions 42. Stack 74 is adjacent to wiring region 42. Conductive structure 92 is Fig.10 Not shown, but usually will be along the Fig.10 The wiring segment 102 is Fig.10 104 and passes through insulating material 104. Wiring segment 102 can be used to couple to Figure 5 1 and 2. The wiring segments 106 may be connected to bit lines and / or other features associated with a memory array (e.g., memory array 34) of the present invention. The wiring segments include conductive material 106. This conductive material may include any suitable conductive composition(s); including, for example, metal-containing materials (e.g., tungsten, titanium nitride, tantalum nitride, copper, aluminum, etc.).

[0050] Insulating material 104 may include any suitable composition(s); such as, for example, silicon dioxide.

[0051] Fig.11 and 12 Display and Figure 5The conductive structure 92 is similar to the prior art assembly 10a but has a block 108 of the stack 74 within the inter-tile area 16. Fig.12 Not shown in FIG. 7A , but it should be understood that such a conductive structure may be below the illustrated region of stack 74 .

[0052] Conventional assemblies (e.g. Figure 5-12 A problem encountered with semiconductor dies of assemblies 10 and 10a) is that such dies may bend, resulting in fracture of components associated with the die. It would be desirable to develop a configuration that avoids this problematic bending. Summary of the invention

[0053] One embodiment of the present application provides an integrated assembly comprising: a semiconductor die having one or more memory array regions and one or more regions peripheral to the one or more memory array regions; the one or more memory array regions having a total area; a stack of alternating insulating levels and conductive levels extending across the one or more memory array regions and into at least one of the regions peripheral to the one or more memory array regions; the stack generating bending stress on the die; and one or more stress relief regions extending through the stack and configured to relieve the bending stress; the one or more stress relief regions having a total area of ​​at least about 5% of the total area of ​​the one or more memory array regions.

[0054] Another embodiment of the present application provides an integrated assembly comprising: a semiconductor die having a first memory device block adjacent to a second memory device block; the first memory device block and the second memory device block are separated from each other by an inter-block area; the first memory device block has a first memory array area, and the second memory device block has a second memory array area; a stack of alternating insulating levels and conductive levels extending across the first memory array area and the second memory array area; a segment of the stack is within the inter-block area; the stack generates bending stress on the die; and a stress relief area extending through the segment of the stack and filled with stress relief material.

[0055] Another embodiment of the present application provides an integrated assembly comprising: a semiconductor die having a memory array region; a stack of alternating insulating levels and conductive levels extending across the memory array region; an interconnect region adjacent to the memory array region and configured to establish connections with the individual conductive levels of the stack; an intermediary region between the interconnect region and the memory array region; a first stress relief region within the intermediary region; a second stress relief region within the interconnect region; and the first stress relief region and the second stress relief region extend through the stack and are filled with stress relief material; the stress relief material comprises silicon and one or more of nitrogen, carbon and oxygen. BRIEF DESCRIPTION OF THE DRAWINGS

[0056] Figure 1 A block diagram of a prior art memory device having a memory array with memory cells is shown.

[0057] Figure 2 Demonstrated in the form of 3D NAND memory devices Figure 1 Schematic diagram of a prior art memory device.

[0058] Figure 3 exhibit Figure 2 A cross-sectional view of a prior art 3D NAND memory device in the XX' direction.

[0059] Figure 4 is a schematic diagram of a prior art NAND memory array.

[0060] Figure 5 is a diagrammatic top view of a prior art integrated assembly showing a pair of blocks associated with a semiconductor die.

[0061] Figure 6-10 yes Figure 5 The prior art integrated assembly is divided into two parts: Figure 5 Diagrammatic cross-sectional side view of lines AA, BB, CC, DD and EE.

[0062] Fig.11 is a diagrammatic top view of a prior art integrated assembly showing a pair of blocks associated with a semiconductor die.

[0063] Fig.12 yes Fig.11 The prior art integrated assembly area along Fig.11 Diagrammatic cross-sectional side view of line FF.

[0064] Fig.13 is a diagrammatic top view of an example integrated assembly showing a pair of blocks associated with a semiconductor die.

[0065] Figure 14-18 yes Fig.13 The example integrated assembly area is along Fig.13 Diagrammatic cross-sectional side view of lines AA, BB, CC, DD and EE.

[0066] Fig.19 is a diagrammatic top view of an example integrated assembly showing a pair of blocks associated with a semiconductor die.

[0067] Fig. 20 yes Fig.19 An example of an integrated assembly is shown along the Fig.19 Diagrammatic cross-sectional side view of line FF. DETAILED DESCRIPTION

[0068] Some embodiments include the recognition that the die bending problem described above in the background section may be caused at least in part by stress applied by conductive material within the above-described stack 74 of alternating conductive and insulating levels. Specifically, the conventional die configuration described above in the background section has a greater amount of conductive material per unit area in a region distal to (far from) the memory structures of a memory array than it does (having a greater conductive material density) along the tightly packed memories of the memory array because the tightly packed pillars of channel material separate the conductive material along the tightly packed memories. Some embodiments utilize stress relief regions to separate the conductive material within regions distal to the tightly packed memories, thereby balancing stresses across the semiconductor die and mitigating or even preventing problematic die bending problems. Reference Figure 13-20 to describe example embodiments.

[0069] refer to Figure 13-18 , the integrated assembly 10b is shown as being similar to the above reference Figure 5 The assembly 10b is similar to the configuration described above. Figure 5 The assembly 10 is similar to the assembly 10, but includes one or more stress relief areas. Fig.13 The potential location of the stress relief area is indicated by a dotted box in the top view of the stack 74. The stress relief area extends through the stack 74 (or at least partially through the stack 74) to reduce (and in some applications, even completely avoid) the problematic die bending described above in the background technology section. The stress relief area may alternatively be referred to as a stress design area, and may be formed in a position designed to reduce undesirable stress across the integrated circuit die. The stress design area may be formed into a suitable size and shape to reduce undesirable stress across the integrated circuit die, and may be filled (or at least partially filled) with a material suitable for reducing undesirable stress across the integrated circuit die.

[0070] In some embodiments, integrated assembly 10b may be considered to include a memory array region (e.g., region 32) and one or more regions (e.g., regions 24, 36, and 70) peripheral to the memory array region. A stack 74 of alternating conductive levels 76 and insulating levels 78 (e.g., in Fig.14 74 and any supporting materials associated with the integrated circuit assembly.

[0071] Fig.14 Along Fig.13 The cross section AA of Figure 6 Specifically, in the illustrated embodiment, there is no stress relief area disposed in the inter-block area 22 and 52. In other embodiments (not illustrated), there may be a stress relief area disposed in one or both of the inter-block area 22 and 52.

[0072] Fig.15 It is along Fig.13 BB, and shows an example stress relief region 120 within the intervening region 66. The stress relief region extends completely through the stack 74 (where the conductive level 76 and the insulating level 78 of the stack 74 are at Fig.15 , as such insulating levels have been removed to form stress relief region 120). Stress relief region 120 can be considered to include a trench formed completely through stack 74 (or at least through all conductive levels of stack 74), which is then filled with stress relief material 122.

[0073] Material 122 may include any suitable composition(s). In some embodiments, material 122 may include, consist essentially of, or consist of silicon dioxide. In some embodiments, material 122 may include a combination of silicon and one or more of nitrogen, oxygen, and carbon. For example, material 122 may include, consist essentially of, or consist of a combination of silicon and oxygen, a combination of silicon and carbon, a combination of silicon and nitrogen, a combination of silicon, nitrogen, and carbon, and the like. In some embodiments, a material including a combination of silicon and one or more of nitrogen, oxygen, and carbon may be considered an example of a ceramic composition that can be used in stress relief region 120.

[0074] exist Fig.13 and 15 In the illustrated embodiment of FIG. 1 , support structure 40 extends through stress relief material 122 of stress relief region 120. In some embodiments, support structure 40 can be considered to extend through the full vertical dimension of stack 74 (where conductive level 76 and insulating level 78 of stack 74 are in the vertical dimension). Fig.15is not visible in the view, but in Figure 7 ), and the stress relief region 120 may also be considered to extend through the full vertical dimension of the stack 74. The stress relief material 122 may completely fill the region 120 (as shown), or may only partially fill the region 120.

[0075] The stress relief region 120 may be designed to achieve a desired reduction in the total bending stress across the die of the integrated assembly 10b. Figure 7 ) can significantly reduce the stress across the die. The stress generated by the metal-containing material 80 can be caused by thermally induced expansion / contraction of the conductive material and / or by any other mechanism. Figure 5-10 Compared to the conventional die 10, the area outside the memory array area (e.g., Fig.13 Removing a majority of the metal-containing material from regions 32, 34, 62, and 64) may reduce the overall problematic bending stress associated with semiconductor die 10b.

[0076] Fig.13 The embodiment of FIG. 4 shows the locations of multiple stress relief regions 120 within intervening regions 36 and 66. It should be noted that stress relief regions 120 are separated from each other within intervening regions 36 and 66 by bridge regions 124. The bridge regions enable segments of conductive levels 76 to pass through the intervening regions to interconnect (step) regions 24 and 54.

[0077] The stress relief region 120 in the intermediate regions 36 and 66 may be formed in Fig.13 Additional stress relief regions 130 may be formed within interconnect regions (step regions) 24 and 54. In the embodiment shown, stress relief regions 130 are between separate trenches (e.g., 26 and 28) in the interconnect regions. Fig.16 It is along Fig.13 1 and shows example stress relief regions 130. Such stress relief regions extend through the insulating material 77 of the interconnect region 24, and in the embodiment shown completely through the stack 74 of the conductive level 76 and the insulating level 78. In other embodiments, one or more of the stress relief regions 130 may only partially pass through the stack 74.

[0078] The stress relief region 130 includes a stress relief material 132. The material 132 at least partially fills the stress relief region 130, and in some embodiments may completely fill such stress relief region. This material may include the stress relief material 132 described above with reference to Fig.15 The stress relief material 132 may have any of the compositions described for the stress relief material 122. The stress relief material 132 may have the same composition as the stress relief material 122, or may have a different composition than the stress relief material 122.

[0079] In some embodiments, Fig.13 The interconnect regions 24 and 54 of the embodiment may be considered as the first interconnect region and the second interconnect region, respectively; and the intermediary regions 36 and 66 may be considered as the first intermediary region and the second intermediary region, respectively. The stress relief region 120 within the first intermediary structure 36 may be considered as the first stress relief region, and the stress relief region 120 within the second intermediary structure 66 may be considered as the second stress relief region. The stress relief region 130 within the first interconnect region 24 may be considered as the third stress relief region, and the stress relief region 130 within the second interconnect region 54 may be considered as the fourth stress relief region. The first stress relief region, the second stress relief region, the third stress relief region, and the fourth stress relief region may all include the same stress relief material as each other; or at least one of such stress relief regions may include a different stress relief material relative to another of such stress relief regions.

[0080] Additional stress relief regions 140 may be formed within the peripheral region 70 . Fig.17 It is along Fig.13 DD of FIG. 7 and shows an example stress relief region 140. The example stress relief region 140 extends completely through the stack 74. In other embodiments, the stress relief region 140 may only partially extend through the stack 74.

[0081] The stress relief region 140 includes a stress relief material 142. The material 142 at least partially fills the stress relief region 140, and in some embodiments, may completely fill the stress relief region. The material 142 may include the stress relief material 142 described above. Fig.15 The stress relief material 142 may have any of the compositions described for the stress relief material 122. The stress relief material 142 may have the same composition as the stress relief material 122, or may have a different composition than the stress relief material 122.

[0082] Additional stress relief regions 150 may be formed along routing regions 42 and 68 . Fig.18 It is along Fig.13 EE of the cross-section EE of FIG. 1 and shows an example stress relief region 150. The example stress relief region 150 extends completely through the stack 74. In other embodiments, the stress relief region 150 may only partially extend through the stack 74.

[0083] The stress relief region 150 includes a stress relief material 152. The material 152 at least partially fills the stress relief region 150, and in some embodiments may completely fill such stress relief region. The material 152 may include the stress relief material 152 described above with reference to Fig.15 The stress relief material 152 may have any of the compositions described for the stress relief material 122. The stress relief material 152 may have the same composition as the stress relief material 122, or may have a different composition than the stress relief material 122.

[0084] exist Fig.18 4. In the embodiment shown, the stress relief material 152 extends completely across the routing region 42. In other embodiments, different materials may be within the routing region 42, and the material 152 may be laterally along the routing region 42. For example, in some embodiments, the insulating material 104 ( Fig.10 ) may remain within the wiring region 42, and stress relief material 152 may be formed laterally along this insulating material. Stress relief region 150 may encompass the entirety of one or more of the wiring regions (e.g., 42 and 68), or may include only a portion of one or more of the wiring regions.

[0085] Fig.19 Display and above reference Fig.11 The assembly described herein is similar to the integrated assembly 10c, and shows that one or more additional stress relief regions 160 may be formed along the inter-tile region 16 to remove the block 108 ( Fig.12 ) at least a portion of the conductive material 80 shown in FIG. Fig. 20 Show along Fig.19 FF, and completely replaces block 108 ( Fig.12 ) of the conductive material 80. In the illustrated embodiment, the stress relief region 160 extends completely through the stack 74 ( Fig.12 ). In other embodiments, the stress relief region may only partially extend through the stack. Stress relief material 162 is within stress relief region 160. In the illustrated embodiment, stress relief material 162 completely fills stress relief region 160. In other embodiments, stress relief material 162 may only partially fill stress relief region 160.

[0086] The stress relief material 162 may include the Fig.15 The stress relief material 162 may include any of the compositions described for the stress relief material 122. The stress relief material 162 may include the same composition as the stress relief material 122, or may include a different composition relative to the stress relief material 122.

[0087] Relative to Fig.19 The configuration 10c shows rather than relative to Fig.13 The configuration 10b shows the stress relief area 160 in order to simplify the description of the stress relief area 160. However, it should be understood that the stress relief area 162 can be Fig.13 Any combination of the stress relief areas 120 , 130 , 140 and 150 is utilized.

[0088] Any of the above-mentioned stress relief materials 122, 132, 142, 152 and 162 may include the same composition as each other, or may include different compositions relative to each other. Moreover, any of the stress relief areas 120, 130, 140, 150 and 160 may be utilized alone or in combination with one or more other of the stress relief areas. In some embodiments, it should be recognized that it may be advantageous to remove Figure 5-12 The term "excess conductive material" refers to conductive material 80 that is not used for word line routing within the memory array region (e.g., 32) and is not used to couple to interconnects within the interconnect region (e.g., 24).

[0089] The total combined area of ​​the stress relief region(s) utilized with respect to the semiconductor die (i.e., one or more of regions 120, 130, 140, 150, and 160) can be comparable to the total size of the memory array region(s) associated with the die. For example, the total combined area of ​​the stress relief region(s) can be at least 5% of the total area of ​​the memory array region(s), at least about 10% of the total area of ​​the memory array region(s), at least about 20% of the total area of ​​the memory array region(s), etc. For example, in Fig.13 and 19 In the embodiment of the present invention, memory array regions 32, 34, 62, and 64 can be considered together to have a total combined area. Stress relief regions 120, 130, 140, 150, and 160 can be considered together to have another total combined area. The total combined area of ​​the stress relief regions can be at least 5% of the total area of ​​the memory array regions, at least about 10% of the total area of ​​the memory array regions, at least about 20% of the total area of ​​the memory array regions, etc.

[0090] In some embodiments, wiring regions 42 and 68 may be considered to be within memory array regions 32, 34, 62, and 64; and thus stress relief region 150 may also be considered to be within memory array regions 32, 34, 62, and 64. In contrast, other stress relief regions 120, 130, 140, and 160 are not within the memory array region (i.e., are outside the memory array region).

[0091] Although the stress relief materials 122, 132, 142, 152, and 162 are shown as Figure 13-20 In some embodiments, the stress relief material may include a liner along the outer periphery of the stress relief zone, and may include a filler within the liner. The filler and liner may include different compositions relative to each other, or may include the same composition as each other.

[0092] The assemblies and structures discussed above may be used within integrated circuits (where the term "integrated circuit" refers to an electronic circuit supported by a semiconductor substrate); and may be incorporated into electronic systems. Such electronic systems may be used, for example, in memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and may include multi-layer, multi-chip modules. The electronic system may be any of a wide range of systems, such as, for example, cameras, wireless devices, displays, chipsets, set-top boxes, game consoles, lighting devices, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0093] Unless otherwise specified, the various materials, substances, compositions, etc. described herein may be formed using any suitable method now known or yet to be developed, including, for example, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), etc.

[0094] The terms "dielectric" and "insulating" may be used to describe materials with insulating electrical properties. In the present invention, the terms are considered synonymous. The use of the term "dielectric" in some examples and the term "insulating" (or "electrically insulating") in other examples may provide language changes within the present invention to simplify the preamble basis within the appended claims and is not intended to indicate any significant chemical or electrical differences.

[0095] The terms "electrically connected" and "electrically coupled" may both be used in the present invention. The terms are considered synonymous. The use of one term in some instances and another term in other instances may provide language changes within the present invention to simplify the preamble basis within the appended claims.

[0096] The specific orientations of the various embodiments in the drawings are for illustrative purposes only, and in some applications the embodiments may be rotated relative to the orientation shown. The description provided herein and the appended claims are directed to any structure having the described relationships between the various features, whether the structure is in a specific orientation of the drawings or rotated relative to such orientation.

[0097] Unless otherwise indicated, the cross-sectional views of the accompanying illustrations show only features within the plane of the cross-section and not material behind the plane of the cross-section in order to simplify the drawings.

[0098] When a structure is referred to above as being "on another structure," "adjacent to another structure," or "against another structure," the structure may be directly on the other structure or there may also be intervening structures. In contrast, when a structure is referred to as being "directly on another structure," "directly adjacent to another structure," or "directly against another structure," there are no intervening structures. The terms "directly below," "directly above," and the like do not indicate direct physical contact (unless expressly stated otherwise), but rather indicate upright alignment.

[0099] A structure (e.g., layer, material, etc.) may be referred to as "vertically extending" to indicate that the structure generally extends upward from an underlying base (e.g., substrate). A vertically extending structure may extend substantially orthogonally to the upper surface of the base, or may extend non-orthogonally to the upper surface of the base.

[0100] Some embodiments include an integrated assembly having a semiconductor die having one or more memory array regions and one or more regions peripheral to the one or more memory array regions. The one or more memory array regions have a total area. A stack of alternating insulating and conductive levels extends across the one or more memory array regions and into at least one of the regions peripheral to the one or more memory array regions. The stack creates bending stress on the die. At least one stress relief region extends through the stack and is configured to relieve the bending stress. All of the stress relief regions have a total area of ​​at least about 5% of the total area of ​​the one or more memory array regions.

[0101] Some embodiments include an integrated assembly comprising a semiconductor die having a first memory device tile adjacent to a second memory device tile. The first memory device tile and the second memory device tile are separated from each other by an inter-tile region. The first memory device tile has a first memory array region, and the second memory device tile has a second memory array region. A stack of alternating insulating levels and conductive levels extends across the first memory array region and the second memory array region. A segment of the stack is within the inter-tile region. The stack generates bending stress on the die. A stress relief region extends through the segment of the stack and is filled with a stress relief material.

[0102] Some embodiments include an integrated assembly comprising a semiconductor die having a memory array region. A stack of alternating insulating levels and conductive levels extends across the memory array region. An interconnect region is adjacent to the memory array region and is configured to establish connections with the individual conductive levels of the stack. An intermediary region is between the interconnect region and the memory array region. A first stress relief region is within the intermediary region. A second stress relief region is within the interconnect region. The first stress relief region and the second stress relief region extend through the stack and are filled with stress relief material. The stress relief material includes silicon and one or more of nitrogen, carbon, and oxygen.

[0103] In compliance with the statute, the subject matter disclosed herein has been described in language more or less specific to structural and methodological features. However, it should be understood that the claims are not limited to the specific features shown and described, as the components disclosed herein include example embodiments. Therefore, the claims should be given their full scope in a literal sense and should be appropriately interpreted in accordance with the doctrine of equivalents.

Claims

1. An integrated assembly comprising: a memory array region extending through a portion of the die, the memory array region comprising a stack of alternating insulating and conductive levels; The stacking generates bending stress on the die; as well as one or more stress relief regions extending through the stack and configured to relieve the bending stress; The one or more stress relief regions collectively have an area that is at least about 5% of a total area of ​​the memory array region.

2. The integrated assembly of claim 1 wherein at least one of the stress relief regions is within the memory array region.

3. The integrated assembly of claim 1 wherein at least one of the stress relief regions is not within the memory array region.

4. The integrated assembly of claim 1, wherein at least one of the stress relief regions is filled with a stress relief material.

5. The integrated assembly of claim 4, wherein the stress relief material comprises silicon dioxide.

6. The integrated assembly of claim 4, wherein the stress relief material comprises a ceramic composition.

7. The integrated assembly of claim 6, wherein the ceramic composition comprises silicon and one or more of nitrogen, oxygen, and carbon.

8. The integrated assembly of claim 1 wherein the area of ​​the one or more stress relief regions is at least about 10% of the total area of ​​the memory array area.

9. The integrated assembly of claim 1 wherein the area of ​​the one or more stress relief regions is at least about 20% of the total area of ​​the memory array area.

10. The integrated assembly of claim 1, wherein the conductive level comprises a metal.

11. The integrated assembly of claim 1 wherein the conductive level comprises tungsten.

12. The integrated assembly of claim 1, wherein at least one of the stress relief regions is only partially filled with stress relief material.

13. The integrated assembly of claim 1, wherein the one or more stress relief regions include a first relief region and a second relief region, the first relief region being different from the second relief region.

14. The integrated assembly of claim 13, wherein the difference between the first relief region and the second relief region comprises different stress relief materials in each stress relief region.

15. The integrated assembly of claim 13, wherein the difference between the first relief region and the second relief region comprises one of the first relief region and the second relief region being only partially filled with stress relief material.

16. The integrated assembly of claim 13, wherein the difference between the first relief area and the second relief area comprises one of the first relief area and the second relief area being completely filled with stress relief material.

Images