Semiconductor device and method of manufacturing semiconductor device

Abstract

The invention relates to a semiconductor device and a method of manufacturing the same. A semiconductor device may include a first electrode, a second electrode, a variable resistance layer between the first electrode and the second electrode and maintaining a phase before and after a programming operation, a non-conductive sealing layer between the first electrode and the variable resistance layer, and a nanostructure inside the non-conductive sealing layer and spaced apart from the variable resistance layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0116007, filed on September 1, 2023, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to an electronic device, and more particularly, to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0004] Recently, with the miniaturization, low power consumption, high performance and diversification of electronic devices, semiconductor devices capable of storing information in a variety of electronic devices such as computers and portable communication devices are desired. Therefore, semiconductor devices capable of storing data using the characteristic of switching between different resistance states according to an applied voltage or current are being studied. Semiconductor devices may include resistive random access memory (RRAM), phase change random access memory (PRAM), ferroelectric random access memory (FRAM), magnetic random access memory (MRAM), electric fuses, etc. Summary of the invention

[0005] According to an embodiment of the present disclosure, a semiconductor device may include: a first electrode; a second electrode; a variable resistance layer located between the first electrode and the second electrode and maintaining a phase before and after a programming operation; a non-conductive sealing layer located between the first electrode and the variable resistance layer; and a nanostructure located inside the non-conductive sealing layer and spaced apart from the variable resistance layer.

[0006] According to an embodiment of the present disclosure, a semiconductor device may include: a first electrode; a second electrode; a variable resistance layer located between the first electrode and the second electrode and maintaining a phase before and after a programming operation; nanodots located on a surface of the first electrode; and a non-conductive sealing layer surrounding the nanodots and extending between the first electrode and the variable resistance layer and between the nanodots and the variable resistance layer.

[0007] According to an embodiment of the present disclosure, a method for manufacturing a semiconductor device may include: forming a first electrode; forming a nanostructure on the first electrode; forming a non-conductive sealing layer on the first electrode to surround the nanostructure; forming a variable resistance layer on the non-conductive sealing layer; and forming a second electrode on the variable resistance layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a diagram showing the structure of a semiconductor device according to an embodiment of the present disclosure.

[0009] Figure 2 is a diagram showing the structure of a semiconductor device according to an embodiment of the present disclosure.

[0010] Figure 3 is a diagram showing the structure of a semiconductor device according to an embodiment of the present disclosure.

[0011] Figure 4A and Figure 4B are diagrams each showing a structure of a semiconductor device according to an embodiment of the present disclosure.

[0012] Figure 5A and Figure 5B 1 and 2 are diagrams each illustrating the operation of the semiconductor device according to an embodiment of the present disclosure.

[0013] Fig. 6A , Figure 6B and Figure 6C is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure.

[0014] Fig. 7A , Figure 7B , Figure 7C and Fig.7D is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0015] Embodiments of the present disclosure provide a semiconductor device having a stable structure and improved characteristics and a method of manufacturing the semiconductor device.

[0016] The integration degree of a semiconductor device can be increased by stacking memory cells in three dimensions. In addition, a semiconductor device having a stable structure and improved reliability can be provided.

[0017] As used herein, "at least one of ... and ..." represents a disjunctive list of each item and possible combinations. For example, "at least one of A and B" means "only A, or only B, or both A and B", and "at least one of A, B, and C" means "only A, or only B, only C, or both A and B, or both A and C, or both B and C, or all of A, B, and C", etc. Hereinafter, embodiments according to the technical spirit of the present disclosure are described with reference to the accompanying drawings.

[0018] Figure 1 is a diagram showing the structure of a semiconductor device according to an embodiment of the present disclosure.

[0019] Reference Figure 1 , the semiconductor device according to the embodiment of the present disclosure may include at least one first access line 11, at least one second access line 12, or at least one first memory cell MC1, or may include +a combination thereof.

[0020] The first access line 11 may extend in a first direction I. The second access line 12 may extend in a second direction II intersecting the first direction I. The first access line 11 and the second access line 12 may be stacked in a third direction III. The third direction III may be a direction orthogonal to a plane defined by the first direction I and the second direction II. The first access line 11 and the second access line 12 may be word lines or bit lines. As an embodiment, the first access line 11 may be a word line, and the second access line 12 may be a bit line. Alternatively, the first access line 11 may be a bit line, and the second access line 12 may be a word line.

[0021] The first memory cell MC1 may be located in a region where the first access line 11 and the second access line 12 cross. The first memory cell MC1 may be arranged along the first direction I and the second direction II. The first memory cell MC1 may be connected between the first access line 11 and the second access line 12.

[0022] The first memory cell MC1 may include at least one of a first electrode 14, a second electrode 16, a variable resistance layer 15, and a sealing layer 17. The variable resistance layer 15 may be located between the first electrode 14 and the second electrode 16. The first electrode 14 may be electrically connected to the first access line 11. The second electrode 16 may be electrically connected to the second access line 12. For reference, the first memory cell MC1 may include a switching layer instead of the variable resistance layer 15, or may include a switching layer in addition to the variable resistance layer 15.

[0023] The sealing layer 17 may include a nanostructure therein, and the nanostructure may be sealed so that the nanostructure does not contact the variable resistance layer 15. The sealing layer 17 may be located in a first region between the first electrode 14 and the variable resistance layer 15, or in a second region between the second electrode 16 and the variable resistance layer 15. In some embodiments, the sealing layer 17 and an additional sealing layer (not shown) having a similar construction to the sealing layer 17 and including the same material as the sealing layer 17 may be located in the first region and the second region, respectively. As an embodiment, the first electrode 14, the sealing layer 17, the variable resistance layer 15, and the second electrode 16 may be stacked in a third direction III. In this case, the nanostructure may be in contact with the first electrode 14 and may be used as an electrode together with the first electrode 14. Specifically, the nanostructure (e.g., nanodots) may have a sufficiently high conductivity to be used as a single integrated electrode together with the first electrode 14. As an embodiment, the first electrode 14, the variable resistance layer 15, the sealing layer 17, and the second electrode 16 may be stacked in a third direction III. In this case, the nanostructure may be in contact with the second electrode 16 and may be used as an electrode together with the second electrode 16.

[0024] In addition, although not shown in the figure, the semiconductor device may further include a circuit for controlling the first access line 11 and the second access line 12. As an embodiment, the semiconductor device may include a first circuit, such as a word line decoder or a word line driver. The first circuit may select a first access line on which a programming operation will be performed according to a row address. The semiconductor device may include a second circuit such as a bit line decoder and a bit line driver. The second circuit may select a second access line on which a programming operation will be performed according to a column address. During the programming operation, a first memory cell MC1 connected between the selected first access line 11 and the selected second access line 12 may be selected.

[0025] According to the above structure, the first memory cell MC1 may include the sealing layer 17, and the nanostructure may be located in the sealing layer 17. The effective areas of the first electrode 14 and the second electrode 16 may be different according to the nanostructure, and the first memory cell MC1 may have an asymmetric electrode structure. Therefore, the programming window may be increased and the programming speed may be improved.

[0026] Figure 2 2 is a diagram showing a structure of a semiconductor device according to an embodiment of the present disclosure. In the following, for the sake of brevity, contents overlapping with the above contents may be omitted.

[0027] Reference Figure 2 The semiconductor device may include at least one of at least one first access line 21 , at least one second access line 22 , at least one second memory cell MC2 , and at least one insulating layer 23 .

[0028] The first access line 21 may be alternately stacked with the insulating layer 23. The second access line 22 may pass through the first access line 21. As an embodiment, the second access line 22 may extend through the first access line 21 and the insulating layer 23 in a vertical direction. The second access line 22 may have a columnar shape, and may have a cross-section of a circle, an ellipse, a polygon, etc. in a plane. The first access line 21 and the second access line 22 may be word lines or bit lines. As an embodiment, the first access line 21 may be a word line, and the second access line 22 may be a bit line. Alternatively, the first access line 21 may be a bit line, and the second access line 22 may be a word line.

[0029] The second memory cell MC2 may be connected between the first access line 21 and the second access line 22. The second memory cell MC2 may be located in a region where the first access line 21 and the second access line 22 cross. The second memory cell MC2 may be stacked along the second access line 22. The stacked second memory cells MC2 may share the second access line 22, the first electrode 24, the second electrode 26, the variable resistance layer 25, and the sealing layer 27.

[0030] The second memory cell MC2 may include at least one of a first electrode 24, a second electrode 26, a variable resistance layer 25, and a sealing layer 27. The first electrode 24, the variable resistance layer 25, the second electrode 26, and the sealing layer 27 may surround the sidewall of the second access line 22. The variable resistance layer 25 may be located between the first electrode 24 and the second electrode 26. The sealing layer 27 may include a nanostructure. The sealing layer 27 may be located in a first region between the first electrode 24 and the variable resistance layer 25, or may be located in a second region between the second electrode 26 and the variable resistance layer 25. In some embodiments, the sealing layer 27 and an additional sealing layer (not shown) having a similar configuration to the sealing layer 27 and including the same material as the sealing layer 27 may be located in the first region and the second region, respectively.

[0031] According to the above structure, the second memory cell MC2 may include the sealing layer 27, and the nanostructure may be located inside the sealing layer 27. The second memory cell MC2 may have an asymmetric electrode structure caused by the nanostructure. Therefore, the programming window may be increased and the programming speed may be improved.

[0032] Figure 3 2 is a diagram showing a structure of a semiconductor device according to an embodiment of the present disclosure. In the following, for the sake of brevity, contents overlapping with the above contents may be omitted.

[0033] Reference Figure 3 The semiconductor device may include at least one of at least one first access line 31 , at least one second access line 32 , at least one third memory cell MC3 , and at least one insulating layer 33 .

[0034] The first access line 31 may be alternately stacked with the insulating layer 33. The second access line 32 may pass through the first access line 31. As an embodiment, the second access line 32 may extend through the first access line 31 and the insulating layer 33 in the vertical direction. The second access line 32 may have a columnar shape, and may have a cross-section of a circle, an ellipse, a polygon, etc. in a plane. The first access line 31 and the second access line 32 may be word lines or bit lines. As an embodiment, the first access line 31 may be a word line, and the second access line 32 may be a bit line. Alternatively, the first access line 31 may be a bit line, and the second access line 32 may be a word line.

[0035] The third memory cell MC3 may be connected between the first access line 31 and the second access line 32. The third memory cell MC3 may be located in a region where the first access line 31 and the second access line 32 cross. The third memory cell MC3 may be stacked along the second access line 32, and the stacked third memory cell MC3 may share the second access line 32.

[0036] The third memory cell MC3 may include at least one of a first electrode 34, a second electrode 36, a variable resistance layer 35, and a sealing layer 37. The first electrode 34, the variable resistance layer 35, the second electrode 36, and the sealing layer 37 may partially surround the sidewall of the second access line 32. The first electrode 34, the second electrode 36, the variable resistance layer 35, and the sealing layer 37 may have a ring shape and may be located between the stacked insulating layers 33. The variable resistance layer 35 may be located between the first electrode 34 and the second electrode 36. The sealing layer 37 may include a nanostructure. The sealing layer 37 may be located in a first region between the first electrode 34 and the variable resistance layer 35, or may be located in a second region between the second electrode 36 and the variable resistance layer 35. In some embodiments, the sealing layer 37 and an additional sealing layer (not shown) having a similar configuration to the sealing layer 37 and including the same material as the sealing layer 37 may be located in the first region and the second region, respectively.

[0037] According to the above structure, the third memory cell MC3 may include the sealing layer 37, and the nanostructure may be located inside the sealing layer 37. The third memory cell MC3 may have an asymmetric electrode structure caused by the nanostructure. Therefore, the programming window may be increased and the programming speed may be improved.

[0038] Figure 4A and Figure 4B 1 and 2 are diagrams each showing a structure of a semiconductor device according to an embodiment of the present disclosure. In the following, for the sake of brevity, contents overlapping with the above contents may be omitted.

[0039] Reference Figure 4A , the semiconductor device may include a first access line L1, a second access line L2, and a memory cell MC. The memory cell MC may be connected between the first access line L1 and the second access line L2. The memory cell MC may include a first electrode 44, a variable resistance layer 45, a second electrode 46, a sealing layer 47, and a nanostructure N.

[0040] The variable resistance layer 45 may be located between the first electrode 44 and the second electrode 46. The variable resistance layer 45 may have a characteristic of reversibly transforming between different resistance states according to a voltage or current applied to the memory cell MC. As an embodiment, when the variable resistance layer 45 has a low resistance state, data having a first value (e.g., a logic high level "1") may be stored, and when the variable resistance layer 45 has a high resistance state, a value having a second value (e.g., a logic low level "0") may be stored.

[0041] As an embodiment, the variable resistance layer 45 may include a resistance material. Data may be stored by causing an electrical path to be generated or eliminated within the variable resistance layer 45. As an embodiment, the variable resistance layer 45 may include a transition metal oxide or a metal oxide, such as a perovskite-based material.

[0042] As an embodiment, the variable resistance layer 45 may have an MTJ structure including a magnetization pinned layer, a tunnel barrier layer, and a magnetization free layer. Data may be stored according to a change in the magnetization direction of the magnetization free layer relative to the magnetization direction of the magnetization pinned layer. As an embodiment, the magnetization pinned layer and the magnetization free layer may include a magnetic material, and the tunnel barrier layer may include a metal oxide.

[0043] As an embodiment, the variable resistance layer 45 may include a phase change material or may include a chalcogenide-based material. The variable resistance layer 45 may change the phase according to a programming operation. As an embodiment, the variable resistance layer 45 may have a crystalline state with low resistance by a set operation. As an embodiment, the variable resistance layer 45 may have an amorphous state with high resistance by a reset operation. Therefore, data may be stored in a memory cell by using a resistance difference according to the phase of the variable resistance layer 45.

[0044] As an embodiment, the variable resistance layer 45 may include a variable resistance material whose resistance changes without phase change. For example, the variable resistance layer 45 may include a chalcogenide-based material. The variable resistance layer 45 may be used as a storage element and a selection element at the same time. The variable resistance layer 45 may maintain an image before and after a programming operation. As an embodiment, the variable resistance layer 45 may have an amorphous state and may remain in an amorphous state without changing to a crystalline state after a programming operation. According to a programming voltage applied to the memory cell, elements in the chalcogenide material may migrate and the composition of the chalcogenide material may change. Therefore, the threshold voltage of the memory cell may be changed, and the memory cell may be programmed to at least two states. As an embodiment, a memory cell may be programmed to a set state or a reset state using programming voltages of different polarities. Therefore, data may be stored in the memory cell by utilizing the threshold voltage difference of the memory cell. For reference, the memory cell MC may additionally include a selection element.

[0045] The sealing layer 47 may be located between the first electrode 44 and the variable resistance layer 45. The nanostructure N may be located inside the sealing layer 47. The nanostructure N may include a structure having a size of several nanometers (nm), such as nanodots, nanorods, nanowires, nanotubes, or nanosheets. The nanostructure N may be located on the surface of the first electrode 44. The nanostructure N may include a conductive material. As an embodiment, the nanostructure N may include at least one of nickel (Ni), silver (Ag), platinum (Pt), gold (Au), copper (Cu), and aluminum (Al). The nanostructure N may be in contact with the first electrode 44 and may be electrically connected to the first electrode 44. The nanostructure N may be used as an electrode together with the first electrode 44.

[0046] The sealing layer 47 may surround the nanostructure N and fill between the first electrode 44 and the variable resistance layer 45 and between the nanostructure N and the variable resistance layer 45. The nanostructure N and the variable resistance layer 45 may be separated by the sealing layer 47. In other words, the nanostructure N may be embedded in the sealing layer 47 so that the nanostructure N contacts the first electrode 44 and is spaced apart from the variable resistance layer 45. The sealing layer 47 may include a non-conductive material. As an embodiment, the sealing layer 47 may include at least one of an oxide, a nitride, and carbon.

[0047] The thermal conductivity of the sealing layer 47 may be related to heat loss occurring during a programming operation. During a programming operation, when a bias voltage is applied to the first electrode 44 and the second electrode 46 and a current flows through the memory cell MC, Joule heating may occur. When a programming operation is performed using a change in the composition of a chalcogenide material, the speed of element movement may be increased and the programming speed may be increased by reducing heat loss.

[0048] When the sealing layer 47 has a relatively high thermal conductivity (such as aluminum oxide Al2O3), the heat generated during the programming operation can be dissipated to the surrounding environment. In this case, the resistance change of the variable resistance layer 45 can be slowed down, and the speed of the programming operation can be reduced. Therefore, the sealing layer 47 may include a material with a relatively low thermal conductivity to reduce heat loss during the programming operation. Specifically, when the sealing layer 47 includes a material with a relatively low thermal conductivity, the sealing layer 47 provides a relatively high thermal resistance to reduce heat loss to the surrounding environment during the programming operation, resulting in a relatively high temperature in the variable resistance layer 45. Such a relatively high temperature can facilitate ion migration of one or more elements in the variable resistance layer 45 to increase the speed of the programming operation. For example, the sealing layer 47 may include a material with a thermal conductivity of less than 20W / mK. As an embodiment, the sealing layer 47 may include an oxide and may include Fe x O y 、SiO x and TiO x The sealing layer 47 may include a non-oxide and may include BN x , graphene and SiN x At least one of .

[0049] For reference, when a programming operation is performed using a phase change of a chalcogenide material, a set operation including a melting process can be improved by reducing heat loss, but a reset operation including a quenching process may be deteriorated due to reduced heat loss. Therefore, the sealing material may be determined in consideration of the material of the variable resistance layer 45, the operating principle of the memory cell, the dielectric constant, etc.

[0050] The sealing layer 47 may be a diffusion barrier layer. The sealing layer 47 may significantly reduce material movement between the first electrode 44, the variable resistance layer 45, and the second electrode 46. Diffusion of metals included in the first electrode 44 and the second electrode 46 to the variable resistance layer 45 may be reduced, and diffusion of elements of the variable resistance layer 45 to the first electrode 44 or the second electrode 46 may be reduced. Therefore, reliability may be improved.

[0051] The first electrode 44 may be electrically connected to the first access line L1, and the second electrode 46 may be electrically connected to the second access line L2. The first electrode 44 and the second electrode 46 may include a conductive material such as polysilicon or a metal. As an example, the first electrode 44 and the second electrode 46 may include polysilicon, tungsten (W), tungsten nitride (WN x ), tungsten silicide (WSi x ), titanium (Ti), titanium nitride (TiN x ), titanium silicon nitride (TiSiN), titanium aluminum nitride (TiAlN), tantalum (Ta), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum aluminum nitride (TaAlN), carbon (C), silicon carbide (SiC), silicon carbonitride (SiCN), copper (Cu), zinc (Zn), nickel (Ni), cobalt (Co), lead (Pd), platinum (Pt), molybdenum (Mo), ruthenium (Ru), etc., and may include combinations thereof. The first electrode 44 and the second electrode 46 may include the same material or may include different materials. As an embodiment, the first electrode 44 and the second electrode 46 may be carbon electrodes.

[0052] Reference Figure 4B , the semiconductor device may include a first access line L1, a second access line L2, and a memory cell MC. The memory cell MC may be connected between the first access line L1 and the second access line L2. The memory cell MC may include a first electrode 44, a variable resistance layer 45, a second electrode 46, a sealing layer 47, and a nanostructure N.

[0053] The sealing layer 47 may be located between the variable resistance layer 45 and the second electrode 46, and the nanostructure N may be located in the sealing layer 47. The sealing layer 47 may surround the nanostructure N and fill between the second electrode 46 and the variable resistance layer 45 and between the nanostructure N and the variable resistance layer 45. The nanostructure N and the variable resistance layer 45 may be separated by the sealing layer 47. In other words, the nanostructure N may be embedded in the sealing layer 47 so that the nanostructure N contacts the second electrode 46 and is spaced apart from the variable resistance layer 45.

[0054] According to the above structure, the sealing layer 47 may be located in the first region between the first electrode 44 and the variable resistance layer 45, or in the second region between the second electrode 46 and the variable resistance layer 45. In some embodiments, Figure 4AThe sealing layer 47 and Figure 4B The sealing layer 47 in the embodiment may be located in the first region and the second region, respectively. The sealing layer 47 may reduce material movement between the first electrode 44, the variable resistance layer 45, and the second electrode 46, and may improve reliability.

[0055] The nanostructure N may be located inside the sealing layer 47, and the nanostructure N may contact at least one of the first electrode 44 and the second electrode 46. Due to the nanostructure N, the memory cell MC may have an asymmetric electrode structure, a programming window may be increased, and a programming speed may be improved.

[0056] Figure 5A and Figure 5B 2 is a diagram illustrating the operation of a semiconductor device according to an embodiment of the present disclosure. Figure 5B yes Figure 5A Hereinafter, for the sake of brevity, the contents overlapping with the above contents may be omitted.

[0057] Reference Figure 5A , the semiconductor device may include at least one of a first electrode E1, a second electrode E2, a variable resistance layer 55, a sealing layer 57, and a nanostructure N. During a programming operation, biases of different polarities may be applied to the first electrode E1 and the second electrode E2 through the first access line L1 and the second access line L2. As an embodiment, during a reset operation, a negative (-) bias may be applied to the first electrode E1, and a positive (+) bias may be applied to the second electrode E2. As an embodiment, during a set operation, a positive (+) bias may be applied to the first electrode E1, and a negative (-) bias may be applied to the second electrode E2.

[0058] Reference Figure 5B, due to the nanostructure N, the effective area of ​​the first electrode E1 may be smaller than the effective area of ​​the second electrode E2. As an embodiment, after manufacturing the semiconductor device, a firing voltage for activating the memory cell MC may be applied to the first electrode E1 and the second electrode E2. Due to the firing voltage, a breakdown of the sealing material between the nanostructure N and the variable resistance layer 55 may be caused, and an effective current path EC in a filamentary form may be formed in the sealing layer 57. Therefore, an effective area of ​​the first electrode E1 having a size of several nanometers corresponding to the area of ​​the nanostructure N may be formed. Since the effective area of ​​the first electrode E1 is reduced by the nanostructure N, the memory cell MC may have an asymmetric electrode structure. For example, when the nanostructure N and the first electrode E1 are used together as a single integrated electrode, the effective current path EC may be formed on the area of ​​the nanostructure N, and the area of ​​the nanostructure N may be used as the first effective area of ​​the single integrated electrode. The first effective area of ​​the single integrated electrode may be smaller than the second effective area of ​​the second electrode E2, on which the active area AC of the variable resistance layer 55 is formed. As a result, a concentrated large electric field may be formed on the first active area of ​​the single integrated electrode to assist ion migration of one or more elements in the variable resistance layer 55, thereby increasing the speed of a programming operation.

[0059] Since the memory cell MC has an asymmetric electrode structure, the variable resistance layer 55 may include an active area AC and an inactive area IN. During a programming operation, movement of an element may be caused in the active area AC, and the element may not move or a relatively small amount of the element may move in the inactive area IN. As an embodiment, selenium ions may move in the active area AC. Since the electric field is concentrated on a small area of ​​the nanostructure N, the movement of the selenium ions may be accelerated and the programming speed may be increased. During a reset operation, selenium ions may increase rapidly around the nanostructure N. Ion crowding may increase the composition variation of the variable resistance layer 55 and increase the threshold voltage difference between the set state and the reset state. Therefore, the memory window may be increased.

[0060] FIG. 6A to FIG. 6C 2 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. In the following, for the sake of brevity, contents overlapping with the above contents may be omitted.

[0061] Reference Fig. 6A, a first electrode 61 may be formed. Subsequently, a nanostructure 62 may be formed on the first electrode 61. The nanostructure 62 may be located on the surface of the first electrode 61 and may be electrically connected to the first electrode 61. As an embodiment, the nanostructure 62 may be formed by an island growth method using sputtering, atomic layer deposition ALD, etc. The nanostructure 62 may include a structure having a size of several nanometers (nm), such as nanodots, nanorods, nanowires, nanotubes, or nanosheets. The nanostructure 62 may include a conductive material. As an embodiment, the nanostructure 62 may include at least one of nickel (Ni), silver (Ag), platinum (Pt), gold (Au), copper (Cu), and aluminum (Al).

[0062] refer to Figure 6B , a sealing layer 63 may be formed. The sealing layer 63 may be formed on the first electrode 61 to surround the nanostructure 62. As an embodiment, the sealing layer 63 may be formed to fill the space between the nanodots and surround each nanodot. The nanostructure 62 may be located inside the sealing layer 63 and substantially completely covered by the sealing layer 63. The sealing layer 63 may include a non-conductive material. As an embodiment, the sealing layer 63 may include at least one of an oxide, a nitride, and carbon. The sealing layer 63 may include a material having a relatively low thermal conductivity. The sealing layer 63 may include a material having a thermal conductivity of less than 20 W / mK. As an embodiment, the sealing layer 63 may include Fe x O y 、SiO x 、TiO x , BN x , graphene and SiN x The sealing layer 63 may be a diffusion barrier layer.

[0063] Reference Figure 6C , the variable resistance layer 64 may be formed on the sealing layer 63. The variable resistance layer 64 may include at least one of a transition metal oxide, a perovskite-based material, an MTJ structure, and a chalcogenide material. The variable resistance layer 64 may change phase or maintain phase before or after a programming operation. As an embodiment, the variable resistance layer 64 may remain amorphous before and after a programming operation. Subsequently, a second electrode 65 may be formed on the variable resistance layer 64.

[0064] Subsequently, after the manufacture of the semiconductor device is completed, an excitation voltage may be applied to the first electrode 61 and the second electrode 65. Therefore, an effective area of ​​the first electrode 61 may be reduced, and a memory cell having an asymmetric electrode structure may be formed.

[0065] According to the above manufacturing method, the nanostructure 62 may be formed on the surface of the first electrode 61, and the nanostructure 62 may be sealed with the sealing layer 63. Therefore, a memory cell including the first electrode 61 and the second electrode 65 having different effective areas may be formed.

[0066] FIG. 7A to FIG. 7D is a diagram illustrating a method of manufacturing a semiconductor device according to an embodiment of the present disclosure. Fig. 7A It can be a floor plan, Figure 7B and Figure 7C Can be along Fig. 7A A cross-sectional view taken along line AA' of Fig.7D Can be along Fig. 7A Hereinafter, for the sake of brevity, contents overlapping with the above contents may be omitted.

[0067] Reference Figure 7B , a first conductive layer 71 may be formed. The first conductive layer 71 may be suitable for forming the first access line L1 and may include a metal such as tungsten.

[0068] Subsequently, a stack structure (or stack) ST may be formed on the first conductive layer 71. The stack ST may include at least one of a first electrode layer 72, a sealing layer (or initial sealing layer) 73, a variable resistance layer (or initial variable resistance layer) 74, and a second electrode layer 75. The stacking order of the layers included in the stack ST may be changed.

[0069] The sealing layer 73 may be located in a first region between the first electrode layer 72 and the variable resistance layer 74, or may be located in a second region between the variable resistance layer 74 and the second electrode layer 75. In some embodiments, the sealing layer 73 and an additional sealing layer (not shown) having a similar configuration to the sealing layer 73 and including the same material as the sealing layer 73 may be located in the first region and the second region, respectively. The nanostructure may be located inside the sealing layer 73. As an embodiment, the nanostructure may be located on the surface of the first electrode layer 72 and may be electrically connected to the first electrode layer 72. The sealing layer 73 may include a non-conductive material. As an embodiment, the sealing layer 73 may include at least one of an oxide, a nitride, and carbon. The sealing layer 73 may include a material having a relatively low thermal conductivity. The sealing layer 73 may include a material having a thermal conductivity of less than 20 W / mK. As an embodiment, the sealing layer 73 may include Fe x O y 、SiO x 、TiO x , BN x , graphene and SiN x The sealing layer 73 may be a diffusion barrier layer that reduces material movement between the first electrode layer 72 , the variable resistance layer 74 , and the second electrode layer 75 .

[0070] Reference Figure 7C , a first access line 71A and a cell pattern CP may be formed. As an embodiment, the cell pattern CP may be formed by etching the stack ST using a mask pattern as an etching barrier. Each cell pattern CP may include a first electrode layer 72', a sealing layer 73', a variable resistance layer 74', and a second electrode layer 75'. The first conductive layer 71 may be etched to form a first access line 71A. The first access line 71A and the cell pattern CP may extend in a first direction I. Subsequently, a first insulating layer 76 may be formed between the cell patterns CP and between the first access lines 71A.

[0071] Subsequently, a second conductive layer 77 may be formed on the cell pattern CP and the first insulating layer 76. The second conductive layer 77 may be suitable for forming the second access line L2 and may include a metal such as tungsten.

[0072] Reference Fig.7D , the second conductive layer 77 may be etched to form a second access line 77A, and the second access line 77A extends in a second direction II intersecting the first direction I. Subsequently, the cell pattern CP and the first insulating layer 76 may be etched to form memory cells MC. Each memory cell MC may include a first electrode 72A, a sealing layer 73A, a variable resistance layer 74A, and a second electrode 75A. The memory cells MC may be located in the intersection region of the first access line 71A and the second access line 77A, respectively. Subsequently, a second insulating layer 78 may be formed between the memory cells MC and between the second access lines 77A.

[0073] According to the above-described manufacturing method, a memory cell MC having an asymmetric electrode structure caused by a nanostructure can be formed. Therefore, a programming window can be increased and a programming speed can be improved.

[0074] Although the embodiments according to the technical spirit of the present disclosure have been described with reference to the accompanying drawings, this is only used to describe some embodiments according to the concept of the present disclosure, and the embodiments of the present disclosure are not limited to the above embodiments. Within the scope of the technical spirit of the present disclosure, various forms of replacement, modification and change of the embodiments are possible.

Claims

1. A semiconductor device, comprising: a first electrode; a second electrode; a variable resistance layer located between the first electrode and the second electrode and maintaining a phase before and after a programming operation; a non-conductive sealing layer, located between the first electrode and the variable resistance layer; as well as A nanostructure is located inside the non-conductive sealing layer and is spaced apart from the variable resistance layer.

2. The semiconductor device according to claim 1, wherein The nanostructure is electrically connected to the first electrode.

3. The semiconductor device according to claim 1, wherein The nanostructure includes nanodots contacting the first electrode.

4. The semiconductor device according to claim 1, wherein: The nanostructure includes at least one of the following: nickel Ni, silver Ag, platinum Pt, gold Au, copper Cu and aluminum Al.

5. The semiconductor device according to claim 1, wherein The nanostructures have sufficient electrical conductivity to function as a single integrated electrode with the first electrode.

6. The semiconductor device according to claim 5, wherein: An effective area of ​​the single integrated electrode is smaller than an effective area of ​​the second electrode.

7. The semiconductor device according to claim 1, wherein The non-conductive sealing layer is a diffusion barrier layer between the first electrode, the variable resistance layer, and the second electrode.

8. The semiconductor device according to claim 1, wherein The thermal conductivity of the non-conductive sealing layer is less than 20 W / mk.

9. The semiconductor device according to claim 1, wherein: The non-conductive sealing layer comprises at least one of the following: Fe x O y 、SiO x 、TiO x , BN x , graphene and SiN x .

10. The semiconductor device according to claim 1, wherein The variable resistance layer includes a chalcogenide material.

11. A semiconductor device comprising: a first electrode; a second electrode; a variable resistance layer located between the first electrode and the second electrode and maintaining a phase before and after a programming operation; Nanodots located on the surface of the first electrode; as well as A non-conductive sealing layer surrounds the nano-dots and is filled between the first electrode and the variable resistance layer and between the nano-dots and the variable resistance layer.

12. The semiconductor device according to claim 11, wherein The nanodots are electrically connected to the first electrode and have sufficient conductivity to function as a single integrated electrode with the first electrode.

13. The semiconductor device according to claim 11, wherein The nanodots include at least one of nickel Ni, silver Ag, platinum Pt, gold Au, copper Cu, and aluminum Al.

14. The semiconductor device according to claim 11, wherein The thermal conductivity of the non-conductive sealing layer is less than 20 W / mk.

15. The semiconductor device according to claim 11, wherein The non-conductive sealing layer comprises at least one of the following: Fe x O y 、SiO x 、TiO x , BN x , graphene and SiN x .

16. The semiconductor device according to claim 11, wherein The variable resistance layer includes a chalcogenide material.

17. A method for manufacturing a semiconductor device, the method comprising: forming a first electrode; forming a nanostructure on the first electrode; forming a non-conductive sealing layer on the first electrode to surround the nanostructure; forming a variable resistance layer on the non-conductive sealing layer; as well as A second electrode is formed on the variable resistance layer.

18. The method according to claim 17, wherein: Forming the nanostructure includes forming nanodots on a surface of the first electrode.

19. The method according to claim 17, wherein: The nanodots include at least one of nickel Ni, silver Ag, platinum Pt, gold Au, copper Cu, and aluminum Al.

20. The method according to claim 17, wherein: The thermal conductivity of the non-conductive sealing layer is less than 20 W / mk.

21. The method according to claim 17, wherein: The non-conductive sealing layer comprises at least one of the following: Fe x O y 、SiO x 、TiO x , BN x , graphene and SiN x .

22. The method according to claim 17, wherein: The variable resistance layer includes a chalcogenide material that maintains a phase before and after a programming operation.

23. The method of claim 17, further comprising: An excitation voltage is applied to the first electrode and the second electrode.

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