Two-dimensional semiconductor field-effect transistor based on high-k gate dielectric and manufacturing method thereof

Abstract

The present invention discloses a method for fabricating a two-dimensional semiconductor field-effect transistor based on a high-k gate dielectric integration technology with an eliminable buffer layer. The method comprises: sequentially depositing a back-gate electrode and a back-gate dielectric on a substrate; transferring a channel layer onto the back-gate dielectric; sequentially forming a buffer layer, a source electrode, a drain electrode, a top-gate dielectric layer formed of a high-k dielectric material, and a top-gate electrode on the channel layer; and annealing the buffer layer in a vacuum environment to sublime the buffer layer, thereby forming van der Waals interfaces between the channel layer and the top-gate dielectric layer, and between the channel layer and the source electrode and the drain electrode. The high-k gate dielectric integration technology based on an eliminable buffer layer provided by the present invention utilizes a buffer layer that can be eliminated after vacuum annealing, thereby avoiding damage to the two-dimensional material, depositing a high-k gate dielectric, achieving interface control between the channel layer and the top-gate dielectric, and miniaturizing the equivalent oxide thickness. Furthermore, the method achieves good contact between the channel layer and the source and drain metals, thereby reducing the contact resistance of the transistor and improving its electrical performance.

Description

Technical Field

[0001] At least one embodiment of the present invention relates to a semiconductor device, and more particularly to a two-dimensional semiconductor field-effect transistor based on a high-k gate dielectric layer integration technology capable of eliminating a buffer layer, and a method for manufacturing the same. Background Art

[0002] Silicon-based technology has long been the cornerstone of complementary metal oxide semiconductor (CMOS) field effect transistor (FET) devices and the primary driver of the rapid growth of information technology. In line with Moore's Law, modern electronics continues to achieve higher speeds and greater capacity through device miniaturization, resulting in enhanced computing performance and lower costs. However, in recent years, further scaling of silicon-based CMOS FETs has been limited by quantum effects, particularly short-channel effects, and unavoidable heat dissipation, posing significant challenges to advancing process nodes.

[0003] Against this backdrop, researchers are eager to explore new channel materials and device architectures that transcend the limitations of traditional silicon-based technology to achieve low-power, high-performance logic devices. Consequently, two-dimensional (2D) materials composed of a single or a few atomic or molecular layers, such as graphene, boron nitride, and transition metal dihalide compounds (TMDCs), have opened up new possibilities and attracted widespread attention from researchers due to their atomic-level thickness, lack of dangling bonds on the surface, and extraordinary optical and electrical properties.

[0004] TMDCs, such as MoS2, MoSe2, WSe2, or WS2, possess high mobilities approaching those of semiconductor silicon, with band gaps mostly exceeding 1 eV. As natural semiconductors, utilizing these materials to develop high-performance field-effect transistors is a crucial development. Transistors based on two-dimensional materials also show potential for scaling beyond silicon. However, to ensure the superior device performance of two-dimensional field-effect transistors (2D FETs), the preparation of a suitable high-k gate dielectric is essential. However, the high energy required to deposit a high-k gate dielectric inevitably damages the two-dimensional material layer during the deposition process. Summary of the Invention

[0005] In view of this, the present invention provides a two-dimensional semiconductor field-effect transistor and a manufacturing method thereof based on a high-k gate dielectric layer integration technology that can eliminate a buffer layer, so as to prepare a high-k gate dielectric layer on the channel layer while avoiding damage to the two-dimensional material of the channel layer.

[0006] As one aspect of the present invention, the present invention provides a method for manufacturing a two-dimensional semiconductor field-effect transistor based on a high-k gate dielectric layer integration technology that can eliminate a buffer layer, comprising: depositing a back gate electrode and a back gate dielectric layer on a substrate in sequence; transferring a channel layer onto the back gate dielectric layer; forming a buffer layer, a source, a drain, a top gate dielectric layer formed of a high-k dielectric material, and a top gate electrode in sequence on the channel layer; and performing annealing in a vacuum environment after forming the top gate electrode, so that the buffer layer sublimates under heating conditions, so that the channel layer and the top gate dielectric layer form a van der Waals interface, and so that the channel layer forms a van der Waals interface with the source and the drain.

[0007] As another aspect of the present invention, the present invention provides a two-dimensional semiconductor field effect transistor obtained by the above-mentioned manufacturing method.

[0008] According to the method for manufacturing a two-dimensional semiconductor field-effect transistor based on the high-k gate dielectric layer integration technology with an eliminable buffer layer provided in the above-mentioned embodiment of the present invention, a buffer layer that can be removed by annealing is deposited on the channel layer, so that a high-quality high-k gate dielectric layer can be deposited on the two-dimensional material layer without damaging the two-dimensional material. This can avoid the problem of poor film formation quality of the top gate dielectric layer due to stress and strain generated between the two-dimensional material layer and the top gate dielectric layer, thereby improving the gate control capability of the two-dimensional semiconductor field-effect transistor, and can also avoid damage to the two-dimensional material lattice caused by the top gate dielectric layer, thereby improving the electrical performance of the two-dimensional semiconductor field-effect transistor, such as improving the mobility of the device, reducing the subthreshold swing, and avoiding hysteresis.

[0009] According to the method for manufacturing a two-dimensional semiconductor field-effect transistor based on high-k gate dielectric layer integration technology with an eliminable buffer layer provided in the above-mentioned embodiment of the present invention, a buffer layer that can be removed by annealing is deposited on the channel layer, which can enable the two-dimensional material to have good contact with the source metal and the drain metal, thereby reducing the contact resistance of the two-dimensional semiconductor field-effect transistor, increasing the on-state current, and further improving the electrical performance of the device.

[0010] According to the method for manufacturing a two-dimensional semiconductor field-effect transistor based on the high-k gate dielectric layer integration technology that can eliminate the buffer layer provided by the above-mentioned embodiment of the present invention, a high-k gate dielectric layer is deposited on the two-dimensional material layer, so that good van der Waals interface contacts are formed between the channel layer and the top gate dielectric layer, and between the channel layer and the source / drain. This can miniaturize the equivalent oxide thickness of the top gate dielectric layer, improve the gate control capability of the transistor, reduce the leakage current, and thereby improve the switching ratio and mobility of the device, thereby realizing a high-performance and high-breakdown field device.

[0011] According to the method for manufacturing a two-dimensional semiconductor field-effect transistor based on a high-k gate dielectric layer integration technology that can eliminate a buffer layer provided in the above-mentioned embodiment of the present invention, since the buffer layer can be removed after annealing, there is no need for the buffer layer to be material-matched and compatible with the top gate dielectric layer, making the manufacturing method highly scalable. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 Flowchart of a method for manufacturing a two-dimensional semiconductor field effect transistor based on a high-k gate dielectric capable of eliminating a buffer layer according to an embodiment of the present invention;

[0013] Figure 2A A schematic diagram of a two-dimensional semiconductor field effect transistor based on a high-k gate dielectric capable of eliminating a buffer layer before annealing according to an embodiment of the present invention;

[0014] Figure 2B is a schematic diagram of a two-dimensional semiconductor field effect transistor based on a high-k gate dielectric with an eliminable buffer layer after annealing according to an embodiment of the present invention; and

[0015] Figure 3 4 is a process flow chart of a dual-gate two-dimensional semiconductor field-effect transistor according to an embodiment of the present invention.

[0016] [Description of Reference Numerals]

[0017] 1-substrate;

[0018] 11-silicon layer;

[0019] 12-silicon dioxide layer;

[0020] 2- back gate electrode;

[0021] 3-back gate dielectric layer;

[0022] 4-channel layer;

[0023] 5- buffer layer;

[0024] 6- Source;

[0025] 7-drain;

[0026] 8-top gate dielectric layer;

[0027] 9-top gate electrode;

[0028] 1'-Si / SiO2 substrate;

[0029] 2'-TiN back gate electrode layer;

[0030] 3'-HfO2 back gate dielectric layer;

[0031] 4'-WSe2 two-dimensional material layer;

[0032] 5'-first photoresist layer;

[0033] 6'-WSe2 channel layer;

[0034] 7'-Se buffer layer;

[0035] 8'-second photoresist layer;

[0036] 9'-Ni, Pd first metal layer;

[0037] 10'-Ni, Pd source;

[0038] 11'-Ni, Pd drain;

[0039] 12'-high-k gate dielectric HfO2 top gate dielectric layer;

[0040] 13'-third photoresist layer;

[0041] 14'-TiN second metal layer;

[0042] 15'-TiN top gate electrode. DETAILED DESCRIPTION

[0043] To make the objectives, technical solutions, and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to specific embodiments and the accompanying drawings. However, the present invention can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make the present invention thorough and complete and to fully convey the scope of the present invention to those skilled in the art. In the drawings, the dimensions and relative dimensions of layers and regions may be exaggerated for clarity, and like reference numerals denote like elements throughout.

[0044] The terms used herein are only for describing specific embodiments and are not intended to limit the present invention. The terms "comprise", "include", etc. used herein indicate the presence of the features, steps, operations and / or components, but do not exclude the presence or addition of one or more other features, steps, operations or components.

[0045] It should be noted that high-k dielectric materials refer to dielectric materials with a dielectric constant greater than that of SiO2 (3.9 to 4.2). The importance of high-k gate dielectrics for 2D FETs is reflected in the following points: (1) high dielectric constant and stronger charge binding ability can reduce the leakage current of field effect transistor devices; (2) good thermal stability is conducive to improving device performance and extending device life; (3) large band gap and high barrier height can reduce the tunneling current of the device; (4) low defect state density and low fixed charge density can effectively reduce interface scattering during carrier transport and improve carrier mobility. It should be noted that fixed charge refers to the charge that permanently exists at the interface or volume in semiconductor devices.

[0046] The inert basal plane of a two-dimensional semiconductor lacks chemical pendant bonds and cannot provide sufficient nucleation sites for the deposition of high-k dielectrics, inhibiting the nucleation and growth of high-k dielectrics using standard atomic layer deposition (ALD) processes. If deposited directly on the surface of a 2D channel material using methods such as atomic layer deposition, the dielectric film quality is poor, often appearing in island or needle-like shapes. Furthermore, the high-k dielectric can severely damage the 2D channel material, creating a large number of impurities and defects at the interface, severely impacting device performance such as carrier mobility and subthreshold swing, and causing significant hysteresis. Therefore, it is necessary to find methods for depositing high-k dielectrics on the surface of two-dimensional channel materials.

[0047] The solutions for integrating a large area of ​​high-k gate dielectric layer on a two-dimensional semiconductor channel can be mainly divided into four methods:

[0048] (1) Surface treatment methods, for example, using UV ozone to treat the two-dimensional semiconductor MoS2 to form a sacrificial oxygen layer on the surface, thereby creating reactive sites on the inert substrate, and using ALD deposition to obtain a uniform, pinhole-free Al2O3 dielectric. The disadvantage of this method is that the surface treatment of the two-dimensional material to form nucleation sites first can produce a large number of defects on the nanoscale surface of the two-dimensional material, which in turn affects the performance of the logic device.

[0049] (2) Improved atomic layer deposition. This method is largely related to surface treatment because it involves steps such as precursor selection and modification or plasma precursors to drive the functionalization of the two-dimensional material surface to form nucleation sites and ultimately nucleation. For example, the precursor tetramethylaluminum (TMA) is first pulsed into the chamber, and then the Al2O3 dielectric is deposited using a water vapor-based ALD process or an O2 plasma-based PEALD process. The disadvantages of this method are the same as those of the surface treatment method.

[0050] (3) Thin film transfer method or conversion method. The thin film transfer method is a physical operation that requires manual operation for mechanical transfer. Common dielectric films transferred include h-BN, MoO3, GaS, CaF2, etc. The conversion method is a chemical reaction. For example, the two-dimensional semiconductor Bi2O2Se is partially converted into a Bi2SeO5 dielectric film with an equivalent oxide thickness (EOT) of approximately 0.9nm through oxidation reaction. The disadvantage of the thin film transfer method is that it requires manual operation and has high requirements for the experimental environment and experimental operation; the disadvantage of the conversion method is that the types of materials that can be used to generate dielectric films through chemical reactions are limited, and the scalability is poor.

[0051] (4) Buffer layer / seed layer growth method. For example, 3,4,9,10-perylene-tetracarboxylic dianhydride (PTCDA) is grown as a seed layer on a two-dimensional material using thermal evaporation deposition, and then a high-k dielectric layer HfO2 with good contact and no defects with PTCDA is deposited using atomic layer deposition (ALD). The disadvantages of this method are: the seed layer (usually with a low dielectric constant) will remain permanently in the dielectric structure, affecting the dielectric capability and gate control capability of the device; it is necessary to find a suitable gate dielectric layer that is compatible with the seed layer, and the scalability is poor.

[0052] In view of this, the present invention provides a two-dimensional semiconductor field-effect transistor and a manufacturing method thereof based on a high-k gate dielectric layer integration technology that can eliminate a buffer layer, so as to deposit a high-k gate dielectric layer on a two-dimensional material of a channel layer, so that the channel layer and the high-k gate dielectric layer form a good van der Waals interface contact, and can reduce the damage to the two-dimensional material layer caused by depositing the high-k gate dielectric layer on the two-dimensional material.

[0053] Figure 1 The flowchart is a method for manufacturing a two-dimensional semiconductor field effect transistor based on a high-k gate dielectric capable of eliminating a buffer layer according to an embodiment of the present invention.

[0054] Figure 2A Schematic diagram of a two-dimensional semiconductor field effect transistor based on a high-k gate dielectric with an eliminable buffer layer before annealing according to an embodiment of the present invention.

[0055] Figure 2B Schematic diagram of a two-dimensional semiconductor field effect transistor based on a high-k gate dielectric with an eliminable buffer layer after annealing according to an embodiment of the present invention.

[0056] According to an exemplary embodiment of the present invention, the present invention provides a method for manufacturing a two-dimensional semiconductor field effect transistor based on a high-k gate dielectric with an eliminable buffer layer, referring to Figure 1 、 Figure 2A and Figure 2B As shown, it includes: steps S01 to S04.

[0057] Step S01 : depositing a back-gate electrode 2 and a back-gate dielectric layer 3 on a substrate 1 in sequence.

[0058] According to an embodiment of the present invention, the substrate 1 includes a silicon layer 11 and a silicon dioxide layer 12 formed on the silicon layer 11 .

[0059] Step S02 , transferring the channel layer 4 onto the back gate dielectric layer 3 .

[0060] According to an embodiment of the present invention, the two-dimensional material layer is transferred to the surface of the back gate dielectric layer 3 , and the two-dimensional material layer is subjected to photolithography, development, and etching to form the channel layer 4 .

[0061] According to an embodiment of the present invention, the two-dimensional material forming the channel layer 4 includes one of MoS 2 , MoSe 2 , WSe 2 , WS 2 , graphene, and black phosphorus.

[0062] In step S03 , a buffer layer 5 , a source electrode 6 , a drain electrode 7 , a top gate dielectric layer 8 made of a high-k dielectric material, and a top gate electrode 9 are sequentially formed on the channel layer 4 .

[0063] According to an embodiment of the present invention, forming a buffer layer 5, a source 6, a drain 7, a top gate dielectric layer 8 and a top gate electrode 9 in sequence on the channel layer 4 includes: depositing a buffer layer 5 on the channel layer 4; forming a source 6 and a drain 7 on the buffer layer 5, the source 6 and the drain 7 partially overlapping with the channel layer 4 in a direction perpendicular to the substrate 1; depositing a top gate dielectric layer 8 on the source 6, the drain 7 and the buffer layer 5, and forming a top gate electrode 9 on the top gate dielectric layer 8.

[0064] According to an embodiment of the present invention, the buffer layer 5 is made of a material with low deposition energy, and the buffer layer 5 can be removed by sublimation after being heated in a high vacuum environment. For example, the material of the buffer layer 5 is selenium.

[0065] It should be noted that the deposition energy of the buffer layer 5 is lower than the deposition energy of the top gate dielectric layer 8. Depositing the buffer layer 5 directly on the channel layer 4 avoids depositing the high-k gate dielectric layer directly on the channel layer 4, which can reduce damage to the two-dimensional material of the channel layer.

[0066] According to an embodiment of the present invention, a source electrode pattern and a drain electrode pattern are defined on the buffer layer 5 , and after metal is deposited, a source electrode 6 and a drain electrode 7 are formed.

[0067] According to an embodiment of the present invention, after depositing the top gate dielectric layer 8 on the source 6, the drain 7 and the buffer layer 5, a photoresist is spin-coated on the top gate electrode layer 8, the photoresist is exposed and developed in a developer to form a photoresist pattern of the top gate electrode, a metal layer is deposited on the photoresist pattern, and then a top gate electrode 9 is formed by stripping the photoresist.

[0068] According to an embodiment of the present invention, the material of the top gate dielectric layer 8 is a high-k dielectric material; wherein the dielectric constant of the high-k dielectric material is higher than the dielectric constant of SiO 2 .

[0069] According to an embodiment of the present invention, the material of the top gate dielectric layer 8 is HfO 2 .

[0070] In step S04, after forming the top gate electrode 9, annealing treatment is performed in a vacuum environment to sublime the buffer layer 5 under heating conditions, so that the channel layer 4 and the top gate dielectric layer 8 form a van der Waals interface, and the channel layer 4 forms a van der Waals interface with the source 6 and the drain 7.

[0071] According to an embodiment of the present invention, the annealing temperature of the annealing treatment is 150°C to 250°C, for example, the annealing temperature can be 150°C, 180°C, 200°C, 220°C, 250°C; the annealing time is 4h to 6h, for example, the annealing time can be 4h, 4.5h, 5h, 5.5h, 6h; the vacuum environment is 10 -7 torr~10 -9 torr, for example, a vacuum environment can be 10 -9 torr, 10 -8 torr, 10 - 7 torr.

[0072] According to an exemplary embodiment of the present invention, the present invention provides a two-dimensional semiconductor field effect transistor obtained by the above-mentioned manufacturing method, referring to Figure 2B As shown, it includes: a substrate 1, including a silicon layer 11 and a silicon dioxide layer 12; a back gate electrode 2, formed on the substrate 1; a back gate dielectric layer 3, formed on the back gate electrode 2; a channel layer 4, formed on the back gate dielectric layer 3; a source 6 and a drain 7, formed at both ends of the channel layer 4, and the source 6 and the drain 7 partially overlap with the channel layer 4 in a direction perpendicular to the substrate 1; a top gate dielectric layer 8 formed of a high-k dielectric material, formed on the source 6, the channel layer 4 and the drain 7; a top gate electrode 9, formed on a portion of the top gate dielectric layer 8; wherein the top gate dielectric layer 8 forms a van der Waals interface with the channel layer 4, and the source 6 and the drain 7 form a van der Waals interface with the channel layer 4.

[0073] According to the method for manufacturing a two-dimensional semiconductor field-effect transistor based on a high-k gate dielectric with an eliminable buffer layer provided in the above-mentioned embodiment of the present invention, a buffer layer that can be removed by annealing is deposited on the channel layer, so that a high-quality high-k gate dielectric layer can be deposited on the two-dimensional material layer without damaging the two-dimensional material. This can avoid the problem of poor film formation quality of the top gate dielectric layer due to stress and strain generated between the two-dimensional material layer and the top gate dielectric layer, thereby improving the gate control capability of the field-effect transistor; it can also avoid damage to the two-dimensional material lattice by the top gate dielectric layer, thereby improving the electrical performance of the field-effect transistor, such as improving the mobility of the device, reducing the subthreshold swing, and avoiding hysteresis.

[0074] According to the method for manufacturing a two-dimensional semiconductor field-effect transistor based on the high-k gate dielectric layer integration technology with an eliminable buffer layer provided in the above-mentioned embodiment of the present invention, a buffer layer that can be removed by annealing is deposited on the channel layer, which can enable the two-dimensional material to have good contact with the source metal and the drain metal, thereby reducing the contact resistance of the field-effect transistor, increasing the on-state current, and further improving the electrical performance of the device.

[0075] According to the method for manufacturing a two-dimensional semiconductor field-effect transistor based on the high-k gate dielectric layer integration technology that can eliminate the buffer layer provided by the above-mentioned embodiment of the present invention, a high-k gate dielectric layer is deposited on the two-dimensional material layer, so that good van der Waals interface contacts are formed between the channel layer and the top gate dielectric layer, and between the channel layer and the source / drain. This can miniaturize the equivalent oxide thickness of the top gate dielectric layer, improve the gate control capability of the transistor, reduce the leakage current, and thereby improve the switching ratio and mobility of the device, thereby realizing a high-performance and high-breakdown field device.

[0076] According to the method for manufacturing a two-dimensional semiconductor field-effect transistor based on a high-k gate dielectric layer integration technology that can eliminate a buffer layer provided in the above-mentioned embodiment of the present invention, since the buffer layer can be removed after annealing, there is no need for the buffer layer to be material-matched and compatible with the top gate dielectric layer, making the manufacturing method highly scalable.

[0077] According to the method for manufacturing a two-dimensional semiconductor field-effect transistor based on high-k gate dielectric layer integration technology that can eliminate the buffer layer provided by the above-mentioned embodiment of the present invention, the deposition process of the buffer layer matches the traditional metal deposition process, does not increase the difficulty of the manufacturing process, and can be applied to large-scale production.

[0078] According to the method for manufacturing a two-dimensional semiconductor field-effect transistor based on high-k gate dielectric layer integration technology that can eliminate the buffer layer provided in the above-mentioned embodiment of the present invention, after the buffer layer is removed, no impurities will remain to affect the flatness of the interface and the dielectric properties of the top gate dielectric layer, which can improve the life and stability of the device.

[0079] The structure of the designed dual-gate two-dimensional semiconductor field-effect transistor and its manufacturing method are schematically described below. It should be noted that this example is only a specific embodiment of the present invention and does not limit the scope of protection of the present invention.

[0080] Example 1

[0081] It should be noted that the following is an example of fabricating a double-gate two-dimensional semiconductor field-effect transistor using HfO2 as the gate dielectric and two-dimensional WSe2 as the channel material. Figure 3 As shown in Figures (a) to (r) in the figure, the method for manufacturing a dual-gate two-dimensional semiconductor field-effect transistor includes: steps S11 to S19.

[0082] In step S11, a Si / SiO2 substrate 1' is pretreated using a Si / SiO2 material as a substrate. The pretreatment process includes ultrasonically cleaning the Si / SiO2 substrate 1' with acetone and isopropyl alcohol for 15 minutes, followed by drying in an oven at 70°C. The Si wafer is heavily p-type doped with a low resistance (<0.005Ω·cm), and the SiO2 is a natural oxide layer with a thickness of approximately 300nm.

[0083] It should be noted that the Si wafer may also be heavily n-doped, and the thickness of the SiO2 layer may be 1-300 nm.

[0084] In step S12, TiN (back gate electrode layer) 2' and HfO2 film (back gate dielectric layer) 3' are sequentially deposited on the Si / SiO2 substrate 1'.

[0085] In step S13, the WSe2 two-dimensional material layer 4' grown on the sapphire substrate is transferred onto the HfO2 film (back gate dielectric layer) 3' using a wet transfer method.

[0086] In step S14, a first photoresist layer 5' is spin-coated on the WSe2 two-dimensional material layer 4', and a channel pattern is defined by photolithography exposure and development. The channel material WSe2 not protected by the photoresist is removed by dry etching, and then a desizing process is performed to obtain a WSe2 channel layer 6'.

[0087] In step S15 , a Se buffer layer 7 ′ is grown on the surface of the WSe2 channel layer 6 ′ by thermal evaporation deposition, wherein the Se buffer layer 7 ′ protects the surface 6 ′ of the two-dimensional material WSe2 .

[0088] In step S16, a second photoresist layer 8' is formed on the Se buffer layer 7' to define source and drain electrode patterns, and Ni and Pd (first metal layer) 9' are deposited and stripped to form source 10' and drain 11'.

[0089] In step S17, a top gate dielectric layer (high-k gate dielectric HfO2) 12' is deposited on the Se buffer layer 7', the source 10', and the drain 11' using electron beam evaporation, wherein the high-energy atoms generated by the electron beam evaporation are deposited on the Se buffer layer 7' without damaging the two-dimensional material of the WSe2 channel layer 6'.

[0090] In step S18, a top gate electrode pattern is defined on the top gate dielectric layer 12' using the third photoresist layer 13', and TiN (second metal layer) 14' is deposited. Then, a stripping process is performed to form a top gate electrode 15'.

[0091] In step S19, after forming the top gate electrode 15', the two-dimensional semiconductor field effect transistor fabricated above is annealed to remove the easily sublimated Se buffer layer 7', thereby completing the preparation of the dual-gate two-dimensional semiconductor field effect transistor device.

[0092] The resulting dual-gate two-dimensional semiconductor field-effect transistor device was subjected to electrical performance testing, including carrier mobility, on-state and off-state currents, subthreshold swing, and hysteresis. The testing was performed using a semi-automatic electrical probe station and a semiconductor analyzer. The testing was conducted in a nitrogen atmosphere to prevent degradation of the device materials due to airborne influence.

[0093] It should be noted that the formula for the carrier mobility of a two-dimensional semiconductor field-effect transistor is as follows:

[0094]

[0095] Where L represents the channel length, W represents the channel width, and C ox Represents dielectric capacitance.

[0096] Example 2

[0097] Using the above-mentioned two-dimensional semiconductor field-effect transistor, NMOS and PMOS inverters based on 2D WSe2 were prepared, and the voltage transfer characteristic curve of the inverter was tested to evaluate its performance such as noise tolerance, gain, and operating logic level.

[0098] The specific embodiments described above further illustrate the objectives, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of protection of the present invention.

Claims

1. A method for manufacturing a two-dimensional semiconductor field-effect transistor based on a high-k gate dielectric, characterized in that: include: Depositing a back gate electrode (2) and a back gate dielectric layer (3) in sequence on a substrate (1); Transferring the channel layer (4) onto the back gate dielectric layer (3); A buffer layer (5), a source electrode (6), a drain electrode (7), a top gate dielectric layer (8) formed of a high-k dielectric material, and a top gate electrode (9) are sequentially formed on the channel layer (4); and After forming the top gate electrode (9), an annealing process is performed in a vacuum environment so that the buffer layer (5) sublimates under heating conditions, so that the channel layer (4) and the top gate dielectric layer (8) form a van der Waals interface, and the channel layer (4) forms a van der Waals interface with the source (6) and the drain (7).

2. The production method according to claim 1, characterized in that A buffer layer (5), a source electrode (6), a drain electrode (7), a top gate dielectric layer (8) formed of a high-k dielectric material, and a top gate electrode (9) are sequentially formed on the channel layer (4), including: Depositing a buffer layer (5) on the channel layer (4); forming a source electrode (6) and a drain electrode (7) on the buffer layer (5), wherein the source electrode (6) and the drain electrode (7) partially overlap with the channel layer (4) in a direction perpendicular to the substrate (1); A top gate dielectric layer (8) formed of a high-k dielectric material is deposited on the source (6), the drain (7) and the buffer layer (5), and a top gate electrode (9) is formed on the top gate dielectric layer (8).

3. The production method according to claim 1, characterized in that Transferring the channel layer (4) onto the back gate dielectric layer (3) comprises: The two-dimensional material layer is transferred to the surface of the back gate dielectric layer (3), and the two-dimensional material layer is subjected to photolithography, development, and etching to form the channel layer (4).

4. The production method according to claim 3, characterized in that: The two-dimensional material layer includes one of MoS2, MoSe2, WSe2, WS2, graphene and black phosphorus.

5. The production method according to claim 1, characterized in that: The deposition energy of the buffer layer (5) is lower than the deposition energy of the top gate dielectric layer (8), and the binding energy of the buffer layer (5) is lower than the binding energy of the top gate dielectric layer (8). The buffer layer (5) is easily sublimated under vacuum conditions, and the sublimation temperature of the buffer layer (5) under vacuum conditions is 150° C. to 250° C.

6. The production method according to claim 1, characterized in that: The material of the buffer layer (5) includes selenium.

7. The production method according to claim 1, characterized in that: The material of the top gate dielectric layer (8) is a high-k dielectric material; Among them, the dielectric constant of the high-k dielectric material is higher than the dielectric constant of SiO2.

8. The production method according to claim 7, characterized in that: The material of the top gate dielectric layer (8) is HfO2.

9. The production method according to claim 1, characterized in that: The substrate (1) comprises a silicon layer and a silicon dioxide layer formed on the silicon layer.

10. The manufacturing method according to claim 1, characterized in that: The annealing temperature of the annealing treatment is 150℃~250℃, the annealing time is 4h~6h, and the vacuum environment is 10 -7 torr~10 -9 torr.

11. A two-dimensional semiconductor field-effect transistor obtained by the manufacturing method according to any one of claims 1 to 10.

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