Semiconductor device and method for manufacturing semiconductor device

Abstract

The present disclosure provides a semiconductor device capable of suppressing current collapse and a method of manufacturing the semiconductor device. A method for manufacturing a semiconductor device includes: forming a dielectric oxide film having a higher relative permittivity than silica on a nitride semiconductor layer; forming a dielectric nitrogen oxide film by nitriding the dielectric oxide film; forming a first silicon nitride film over the dielectric nitrogen oxide film by a thermal film forming method; forming a second silicon nitride film over the first silicon nitride film; forming an opening reaching the dielectric nitrogen oxide film in the second silicon nitride film and the first silicon nitride film; and forming a gate electrode over the second silicon nitride film in contact with the dielectric nitrogen oxide film via the opening.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] Conventionally, a high electron mobility transistor (HEMT) has been proposed in which the polarity of the upper surface of a nitride semiconductor layer is gallium (Ga) polarity and a hafnium silicon oxynitride (HfSiON) film is provided as a gate insulating film.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application No. 2009-506537

[0006] Patent Document 2: Japanese Patent Application Laid-Open No. 5-223855

[0007] In recent years, there has been an increasing demand for suppression of current collapse. Summary of the invention

[0008] An object of the present disclosure is to provide a semiconductor device capable of suppressing current collapse and a method for manufacturing the semiconductor device.

[0009] The manufacturing method of the semiconductor device disclosed in the present invention has the following steps: forming a dielectric oxide film having a relative dielectric constant higher than that of silicon dioxide on a nitride semiconductor layer; nitriding the dielectric oxide film to form a dielectric nitride oxide film; forming a first silicon nitride film on the dielectric nitride oxide film by a thermal film forming method; forming a second silicon nitride film on the first silicon nitride film; forming an opening reaching the dielectric nitride oxide film in the second silicon nitride film and the first silicon nitride film; and forming a gate electrode on the second silicon nitride film to be connected to the dielectric nitride oxide film via the opening.

[0010] Effects of the Invention

[0011] According to the present disclosure, current collapse can be suppressed. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 is a cross-sectional view showing a semiconductor device according to an embodiment.

[0013] Figure 2 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment (Part 1).

[0014] Figure 3 This is a cross-sectional view showing the method for manufacturing a semiconductor device according to the embodiment (part 2).

[0015] Figure 4 It is a cross-sectional view showing the method for manufacturing a semiconductor device according to the embodiment (part 3).

[0016] Figure 5 It is a cross-sectional view showing the method for manufacturing a semiconductor device according to an embodiment (Part 4).

[0017] Figure 6 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment (Part 5).

[0018] Figure 7 It is a cross-sectional view showing the method for manufacturing a semiconductor device according to an embodiment (the sixth).

[0019] Figure 8 This is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment (part seven).

[0020] Fig. 9 It is a cross-sectional view showing a method for manufacturing a semiconductor device according to an embodiment (the eighth one).

[0021] Description of Reference Numerals

[0022] 1: Semiconductor devices;

[0023] 10: Growth substrate;

[0024] 20: nitride semiconductor layer;

[0025] 21: buffer layer;

[0026] 22: barrier layer;

[0027] 23: spacer layer;

[0028] 24: channel layer;

[0029] 24A: upper surface;

[0030] 25: cap layer;

[0031] 26: channel area;

[0032] 31: dielectric nitride oxide film;

[0033] 31D, 31S, 51D, 51G, 51S, 52D, 52G, 52S: opening;

[0034] 39: Dielectric oxide film;

[0035] 40D, 40S: concave part;

[0036] 41D, 41S: regrowth layer;

[0037] 42D: drain electrode;

[0038] 42S: source electrode;

[0039] 43: gate electrode;

[0040] 51: first SiN film;

[0041] 52: Second SiN film. DETAILED DESCRIPTION

[0042] [Description of Embodiments of the Present Disclosure]

[0043] First, embodiments of the present disclosure will be described by way of examples.

[0044] [1] A method for manufacturing a semiconductor device according to one embodiment of the present disclosure comprises the following steps: forming a dielectric oxide film having a relative dielectric constant higher than that of silicon dioxide on a nitride semiconductor layer; nitriding the dielectric oxide film to form a dielectric nitride oxide film; forming a first silicon nitride film on the dielectric nitride oxide film by a thermal film forming method; forming a second silicon nitride film on the first silicon nitride film; forming an opening in the second silicon nitride film and the first silicon nitride film so as to reach the dielectric nitride oxide film; and forming a gate electrode on the second silicon nitride film so as to be connected to the dielectric nitride oxide film via the opening.

[0045] The dielectric nitride oxide film functions as a gate insulating film. The dielectric nitride oxide film has higher insulation and withstand voltage than the dielectric oxide film, and can reduce gate leakage. In addition, the first silicon nitride film is formed on the dielectric nitride oxide film by a thermal film forming method before the second silicon nitride film is formed, so that the detachment of nitrogen from the dielectric nitride oxide film when the second silicon nitride film is formed is suppressed. Therefore, the current collapse associated with the detachment of nitrogen from the dielectric nitride oxide film can be suppressed.

[0046] [2] In [1], the dielectric oxide film may include at least one selected from the group consisting of hafnium, lanthanum, and zirconium. In this case, a high relative dielectric constant can be easily obtained in the dielectric oxynitride film.

[0047] [3] In [2], the dielectric oxide film may include at least one selected from the group consisting of silicon and aluminum. In this case, a high relative dielectric constant can be easily obtained in the dielectric oxynitride film.

[0048] [4] In any one of [1] to [3], the surface of the nitride semiconductor layer facing the dielectric oxide film may have nitrogen polarity. In this case, it is easy to achieve low resistance.

[0049] [5] In any one of [1] to [4], the thickness of the first silicon nitride film may be greater than 0.2 nm and less than 5 nm. When the thickness of the first silicon nitride film is less than 0.2 nm, it may be difficult to suppress the release of nitrogen from the dielectric oxynitride film, and when the thickness of the first silicon nitride film is greater than 5 nm, traps contained in the first silicon nitride film may cause current collapse.

[0050] [6] In any one of [1] to [5], the nitridation of the dielectric oxide film and the formation of the first silicon nitride film may be performed in the same film forming chamber. In this case, it is easy to suppress the release of nitrogen from the dielectric oxynitride film before the first silicon nitride film is formed.

[0051] [7] In any one of [1] to [6], the second silicon nitride film may be formed using nitrogen plasma.

[0052] [8] Another embodiment of the semiconductor device disclosed herein comprises: a nitride semiconductor layer; a dielectric nitride oxide film disposed on the nitride semiconductor layer; a first silicon nitride film disposed on the dielectric nitride oxide film; a second silicon nitride film disposed on the first silicon nitride film; an opening formed in the second silicon nitride film and the first silicon nitride film and reaching the dielectric nitride oxide film; and a gate electrode formed on the second silicon nitride film and connected to the dielectric nitride oxide film via the opening.

[0053] The first silicon nitride film can be formed by a thermal film forming method. Therefore, it is possible to suppress the detachment of nitrogen from the dielectric nitride oxide film when the first silicon nitride film is formed. In addition, the second silicon nitride film is provided on the first silicon nitride film. Therefore, it is also possible to suppress the detachment of nitrogen from the dielectric nitride oxide film when the second silicon nitride film is formed. Therefore, it is possible to suppress the current collapse associated with the detachment of nitrogen from the dielectric nitride oxide film.

[0054] [9] In [8], the concentration of hydrogen atoms in the first silicon nitride film may be lower than the concentration of hydrogen atoms in the second silicon nitride film. When the first silicon nitride film is formed by a thermal film forming method and the second silicon nitride film is formed using nitrogen plasma, it is easy to make the concentration of hydrogen atoms in the first silicon nitride film lower than the concentration of hydrogen atoms in the second silicon nitride film.

[0055]

[10] In [8] or [9], the density of the first silicon nitride film may be higher than the density of the second silicon nitride film. When the first silicon nitride film is formed by a thermal film forming method and the second silicon nitride film is formed using nitrogen plasma, it is easy to make the density of the first silicon nitride film higher than the density of the second silicon nitride film.

[0056] [Details of the embodiments of the present disclosure]

[0057] The following describes the embodiments of the present disclosure in detail, but the present disclosure is not limited to these contents. It should be noted that in this specification and the drawings, for components having substantially the same functional configuration, repeated descriptions are sometimes omitted by marking the same figure numbers. In the present disclosure, "looking down" refers to observing an object from above.

[0058] The embodiment relates to a semiconductor device including a GaN-based high electron mobility transistor (HEMT). Figure 1 is a cross-sectional view showing a semiconductor device according to an embodiment.

[0059] like Figure 1 As shown, the semiconductor device 1 of the embodiment mainly includes a growth substrate 10, a nitride semiconductor layer 20, a dielectric nitride oxide film 31, a first silicon nitride (SiN) film 51, a second SiN film 52, a regrown layer 41S, a regrown layer 41D, a gate electrode 43, a source electrode 42S and a drain electrode 42D.

[0060] The growth substrate 10 is, for example, a semi-insulating silicon carbide (SiC) substrate. When the growth substrate 10 is a SiC substrate, the upper surface of the growth substrate 10 is a carbon (C) surface. When the surface of the growth substrate 10 is a C surface, the nitride semiconductor layer 20 can grow crystals with the nitrogen (N) polarity surface as the growth surface.

[0061] The nitride semiconductor layer 20 includes a buffer layer 21 , a barrier layer 22 , a spacer layer 23 , a channel layer 24 , and a cap layer 25 .

[0062] The buffer layer 21 is located on the growth substrate 10. The buffer layer 21 is, for example, an aluminum nitride (AlN) layer. The thickness of the AlN layer is, for example, not less than 1 nm and not more than 2000 nm. The buffer layer 21 may also include an AlN layer and a GaN layer or an aluminum gallium nitride (AlGaN) layer on the AlN layer.

[0063] The barrier layer 22 is located on the buffer layer 21. The barrier layer 22 is, for example, an AlGaN layer. The band gap of the barrier layer 22 is greater than the band gap of the channel layer 24. The thickness of the barrier layer 22 is, for example, greater than 1 nm and less than 50 nm. The composition of the barrier layer 22 is, for example, Al Y Ga 1－Y N (0.15≤Y≤0.55). The conductivity type of the barrier layer 22 is, for example, n-type or non-doped (i-type). A scandium aluminum nitride (ScAlN) layer, an indium aluminum nitride (InAlN) layer, or an indium aluminum gallium nitride (InAlGaN) layer may be used instead of the AlGaN layer.

[0064] The spacer layer 23 is located on the barrier layer 22. The spacer layer 23 is, for example, an AlN layer. The thickness of the spacer layer 23 is, for example, in the range of 0.2 nm to 5 nm.

[0065] The channel layer 24 is located on the spacer layer 23. The channel layer 24 is, for example, a GaN layer. The band gap of the channel layer 24 is smaller than the band gap of the barrier layer 22. The thickness of the channel layer 24 is, for example, greater than 1 nm and less than 50 nm. Between the channel layer 24 and the barrier layer 22 and the spacer layer 23, strain is generated due to the difference in their lattice constants, and the strain causes piezoelectric charge at the interface between the two. As a result, a two-dimensional electron gas (two dimensional electron gas: 2DEG) is generated near the surface of the channel layer 24 that is opposite to the barrier layer 22, and a channel region 26 is formed. The conductivity type of the channel layer 24 is, for example, n-type or non-doped (i-type).

[0066] The cap layer 25 is located on the channel layer 24. The cap layer 25 is, for example, an AlGaN layer. The thickness of the cap layer 25 is, for example, not less than 0.2 nm and not more than 100 nm. The thickness may also be not less than 0.2 nm and not more than 10 nm.

[0067] On the C-plane of the SiC substrate, the buffer layer 21, the barrier layer 22, the spacer layer 23, the channel layer 24, and the cap layer 25 grow crystals with the N-polarity plane as the growth plane. Therefore, the upper surfaces of the buffer layer 21, the barrier layer 22, the spacer layer 23, the channel layer 24, and the cap layer 25 have N-polarity, and the lower surfaces have gallium (Ga) polarity.

[0068] A recess 40S for the source and a recess 40D for the drain are formed in the nitride semiconductor layer 20. The bottom of the recess 40S and the bottom of the recess 40D are closer to the lower surface of the nitride semiconductor layer 20 than the upper surface 24A of the channel layer 24. That is, the recess 40S and the recess 40D are formed deeper than the upper surface 24A of the channel layer 24. The bottom of the recess 40S and the bottom of the recess 40D may be located in the channel layer 24, in the spacer layer 23, or in the barrier layer 22.

[0069] The dielectric nitride oxide film 31 is located on the nitride semiconductor layer 20. The dielectric nitride oxide film 31 is in contact with the upper surface of the nitride semiconductor layer 20. The relative dielectric constant of the dielectric nitride oxide film 31 is higher than the relative dielectric constant of silicon dioxide (SiO2). The dielectric nitride oxide film 31 is a high dielectric constant film. The dielectric nitride oxide film 31 may include at least one selected from the group consisting of hafnium (Hf), lanthanum (La) and zirconium (Zr). In addition, the dielectric nitride oxide film 31 may also include at least one selected from the group consisting of silicon (Si) and aluminum (Al). For example, the dielectric nitride oxide film 31 is a hafnium silicon oxynitride (HfSiON) film or a hafnium aluminum oxynitride (HfAlON) film. The thickness of the dielectric nitride oxide film 31 is, for example, greater than 1 nm and less than 30 nm. An opening 31S for a source and an opening 31D for a drain are formed in the dielectric nitride oxide film 31. The opening 31S is connected to the recessed portion 40S, and the opening 31D is connected to the recessed portion 40D.

[0070] The first SiN film 51 is located on the dielectric oxynitride film 31. The first SiN film 51 may also contain an oxide near the interface between the first SiN film 51 and the dielectric oxynitride film 31. Therefore, the first SiN film 51 may also partially contain silicon oxynitride (SiON) as the oxide. The first SiN film 51 is in contact with the upper surface of the dielectric oxynitride film 31. There is a dielectric oxynitride film 31 between the nitride semiconductor layer 20 and the first SiN film 51, and the first SiN film 51 and the nitride semiconductor layer 20 are separated by the dielectric oxynitride film 31. The thickness of the first SiN film 51 is, for example, greater than 0.2 nm and less than 5 nm. An opening 51S for the source, an opening 51D for the drain, and an opening 51G for the gate are formed in the first SiN film 51. The opening 51S is connected to the opening 31S, and the opening 51D is connected to the opening 31D. When viewed from above, the opening 51G is located between the opening 51S and the opening 51D. A portion of the dielectric oxynitride film 31 is exposed from the opening 51G.

[0071] The regrown layer 41S is located on the channel layer 24, the spacer layer 23 or the barrier layer 22 in the recess 40S. The regrown layer 41D is located on the channel layer 24, the spacer layer 23 or the barrier layer 22 in the recess 40D. The regrown layer 41S and the regrown layer 41D are, for example, n-type GaN layers. The regrown layer 41S and the regrown layer 41D contain germanium (Ge) or Si as n-type impurities. The resistance of the regrown layer 41S and the regrown layer 41D is lower than the resistance of the channel layer 24. For example, the regrown layer 41S and the regrown layer 41D are formed by regrowing the n-type GaN layer after the recess 40S and the recess 40D are formed in the nitride semiconductor layer 20.

[0072] The source electrode 42S is located on the regrown layer 41S, and the drain electrode 42D is located on the regrown layer 41D. The source electrode 42S is in contact with the regrown layer 41S, and the drain electrode 42D is in contact with the regrown layer 41D. The source electrode 42S is in ohmic contact with the regrown layer 41S, and the drain electrode 42D is in ohmic contact with the regrown layer 41D.

[0073] The second SiN film 52 covers the first SiN film 51, the regrown layer 41S, the regrown layer 41D, the source electrode 42S, and the drain electrode 42D. The thickness of the second SiN film 52 is, for example, 5 nm or more and 100 nm or less in a portion where the thickness is uniform on the first SiN film 51. The second SiN film 52 is formed with an opening 52S for the source electrode, an opening 52D for the drain electrode, and an opening 52G for the gate electrode. A portion of the source electrode 42S is exposed from the opening 52S, and a portion of the drain electrode 42D is exposed from the opening 52D. The opening 52G is connected to the opening 51G.

[0074] The gate electrode 43 is located between the source electrode 42S and the drain electrode 42D in a plan view. The gate electrode 43 is located on the second SiN film 52, the first SiN film 51, and the dielectric oxynitride film 31, and is in contact with the dielectric oxynitride film 31 via the opening 52G and the opening 51G.

[0075] Next, a method for manufacturing the semiconductor device 1 according to the embodiment will be described. Figures 2 to 9 It is a cross-sectional view showing a method for manufacturing the semiconductor device 1 according to the embodiment.

[0076] First, if Figure 2 As shown, a nitride semiconductor layer 20 is formed on a growth substrate 10 by metal organic chemical vapor deposition (MOCVD) method, for example. In the formation of the nitride semiconductor layer 20, a buffer layer 21, a barrier layer 22, a spacer layer 23, a channel layer 24 and a cap layer 25 are sequentially formed.

[0077] Then, if Figure 3 As shown, a dielectric oxide film 39 is formed on the nitride semiconductor layer 20. The dielectric oxide film 39 can be formed, for example, by an atomic layer deposition (ALD) method. The dielectric oxide film 39 is in contact with the upper surface of the nitride semiconductor layer 20. The relative dielectric constant of the dielectric oxide film 39 is higher than the relative dielectric constant of silicon dioxide (SiO2). The dielectric oxide film 39 is a high dielectric constant film. The dielectric oxide film 39 may also include at least one selected from the group consisting of Hf, La, and Zr. In addition, the dielectric oxide film 39 may also include at least one selected from the group consisting of Si and Al. For example, the dielectric oxide film 39 is hafnium silicate (HfSiOX ) film or hafnium aluminate (HfAlO X The thickness of the dielectric oxide film 39 is, for example, not less than 1 nm and not more than 30 nm.

[0078] Then, if Figure 4 As shown, the dielectric oxide film 39 is nitrided to form the dielectric nitride oxide film 31. The nitridation of the dielectric oxide film 39 is performed in a chamber of a film forming apparatus such as an MOCVD apparatus, for example. As an N source in the nitridation of the dielectric oxide film 39, N atoms generated by thermally decomposing ammonia (NH3), for example, are used.

[0079] Then, if Figure 5 As shown, a first SiN film 51 is formed on the dielectric oxynitride film 31 by a thermal film forming method such as a thermal CVD method. The first SiN film 51 is formed in a chamber for nitriding the dielectric oxide film 39. As a raw material of the first SiN film 51, for example, silane (SiH4) and NH3 are used.

[0080] Then, if Figure 6 As shown, an opening 51S for the source and an opening 51D for the drain are formed in the first SiN film 51, an opening 31S for the source and an opening 31D for the drain are formed in the dielectric nitride oxide film 31, and a recess 40S for the source and a recess 40D for the drain are formed in the nitride semiconductor layer 20. The bottom of the recess 40S and the bottom of the recess 40D may be closer to the lower surface of the nitride semiconductor layer 20 than the upper surface 24A of the channel layer 24. That is, the recess 40S and the bottom of the recess 40D may be formed deeper than the upper surface 24A of the channel layer 24. The bottom of the recess 40S and the bottom of the recess 40D may be located in the channel layer 24, in the spacer layer 23, or in the barrier layer 22.

[0081] The opening 51S, the opening 51D, the opening 31S, the opening 31D, the recess 40S, and the recess 40D can be formed, for example, by reactive ion etching (RIE) using a mask (not shown). For example, in the formation of the opening 51S and the opening 51D, a fluorine (F)-based gas is used as a reactive gas, and in the formation of the opening 31S, the opening 31D, the recess 40S, and the recess 40D, a chlorine (Cl)-based gas is used as a reactive gas.

[0082] Then, if Figure 7As shown, a regrown layer 41S is formed in the recess 40S and on the channel layer 24, the spacer layer 23 or the barrier layer 22, and a regrown layer 41D is formed in the recess 40D and on the channel layer 24, the spacer layer 23 or the barrier layer 22. The regrown layer 41S and the regrown layer 41D can be formed by a physical vapor deposition (PVD) method such as evaporation, sputtering, or molecular beam epitaxy (MBE). The regrown layer 41S and the regrown layer 41D can also be formed by MOCVD, for example.

[0083] Then, if Figure 8 As shown, a source electrode 42S is formed on the regrown layer 41S, and a drain electrode 42D is formed on the regrown layer 41D. In forming the source electrode 42S and the drain electrode 42D, first, a metal layer (not shown) constituting the source electrode 42S and the drain electrode 42D is formed. When forming the metal layer, for example, a growth mask (not shown) having an opening formed in a region where the metal layer is to be formed is used to form a film, and then the growth mask is removed together with the metal layer (not shown) formed thereon. That is, lift-off is performed.

[0084] Then, if Fig. 9 As shown in FIG. 1 , a second SiN film 52 is formed on the first SiN film 51, the regrown layer 41S, the regrown layer 41D, the source electrode 42S, and the drain electrode 42D. The second SiN film 52 covers the first SiN film 51, the regrown layer 41S, the regrown layer 41D, the source electrode 42S, and the drain electrode 42D. The second SiN film 52 is formed, for example, by a plasma CVD method. That is, the second SiN film 52 is formed, for example, using nitrogen plasma.

[0085] Next, an opening 52G for a gate is formed in the second SiN film 52, and an opening 51G for a gate is formed in the first SiN film 51 (see Figure 1 The opening 52G and the opening 51G can be formed, for example, by RIE using a mask (not shown). For example, in forming the opening 52G and the opening 51G, an F-based gas is used as a reactive gas.

[0086] Next, a gate electrode 43 is formed on the second SiN film 52 so as to be in contact with the dielectric oxynitride film 31 via the opening 52G and the opening 51G (see Figure 1 ). When forming the gate electrode 43, for example, a metal layer is formed using a growth mask (not shown) having an opening in a region where the gate electrode 43 is to be formed, and then the growth mask is removed together with the metal layer (not shown) formed thereon. That is, lift-off is performed.

[0087] Next, an opening 52S for the source and an opening 52D for the drain are formed in the second SiN film 52 (see Figure 1 The opening 52S and the opening 52D can be formed, for example, by RIE using a mask (not shown). For example, in forming the opening 52S and the opening 52D, an F-based gas is used as a reactive gas.

[0088] In this way, the semiconductor device 1 can be manufactured.

[0089] In the semiconductor device 1 of the embodiment, the dielectric oxynitride film 31 functions as a gate insulating film, and the second SiN film 52 functions as a passivation film. In addition, the first SiN film 51 formed by the thermal film forming method suppresses the release of nitrogen from the dielectric oxynitride film 31 when the second SiN film 52 is formed by the plasma CVD method. Therefore, according to the present embodiment, the current collapse associated with the release of nitrogen from the dielectric oxynitride film 31 can be suppressed.

[0090] Furthermore, when the second SiN film 52 is formed using nitrogen plasma, the film forming temperature of the second SiN film 52 can be lowered. Therefore, even a metal material that cannot be used from the viewpoint of melting point, etc., when the second SiN film 52 is formed by thermal CVD can be used for the source electrode 42S and the drain electrode 42D. Furthermore, according to the plasma CVD method, the productivity can be improved compared with the thermal CVD method.

[0091] The first SiN film 51 formed by the thermal film forming method and the second SiN film 52 formed using nitrogen plasma are different as follows. That is, the concentration of hydrogen (H) atoms in the first SiN film 51 is likely to be lower than the concentration of H atoms in the second SiN film 52. In addition, the density of the first SiN film 51 is likely to be higher than the density of the second SiN film 52. The concentration of H atoms in the first SiN film 51 and the concentration of H atoms in the second SiN film 52 can be measured, for example, by Fourier transform infrared spectroscopy (FTIR: Fourier Transform Infrared Spectrometer). In addition, the density of the first SiN film 51 and the density of the second SiN film 52 can be measured, for example, by X-ray reflectivity (XRR: X-ray reflectivity).

[0092] The dielectric oxide film 39 includes at least one selected from the group consisting of hafnium, lanthanum, and zirconium, thereby making it easy to obtain a high relative dielectric constant in the dielectric oxynitride film 31. Furthermore, the dielectric oxide film 39 includes at least one selected from the group consisting of silicon and aluminum, thereby making it easy to obtain a high relative dielectric constant in the dielectric oxynitride film 31.

[0093] The surface of the nitride semiconductor layer 20 facing the dielectric oxide film 39 and the surface facing the dielectric oxynitride film 31 after nitridation have N polarity, thereby easily shortening the distance between the channel region 26 and the source electrode 42S and the drain electrode 42D, and easily achieving low resistance.

[0094] It should be noted that when the thickness of the first SiN film 51 is less than 0.2 nm, it may be difficult to suppress the release of nitrogen from the dielectric oxynitride film 31. On the other hand, when the thickness of the first SiN film 51 is greater than 5 nm, there is a possibility that traps included in the first SiN film 51 may cause current collapse. The thickness of the first SiN film 51 may be greater than 0.2 nm and less than 4 nm, or may be greater than 0.2 nm and less than 3 nm.

[0095] The nitridation of the dielectric oxide film 39 and the formation of the first SiN film 51 may not be performed in the same film forming chamber, but by performing the nitridation of the dielectric oxide film 39 and the formation of the first SiN film 51 in the same film forming chamber, it is easy to suppress the detachment of nitrogen from the dielectric nitride oxide film 31 before the formation of the first SiN film 51.

[0096] The polarity of the nitride semiconductor layer is not limited. That is, when the nitride semiconductor layer contains gallium, the surface of the nitride semiconductor layer facing the dielectric oxide film may have gallium polarity.

[0097] As mentioned above, although embodiment is described in detail, this disclosure is not limited to a specific embodiment, Various deformation|transformation and change are possible within the range described in a claim.

Claims

1. A method for manufacturing a semiconductor device, comprising the following steps: forming a dielectric oxide film having a relative dielectric constant higher than that of silicon dioxide on the nitride semiconductor layer; nitriding the dielectric oxide film to form a dielectric oxynitride film; forming a first silicon nitride film on the dielectric oxynitride film by a thermal film forming method; forming a second silicon nitride film on the first silicon nitride film; forming an opening reaching the dielectric oxynitride film in the second silicon nitride film and the first silicon nitride film; as well as A gate electrode is formed on the second silicon nitride film so as to be in contact with the dielectric oxynitride film via the opening.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The dielectric oxide film includes at least one selected from the group consisting of hafnium, lanthanum, and zirconium.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: The dielectric oxide film includes at least one selected from the group consisting of silicon and aluminum.

4. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein: A surface of the nitride semiconductor layer facing the dielectric oxide film has nitrogen polarity.

5. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein: The thickness of the first silicon nitride film is greater than or equal to 0.2 nm and less than or equal to 5 nm.

6. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein: The nitridation of the dielectric oxide film and the formation of the first silicon nitride film are performed in the same film formation chamber.

7. The method for manufacturing a semiconductor device according to any one of claims 1 to 3, wherein: The second silicon nitride film is formed using nitrogen plasma.

8. A semiconductor device comprising: a nitride semiconductor layer; a dielectric nitride oxide film, disposed on the nitride semiconductor layer; a first silicon nitride film disposed on the dielectric oxynitride film; a second silicon nitride film, disposed on the first silicon nitride film; an opening formed in the second silicon nitride film and the first silicon nitride film and reaching the dielectric oxynitride film; as well as A gate electrode is formed on the second silicon nitride film and is in contact with the dielectric oxynitride film through the opening.

9. The semiconductor device according to claim 8, wherein: A concentration of hydrogen atoms in the first silicon nitride film is lower than a concentration of hydrogen atoms in the second silicon nitride film.

10. The semiconductor device according to claim 8 or 9, wherein: The density of the first silicon nitride film is higher than the density of the second silicon nitride film.

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