Semiconductor device with improved termination region and corresponding method and power device

Abstract

A semiconductor device includes a semiconductor body including a semiconductor substrate and an epitaxial layer formed on the semiconductor substrate, the epitaxial layer having a first conductivity type, and in which an active region and a termination region adjacent to the active region are arranged in the epitaxial layer, wherein the termination region comprises: a junction termination extension (JTE) layer of a second conductivity type formed in the epitaxial layer, extending laterally from the active region, thereby forming a JTE region; a plurality of laterally spaced-apart regions having a second conductivity type and doped more highly than the JTE layer, where a first portion of the plurality of laterally spaced-apart regions is formed within the JTE region such that the first portion of the plurality of laterally spaced-apart regions penetrates the JTE layer, and where a second portion of the plurality of laterally spaced-apart regions is formed within the JTE region such that the second portion of the plurality of laterally spaced-apart regions penetrates the JTE layer. And a second portion of the plurality of laterally spaced apart regions is formed outside the JTE region such that the second portion of the plurality of laterally spaced apart regions does not penetrate the JTE layer.

Description

Technical Field

[0001] The present disclosure relates generally to the field of semiconductor devices, and more particularly to edge termination of active areas of semiconductor devices. Background Art

[0002] Edge termination is an important part of power devices. Most planar and trench power devices are based on one or several PN type junctions. When the active part of the junction terminates at the side of the device, very high electric fields may occur under reverse voltage bias due to the junction bend or trench corner.

[0003] Peripheral protection known as edge termination may be required. Reliable and robust high voltage devices may require effective edge termination structures to protect the device periphery so that blocking values ​​close to the ideal 1D avalanche voltage value can be achieved.

[0004] Several physical limitations make the design of SiC edge terminations quite complex. The main limitation is the low diffusion coefficient of dopant atoms inside the semiconductor. Deep junctions, for example >1μm, may be difficult to achieve and lateral dopant diffusion may be very limited. In addition, the higher interface trap levels observed in the SiC / passivation interface compared to silicon may also affect the efficiency of standard Si termination architectures in SiC power devices.

[0005] Charge can accumulate at the interface, producing breakdown voltage instabilities and early failures, especially with temperature. Finally, termination design may also be concerned with achieving high avalanche robustness to meet applications prone to unclamped inductive switching UIS.

[0006] Among all the possible termination structures integrated on SiC power devices, P+ floating guard rings (Kao rings) implemented in n-doped substrates have been proposed in the past. The width and distance of the P rings increase as the distance to the active area (i.e., towards the end of the diode or saw lane) increases.

[0007] In standard implementations, a P+ floating ring is integrated by implanting P-type impurities (e.g., Al) onto an N-doped epitaxial layer. However, the limited junction depth achievable on SiC and the high crystal damage caused by the use of high-dose implants (necessary for poor activation of the P dopants) motivate the search for suitable alternatives to the floating ring design that are compatible with the definition of the P-doped regions by epitaxy rather than just by implantation.

[0008] In fact, on one hand, the above-mentioned process limitations impose some restrictions on the appropriate terminal design, and on the other hand, when the device is operated under high stress conditions (e.g., high humidity, high temperature or high voltage), the high surface damage caused by the implantation process combined with the passivation charge may produce breakdown voltage instability and early failures.

[0009] Additionally, a highly doped channel stop region around the saw street area can be used to avoid depletion and / or inversion of the semiconductor due to passivation charges. If not designed properly, some leakage paths may appear at the interface between the passivation layer and the termination, ultimately resulting in reduced blocking voltage and sometimes early failure. The termination design will undoubtedly benefit from the integration of additional features to prevent inversion of the middle layers in the termination area. Summary of the invention

[0010] An object of the present disclosure is to provide a semiconductor device with an improved termination area.

[0011] It would further be advantageous to realize corresponding methods and power devices.

[0012] In a first aspect of the present disclosure, there is provided a semiconductor device, comprising:

[0013] A semiconductor body comprising a semiconductor substrate and an epitaxial layer formed on the semiconductor substrate, the epitaxial layer having a first conductivity type, and wherein an active region and a terminal region adjacent to the active region are arranged in the epitaxial layer, wherein the terminal region comprises:

[0014] - a junction termination extension JTE layer of a second conductivity type formed in the epitaxial layer and extending laterally from the active area, thereby forming a JTE region;

[0015] - a plurality of laterally spaced-apart regions having a second conductivity type and being higher in height than the JTE layer

[0016] Doping, where:

[0017] - a first portion of the plurality of laterally spaced-apart regions is formed within the JTE region such that the first portion of the plurality of laterally spaced-apart regions penetrates the JTE layer,

[0018] - A second portion of the plurality of laterally spaced-apart regions is formed outside the JTE region such that the second portion of the plurality of laterally spaced-apart regions does not penetrate the JTE layer.

[0019] The present disclosure relates to the concept of providing a JTE layer in a termination area and also providing a plurality of spaced-apart zones in the termination area.

[0020] A first portion of the plurality of spaced-apart regions penetrates the JTE layer. From a lateral perspective, a first portion of the plurality of spaced-apart regions is disposed within a region where the JTE layer is disposed.

[0021] In the context of the present disclosure, the word "through" means that the spaced-apart regions extend into the JTE layer, but not necessarily through the entire JTE layer. The spaced-apart regions may be shallower than the JTE layer.

[0022] In one example, the depth of the spaced-apart regions is about 50% to 150% of the depth of the JTE layer.

[0023] The second portion of the plurality of spaced-apart regions is disposed in a region where no JTE layer is disposed. Thus, the JTE layer stops at a specific lateral distance from the active region. The second portion of the plurality of spaced-apart regions is disposed starting from the specific lateral distance and further away from the active region.

[0024] The second portion of the plurality of spaced-apart zones may have the same size, ie, the same width and depth parameters, as compared to the first portion of the plurality of spaced-apart zones.

[0025] From a top view of the semiconductor device, each of the plurality of spaced-apart regions may surround the active area. This may mean that the regions may surround the active area, for example in a rounded rectangle, an ellipse or any similar shape.

[0026] The active area of ​​a semiconductor device includes functional components such as transistors, diodes or other functional elements, in which the desired electrical or electronic functions are realized. On the other hand, the termination area is the part of the device that is located outside the active area and is used for specific purposes related to device performance and protection.

[0027] The main function of the termination region is to provide a controlled transition from the active region to the surrounding environment. It helps manage the electric field distribution and prevents undesirable effects (such as electrical breakdown or leakage) that may occur at the edge or periphery of the active region.

[0028] The termination region is particularly important in high-voltage semiconductor devices such as SiC-based power devices. It is designed to distribute the electric field more evenly and reduce the concentration of electric field lines at the edges. This helps prevent voltage crowding or field-induced breakdown, improving breakdown voltage and overall device performance.

[0029] The present disclosure defines a plurality of spaced-apart zones, wherein for some of the zones, ie, the first portion, a JTE layer is disposed therebetween, and for other zones, ie, the second portion, a JTE layer is not disposed therebetween.

[0030] Thus, the JTE layer is discontinuous in that it is interrupted by a first portion of the plurality of spaced-apart regions.

[0031] It should be noted that the average doping of the spaced-apart regions may be higher than 1e18 cm^-3. This indicates that the spaced-apart regions are highly doped and not just another JTE layer with slightly more highly doped.

[0032] In the following description, a first partition is used to denote a lateral portion of a terminal area in which a JTE area is provided. A second partition is used to denote a lateral portion of a terminal area in which no JTE area is provided and in which a second portion of a spaced-apart zone is provided.

[0033] The advantage of the first sub-region is that the stability and / or robustness against negative surface charges that may be induced on top of the drift / epitaxial region can be enhanced. It further improves the process window of the first region (i.e. the region closest to the active region). This is also shown in the accompanying drawings and is explained in more detail there.

[0034] The advantage of the second partition is that it is suitable for an almost ideal situation where there are no surface charges.

[0035] Based on the above, the semiconductor device according to the present disclosure improves the stability and / or robustness performance of the termination region, especially in the presence of surface charges induced during the manufacturing process.

[0036] In one example, the terminal region further includes:

[0037] - a second JTE layer formed in the epitaxial layer and extending laterally from a region of the second portion of the plurality of laterally spaced-apart regions that is furthest from the active area.

[0038] This example defines that a second JTE layer is disposed at the lateral ends of the plurality of spaced-apart regions.

[0039] In the following description, the third region is used to indicate a lateral portion of the termination region in which the second JTE layer is disposed.

[0040] The third region serves to enhance stability and / or robustness against positive surface charges induced on top of the drift / epitaxial region.

[0041] In further examples, any of the following:

[0042] - the number of zones in the first part is equal to the number of zones in the second part;

[0043] - The number of regions in the second part is greater than the number of regions in the first part.

[0044] The inventors have found that the number of zones in the first part and the second part may be different. If the second JTE layer is not provided, it may be necessary to have more zones in the second part than in the first part. If the second JTE layer is provided, the same number of zones may be provided in the first part and the second part.

[0045] In another example, the terminal region further includes:

[0046] - a current spreading layer CSL of a first conductivity type, wherein the doping concentration of the CSL is higher than the doping concentration of the epitaxial layer, and wherein the CSL is arranged laterally adjacent to the JTE region so that at least one of the second portions of the plurality of laterally spaced-apart regions penetrates the CSL layer.

[0047] A current spreading layer (CSL) may be a component used in semiconductor devices to improve current distribution across the active area of ​​the device. It is designed to mitigate the effects of current crowding, which can cause current non-uniformity and localized heating within the device.

[0048] The CSL layer in the termination region can be formed in the same process step as the CSL layer in the active region. Therefore, the CSL layer can have the same depth and the same doping concentration as the CSL layer in the active region. Therefore, no additional method / process steps are required to produce such a CSL.

[0049] In one example, a depth of the CSL in the semiconductor body is substantially equal to a depth of the JTE region in the semiconductor body.

[0050] In further examples, the CSL layer includes any of the following:

[0051] - Non-uniform doping profile;

[0052] -Vertically graded doping profile.

[0053] A gradient profile may be preferred, such as having increasing doping from the top surface to the body, for better balancing the on-state performance of the semiconductor device.

[0054] In another example, the semiconductor device is any one of the following:

[0055] -Silicon carbide-based power devices;

[0056] - Metal oxide semiconductor MOS field effect transistor FET based on silicon carbide;

[0057] - Silicon carbide-based junction field effect transistors;

[0058] -Schottky barrier SB diodes based on silicon carbide;

[0059] -Junction Barrier Schottky JBS diode based on silicon carbide;

[0060] -Silicon Carbide based Merged PiN Schottky Diode.

[0061] In yet another example, the semiconductor body includes any one of silicon carbide SiC and gallium nitride GaN.

[0062] In even further examples, a plurality of laterally spaced-apart zones are floating.

[0063] Floating means that the first region is not connected to any particular potential or reference point. In other words, it is not electrically connected to any voltage source or ground.

[0064] For example, a P-type floating ring can act as a voltage isolation structure. By making it float, it can help electrically isolate or separate different areas or components within a semiconductor device, preventing undesired electrical coupling or interference. This isolation can be very important to ensure proper device function and avoid unwanted electrical interactions.

[0065] The floating ring can be designed to shape or control the electric field distribution within the terminal area. Its floating nature allows it to modify the electric field gradient or pattern, thereby affecting the electrical behavior of the device. This can help optimize performance, increase breakdown voltage, reduce electric field crowding, or mitigate other electric field related effects.

[0066] In another example, the active region further comprises:

[0067] a well of the second conductivity type, which is arranged in the epitaxial layer and extends from the top surface of the semiconductor body into the epitaxial layer with a penetration depth;

[0068] Wherein each region of the plurality of spaced-apart regions extends from the top surface of the semiconductor body into the epitaxial layer at a penetration depth.

[0069] An advantage of this particular example is that the process does not require additional process steps to obtain the spaced-apart regions.The spaced-apart regions can be provided in the termination region at one go, ie together with obtaining the wells in the active region.

[0070] In further examples, any of the following:

[0071] - a lateral distance between the active area and a region of the first portion of the plurality of laterally spaced-apart regions that is closest to the active area is at most 1.5 μm;

[0072] - a lateral distance between any of said plurality of laterally spaced-apart regions is between 1 μm and 4 μm.

[0073] In yet another example, a depth of the JTE region is less than a depth of the plurality of spaced-apart regions.

[0074] In further examples, distances between adjacent regions of the plurality of laterally spaced-apart regions are equal or increase for regions further away from the active region.

[0075] In one example, each region of the plurality of spaced-apart regions is uniformly doped.

[0076] In another example, the first conductivity type corresponds to an N type, and the second conductivity type corresponds to a P type.

[0077] In yet another example, the device further includes a passivation stack including silicon nitride and / or silicon dioxide.

[0078] This allows the design to tolerate effective surface charges up to + / -5e12cm^-2.

[0079] In a second aspect of the present disclosure, a method for manufacturing a semiconductor device according to any one of the above examples is provided, wherein the method comprises the following steps:

[0080] - providing a junction termination extension JTE layer of the second conductivity type in the epitaxial layer, wherein the junction termination extension JTE layer extends laterally from the active area to form a JTE region;

[0081] - providing the plurality of laterally spaced-apart regions, the regions being of the second conductivity type and being more highly doped than the JTE layer, wherein the step of providing comprises:

[0082] - arranging the first portion of the plurality of laterally spaced-apart regions to be within the JTE region such that the first portion of the plurality of laterally spaced-apart regions penetrates the JTE layer,

[0083] - arranging the second portion of the plurality of laterally spaced-apart regions to be outside the JTE region such that the second portion of the plurality of laterally spaced-apart regions does not penetrate the JTE layer.

[0084] It should be noted that the advantages as explained with reference to the first aspect of the present disclosure (being a semiconductor device) also apply to the second aspect of the present disclosure (being a method of manufacturing such a semiconductor device).

[0085] In a third aspect of the present disclosure, a power device is provided, comprising the semiconductor device according to any one of the aforementioned examples.

[0086] The present disclosure is described in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0087] In the accompanying drawings, similar components and / or features may have the same reference number. In addition, various components of the same type may be distinguished by following the reference number with a dash and a second label that distinguishes between the similar components. If only the first reference label is used in the specification, the description applies to any one of the similar components having the same first reference label, regardless of the second reference label.

[0088] These and other aspects of the disclosure will be apparent from and elucidated with reference to the examples described hereinafter. BRIEF DESCRIPTION OF THE DRAWINGS

[0089] Figure 1 Examples of semiconductor devices according to the present disclosure are disclosed;

[0090] Figure 2 Another example of a semiconductor device according to the present disclosure is disclosed;

[0091] Figure 3 Further examples of semiconductor devices according to the present disclosure are disclosed;

[0092] Figure 4 Examples of semiconductor devices according to the present disclosure are disclosed;

[0093] Figure 5 Another example of a semiconductor device according to the present disclosure is disclosed;

[0094] Figure 6 Yet another example of a semiconductor device according to the present disclosure is disclosed. DETAILED DESCRIPTION

[0095] It should be noted that in the description of the drawings, the same reference numerals indicate the same or similar components performing the same or substantially similar functions.

[0096] A more detailed description will be given with reference to specific examples, some of which are illustrated in the accompanying drawings in a manner that enables the features of the present disclosure to be understood in more detail. It should be noted that the drawings illustrate only typical examples and therefore should not be considered to limit the scope of the subject matter of the claims. The drawings are incorporated to facilitate understanding of the present disclosure and are therefore not necessarily drawn to scale. Upon reading the specification in conjunction with the drawings, the advantages of the subject matter as claimed will become apparent to those skilled in the art.

[0097] The following description above provides only preferred exemplary embodiments and is not intended to limit the scope, applicability or configuration of the present disclosure. Instead, the following description of the preferred exemplary embodiments will provide those skilled in the art with an enabling description for implementing the preferred exemplary embodiments of the present disclosure, and it should be understood that various changes may be made in the function and arrangement of elements, including combinations of features from different embodiments, without departing from the scope of the present disclosure.

[0098] Unless the context clearly requires otherwise, throughout the specification and claims, the words "comprise", "comprising", etc. should be interpreted in an inclusive sense, rather than in an exclusive or exhaustive sense; that is, in the sense of "including but not limited to". As used herein, the terms "connected", "coupled", or any variation thereof, mean any direct or indirect connection or coupling between two or more elements; the coupling or connection between elements may be physical, logical, electromagnetic, or a combination thereof. In addition, the words "herein", "above", "below", and words of similar meaning, when used in this application, refer to this application as a whole, not to any particular part of this application. Where the context permits, words used in the singular or plural in the detailed description may also include the plural or singular, respectively. The word "or" when referring to a list of two or more items encompasses all of the following interpretations of the word: any item in the list, all items in the list, and any combination of items in the list.

[0099] According to the following detailed description, these and other changes can be made to the technology. Although the specification describes certain examples of the technology and describes the expected best mode, no matter how detailed the specification seems, the technology can be practiced in many ways. The details of the system can vary considerably in its specific implementation, while still being covered by the technology disclosed in this article. As mentioned above, the specific terms used when describing certain features or aspects of the technology should not be understood to imply that the term is redefined in this article to be limited to any specific characteristics, features or aspects of the technology associated with the term. In general, the terms used in the attached claims should not be interpreted as limiting the technology to the specific examples disclosed in the specification, unless such terms are clearly defined in the specific implementation section. Therefore, the actual scope of the technology not only covers the disclosed examples, but also covers all equivalent ways of practicing or realizing the technology under the claims.

[0100] Figure 1 Examples of semiconductor devices according to the present disclosure are disclosed.

[0101] Figure 1 A semiconductor device is disclosed, comprising a semiconductor body including a semiconductor substrate and an epitaxial layer formed on the semiconductor substrate, the epitaxial layer having a first conductivity type, and wherein an active region and a terminal region adjacent to the active region are arranged in the epitaxial layer.

[0102] An epitaxial layer can refer to a layer of semiconductor material that is grown or deposited on top of a substrate or base material. Epitaxy is the process of growing this layer and may involve the controlled deposition of atoms or molecules on the substrate, allowing them to align with the existing lattice structure of the substrate.

[0103] The purpose of growing epitaxial layers is to produce semiconductor materials with specific properties that differ from the substrate material. For example, in the context of integrated circuits, epitaxial layers can be used to introduce regions with different doping concentrations or material compositions, allowing the creation of different transistor structures or other device components.

[0104] exist Figure 1 In the example shown, three different partitions can be identified: a first partition, a second partition and a third partition. All three partitions are located within the termination area. The active area is the area in which the functional components are formed.

[0105] The terminal region includes a junction terminal extension JTE layer of the second conductivity type. The JTE layer is formed in the epitaxial layer and extends laterally from the active area to form a JTE region. Figure 1 The first partition in is represented.

[0106] The termination region further includes a plurality of laterally spaced-apart regions, wherein the regions have the second conductivity type and are more highly doped than the JTE layer.

[0107] According to the present disclosure, the laterally spaced regions are arranged in the first partition and the second partition. That is, a first portion of the plurality of laterally spaced regions is formed within the JTE region so that the first portion of the plurality of laterally spaced regions penetrates the JTE layer. A second of the plurality of laterally spaced regions is formed outside the JTE region so that the second portion of the plurality of laterally spaced regions does not penetrate the JTE layer.

[0108] Thus, the first partition includes a combination of laterally spaced-apart zones and a JTE layer, while the second partition does not include a JTE layer.

[0109] A second JTE layer is formed in the epitaxial layer and extends laterally from a region of the second portion of the plurality of laterally spaced regions that is farthest from the active area. Figure 1 The third sub-region in the semiconductor is shown.

[0110] These figures also show two passivation layers, an organic passivation layer and an oxide / nitride based passivation layer.

[0111] In the context of semiconductors, passivation refers to the process of applying a protective layer on the surface of a semiconductor device to prevent degradation and improve its long-term reliability. The termination area is an area that may require protection because it is exposed to various environmental factors and potential sources of damage.

[0112] The organic passivation layer is usually made of polymer or organic materials. Its main function is to provide mechanical protection from physical damage and act as a moisture barrier. Moisture and other contaminants can negatively affect the performance and reliability of semiconductor devices. The organic passivation layer acts as a protective shield, preventing moisture and other harmful substances from reaching the semiconductor material below.

[0113] Oxide or nitride based passivation layers are usually made of materials such as silicon dioxide SiO2 or silicon nitride Si3N4. Its main purpose is to provide additional protection against moisture, chemical exposure and other environmental factors. Silicon dioxide and silicon nitride are known for their excellent dielectric properties, which make them effective insulators that can help prevent leakage and interference between adjacent components on a semiconductor chip.

[0114] The figures also show a channel stop layer. A channel stop layer refers to a structure or technology used to prevent the formation of an undesired conductive path (ie, a channel) between different features or regions on a semiconductor substrate or wafer.

[0115] The main purpose of the channel stop layer is to isolate different areas on the semiconductor substrate, especially the active area where transistors or other electronic components are made. By preventing unintended channel formation, the channel stop layer helps maintain the integrity and normal function of the individual components on the chip. Uncontrolled channels between components can cause leakage currents, increased power consumption, and other undesirable effects that reduce the performance of the integrated circuit.

[0116] The channel stop layer is usually created by introducing a heavily doped region of the same polarity (e.g., N-type) compared to the main substrate doping. This region effectively creates a barrier that hinders the formation of a channel between adjacent active regions. The channel stop layer is usually placed under an insulating layer (such as silicon dioxide) to further isolate it from other components.

[0117] Figure 2 Another example of a semiconductor device according to the present disclosure is disclosed.

[0118] It should be noted that Figure 2 The semiconductor shown has no second JTE layer. The inventors have found that the third sub-area can be omitted since no second JTE layer is provided. In this particular case, the number of laterally spaced regions in the second sub-area can be increased to compensate for the lack of a second JTE layer.

[0119] Figure 3 Another example of a semiconductor device according to the present disclosure is disclosed.

[0120] In this particular case, a current spreading layer CSL is provided between the laterally spaced apart regions provided in the second sub-area. This improves the on-state performance of the device in the active region. The CSL in the termination is used to improve the positive surface charge tolerance. If there is positive surface charge induced in the termination region, a CSL with opposite carrier polarity can help to compensate slightly.

[0121] Figure 4 A semiconductor device is disclosed, which is Figure 3 Variation shown.

[0122] Figure 5 and Figure 6 Further examples of semiconductor devices according to the present disclosure are shown.

[0123] In order to reduce the number of claims, certain aspects of the technology are presented below in certain claim forms, but applicants contemplate various aspects of the technology in any number of claim forms. For example, while some aspects of the technology may be recited as computer-readable medium claims, other aspects may also be embodied as computer-readable medium claims, or in other forms, such as in device-plus-function claims.

[0124] In the above description, for the purpose of explanation, many specific details are set forth in order to provide a comprehensive understanding of the implementation of the disclosed technology. However, it will be apparent to those skilled in the art that the embodiments of the disclosed technology can be practiced without some of these specific details.

[0125] Other variations of the disclosed embodiments may be understood and effected by those skilled in the art in practicing the claimed invention by studying the drawings, the disclosure and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. The recitation of certain measures in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage. Any reference signs in the claims should not be construed as limiting the scope thereof.

Claims

1. A semiconductor device, comprising: A semiconductor body comprising a semiconductor substrate and an epitaxial layer formed on the semiconductor substrate, the epitaxial layer having a first conductivity type, and wherein an active region and a terminal region adjacent to the active region are arranged in the epitaxial layer, wherein the terminal region comprises: - a junction termination extension (JTE) layer of a second conductivity type formed in the epitaxial layer and extending laterally from the active area to form a JTE region; - a plurality of laterally spaced-apart regions, said regions being of a second conductivity type and being more highly doped than said JTE layer, wherein: - a first portion of the plurality of laterally spaced-apart regions is formed within the JTE region such that the first portion of the plurality of laterally spaced-apart regions penetrates the JTE layer, - A second portion of the plurality of laterally spaced-apart regions is formed outside the JTE region such that the second portion of the plurality of laterally spaced-apart regions does not penetrate the JTE layer.

2. The semiconductor device according to claim 1, wherein the termination region further comprises: - a second JTE layer formed in the epitaxial layer and extending laterally from a region of the second portion of the plurality of laterally spaced-apart regions that is furthest from the active area.

3. A semiconductor device according to any one of the preceding claims, wherein any one of the following: - the number of zones in the first part is equal to the number of zones in the second part; - The number of regions in the second part is greater than the number of regions in the first part.

4. The semiconductor device according to any one of the preceding claims, wherein the termination region further comprises: - a current spreading layer CSL of a first conductivity type, wherein the doping concentration of the CSL is higher than the doping concentration of the epitaxial layer, and wherein the CSL is arranged laterally adjacent to the JTE region so that at least one of the second portions of the plurality of laterally spaced-apart regions penetrates the CSL layer.

5. The semiconductor device according to claim 4, wherein the CSL layer comprises any one of the following: - Non-uniform doping profile; -Vertically graded doping profile.

6. A semiconductor device according to any one of the preceding claims, wherein the device is any one of the following: -Silicon carbide-based power devices; - Metal oxide semiconductor MOS field effect transistor FET based on silicon carbide; - Silicon carbide-based junction field effect transistors; -Schottky barrier SB diodes based on silicon carbide; -Junction Barrier Schottky JBS diode based on silicon carbide; -Silicon Carbide based Merged PiN Schottky Diode. 7 . The semiconductor device according to claim 1 , wherein the semiconductor body comprises any one of silicon carbide (SiC) and gallium nitride (GaN).

8. The semiconductor device of any one of the preceding claims, wherein the plurality of laterally spaced-apart regions are floating.

9. The semiconductor device according to any one of the preceding claims, wherein the active region further comprises: a well of the second conductivity type, which is arranged in the epitaxial layer and extends from the top surface of the semiconductor body into the epitaxial layer with a penetration depth; Wherein each region of the plurality of spaced-apart regions extends from the top surface of the semiconductor body into the epitaxial layer at the penetration depth.

10. A semiconductor device according to any one of the preceding claims, wherein any of the following: - a width between the active region and a region of the first portion of the plurality of laterally spaced-apart regions closest to the active region of at most 1.5 μm; - the width of any one of the plurality of laterally spaced-apart regions is between 1 μm and 4 μm.

11. The semiconductor device of any one of the preceding claims, wherein a depth of the JTE region is less than a depth of the plurality of spaced-apart regions. 12 . The semiconductor device of claim 1 , wherein distances between adjacent regions of the plurality of laterally spaced-apart regions are equal or increase for regions further away from the active area.

13. A semiconductor device as claimed in any preceding claim, wherein each region of the plurality of spaced-apart regions is uniformly doped.

14. A method of manufacturing a semiconductor device according to any one of the preceding claims, wherein the method comprises the following steps: - providing the junction termination extension JTE layer of the second conductivity type in the epitaxial layer, the junction termination extension JTE layer extending laterally from the active area to form a JTE region; - providing the plurality of laterally spaced-apart regions, the regions being of the second conductivity type and being more highly doped than the JTE layer, wherein the step of providing comprises: - arranging the first portion of the plurality of laterally spaced-apart regions to be within the JTE region such that the first portion of the plurality of laterally spaced-apart regions penetrates the JTE layer, - arranging the second portion of the plurality of laterally spaced-apart regions to be outside the JTE region such that the second portion of the plurality of laterally spaced-apart regions does not penetrate the JTE layer. 15 . A power device comprising the semiconductor device according to claim 1 .

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