Semiconductor device and method for manufacturing the same

Abstract

The invention relates to a semiconductor device and a method for manufacturing the same. A semiconductor device includes: a semiconductor substrate formed to include a first active region and a second active region; a first dielectric layer disposed over the first active region; a second dielectric layer disposed over the second active region; a first gate electrode disposed over the first dielectric layer; and a second gate electrode disposed over the second dielectric layer. The first active region and the second active region have different impurity doping types from each other, and a fluorine concentration of the first dielectric layer is higher than a fluorine concentration of the second dielectric layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This patent document claims priority to and the benefit of Korean Patent Application No. 10-2023-0112115, filed on August 25, 2023, the disclosure of which is incorporated by reference in its entirety as a part of the disclosure of this patent document. Technical Field

[0003] Technologies and embodiments disclosed in this patent document relate generally to semiconductor devices and methods for manufacturing the same, and more particularly to semiconductor devices including an interlayer and a dielectric layer and methods for manufacturing the same. Background Art

[0004] The demand for semiconductor devices with ever higher levels of integration continues unabated, however, the difficulty of designing integrated circuits (ICs) increases exponentially, requiring new and innovative solutions.

[0005] More specifically, during the development of semiconductor devices, the number of devices included per unit chip area has rapidly increased while the size of each device has gradually decreased, and such high integration in semiconductor devices has led to increased complexity in integrated circuit (IC) processing and IC manufacturing.

[0006] For example, as the size of each semiconductor device decreases, (a plurality of) P-type metal oxide semiconductor (PMOS) transistors and (a plurality of) N-type metal oxide semiconductor (NMOS) transistors may be provided in one substrate.

[0007] The PMOS transistor and the NMOS transistor may require different threshold voltages due to their operating characteristics, and the threshold voltage may be adjusted by changing the properties of the dielectric layer or adjusting the thickness of an interlayer disposed between the substrate and the dielectric layer. Summary of the invention

[0008] Various embodiments of the disclosed technology relate to a semiconductor device in which the quality of a dielectric layer and the quality of an interlayer are adjusted. Embodiments of the present invention provide a semiconductor device including an interlayer having fewer dangling bonds. Dangling bonds generally refer to unpaired electrons in the interlayer, which, if not handled, can affect the electronic properties of these layers and the overall performance characteristics of the semiconductor device.

[0009] According to one embodiment of the disclosed technology, a semiconductor device may include: a semiconductor substrate formed to include a first active region and a second active region; a first dielectric layer disposed above the first active region; a second dielectric layer disposed above the second active region; a first gate electrode disposed above the first dielectric layer; and a second gate electrode disposed above the second dielectric layer, wherein the first active region and the second active region have different impurity doping types from each other; and a fluorine concentration of the first dielectric layer is higher than a fluorine concentration of the second dielectric layer.

[0010] In some embodiments, the semiconductor device may further include: a first interlayer disposed between the semiconductor substrate and the first dielectric layer; and a second interlayer disposed between the semiconductor substrate and the second dielectric layer.

[0011] In some embodiments, the fluorine concentration of the first interlayer may be higher than that of the second interlayer.

[0012] In some embodiments, the fluorine concentration of a region where the first interlayer contacts the semiconductor substrate may be lower than the fluorine concentration of a region where the first interlayer contacts the first dielectric layer, and the fluorine concentration of a region where the second interlayer contacts the semiconductor substrate may be lower than the fluorine concentration of a region where the second interlayer contacts the second dielectric layer.

[0013] In some embodiments, the fluorine concentration of the region where the first dielectric layer contacts the first interlayer may be lower than the fluorine concentration of the region where the first dielectric layer contacts the first gate electrode, and the fluorine concentration of the region where the second dielectric layer contacts the second interlayer may be lower than the fluorine concentration of the region where the second dielectric layer contacts the second gate electrode.

[0014] In some embodiments, the first interlayer or the second interlayer may have or greater thickness.

[0015] In some embodiments, each of the first dielectric layer and the second dielectric layer may include a dipole material formed of at least one of magnesium (Mg), aluminum (Al), lanthanum (La), scandium (Sc), or erbium (Er).

[0016] In some embodiments, the dipole material included in the first dielectric layer can be different from the dipole material included in the second dielectric layer.

[0017] In some embodiments, the semiconductor device may further include a metal pattern layer disposed between the second dielectric layer and the second gate electrode.

[0018] According to another embodiment of the disclosed technology, a method for manufacturing a semiconductor device may include: forming a first active region and a second active region in a semiconductor substrate; forming a first pre-interlayer overlapping the first active region; forming a second pre-interlayer overlapping the second active region; forming a first pre-dielectric layer above the first pre-interlayer; forming a second pre-dielectric layer above the second pre-interlayer; forming a metal pattern layer above the second pre-dielectric layer; injecting a first fluorine into the first pre-dielectric layer and the metal pattern layer; forming a dipole material layer above the first pre-dielectric layer; forming a metal diffusion layer above the dipole material layer and the metal pattern layer; forming a first silicon diffusion layer above the metal diffusion layer; injecting a second fluorine into the first silicon diffusion layer; annealing the dipole material layer and the fluorine to form a first dielectric layer and a second dielectric layer; and forming a first gate electrode and a second gate electrode respectively above the first dielectric layer and the second dielectric layer.

[0019] In some other embodiments, the method may further include: after annealing the implanted fluorine, removing the metal pattern layer, the metal diffusion layer, and the first silicon diffusion layer.

[0020] In some other embodiments, the method may further include: forming an oxide layer over the first silicon diffusion layer; and forming a second silicon diffusion layer over the oxide layer.

[0021] In some other embodiments, the method may further include: after annealing the implanted fluorine, removing the metal pattern layer, the metal diffusion layer, the first silicon diffusion layer, the oxide layer, and the second silicon diffusion layer.

[0022] In some other embodiments, the method may further include: forming a first interlayer from the first pre-interlayer by annealing the fluorine; and forming a second interlayer from the second pre-interlayer by annealing the fluorine, wherein the fluorine concentration of the first interlayer is higher than the fluorine concentration of the second interlayer.

[0023] In some other embodiments, the first pre-interlayer or the second pre-interlayer may have or greater thickness.

[0024] It is to be understood that both the foregoing general description and the following detailed description of the disclosed technology are illustrative and explanatory and are intended to provide further explanation of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and other features and advantageous aspects of the disclosed technology will become apparent with reference to the following detailed description when considered in conjunction with the accompanying drawings.

[0026] Figure 1 is a schematic cross-sectional view illustrating one example of a semiconductor device based on some embodiments of the disclosed technology.

[0027] Figure 2 is a flow chart illustrating one example of a method for manufacturing a semiconductor device based on some embodiments of the disclosed technology.

[0028] FIG. 3A to FIG. 3H is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device based on some embodiments of the disclosed technology.

[0029] Figure 4 is a flow chart illustrating one example of a method for manufacturing a semiconductor device based on some other embodiments of the disclosed technology.

[0030] FIG. 5A to FIG. 5D is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device based on some other embodiments of the disclosed technology. DETAILED DESCRIPTION

[0031] This patent document provides embodiments and examples of semiconductor devices including interlayers and dielectric layers, as well as embodiments and examples of methods for manufacturing the semiconductor devices, which can be used in a configuration to substantially solve one or more technical or engineering problems and alleviate limitations or disadvantages encountered in some other semiconductor device designs. Some embodiments of the disclosed technology relate to a semiconductor device in which the quality of the dielectric layer and the quality of the interlayer are adjusted. Recognizing the above problems, the disclosed technology provides a semiconductor device in which the fluorine concentration of the dielectric layer and the interlayer can be adjusted in response to the impurity doping type of the active region, thereby obtaining an embodiment of a semiconductor device with improved characteristics.

[0032] Reference will now be made in detail to embodiments of the disclosed technology, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals will be used throughout the accompanying drawings to refer to the same or similar parts. Although the present disclosure is susceptible to various modifications and alternative forms, specific embodiments of the present disclosure are illustrated by way of example in the accompanying drawings. However, the present disclosure should not be construed as being limited to the embodiments set forth herein.

[0033] In the following, various embodiments will be described with reference to the accompanying drawings. However, it should be understood that the disclosed technology is not limited to specific embodiments, but includes various modifications, equivalents and / or substitutions of the embodiments. The embodiments of the disclosed technology can provide various effects that can be directly or indirectly recognized by the disclosed technology.

[0034] The drawings may not necessarily be drawn to scale, and in some examples, the proportions of at least some structures in the drawings may be exaggerated to clearly illustrate the features of an embodiment or implementation. When a multilayer structure having two or more layers is disclosed in a drawing or detailed description, the relative positional relationship or arrangement order of the layers only reflects a specific embodiment. However, the scope or spirit of the disclosed technology is not limited thereto, and it should be noted that the relative positional relationship or arrangement order of the layers may also be changed as needed. In addition, the drawings or detailed descriptions of the multilayer structure may not reflect all the layers present in a particular multilayer structure (for example, one or more additional layers may be present between two illustrated layers). As a specific example, when the first layer in the multilayer structure is referred to as being "on" or "above" the second layer or "on" or "above" the substrate, the first layer may be formed directly on the second layer or substrate, but may also represent a structure in which one or more other layers are present between the first layer and the second layer or between the first layer and the substrate.

[0035] Hereinafter, a semiconductor device and a method for manufacturing the semiconductor device based on some embodiments of the disclosed technology will be described in detail with reference to the accompanying drawings.

[0036] The threshold voltage (Vt) may refer to a voltage required to create a conductive channel for operation of a transistor included in a semiconductor device. In other words, when the threshold voltage is applied to a gate electrode included in a transistor, a conductive channel may be formed in a substrate included in the transistor.

[0037] The threshold voltage may be affected by various factors, such as a work function difference between the gate and the substrate of the transistor, an amount of charge in a depletion layer in the substrate, a capacitance of a dielectric layer between the gate and the substrate, a thickness of the dielectric layer, an interface potential (body potential), etc. More specifically, the threshold voltage may be inversely proportional to the capacitance of a dielectric layer included in the transistor, and may be inversely proportional to the concentration of a dipole material included in the dielectric layer.

[0038] Since an operation state of a transistor is determined depending on a threshold voltage, it may be necessary to improve the quality of a dielectric layer and an interlayer included in the transistor in order to maintain a constant threshold voltage.

[0039] More specifically, each of the dielectric layer and the interlayer included in the transistor may include impurities that make the electrical properties unstable (e.g., silicon dangling bonds, etc.), and the quality of the dielectric layer and the quality of the interlayer can be improved by removing the impurities that make the electrical properties unstable (e.g., silicon dangling bonds, etc.) with fluorine provided by fluorine implantation and heat treatment (annealing).

[0040] Figure 1 is a schematic cross-sectional view illustrating one example of a semiconductor device based on some embodiments of the disclosed technology.

[0041] refer to Figure 1 , the semiconductor device may include a plurality of transistors TR1 and TR2 disposed on a semiconductor substrate 10. The semiconductor substrate 10 may include a plurality of active regions ACT1 and ACT2 doped with impurities of different doping types.

[0042] In some embodiments, the first active region ACT1 may be a region doped with N-type impurities, and the second active region ACT2 may be a region doped with P-type impurities.

[0043] Each of the active regions ACT1 and ACT2 may include source / drain regions, and an isolation region formed to separate the plurality of transistors TR1 and TR2 from each other.

[0044] Interlayers 110 and 210 may be formed over or on active regions ACT1 and ACT2, respectively. In more detail, interlayer 110 may be formed over or on active region ACT1, and interlayer 210 may be formed over or on active region ACT2.

[0045] The interlayer 110 can reduce interface defects between the semiconductor substrate 10 and the dielectric layer 120, and the interlayer 210 can reduce interface defects between the semiconductor substrate 10 and the dielectric layer 220. In some embodiments, each of the interlayers 110 and 210 can be formed of a low dielectric constant material. For example, each of the interlayers 110 and 210 can include fluorine-containing silicon oxide or fluorine-containing silicon oxynitride.

[0046] Each of the interlayers 110 and 210 may include dangling bonds, which may cause fluctuations in threshold voltage by generating defect levels.

[0047] More specifically, the dangling bonds may be the outermost electrons of silicon atoms that are not bonded to other atoms when the interlayers 110 and 210 are grown on the semiconductor substrate 10. Since the dangling bonds are unsaturated bonds, the dangling bonds may be combined with hydrogen atoms. Therefore, removing or reducing the dangling bonds in the interlayers 110 and 210 may significantly improve the stability of the energy levels of the interlayers 110 and 210.

[0048] The dangling bonds may be removed by a film quality improvement process. For example, the film quality improvement process may include an operation of annealing (or heat treating) the interlayers 110 and 210 and an operation of providing a defect removal material (e.g., hydrogen and / or fluorine, etc.). The defect removal material may be provided to the interlayers 110 and 210 before the annealing operation.

[0049] When fluorine is used, the fluorine concentration of the first interlayer 110 may be higher than the fluorine concentration of the second interlayer 210. In addition, the fluorine concentration of the region where the first interlayer 110 contacts the semiconductor substrate 10 is lower than the fluorine concentration of the region where the first interlayer 110 contacts the first dielectric layer 120. For example, the fluorine concentration in the first interlayer 110 may have a gradient concentration distribution starting from the highest concentration at the region bordering the first dielectric layer 120 and the lowest concentration at the region bordering the first active region ACT1. The fluorine concentration of the region where the second interlayer 210 contacts the semiconductor substrate 10 may be lower than the fluorine concentration of the region where the second interlayer 210 contacts the second dielectric layer 220. For example, the fluorine concentration in the second interlayer 210 may have a gradient concentration distribution starting from the highest concentration at the region bordering the second dielectric layer 220 and the lowest concentration at the region bordering the second active region ACT2.

[0050] The first interlayer 110 and / or the second interlayer 210 may have a fluorine concentration profile having an increasing fluorine concentration as the distance from the semiconductor substrate 10 increases.

[0051] In some embodiments, the interlayers 110 and 210 may be formed to have the same thickness. In some other embodiments, the interlayers 110 and 210 may be formed to have different thicknesses.

[0052] The thickness of the interlayer 110 or 210 may be adjusted according to the threshold voltage characteristics of the first transistor TR1 or the second transistor TR2. In more detail, the thickness of the interlayer 110 may be adjusted according to the threshold voltage characteristics of the first transistor TR1, and the thickness of the interlayer 210 may be adjusted according to the threshold voltage characteristics of the second transistor TR2.

[0053] For example, when the interlayer has When the thickness of the interlayer is 100 Å or greater, the interlayer may be considered as a thick transistor. In general, as the thickness of each of the interlayers 110 and 210 increases, the high voltage operation stability of the transistor (eg, TR1) may be improved.

[0054] The dielectric layers 120 and 220 may be disposed above the interlayers 110 and 210 or on the interlayers 110 and 210, respectively. The dielectric layers 120 and 220 may be made of or include a dipole material having a higher dielectric constant, i.e., a higher dielectric constant, than the interlayers 110 and 210. That is, the dielectric layer 120 may include a dipole material having a higher dielectric constant than the interlayer 110, and the dielectric layer 220 may include a dipole material having a higher dielectric constant than the interlayer 210. For example, suitable dipole materials may include hafnium (Hf), aluminum (Al), lanthanum (La), zirconium (Zr), scandium (Sc), erbium (Er), etc.

[0055] In some embodiments, each of the dielectric layers 120 and 220 may be provided as a single layer structure including a dielectric material having a high dielectric constant (i.e., a high dielectric constant). For example, the dielectric material may be formed of any one of hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium zirconium oxide (HfZrO), hafnium zirconium silicate (HfSiZrO), hafnium oxynitride (HfON), and hafnium silicate nitride (HfSiON).

[0056] In some other embodiments, dielectric layers 120 and 220 may include a multi-layer structure including different dielectric materials.

[0057] The diffusivity of the dipole material may differ depending on the type of dielectric material included in each of the dielectric layers 120 and 220. In addition, the threshold voltage of the transistor TR1 including the dielectric layer 120 and the threshold voltage of the transistor TR2 including the dielectric layer 220 may vary depending on the concentration of the dipole material.

[0058] When each of the dielectric layers 120 and 220 includes a dielectric material having a high diffusivity of the dipole material, the dipole material may be easily diffused into the dielectric layers 120 and 220. As the concentration of the dipole material increases, the dielectric constant (i.e., dielectric constant) of each of the dielectric layers 120 and 220 may increase and the threshold voltage of each of the transistors TR1 and TR2 may decrease.

[0059] In some embodiments, the dielectric layer 120 included in the transistor TR1 and the dielectric layer 220 included in the transistor TR2 may include different types of dipoles or different concentrations of dipoles.

[0060] In the same manner as described for the interlayers 110 and 210, defects included in the dielectric layers 120 and 220 may be removed by a film quality improvement process. For example, the film quality improvement process may include an annealing process (or heat treatment) of the dielectric layers 120 and 220 and an operation of providing a defect removal material (e.g., hydrogen and / or fluorine, etc.).

[0061] When fluorine is used, the fluorine concentration of the first dielectric layer 120 may be higher than the fluorine concentration of the second dielectric layer 220. In addition, the fluorine concentration of the region where the first dielectric layer 120 contacts the first interlayer 110 is lower than the fluorine concentration of the region where the first dielectric layer 120 contacts the first gate electrode 130. For example, the fluorine concentration in the first dielectric layer 120 may have a gradient concentration distribution, in which the concentration is highest at the interface with the first gate electrode 130, and the concentration is lowest at the interface with the first interlayer 110. The fluorine concentration of the region where the second dielectric layer 220 contacts the second interlayer 210 may be lower than the fluorine concentration of the region where the second dielectric layer 220 contacts the second gate electrode 230. For example, the fluorine concentration in the second dielectric layer 220 may have a gradient concentration distribution, in which the concentration is highest at the interface with the second gate electrode 230, and the concentration is lowest at the interface with the second interlayer 210.

[0062] More specifically, the first dielectric layer 120 and / or the second dielectric layer 220 may have a fluorine concentration profile having an increasing fluorine concentration as the distance from the semiconductor substrate 10 increases.

[0063] The first gate electrode 130 and the second gate electrode 230 may be disposed above or on the first dielectric layer 120 and the second dielectric layer 220, respectively. Figure 1 As illustrated in FIG. 1 , the first gate electrode 130 and the second gate electrode 230 may overlap (entirely or at least partially) the first dielectric layer 120 and the second dielectric layer 220 , respectively.

[0064] The first dielectric layer 120 and the second dielectric layer 220 may be disposed above the first interlayer 110 and the second interlayer 210 or on the first interlayer 110 and the second interlayer 210, respectively. Figure 1 As illustrated in FIG. 1 , the first dielectric layer 120 and the second dielectric layer 220 may overlap (entirely or at least partially) the first interlayer 110 and the second interlayer 210 , respectively.

[0065] In other words, the dielectric layers 120 and 220 may be disposed between the gate electrodes 130 and 230 and the active regions ACT1 and ACT2. The gate electrodes 130 and 230 may be formed of any one of tungsten, copper, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal nitrides or a combination thereof.

[0066] In some embodiments, the first gate electrode 130 and the second gate electrode 230 may include the same conductive material. During the manufacturing process of the semiconductor device, after removing the metal diffusion layer and the silicon diffusion layer formed over the first active area ACT1, the metal pattern layer, the metal diffusion layer, the silicon diffusion layer formed over the second active area ACT2 are removed, and a gate electrode material is formed, so that the first gate electrode 130 and the second gate electrode 230 can be formed of the same conductive material.

[0067] In some other embodiments, the first gate electrode 130 and the second gate electrode 230 may include a plurality of different conductive material layers. More specifically, during the manufacturing process of the semiconductor device, when the metal pattern layer, the metal diffusion layer, and the silicon diffusion layer formed over the second active area ACT2 are not removed without removing the metal diffusion layer and the silicon diffusion layer formed over the first active area ACT1, the first gate electrode 130 may be formed to have the metal diffusion layer, the silicon diffusion layer, and the gate electrode material, and the second gate electrode 230 may be formed to have the metal pattern layer, the metal diffusion layer, the silicon diffusion layer, and the gate electrode material.

[0068] The threshold voltage may be affected by the work function difference between the gate substrate 10 and the gate electrodes 130 and 230 , the dielectric constants of the interlayers 110 and 210 and the dielectric layers 120 and 220 , and the thicknesses of the interlayers 110 and 210 and the dielectric layers 120 and 220 .

[0069] The dielectric constants of the dielectric layers 120 and 220 may vary depending on the types of dipole materials included in the dielectric layers 120 and 220 .

[0070] In some embodiments, the first dielectric layer 120 may include lanthanum as a dipole material, and the second dielectric layer 220 may include aluminum as a dipole material. The dipole material included in each dielectric layer 120 or 220 may be adjusted according to a manufacturing process of a semiconductor device.

[0071] In some embodiments, the diffusivity of the dipole material may be determined by whether the dielectric material contains nitrogen (N) or by the concentration of nitrogen (N). Nitrogen (N) may hinder the diffusion of dipoles into the dielectric material, and the concentration of nitrogen (N) may be inversely proportional to the diffusivity of the dipole material.

[0072] The threshold voltages of the transistors TR1 and TR2 included in the semiconductor device may be controlled by adjusting the diffusion rate of the dipole material.

[0073] In addition, additional improvement in physical properties can be expected by controlling the degree and depth of diffusion of the defect removal material (e.g., fluorine) during the film quality improvement process of the interlayers 110 and 210 and the dielectric layers 120 and 220. After the implantation process is completed, fluorine can be diffused into the dielectric layer (e.g., 120) and the interlayer (e.g., 110) included in the transistor (e.g., TR1) by heat treatment (annealing).

[0074] As an example, in the first transistor TR1 including an active region doped with N-type impurities, annealing may allow fluorine serving as a defect removing material to diffuse and penetrate into the first dielectric layer 120 and the first interlayer 110 and may thus remove defects, thereby improving transistor characteristics.

[0075] On the other hand, when fluorine is deeply diffused into the second dielectric layer 220 and the second interlayer 210, the operating current of the second transistor TR2 including the active region doped with P-type impurities can be reduced. As a result, the diffusion of fluorine into the interface region (i.e., the region contacting the gate electrode) of the second dielectric layer 220 can help improve transistor characteristics.

[0076] In some embodiments, a metal pattern layer may be disposed above a second dielectric layer 220 located above an active region doped with P-type impurities, and fluorine may diffuse into the second dielectric layer 220 through the metal pattern layer, so that less fluorine diffusion may occur in the second transistor TR2 rather than in the first transistor TR1.

[0077] Therefore, since the metal pattern layer is disposed over the second dielectric layer 220 , a high operating current of the second transistor TR2 may be secured and the film quality of the second dielectric layer 220 may be improved.

[0078] In other words, through the metal pattern layer, the distribution of fluorine diffused into each of the first transistor TR1 and the second transistor TR2 may be adjusted.

[0079] During the film quality improvement process adopted by the present invention, a metal pattern layer may be provided in a semiconductor device so that the fluorine concentration of the first dielectric layer 120 may be higher than that of the second dielectric layer 220 , and the fluorine concentration of the first interlayer 110 may be higher than that of the second interlayer 210 .

[0080] Now refer to Figure 2 and FIG. 3A to FIG. 3H A more detailed description of the manufacturing process of the first transistor TR1 and the second transistor TR2 is provided.

[0081] Figure 2 is a flow chart illustrating one example of a method for manufacturing a semiconductor device based on some embodiments of the disclosed technology.

[0082] FIG. 3A to FIG. 3H is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device based on some embodiments of the disclosed technology.

[0083] refer to Figure 2 and Figure 3A , a first active area ACT1 and a second active area ACT2 may be defined in the semiconductor substrate 10, a first pre-interlayer 110' may be formed over the first active area ACT1 (S100), and a second pre-interlayer 210' may be formed over the second active area ACT2 (S200). In addition, a first pre-dielectric layer 120' may be formed over the first pre-interlayer 110' (S300), and a second pre-dielectric layer 220' may be formed over the second pre-interlayer 210' (S400).

[0084] Each of the pre-interlayers 110' and 210' refers to an interlayer before a film quality improvement process is performed. Each of the pre-dielectric layers 120' and 220' may refer to a dielectric layer before a film quality improvement process and diffusion of a dipole material.

[0085] Through the film quality improvement process, dangling bonds of the pre-interlayers 110 ′ and 210 ′ may be removed or at least significantly reduced, and as a result, electrical characteristics of the pre-interlayers 110 ′ and 210 ′ may be improved.

[0086] Through the dipole material improvement process, dangling bonds of the pre-dielectric layers 120 ′ and 220 ′ may be removed or at least significantly reduced, and as a result, the dielectric constant characteristics of the pre-dielectric layers 120 ′ and 220 ′ may be improved.

[0087] refer to Figure 2 and Figure 3B , a metal pattern layer 222 may be formed over the second pre-dielectric layer 220 ′ ( S500 ), and fluorine may be first implanted into the first pre-dielectric layer 120 ′ and the metal pattern layer 222 , ie, first fluorine implantation ( S600 ).

[0088] Since the metal pattern layer 222 formed over the first pre-dielectric layer 120 ′ is etched, the metal pattern layer 222 may be selectively formed over the second pre-dielectric layer 220 ′.

[0089] The metal pattern layer 222 may include a plurality of metal material layers. In some embodiments, the metal pattern layer 222 may include an interface metal layer contacting the second pre-dielectric layer 220 ′, a dipole metal layer formed over the interface metal layer, and a barrier metal layer formed over the dipole metal layer.

[0090] The interface metal layer may include any one of titanium nitride (TiN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), and tantalum nitride (TaN).

[0091] The dipole metal layer may include any one of aluminum (Al), niobium (Nb), or tungsten (W). In some embodiments, the dipole metal material may be diffused from the dipole metal layer to the second pre-dielectric layer 220' by heat treatment (annealing). Therefore, the dielectric constant of the second dielectric layer 220 may be controlled by adjusting the type of metal included in the dipole metal layer.

[0092] The barrier metal layer may include any one of titanium nitride (TiN), titanium aluminide (TiAl), titanium aluminum nitride (TiAlN), and tantalum nitride (TaN).

[0093] refer to Figure 3C , fluorine-implanted regions 120a and 222a may be formed on the first pre-dielectric layer 120' and the metal pattern layer 222, respectively, by the first fluorine implantation. As a result, the fluorine-implanted region 120a may be formed on the first pre-dielectric layer 120' by the first fluorine implantation, and the fluorine-implanted region 222a may be formed on the metal pattern layer 222 by the first fluorine implantation. Figure 3C As illustrated in FIG. 1 , the fluorine implantation region 120 a may be formed on the first pre-dielectric layer 120 ′, and the fluorine implantation region 222 a may be formed on the metal pattern layer 222 .

[0094] For example, the first fluorine implantation may be performed by ion implantation or plasma assisted doping (PLAD). Through the first fluorine implantation, regions 120a and 222a having a local high fluorine concentration may be formed over the first pre-dielectric layer 120' and the metal pattern layer 222, respectively. In more detail, the region 120a having a local high fluorine concentration may be formed over the first pre-dielectric layer 120', and the region 222a having a local high fluorine concentration may be formed over the metal pattern layer 222.

[0095] Fluorine may be diffused from the fluorine-implanted regions 120a and 222a to the pre-dielectric layers 120' and 220' and the pre-interlayers 110' and 210' by thermal treatment (e.g., annealing treatment). In more detail, fluorine may be diffused from the fluorine-implanted region 120a to the pre-dielectric layer 120' and the pre-interlayer 110' by thermal treatment (annealing), and fluorine may be diffused from the fluorine-implanted region 222a to the pre-dielectric layer 220' and the pre-interlayer 210' by thermal treatment (annealing).

[0096] refer to Figure 2 and Figure 3D , a dipole material layer 122 may be formed over the first pre-dielectric layer 120 ′ ( S700 ).

[0097] The dipole material layer 122 may include any one of hafnium (Hf), aluminum (Al), lanthanum (La), zirconium (Zr), scandium (Sc), or erbium (Er).

[0098] In some embodiments, the dipole material layer 122 may be selectively provided over or on the first pre-dielectric layer 120'. More specifically, since the dipole material formed over or on the metal pattern layer 222 is removed, the dipole material layer 122 may be selectively provided over or on the first pre-dielectric layer 120'.

[0099] During the thermal treatment (annealing) process, the dipole material may diffuse from the dipole material layer 122 to the first pre-dielectric layer 120 ′, so that the dielectric constant of the first dielectric layer 120 may be adjusted by adjusting the material included in the dipole material layer 122 .

[0100] refer to Figure 2 and Figure 3E , metal diffusion layers 124 and 224 may be formed over the dipole material layer 122 and the metal pattern layer 222, respectively (S800). Each of the metal diffusion layers 124 and 224 may include, for example, titanium nitride (TiN). Each of the metal diffusion layers 124 and 224 may be formed by a deposition process.

[0101] In addition, first silicon diffusion layers 126 and 226 may be formed over the metal diffusion layers 124 and 224, respectively (S900). The metal diffusion layers 124 and 224 and the first silicon diffusion layers 126 and 226 may be used to prevent external leakage (also referred to as "outward diffusion") of the first-implanted fluorine during the thermal treatment (annealing) process.

[0102] refer to Figure 3E , fluorine may be implanted into the first silicon diffusion layers 126 and 226, ie, secondary fluorine implantation (S1000). The fluorine implantation may be performed by ion implantation or plasma assisted doping (PLAD).

[0103] refer to Figure 2 and Figure 3F After the secondary fluorine implantation is completed, regions 126a and 226a each having a local high fluorine concentration may be formed above or on the first silicon diffusion layers 126 and 226, respectively. Since the fluorine implantation regions 126a and 226a are formed in the first silicon diffusion layers 126 and 226, respectively, when fluorine is diffused by heat treatment (annealing), external leakage of fluorine may be prevented.

[0104] After the secondary fluorine implantation, the first dielectric layer 120 and the second dielectric layer 220 may be formed by thermal treatment (annealing) (S1100). The thermal treatment (annealing) process may diffuse fluorine into the pre-dielectric layers 120' and 220' and the pre-interlayers 110' and 210'. In addition, during the thermal treatment (annealing) process, the dipole material included in the dipole material layer 122 and the dipole metal included in the metal pattern layer 222 may be diffused into the pre-dielectric layers 120' and 220', respectively.

[0105] In some embodiments, dielectric layers 120 and 220 may be formed from pre-dielectric layers 120 ′ and 220 ′, respectively, by thermal treatment (annealing), and interlayers 110 and 210 may be formed from pre-interlayers 110 ′ and 210 ′, respectively, by thermal treatment (annealing).

[0106] The dielectric constants of the first dielectric layer 120 and the second dielectric layer 220 may be determined by a thermal treatment (annealing) process. In addition, fluorine diffused during the thermal treatment (annealing) process may improve film quality and electrical properties by removing defects (e.g., dangling bonds) of the pre-dielectric layers 120' and 220' and the pre-interlayers 110' and 210'.

[0107] Since the metal diffusion layers 124 and 224 and the first silicon diffusion layers 126 and 226 are formed in the semiconductor device, external leakage of fluorine may be prevented and fluorine may be easily diffused into the pre-dielectric layers 120' and 220' and the pre-interlayers 110' and 210'.

[0108] refer to Figure 2 and Figure 3G , the metal pattern layer 222 , the metal diffusion layers 124 and 224 , and the first silicon diffusion layers 126 and 226 may be removed ( S1200 ).

[0109] refer to Figure 3G , showing the dielectric layers 120 and 220 and the interlayers 110 and 210 formed after thermal treatment (annealing).

[0110] Since the metal pattern layer 222 , the metal diffusion layers 124 and 224 , and the first silicon diffusion layers 126 and 226 are removed, the first transistor TR1 and the second transistor TR2 may be adjusted to have the same height.

[0111] In some other embodiments, the metal pattern layer 222, the metal diffusion layers 124 and 224, and the first silicon diffusion layers 126 and 226 may not be removed. When the metal pattern layer 222, the metal diffusion layers 124 and 224, and the first silicon diffusion layers 126 and 226 are not removed, the unremoved layers may be included as part of the gate electrode.

[0112] refer to Figure 2 and Figure 3H , a first gate electrode 130 and a second gate electrode 230 may be formed on the first dielectric layer 120 and the second dielectric layer 220, respectively (S1300). In some embodiments, the first gate electrode 130 and the second gate electrode 230 may include a conductive material. More specifically, the first gate electrode 130 and the second gate electrode 230 may be made of any one or a combination of tungsten, copper, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, and conductive metal nitrides.

[0113] Each of the first gate electrode 130 and the second gate electrode 230 may be formed of a plurality of conductive material layers, and a threshold voltage of the transistor may be controlled by adjusting the work function of the gate electrodes 130 and 230 .

[0114] For example, each of the first gate electrode 130 and the second gate electrode 230 may include a titanium nitride layer and a polysilicon layer.

[0115] Figure 4 is a flow chart illustrating one example of a method for manufacturing a semiconductor device based on some other embodiments of the disclosed technology.

[0116] FIG. 5A to FIG. 5D is a schematic cross-sectional view illustrating an example of a method for manufacturing a semiconductor device based on some other embodiments of the disclosed technology.

[0117] In some other embodiments, until the secondary fluorine injection process (i.e., Figure 2 The manufacturing process of S1000 can be Figure 2 The manufacturing process of is basically the same, and therefore for the sake of brevity, redundant description thereof will be omitted herein.

[0118] refer to Figure 4 and Figure 5A After the second fluorine implantation process, oxide layers 127 and 227 may be formed respectively over the fluorine implantation regions 126a and 226a respectively included in the first silicon diffusion layers 126 and 226 (S2000). In more detail, the oxide layer 127 may be formed over the fluorine implantation region 126a included in the first silicon diffusion layer 126, and the oxide layer 227 may be formed over the fluorine implantation region 226a included in the first silicon diffusion layer 226 (S2000).

[0119] Each of the oxide layers 127 and 227 may include, for example, silicon oxide.

[0120] Since the oxide layers 127 and 227 are formed, external leakage of fluorine can be more easily prevented, and the film quality improvement effect caused by the diffusion of fluorine can be increased.

[0121] refer to Figure 4 and Figure 5B , second silicon diffusion layers 128 and 228 may be formed over the oxide layers 127 and 227, respectively (S2100). In the same manner as the first silicon diffusion layers 126 and 226, the second silicon diffusion layers 128 and 228 may be layers that prevent external diffusion of fluorine.

[0122] After the secondary formation of the silicon diffusion layers 128 and 228, the first dielectric layer 120 and the second dielectric layer 220 may be formed by heat treatment (annealing) (S2200). The heat treatment (annealing) process may be used to diffuse fluorine into the pre-dielectric layers 120' and 220' and the pre-interlayers 110' and 210'. In addition, during the heat treatment (annealing) process, the dipole material included in the dipole material layer 122 and the dipole metal included in the metal pattern layer 222 may be diffused into the pre-dielectric layers 120' and 220', respectively.

[0123] In some embodiments, dielectric layers 120 and 220 may be formed from pre-dielectric layers 120 ′ and 220 ′, respectively, by thermal treatment (annealing), and interlayers 110 and 210 may be formed from pre-interlayers 110 ′ and 210 ′, respectively, by thermal treatment (annealing).

[0124] The dielectric constants of the first dielectric layer 120 and the second dielectric layer 220 may be determined by a thermal treatment (annealing) process. In addition, fluorine diffused during the thermal treatment (annealing) process may improve film quality and electrical properties by removing defects of the pre-dielectric layers 120' and 220' and the pre-interlayers 110' and 210'.

[0125] Since the metal diffusion layers 124 and 224, the first silicon diffusion layers 126 and 226, the oxide layers 127 and 227, and the second silicon diffusion layers 128 and 228 are formed in the semiconductor device, external leakage of fluorine can be prevented and fluorine can be easily diffused into the pre-dielectric layers 120' and 220' and the pre-interlayers 110' and 210'.

[0126] refer to Figure 4 and Figure 5C , the metal pattern layer 222 , the metal diffusion layers 124 and 224 , the first silicon diffusion layers 126 and 226 , the oxide layers 127 and 227 , and the second silicon diffusion layers 128 and 228 may be removed ( S2300 ).

[0127] refer to Figure 5C , showing the dielectric layers 120 and 220 and the interlayers 110 and 210 formed after thermal treatment (annealing).

[0128] Since the metal pattern layer 222 , the metal diffusion layers 124 and 224 , the first silicon diffusion layers 126 and 226 , the oxide layers 127 and 227 , and the second silicon diffusion layers 128 and 228 are removed, the first transistor TR1 and the second transistor TR2 may be adjusted to have the same height.

[0129] refer to Figure 4 and Figure 5D , a first gate electrode 130 and a second gate electrode 230 may be formed over the first dielectric layer 120 and the second dielectric layer 220, respectively (S2400). In some embodiments, the first gate electrode 130 and the second gate electrode 230 may include a conductive material. More specifically, the first gate electrode 130 and the second gate electrode 230 may be formed of any one or a combination of tungsten, copper, hafnium, zirconium, titanium, tantalum, aluminum, ruthenium, palladium, platinum, cobalt, nickel, and a conductive metal nitride.

[0130] Each of the first gate electrode 130 and the second gate electrode 230 may be formed of a plurality of conductive material layers, and a threshold voltage of the transistor may be controlled by adjusting the work function of the gate electrodes 130 and 230 .

[0131] For example, each of the first gate electrode 130 and the second gate electrode 230 may include a titanium nitride layer and a polysilicon layer.

[0132] As described in the above-mentioned embodiments of the disclosed technology, in a plurality of transistors included in one substrate, fluorine can be implanted into different layers a plurality of times, and diffusion of fluorine can be controlled during heat treatment (annealing).

[0133] By adjusting the diffusion of fluorine, a dielectric layer or an interlayer included in each transistor may be adjusted to have different fluorine concentrations depending on the doping type of an active region included in each transistor.

[0134] Semiconductor devices based on some embodiments of the disclosed technology can allow the dielectric layer or interlayer included in each transistor to have different fluorine concentrations, so that the semiconductor device can improve the film quality of the dielectric layer or interlayer and prevent degradation of the operating characteristics of the transistor (e.g., operating current).

[0135] According to the above description, semiconductor devices according to some embodiments of the disclosed technology adjust the fluorine concentration of the dielectric layer and the interlayer in response to the impurity doping type of the active region, thereby obtaining embodiments of semiconductor devices with improved characteristics.

[0136] Embodiments of the disclosed technology can provide various effects that can be directly or indirectly recognized through the above-mentioned patent documents.

[0137] Those skilled in the art will appreciate that the disclosed technology can be implemented in other specific ways besides those specific ways set forth herein. In addition, as an embodiment, claims that are not explicitly presented in the appended claims can be presented in combination, or be included as new claims by subsequent amendments after submitting this application.

[0138] Although a number of illustrative embodiments have been described, it should be appreciated that modifications and / or enhancements to the disclosed embodiments and other embodiments may be devised based on what is described and / or illustrated in this patent document.

Claims

1. A semiconductor device comprising: a semiconductor substrate comprising a first active region and a second active region; A first dielectric layer and a second dielectric layer, which are respectively disposed above the first active region and the second active region; A first gate electrode and a second gate electrode, which are disposed on the first dielectric layer and the second dielectric layer, respectively; and in The first active region and the second active region have different impurity doping types from each other; and The fluorine concentration of the first dielectric layer is higher than the fluorine concentration of the second dielectric layer.

2. The semiconductor device according to claim 1, further comprising: a first interlayer disposed between the semiconductor substrate and the first dielectric layer; as well as A second interlayer is disposed between the semiconductor substrate and the second dielectric layer.

3. The semiconductor device according to claim 2, wherein: The first interlayer has a fluorine concentration higher than that of the second interlayer.

4. The semiconductor device according to claim 2, wherein: The fluorine concentration at the interface between the first interlayer and the semiconductor substrate is lower than the fluorine concentration at the interface between the first interlayer and the first dielectric layer; and A fluorine concentration at an interface between the second interlayer and the semiconductor substrate is lower than a fluorine concentration at an interface between the second interlayer and the second dielectric layer.

5. The semiconductor device according to claim 2, wherein: wherein a fluorine concentration in a region where the first dielectric layer contacts the first interlayer is lower than a fluorine concentration in a region where the first dielectric layer contacts the first gate electrode; and A fluorine concentration in a region where the second dielectric layer contacts the second interlayer is lower than a fluorine concentration in a region where the second dielectric layer contacts the second gate electrode.

6. The semiconductor device according to claim 2, wherein: The first interlayer or the second interlayer has or greater thickness, and The thickness is measured in a direction perpendicular to the surface of the semiconductor substrate.

7. The semiconductor device according to claim 1, wherein: Each of the first dielectric layer and the second dielectric layer includes a dipole material formed of at least one of magnesium (Mg), aluminum (Al), lanthanum (La), scandium (Sc), or erbium (Er).

8. The semiconductor device according to claim 7, wherein: The dipole material included in the first dielectric layer is different from the dipole material included in the second dielectric layer.

9. The semiconductor device according to claim 1, further comprising: The metal pattern layer is disposed between the second dielectric layer and the second gate electrode.

10. A method for manufacturing a semiconductor device, comprising: forming a first active region and a second active region in a semiconductor substrate; forming a first pre-interlayer overlapping the first active region; forming a second pre-interlayer overlapping the second active region; forming a first pre-dielectric layer over the first pre-interlayer; forming a second pre-dielectric layer over the second pre-interlayer; forming a metal pattern layer over the second pre-dielectric layer; injecting fluorine into the first pre-dielectric layer and the metal pattern layer for the first time; forming a dipole material layer over the first pre-dielectric layer; forming a metal diffusion layer above the dipole material layer and the metal pattern layer; forming a first silicon diffusion layer above the metal diffusion layer; injecting secondary fluorine into the first silicon diffusion layer; annealing the dipole material layer and fluorine to form a first dielectric layer and a second dielectric layer; as well as A first gate electrode and a second gate electrode are formed over the first dielectric layer and the second dielectric layer, respectively.

11. The method according to claim 10, further comprising: After annealing the implanted fluorine, The metal pattern layer, the metal diffusion layer and the first silicon diffusion layer are removed.

12. The method according to claim 10, further comprising: forming an oxide layer over the first silicon diffusion layer; as well as A second silicon diffusion layer is formed over the oxide layer.

13. The method according to claim 12, further comprising: After annealing the implanted fluorine, The metal pattern layer, the metal diffusion layer, the first silicon diffusion layer, the oxide layer, and the second silicon diffusion layer are removed.

14. The method according to claim 10, further comprising: forming a first interlayer from the first pre-interlayer by annealing with fluorine; as well as forming a second interlayer from the second pre-interlayer by annealing with fluorine, in The first interlayer has a fluorine concentration higher than that of the second interlayer.

15. The method of claim 10, wherein: The first pre-interlayer or the second pre-interlayer has or greater thickness.

16. A method for manufacturing a semiconductor device, comprising: forming a first pre-interlayer and a second pre-interlayer over the substrate; forming a first pre-dielectric layer and a second pre-dielectric layer respectively overlapping the first pre-interlayer and the second pre-interlayer; forming a metal pattern layer overlapping the second pre-dielectric layer; forming a fluorine implantation region overlapping the first pre-dielectric layer and the metal pattern layer; forming a dipole material layer above the fluorine implantation region, the dipole material layer overlapping the first pre-dielectric layer; forming a metal diffusion layer overlapping the dipole material layer and the metal pattern layer; forming a first silicon diffusion layer overlapping the metal diffusion layer; injecting additional fluorine into the first silicon diffusion layer; subjecting the obtained structure to a heat treatment so that fluorine diffuses into the first and second pre-interlayers and the first and second pre-dielectric layers to form a first dielectric layer and a second dielectric layer; as well as A first gate electrode and a second gate electrode are formed over the first dielectric layer and the second dielectric layer, respectively.

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