Display substrate and display device

Abstract

The invention discloses a display substrate and a display device. The display substrate comprises a substrate body and a plurality of sub-pixels distributed on the substrate body in an array mode. The sub-pixel includes: a data line pattern extending in a first direction; a power signal line pattern including a portion extending in a first direction; the sub-pixel driving circuit comprises two switching transistors, a driving transistor and a storage capacitor; a first pole plate of the storage capacitor is coupled with the grid electrode of the driving transistor, and a second pole plate of the storage capacitor is coupled with the power supply signal line pattern; second poles of the two switch transistors are coupled with a first pole of the driving transistor, and the orthographic projection of the second pole of at least one of the two switch transistors on the substrate is at least partially overlapped with the orthographic projection of the power signal line pattern on the substrate. And the orthographic projection of the second polar plate of the storage capacitor on the substrate is at least partially overlapped.

Description

[0001] This application is a divisional application of the Chinese patent application with application number 201980002702.4, filed on November 29, 2019. Technical Field

[0002] The present disclosure relates to the field of display technology, and in particular to a display substrate and a display device. Background Art

[0003] Organic Light-Emitting Diode (OLED) display products are widely used in various fields due to their advantages such as high brightness, low power consumption, fast response, high clarity, good flexibility and high luminous efficiency.

[0004] As the application scope of OLED display products becomes wider and wider, the display quality requirements of OLED display products are getting higher and higher. There are many factors that affect the display quality of display products. Among them, the crosstalk phenomenon caused by the pixel circuit structure included in the display product is an important factor that has attracted widespread attention.

[0005] Public Content

[0006] An object of the present disclosure is to provide a display substrate and a display device.

[0007] A first aspect of the present disclosure provides a display substrate, comprising: a substrate and a plurality of sub-pixels distributed in an array on the substrate; the sub-pixels comprising:

[0008] A data line pattern extending along a first direction;

[0009] a power signal line pattern, the power signal line pattern including a portion extending along the first direction;

[0010] A sub-pixel driving circuit, the sub-pixel driving circuit comprising: two switching transistors, a driving transistor and a storage capacitor; the first plate of the storage capacitor is coupled to the gate of the driving transistor, and the second plate of the storage capacitor is coupled to the power signal line pattern; the second electrodes of the two switching transistors are both coupled to the first electrode of the driving transistor, and the orthographic projection of the second electrode of at least one of the two switching transistors on the substrate at least partially overlaps with the orthographic projection of the power signal line pattern on the substrate, and at least partially overlaps with the orthographic projection of the second plate of the storage capacitor on the substrate.

[0011] Optionally, the second electrodes of the two switching transistors and the first electrode of the driving transistor are an integrated structure, and the integrated structure includes a first conductive portion extending along the first direction, and the orthographic projection of the first conductive portion on the substrate, the orthographic projection of the power signal line pattern on the substrate, and the orthographic projection of the second electrode plate of the storage capacitor on the substrate have a first overlapping area, and the first overlapping area does not overlap with the orthographic projection of the data line pattern on the substrate.

[0012] Optionally, the orthographic projection of the first electrode of the driving transistor on the substrate is located inside the orthographic projection of the second electrode plate of the storage capacitor on the substrate.

[0013] Optionally, the sub-pixel further includes: a gate line pattern and a light emitting control signal line pattern both extending along a second direction, and the second direction intersects the first direction;

[0014] The sub-pixel driving circuit further includes: a first transistor and a sixth transistor; the two switch transistors include a fourth transistor and a fifth transistor;

[0015] The gate of the fourth transistor is coupled to the gate line pattern, the first electrode of the fourth transistor is coupled to the data line pattern, the second electrode of the fourth transistor is coupled to the second electrode of the fifth transistor, the gate of the fifth transistor is coupled to the light emitting control signal line pattern, and the first electrode of the fifth transistor is coupled to the power signal line pattern;

[0016] The gate of the first transistor is coupled to the gate line pattern, the second electrode of the first transistor is coupled to the gate of the driving transistor, the first electrode of the first transistor, the first electrode of the sixth transistor and the second electrode of the driving transistor form an integrated structure, the integrated structure includes a second conductive portion extending along the first direction, the gate of the sixth transistor is coupled to the light emitting control signal line pattern, and the second electrode of the sixth transistor is coupled to the light emitting element in the sub-pixel;

[0017] The orthographic projection of the channel region of the driving transistor on the substrate is located between the orthographic projection of the first conductive part on the substrate and the orthographic projection of the second conductive part on the substrate; and along the second direction, the minimum distance between the orthographic projection of the channel region of the driving transistor on the substrate and the orthographic projection of the first conductive part on the substrate is smaller than the minimum distance between the orthographic projection of the channel region on the substrate and the orthographic projection of the second conductive part on the substrate.

[0018] Optionally, the sub-pixel further includes: a gate line pattern and a light emitting control signal line pattern both extending along a second direction, and the second direction intersects the first direction;

[0019] The sub-pixel driving circuit further includes: a first transistor and a sixth transistor; the two switch transistors include a fourth transistor and a fifth transistor;

[0020] The gate of the fourth transistor is coupled to the gate line pattern, the first electrode of the fourth transistor is coupled to the data line pattern, the second electrode of the fourth transistor is coupled to the second electrode of the fifth transistor, the gate of the fifth transistor is coupled to the light emitting control signal line pattern, and the first electrode of the fifth transistor is coupled to the power signal line pattern;

[0021] The gate of the first transistor is coupled to the gate line pattern, the second electrode of the first transistor is coupled to the gate of the driving transistor, the first electrode of the first transistor, the first electrode of the sixth transistor and the second electrode of the driving transistor form an integrated structure, the integrated structure includes a second conductive portion extending along the first direction, the gate of the sixth transistor is coupled to the light emitting control signal line pattern, and the second electrode of the sixth transistor is coupled to the light emitting element in the sub-pixel;

[0022] The orthographic projection of the channel region of the driving transistor on the substrate is located between the orthographic projection of the first conductive part on the substrate and the orthographic projection of the second conductive part on the substrate; the first pole and the second pole of the driving transistor both include a first part extending along the second direction, and the length of the first part of the first pole along the second direction is different from the length of the first part of the second pole extending along the second direction.

[0023] Optionally, the sub-pixel further includes an initialization signal line pattern, the initialization signal line pattern includes a portion extending along a second direction, the second direction intersects the first direction, and the initialization signal line pattern is used to transmit an initialization signal with a fixed potential;

[0024] The sub-pixel driving circuit further includes a second transistor coupled to a gate of the driving transistor, wherein the second transistor includes:

[0025] A first semiconductor pattern, a second semiconductor pattern, and a third conductor pattern coupled to the first semiconductor pattern and the second semiconductor pattern, respectively, wherein the conductivity of the third conductor pattern is better than the conductivity of the first semiconductor pattern and the conductivity of the second semiconductor pattern;

[0026] a first gate pattern and a second gate pattern, wherein an orthographic projection of the first gate pattern on the substrate at least partially overlaps with an orthographic projection of the first semiconductor pattern on the substrate, and an orthographic projection of the second gate pattern on the substrate at least partially overlaps with an orthographic projection of the second semiconductor pattern on the substrate;

[0027] The orthographic projection of the third conductor pattern on the substrate does not overlap with the orthographic projection of the first gate pattern on the substrate, and the orthographic projection of the second gate pattern on the substrate;

[0028] The orthographic projection of the third conductor pattern on the substrate at least partially overlaps with the orthographic projection of the initialization signal line pattern on the substrate.

[0029] Optionally, the sub-pixel driving circuit further includes a first extending portion extending from the first semiconductor pattern, and the first extending portion has a better conductivity than the first semiconductor pattern;

[0030] The first extension portion includes a first portion, a second portion and a third portion, the first portion and the third portion both extend along the first direction, the second portion extends along the second direction, one end of the second portion is coupled to the first portion, and the other end of the second portion is coupled to the third portion;

[0031] One end of the third portion away from the second portion is coupled to the first transistor.

[0032] Optionally, the sub-pixel driving circuit further includes: a first transistor and a sixth transistor; the first transistor includes:

[0033] a fourth semiconductor pattern, a fifth semiconductor pattern, and a sixth conductor pattern respectively coupled to the fourth semiconductor pattern and the fifth semiconductor pattern, wherein the conductivity of the sixth conductor pattern is better than the conductivity of the fourth semiconductor pattern and the conductivity of the fifth semiconductor pattern;

[0034] A third gate pattern and a fourth gate pattern coupled to each other, wherein the orthographic projection of the third gate pattern on the substrate partially overlaps with the orthographic projection of the fourth semiconductor pattern on the substrate, and the orthographic projection of the fourth gate pattern on the substrate partially overlaps with the orthographic projection of the fifth semiconductor pattern on the substrate;

[0035] The orthographic projection of the sixth conductor pattern on the substrate does not overlap with the orthographic projection of the third gate pattern on the substrate, and the orthographic projection of the fourth gate pattern on the substrate.

[0036] Optionally, the sub-pixel further includes an initialization signal line pattern, the initialization signal line pattern includes a portion extending along a second direction, the second direction intersects the first direction, and the initialization signal line pattern is used to transmit an initialization signal with a fixed potential;

[0037] The sub-pixel driving circuit further includes:

[0038] A first shielding component coupled to the initialization signal line pattern, wherein an orthographic projection of the first shielding component on the substrate at least partially overlaps with an orthographic projection of the sixth conductor pattern on the substrate.

[0039] Optionally, the sub-pixel further includes an initialization signal line pattern, the initialization signal line pattern includes a portion extending along a second direction, the second direction intersects the first direction, and the initialization signal line pattern is used to transmit an initialization signal with a fixed potential;

[0040] The sub-pixel driving circuit further includes:

[0041] A first shielding component coupled to the initialization signal line pattern, a second shielding component coupled to the first shielding component, and an orthographic projection of the second shielding component on the substrate at least partially overlaps with an orthographic projection of the sixth conductor pattern on the substrate.

[0042] Optionally, the first shielding component is an extended structure extending from the initialization signal line pattern.

[0043] Optionally, the first shielding component and the initialization signal line pattern are arranged in different layers, an orthographic projection of the first shielding component on the substrate and an orthographic projection of the initialization signal line pattern on the substrate have a first overlapping area, and the first shielding component is coupled to the initialization signal line pattern through a first via hole arranged in the first overlapping area;

[0044] The second shielding component and the first shielding component are arranged in different layers, and there is a second overlapping area between the orthographic projection of the second shielding component on the substrate and the orthographic projection of the first shielding component on the substrate, and the second shielding component and the first shielding component are coupled through a second via hole arranged in the second overlapping area.

[0045] Optionally, the first shielding component and the data line pattern are made of the same material.

[0046] Optionally, the display substrate includes a first interlayer insulating layer, and the first shielding component and the data line pattern are both located on a surface of the first interlayer insulating layer facing away from the base.

[0047] Optionally, the second shielding component and the initialization signal line pattern are made of the same material.

[0048] Optionally, the display substrate further includes a second interlayer insulating layer, and the second shielding component and the initialization signal line pattern are both located on a surface of the second interlayer insulating layer facing away from the base.

[0049] Optionally, the first electrode in the storage capacitor is reused as the gate of the driving transistor, the second electrode in the storage capacitor is made of the same material as the second shielding component, and the second electrode in the storage capacitor is located on the surface of the second interlayer insulating layer facing away from the substrate.

[0050] Optionally, the sub-pixel further includes: a reset signal line pattern extending along a second direction intersecting the first direction, and the sub-pixel driving circuit further includes:

[0051] a first conductive connection portion, wherein an orthographic projection of the first conductive connection portion on the substrate covers at least a portion of an orthographic projection of the sixth conductor pattern on the substrate;

[0052] A second transistor, wherein a first electrode of the second transistor is coupled to the initialization signal line pattern through the first conductive connection portion, a second electrode of the second transistor is coupled to the gate of the driving transistor, and a gate of the second transistor is coupled to the reset signal line pattern.

[0053] Optionally, the sub-pixel further includes: a gate line pattern, a light emitting control signal line pattern, a reset signal line pattern and an initialization signal line pattern; the gate line pattern, the light emitting control signal line pattern, the reset signal line pattern and the initialization signal line pattern all extend along a second direction, and the second direction intersects the first direction;

[0054] The two switch transistors include a fourth transistor and a fifth transistor;

[0055] The sub-pixel driving circuit further includes: a first transistor, a second transistor, a sixth transistor and a seventh transistor;

[0056] The gate of the driving transistor is coupled to the second electrode of the first transistor, the first electrode of the driving transistor is coupled to the second electrode of the fifth transistor, and the second electrode of the driving transistor is coupled to the first electrode of the first transistor;

[0057] The gate of the first transistor is coupled to the gate line pattern;

[0058] The gate of the second transistor is coupled to the reset signal line pattern, the first electrode of the second transistor is coupled to the initialization signal line pattern, and the second electrode of the second transistor is coupled to the gate of the driving transistor;

[0059] The gate electrode of the fourth transistor is coupled to the gate line pattern, the first electrode of the fourth transistor is coupled to the data line pattern, and the second electrode of the fourth transistor is coupled to the first electrode of the driving transistor;

[0060] The gate electrode of the fifth transistor is coupled to the light emitting control signal line pattern, and the first electrode of the fifth transistor is coupled to the power supply signal line pattern;

[0061] The gate of the sixth transistor is coupled to the light emitting control signal line pattern, the first electrode of the sixth transistor is coupled to the second electrode of the driving transistor, and the second electrode of the sixth transistor is coupled to the corresponding light emitting element in the sub-pixel;

[0062] The gate of the seventh transistor is coupled to the reset signal line pattern included in the next sub-pixel adjacent to the first direction, the first electrode of the seventh transistor is coupled to the initialization signal line pattern included in the next sub-pixel, and the second electrode of the seventh transistor is coupled to the light-emitting element in the sub-pixel.

[0063] A second aspect of the present disclosure provides a display substrate, comprising: a substrate and a plurality of sub-pixels distributed in an array on the substrate; the sub-pixels comprising:

[0064] A data line pattern extending along a first direction;

[0065] an initialization signal line pattern, the initialization signal line pattern including a portion extending along a second direction, the second direction intersecting the first direction, the initialization signal line pattern being used to transmit an initialization signal having a fixed potential;

[0066] A sub-pixel driving circuit, the sub-pixel driving circuit comprising: a driving transistor, a first transistor coupled to the gate of the driving transistor, and a first shielding component coupled to the initialization signal line pattern, the first shielding component having an orthographic projection on the substrate located between the orthographic projection of the first transistor on the substrate and the orthographic projection of the target data line pattern on the substrate; the target data line pattern is included in the next sub-pixel adjacent to the sub-pixel along the second direction.

[0067] Optionally, the plurality of sub-pixels include a plurality of rows of sub-pixels, each row of sub-pixels includes a plurality of sub-pixels arranged along the second direction, and the initialization signal line patterns in the sub-pixels in the same row are coupled in sequence to form an initialization signal line corresponding to the sub-pixels in the row;

[0068] The first shielding part extends along the first direction and is coupled to at least one of the initialization signal lines.

[0069] Optionally, the first shielding component is coupled to two adjacent initialization signal lines.

[0070] Optionally, the first shielding component and the initialization signal line pattern are arranged in different layers, and the orthographic projection of the first shielding component on the substrate and the orthographic projection of the initialization signal line pattern on the substrate have a first overlapping area, and the first shielding component is coupled to the initialization signal line pattern through a first via hole arranged in the first overlapping area.

[0071] Optionally, the first shielding component and the data line pattern are made of the same material.

[0072] Optionally, the display substrate includes a first interlayer insulating layer, and the first shielding component and the data line pattern are both located on a surface of the first interlayer insulating layer facing away from the base.

[0073] Optionally, the sub-pixel driving circuit further includes a second transistor coupled to the gate of the driving transistor, and the second transistor includes:

[0074] A first semiconductor pattern, a second semiconductor pattern, and a third conductor pattern coupled to the first semiconductor pattern and the second semiconductor pattern, respectively, wherein the conductivity of the third conductor pattern is better than the conductivity of the first semiconductor pattern and the conductivity of the second semiconductor pattern;

[0075] A first gate pattern and a second gate pattern coupled to each other, wherein an orthographic projection of the first gate pattern on the substrate at least partially overlaps with an orthographic projection of the first semiconductor pattern on the substrate, and an orthographic projection of the second gate pattern on the substrate at least partially overlaps with an orthographic projection of the second semiconductor pattern on the substrate;

[0076] The orthographic projection of the third conductor pattern on the substrate does not overlap with the orthographic projection of the first gate pattern on the substrate, and the orthographic projection of the second gate pattern on the substrate;

[0077] The orthographic projection of the third conductor pattern on the substrate at least partially overlaps with the orthographic projection of the initialization signal line pattern on the substrate.

[0078] Optionally, the sub-pixel driving circuit further includes a first extending portion extending from the first semiconductor pattern, and the first extending portion has a better conductivity than the first semiconductor pattern;

[0079] The first extension portion includes a first portion, a second portion and a third portion, the first portion and the third portion both extend along the first direction, the second portion extends along the second direction, one end of the second portion is coupled to the first portion, and the other end of the second portion is coupled to the third portion;

[0080] One end of the third portion away from the second portion is coupled to the first transistor.

[0081] Optionally, the first transistor includes:

[0082] a fourth semiconductor pattern, a fifth semiconductor pattern, and a sixth conductor pattern respectively coupled to the fourth semiconductor pattern and the fifth semiconductor pattern, wherein the conductivity of the sixth conductor pattern is better than the conductivity of the fourth semiconductor pattern and the conductivity of the fifth semiconductor pattern;

[0083] A third gate pattern and a fourth gate pattern coupled to each other, wherein the orthographic projection of the third gate pattern on the substrate partially overlaps with the orthographic projection of the fourth semiconductor pattern on the substrate, and the orthographic projection of the fourth gate pattern on the substrate partially overlaps with the orthographic projection of the fifth semiconductor pattern on the substrate;

[0084] The orthographic projection of the sixth conductor pattern on the substrate does not overlap with the orthographic projection of the third gate pattern on the substrate, and the orthographic projection of the fourth gate pattern on the substrate.

[0085] Optionally, an orthographic projection of the first shielding component on the substrate at least partially overlaps with an orthographic projection of the sixth conductor pattern on the substrate.

[0086] Optionally, the sub-pixel driving circuit further includes:

[0087] A second shielding component is coupled to the first shielding component, and an orthographic projection of the second shielding component on the substrate at least partially overlaps with an orthographic projection of the sixth conductor pattern on the substrate.

[0088] Optionally, the second shielding component and the first shielding component are arranged in different layers, and there is a second overlapping area between the orthographic projection of the second shielding component on the substrate and the orthographic projection of the first shielding component on the substrate, and the second shielding component and the first shielding component are coupled through a second via arranged in the second overlapping area.

[0089] Optionally, the second shielding component and the initialization signal line pattern are made of the same material.

[0090] Optionally, the display substrate further includes a second interlayer insulating layer, and the second shielding component and the initialization signal line pattern are both located on a surface of the second interlayer insulating layer facing away from the base.

[0091] Optionally, the sub-pixel also includes a power signal line pattern, the power signal line pattern includes a portion extending along the first direction, and the sub-pixel driving circuit also includes a storage capacitor, the first electrode in the storage capacitor is reused as the gate of the driving transistor, the second electrode in the storage capacitor is coupled to the power signal line pattern, and the second electrode in the storage capacitor is located on the surface of the second interlayer insulating layer facing away from the substrate.

[0092] Optionally, the sub-pixel further includes: a reset signal line pattern extending along a second direction intersecting the first direction, and the sub-pixel driving circuit further includes:

[0093] a first conductive connection portion, wherein an orthographic projection of the first conductive connection portion on the substrate covers at least a portion of an orthographic projection of the sixth conductor pattern on the substrate;

[0094] A second transistor, wherein a first electrode of the second transistor is coupled to the initialization signal line pattern through the first conductive connection portion, a second electrode of the second transistor is coupled to the gate of the driving transistor, and a gate of the second transistor is coupled to the reset signal line pattern.

[0095] Optionally, the sub-pixel further includes: a gate line pattern, a light emitting control signal line pattern, a reset signal line pattern and a power signal line pattern; the gate line pattern, the light emitting control signal line pattern and the reset signal line pattern all extend along the second direction, and the power signal line pattern includes a portion extending along the first direction;

[0096] The sub-pixel driving circuit further includes: a second transistor, a fourth transistor, a fifth transistor, a sixth transistor and a seventh transistor;

[0097] The gate of the driving transistor is coupled to the second electrode of the first transistor, the first electrode of the driving transistor is coupled to the second electrode of the fifth transistor, and the second electrode of the driving transistor is coupled to the first electrode of the first transistor;

[0098] The gate of the first transistor is coupled to the gate line pattern;

[0099] The gate of the second transistor is coupled to the reset signal line pattern, the first electrode of the second transistor is coupled to the initialization signal line pattern, and the second electrode of the second transistor is coupled to the gate of the driving transistor;

[0100] The gate electrode of the fourth transistor is coupled to the gate line pattern, the first electrode of the fourth transistor is coupled to the data line pattern, and the second electrode of the fourth transistor is coupled to the first electrode of the driving transistor;

[0101] The gate electrode of the fifth transistor is coupled to the light emitting control signal line pattern, and the first electrode of the fifth transistor is coupled to the power supply signal line pattern;

[0102] The gate of the sixth transistor is coupled to the light emitting control signal line pattern, the first electrode of the sixth transistor is coupled to the second electrode of the driving transistor, and the second electrode of the sixth transistor is coupled to the light emitting element in the sub-pixel;

[0103] The gate of the seventh transistor is coupled to the reset signal line pattern included in the next sub-pixel adjacent to the first direction, the first electrode of the seventh transistor is coupled to the initialization signal line pattern included in the next sub-pixel, and the second electrode of the seventh transistor is coupled to the light-emitting element in the sub-pixel.

[0104] Optionally, the sub-pixel also includes: a gate line pattern, a light-emitting control signal line pattern, a reset signal line pattern and a power signal line pattern; the gate line pattern, the light-emitting control signal line pattern and the reset signal line pattern all extend along the second direction, and the power signal line pattern includes a portion extending along the first direction; the orthographic projection of the first shielding component on the substrate overlaps with the orthographic projection of the gate line pattern on the substrate and the orthographic projection of the light-emitting control signal line pattern on the substrate, respectively.

[0105] Based on the technical solution of the above-mentioned display substrate, a third aspect of the present disclosure provides a display device, comprising the above-mentioned display substrate.

[0106] Based on the technical solution of the above-mentioned display substrate, the fourth aspect of the present disclosure provides a method for manufacturing a display substrate, the manufacturing method comprising: manufacturing a plurality of sub-pixels distributed in an array on a substrate; the sub-pixels comprising: a data line pattern extending along a first direction; a power signal line pattern, the power signal line pattern comprising a portion extending along the first direction; a sub-pixel driving circuit, the sub-pixel driving circuit comprising: two switching transistors, a driving transistor and a storage capacitor; the first plate of the storage capacitor is coupled to the gate of the driving transistor, and the second plate of the storage capacitor is coupled to the power signal line pattern; the second poles of the two switching transistors are both coupled to the first pole of the driving transistor, and the orthographic projection of the second pole of at least one of the two switching transistors on the substrate at least partially overlaps with the orthographic projection of the power signal line pattern on the substrate, and at least partially overlaps with the orthographic projection of the second plate of the storage capacitor on the substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0107] The drawings described herein are used to provide a further understanding of the present disclosure and constitute a part of the present disclosure. The illustrative embodiments of the present disclosure and their descriptions are used to explain the present disclosure and do not constitute an improper limitation on the present disclosure. In the drawings:

[0108] Figure 1 A schematic diagram of the structure of a sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0109] Figure 2 A working timing diagram corresponding to the sub-pixel driving circuit provided in an embodiment of the present disclosure;

[0110] Figure 3 A first schematic layout diagram of a sub-pixel driving circuit in a display substrate provided by an embodiment of the present disclosure;

[0111] Figure 4 A first schematic layout diagram of an active film layer provided in an embodiment of the present disclosure;

[0112] Figure 5 A first layout schematic diagram of a first gate metal layer provided in an embodiment of the present disclosure;

[0113] Figure 6 A first schematic layout diagram of a second gate metal layer provided in an embodiment of the present disclosure;

[0114] Figure 7 A first schematic layout diagram of a source-drain metal layer provided in an embodiment of the present disclosure.

[0115] Figure 8 for Figure 3 Schematic diagram of the cross section along the A1A2 direction;

[0116] Fig. 9 A second schematic layout diagram of a sub-pixel driving circuit in a display substrate provided in an embodiment of the present disclosure;

[0117] Fig.10 A third schematic layout diagram of a sub-pixel driving circuit in a display substrate provided by an embodiment of the present disclosure;

[0118] Fig.11 A fourth schematic layout diagram of a sub-pixel driving circuit in a display substrate provided by an embodiment of the present disclosure;

[0119] Fig.12 A fifth schematic layout diagram of a sub-pixel driving circuit in a display substrate provided by an embodiment of the present disclosure;

[0120] Fig.13 for Fig.11 Schematic diagram of the cross section along the B1B2 direction;

[0121] Fig.14A sixth schematic layout diagram of a sub-pixel driving circuit in a display substrate provided by an embodiment of the present disclosure;

[0122] Fig.15 A schematic diagram of a first layout of a plurality of sub-pixels in a display substrate provided in an embodiment of the present disclosure;

[0123] Fig.16 A seventh schematic layout diagram of a sub-pixel driving circuit in a display substrate provided by an embodiment of the present disclosure;

[0124] Fig.17 for Fig.16 Schematic diagram of the cross section along the C1C2 direction;

[0125] Fig.18 A second schematic layout diagram of an active film layer provided in an embodiment of the present disclosure;

[0126] Fig.19 An eighth schematic layout diagram of a sub-pixel driving circuit in a display substrate provided by an embodiment of the present disclosure;

[0127] Fig. 20 A ninth layout diagram of a sub-pixel driving circuit in a display substrate provided by an embodiment of the present disclosure;

[0128] Fig.21 A tenth schematic layout diagram of a sub-pixel driving circuit in a display substrate provided by an embodiment of the present disclosure;

[0129] Fig. 22 for Fig.21 Schematic diagram of the cross section along the D1D2 direction;

[0130] Fig.23 is a schematic diagram of the layout of the third metal layer;

[0131] Fig.24 A second schematic diagram of the layout of multiple sub-pixels in a display substrate provided by an embodiment of the present disclosure;

[0132] Fig.25 A schematic diagram of the crosstalk phenomenon occurring at the gate of a driving transistor in the related art;

[0133] Fig.26 An eleventh schematic layout diagram of a sub-pixel driving circuit in a display substrate provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0134] In order to further illustrate the display substrate and the display device provided by the embodiments of the present disclosure, a detailed description is given below in conjunction with the accompanying drawings.

[0135] In the related art, there are various reasons for the crosstalk generated in OLED display products, among which the main crosstalk is the crosstalk caused by the data line pattern located around the driving transistor in the sub-pixel driving circuit to the driving transistor. In more detail, when the sub-pixel driving circuit is laid out, the periphery of the driving transistor in the sub-pixel driving circuit also includes various transistors with other functions, and these transistors are all composed of multi-layer conductive patterns. Moreover, various signal line patterns for transmitting different signals are also arranged around the driving transistor. When the sub-pixel driving circuit is working, the conductive patterns included in the various transistors and the signal changes on the various signal line patterns are likely to cause crosstalk to the driving transistor, thereby affecting the working performance of the driving transistor.

[0136] Based on the existence of the above problems, the inventors of the present disclosure have found through research that the crosstalk affecting the working performance of the driving transistor mainly includes: the crosstalk problem caused by the coupling between the data line pattern and the gate of the driving transistor, and the crosstalk problem caused by the coupling between the data line pattern and the first electrode of the driving transistor.

[0137] The inventors of the present disclosure have further discovered that a pattern with a fixed potential can be formed on the first electrode of the driving transistor, and the first electrode of the driving transistor can be shielded by the pattern with a fixed potential, thereby reducing the coupling effect between the data line pattern located near the first electrode of the driving transistor and the first electrode of the driving transistor, thereby weakening the crosstalk problem caused by the data line pattern to the driving transistor, and enabling the display product to achieve a better display effect.

[0138] It should be noted that one or more embodiments described herein correspond to a display substrate having a 7T1C (i.e., 7 thin film transistors and 1 capacitor) sub-pixel driving circuit. In another embodiment, the display substrate may include a different sub-pixel driving circuit, for example, more than or less than 7 thin film transistors, and one or more capacitors.

[0139] like Figure 1 As shown, the display substrate provided by the present disclosure includes multiple sub-pixels, and each sub-pixel may include: a gate line graphic GATE, a first reset signal line graphic RST1, a first initialization signal line graphic VINT1, a data line graphic DATA, a light emitting control signal line graphic EM, a power signal line graphic VDD, a second reset signal line graphic RST2 and a second initialization signal line graphic VINT2.

[0140] The sub-pixel driving circuit in each sub-pixel may include: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and a storage capacitor Cst. In addition, Figure 1The first capacitor C1 is also included, and the first capacitor C1 is a parasitic capacitor.

[0141] Taking a sub-pixel driving circuit as an example, each transistor included in the sub-pixel driving circuit is a P-type transistor, wherein the first transistor T1 is a dual-gate structure, the gate 201g of the first transistor T1 is coupled to the gate line pattern GATE, the source S1 of the first transistor T1 is coupled to the drain D3 of the third transistor T3, and the drain D1 of the first transistor T1 is coupled to the gate 203g of the third transistor T3.

[0142] The second transistor T2 has a dual-gate structure, a gate 202g of the second transistor T2 is coupled to the first reset signal line pattern RST1, a source S2 of the second transistor T2 is coupled to the first initialization signal line pattern VINT1, and a drain D2 of the second transistor T2 is coupled to the gate 203g of the third transistor T3.

[0143] The gate 204g of the fourth transistor T4 is coupled to the gate line pattern GATE, the source S4 of the fourth transistor T4 is coupled to the data line pattern DATA, and the drain D4 of the fourth transistor T4 is coupled to the source S3 of the third transistor T3.

[0144] The gate 205g of the fifth transistor T5 is coupled to the light emitting control signal line pattern EM, the source S5 of the fifth transistor T5 is coupled to the power signal line pattern VDD, and the drain D5 of the fifth transistor T5 is coupled to the source S3 of the third transistor T3.

[0145] The gate 206g of the sixth transistor T6 is coupled to the light emitting control signal line pattern EM, the source S6 of the sixth transistor T6 is coupled to the drain D3 of the third transistor T3, and the drain D6 of the sixth transistor T6 is coupled to the anode of the light emitting element OLED.

[0146] The gate 207g of the seventh transistor T7 is coupled to the second reset signal line pattern RST2, the drain D7 of the seventh transistor T7 is coupled to the anode of the light emitting element OLED, and the source S7 of the seventh transistor T7 is coupled to the second initialization signal line pattern VINT2.

[0147] The first plate Cst1 of the storage capacitor Cst is coupled to the gate 203g of the third transistor T3, and the second plate Cst2 of the storage capacitor Cst is coupled to the power signal line pattern VDD.

[0148] like Figure 2 As shown, when the sub-pixel driving circuit of the above structure is working, each working cycle includes a first reset period P1, a writing compensation period P2, a second reset period P3 and a light emitting period P4.

[0149] In the first reset period P1, the first reset signal input by the first reset signal line graph RST1 is at a valid level, the second transistor T2 is turned on, and the initialization signal transmitted by the first initialization signal line graph VINT1 is input to the gate 203g of the third transistor T3, so that the gate-source voltage Vgs maintained on the third transistor T3 in the previous frame is cleared, thereby resetting the gate 203g of the third transistor T3.

[0150] During the write compensation period P2, the first reset signal is at a non-valid level, the second transistor T2 is turned off, the gate scan signal input by the gate line pattern GATE is at a valid level, the first transistor T1 and the fourth transistor T4 are controlled to be turned on, the data line pattern DATA writes the data signal, and transmits it to the source S3 of the third transistor T3 through the fourth transistor T4. At the same time, the first transistor T1 and the fourth transistor T4 are turned on, so that the third transistor T3 forms a diode structure. Therefore, the threshold voltage compensation of the third transistor T3 is realized by the cooperation of the first transistor T1, the third transistor T3 and the fourth transistor T4. When the compensation time is long enough, the gate 203g potential of the third transistor T3 can be controlled to finally reach Vdata+Vth, wherein Vdata represents the data signal voltage value, and Vth represents the threshold voltage of the third transistor T3.

[0151] In the second reset period P3, the gate scan signal is at a non-valid level, the first transistor T1 and the fourth transistor T4 are both turned off, the second reset signal input by the second reset signal line RST2 is at a valid level, the seventh transistor T7 is controlled to be turned on, and the initialization signal transmitted by the second initialization signal line graph VINT2 is input to the anode of the light-emitting element OLED, controlling the light-emitting element OLED not to emit light.

[0152] During the light-emitting period P4, the light-emitting control signal written in the light-emitting control signal line graphic EM is at a valid level, and the fifth transistor T5 and the sixth transistor T6 are controlled to be turned on, so that the power signal transmitted by the power signal line graphic VDD is input to the source S3 of the third transistor T3. At the same time, since the gate 203g of the third transistor T3 is maintained at Vdata+Vth, the third transistor T3 is turned on, and the gate-source voltage corresponding to the third transistor T3 is Vdata+Vth-VDD, wherein VDD is the voltage value corresponding to the power signal, and the leakage current generated based on the gate-source voltage flows to the anode of the corresponding light-emitting element OLED, driving the corresponding light-emitting element OLED to emit light.

[0153] like Figure 3 As shown, when manufacturing the above sub-pixel driving circuit, the layout of each film layer corresponding to the sub-pixel driving circuit is as follows:

[0154] An active film layer, a gate insulating layer, a first gate metal layer, a first interlayer insulating layer, a second gate metal layer, a second interlayer insulating layer, a first source-drain metal layer and a third interlayer insulating layer are sequentially stacked in a direction away from the substrate.

[0155] like Figure 4 As shown, the active film layer is used to form the channel region (such as: 101pg ~ 107pg), source formation region (such as: 101ps ~ 107ps) and drain formation region (such as: 101pd ~ 107pd) of each transistor in the sub-pixel driving circuit. The active film layer corresponding to the source formation region and the drain formation region has better conductivity than the active film layer corresponding to the channel region due to doping. The active film layer can be made of amorphous silicon, polycrystalline silicon, oxide semiconductor materials, etc. It should be noted that the above-mentioned source region and drain region can be regions doped with n-type impurities or p-type impurities.

[0156] In addition, it is worth noting that the active film layers corresponding to the source formation region and the drain formation region can be directly used as the corresponding source or drain, or, the source in contact with the source formation region can be made of metal material, and the drain in contact with the drain formation region can be made of metal material.

[0157] like Figure 5 As shown, the first gate metal layer is used to form the gate of each transistor in the sub-pixel driving circuit (such as: 201g~207g), and the display substrate includes a gate line graphic GATE, a light-emitting control signal line graphic EM, a first reset signal line graphic RST1 and a second reset signal line graphic RST2 and other structures. The gate 203g of the third transistor T3 in each sub-pixel driving circuit is reused as the first plate Cst1 of the storage capacitor Cst in the sub-pixel driving circuit.

[0158] like Figure 6 As shown, the second gate metal layer is used to form the second electrode plate Cst2 of the storage capacitor Cst, and the display substrate includes a first initialization signal line pattern VINT1 and a second initialization signal line pattern VINT2.

[0159] like Figure 1 , Figure 3 and 7 As shown, the first source-drain metal layer is used to form the source (eg, S1-S7) and drain (eg, D1-D7) of each transistor in the sub-pixel driving circuit, as well as the data line pattern (eg, DATA1 and DATA2) and the power signal line pattern VDD included in the display substrate.

[0160] For more details, please refer to Figure 3 , Figure 7 to Figure 10, the gate 201g of the first transistor T1 covers the first channel region 101pg, the source S1 of the first transistor T1 is located in the first source formation region 101ps, and the drain D1 of the first transistor T1 is located in the first drain formation region 101pd.

[0161] The gate 202g of the second transistor T2 covers the second channel region 102pg, the source S2 of the second transistor T2 is located in the second source formation region 102ps, and the drain D2 of the second transistor T2 is located in the second drain formation region 102pd.

[0162] The gate 203g of the third transistor T3 covers the third channel region 103pg, the source S3 of the third transistor T3 is located in the third source formation region 103ps, and the drain D3 of the third transistor T3 is located in the third drain formation region 103pd.

[0163] The gate 204g of the fourth transistor T4 covers the fourth channel region 104pg, the source S4 of the fourth transistor T4 is located in the fourth source formation region 104ps, and the drain D4 of the fourth transistor T4 is located in the fourth drain formation region 104pd.

[0164] The gate 205g of the fifth transistor T5 covers the fifth channel region 105pg, the source S5 of the fifth transistor T5 is located in the fifth source formation region 105ps, and the drain D5 of the fifth transistor T5 is located in the fifth drain formation region 105pd.

[0165] The gate 206g of the sixth transistor T6 covers the sixth channel region 106pg, the source S6 of the sixth transistor T6 is located in the sixth source formation region 106ps, and the drain D6 of the sixth transistor T6 is located in the sixth drain formation region 106pd.

[0166] The gate 207g of the seventh transistor T7 covers the seventh channel region 107pg, the source S7 of the seventh transistor T7 is located in the seventh source formation region 107ps, and the drain D7 of the seventh transistor T7 is located in the seventh drain formation region 107pd.

[0167] The gate 203g of the third transistor T3 is multiplexed as a first plate Cst1 of the storage capacitor Cst, and a second plate Cst2 of the storage capacitor Cst is coupled to the power signal line pattern VDD.

[0168] Need to explain, Figure 1 The connecting lines 401, 402 and 403 in FIG. 1 are all formed by the first source-drain metal layer. The specific layout is as follows: Figure 3 and Figure 7 shown. Figure 1 The first capacitor C1 in is a parasitic capacitor, such as Figure 3As shown, the orthographic projection of the second plate Cst2 of the storage capacitor Cst on the substrate overlaps with the orthographic projection of the downwardly extended portion of the fourth drain forming region 104pd corresponding to the fourth transistor T4 on the substrate, and the overlapping region forms the first capacitor C1 shown.

[0169] In addition, in the display substrate provided by the present disclosure, the multiple sub-pixels included may be distributed in an array, and the multiple sub-pixels may be divided into multiple rows of sub-pixels and multiple columns of sub-pixels, each row of sub-pixels includes multiple sub-pixels arranged along a second direction, and each column of sub-pixels includes multiple sub-pixels arranged along a first direction, and the first direction intersects with the second direction; the gate line graphic GATE, the first reset signal line graphic RST1, the first initialization signal line graphic VINT1, the light emitting control signal line graphic EM, the second reset signal line graphic RST2, and the second initialization signal line graphic VINT2 included in the sub-pixels may all extend along the second direction; the data line graphic DATA and the power signal line graphic VDD included in the sub-pixels both extend along the first direction.

[0170] The gate line graph GATE located in the same row can be formed into a gate line of an integrated structure, the first reset signal line graph RST1 located in the same row can be formed into a first reset signal line of an integrated structure, the first initialization signal line graph VINT1 located in the same row can be formed into a first initialization signal line of an integrated structure, the light-emitting control signal line graph EM located in the same row can be formed into a light-emitting control signal line of an integrated structure, the second reset signal line graph RST2 located in the same row can be formed into a second reset signal line of an integrated structure, and the second initialization signal line graph VINT2 located in the same row can be formed into a second initialization signal line of an integrated structure. The data line graph DATA located in the same column can be formed into a data line of an integrated structure, and the power signal line graph VDD located in the same column can be formed into a power signal line of an integrated structure.

[0171] In order to simplify the layout space of sub-pixels, the second reset signal line corresponding to a row of sub-pixels can be multiplexed as the first reset signal line corresponding to the next adjacent row of sub-pixels; similarly, the second initialization signal line corresponding to a row of sub-pixels can be multiplexed as the first initialization signal line corresponding to the next adjacent row of sub-pixels.

[0172] like Figure 3As shown, in some embodiments, taking the sub-pixel driving circuit included in a sub-pixel as an example, in the first direction (such as the Y direction), the gate 204g of the fourth transistor T4, the gate 201g of the first transistor T1, and the gate 202g of the second transistor T2 are all located on the first side of the gate of the driving transistor (i.e., the gate 203g of the third transistor T3), and the gate of the seventh transistor T7, the gate 206g of the sixth transistor T6, and the gate of the fifth transistor T5 are all located on the second side of the gate of the driving transistor. Exemplarily, the first side and the second side of the gate of the driving transistor are two sides of the gate of the driving transistor opposite to each other in the first direction, and further, the first side of the gate of the driving transistor can be the upper side of the gate of the driving transistor, and the second side of the gate of the driving transistor can be the lower side of the gate of the driving transistor T1. The lower side, for example, the side of the display substrate used for binding the IC is the lower side of the display substrate, and the lower side of the gate of the driving transistor is the side of the gate of the driving transistor that is closer to the IC. The upper side is the opposite side of the lower side, for example, the side of the gate of the driving transistor that is farther away from the IC.

[0173] In some embodiments, Figure 3 As shown, in the second direction (such as the X direction), the gate 204g of the fourth transistor T4 and the gate 205g of the fifth transistor T5 are both located on the third side of the gate of the driving transistor, and the gate 201g of the first transistor T1 and the gate 206g of the sixth transistor T6 are both located on the fourth side of the gate of the driving transistor T1. Exemplarily, the third side and the fourth side of the gate of the driving transistor are two sides of the gate of the driving transistor that are opposite to each other in the second direction X; further, the third side of the gate of the driving transistor may be the left side of the gate of the driving transistor, and the fourth side of the gate of the driving transistor may be the right side of the gate of the driving transistor. The left side and the right side, for example, in the same sub-pixel, the first data line graph DATA1 is located on the left side of the power signal line graph VDD, and the power signal line graph VDD is on the right side of the first data line graph DATA1.

[0174] See also Figure 3 and Figure 8 The embodiment of the present disclosure provides a display substrate, comprising: a substrate 50 and a plurality of sub-pixels distributed in an array on the substrate 50; the sub-pixels include:

[0175] The data line pattern extending along the first direction (such as Figure 3 DATA1 in );

[0176] Initialize the signal line graphics (such as Figure 3The initialization signal line pattern includes a portion extending along a second direction, the second direction intersects the first direction, and the initialization signal line pattern is used to transmit an initialization signal having a fixed potential;

[0177] A sub-pixel driving circuit, the sub-pixel driving circuit comprising: a driving transistor (such as Figure 3 T3 in the figure), a first transistor T1 coupled to the gate of the driving transistor, and a first shielding component 404 coupled to the initialization signal line pattern, wherein the positive projection of the first shielding component 404 on the substrate 50 is located between the positive projection of the first transistor T1 on the substrate 50 and the target data line pattern (such as Figure 3 DATA2 in the sub-pixel) between the positive projections on the substrate 50; the next sub-pixel adjacent to the sub-pixel along the second direction includes the target data line pattern.

[0178] Specifically, the display substrate generally includes a plurality of sub-pixels distributed in an array, and each sub-pixel includes: a data line pattern extending along a first direction (eg Figure 3 DATA1 in ), and an initialization signal line pattern extending at least partially along the second direction (such as Figure 3 VINT1 in the figure); the data line pattern is used to transmit a data signal, and the initialization signal line pattern is used to transmit an initialization signal with a fixed potential; exemplarily, the first direction includes a Y direction, and the second direction includes an X direction.

[0179] The target data line pattern is: a data line pattern included in a next sub-pixel adjacent to the current sub-pixel along the second direction.

[0180] Each sub-pixel also includes a sub-pixel driving circuit and a light-emitting element corresponding to the sub-pixel driving circuit one by one, the light-emitting element includes a stacked anode, an organic light-emitting material layer and a cathode, wherein the anode of the light-emitting element is coupled to the corresponding sub-pixel driving circuit, and the light-emitting element emits light under the drive signal provided by the sub-pixel driving circuit.

[0181] In more detail, Figure 1 , Figure 3 and Figure 4 As shown, taking the sub-pixel driving circuit including the above 7T1C as an example, the gate 203g of the third transistor T3 (i.e., the driving transistor) is coupled to the drain D1 of the first transistor T1 through the connecting line 401, and the drain D3 of the third transistor T3 is coupled to the source S1 of the first transistor T1. Along the X direction, the positive projection of the first channel region 101pg of the first transistor T1 on the substrate 50 is aligned with the target data line pattern (e.g., Figure 3The minimum distance between the orthographic projections of the first channel region 101pg and the third channel region 103pg of the third transistor T3 on the substrate 50 and the orthographic projections of the target data line pattern on the substrate 50 is smaller than the minimum distance between the orthographic projections of the third channel region 103pg of the third transistor T3 on the substrate 50 and the orthographic projections of the target data line pattern on the substrate 50. It is worth noting that the orthographic projections of the above-mentioned channel regions (such as the first channel region 101pg and the third channel region 103pg) on ​​the substrate 50 and the orthographic projections of the target data line pattern (such as Figure 3 The minimum distance between the orthographic projections of the channel region on the substrate 50 is: the boundary of the orthographic projection of the channel region on the substrate 50 that is closest to the target data line pattern and the target data line pattern (such as Figure 3 DATA2 in (the minimum distance between the orthographic projections on the substrate 50).

[0182] In the sub-pixel driving circuit of the above structure, when the data signal transmitted by the target data line pattern changes, the performance of the first transistor T1 will be affected. Since the first transistor T1 is coupled to the third transistor T3 through the connecting line 401, the working performance of the third transistor T3 will be affected.

[0183] In the embodiment of the present disclosure, a sub-pixel driving circuit is provided with a signal line pattern (such as Figure 3 The first shielding component 404 is coupled to the VINT1 in the substrate 50, so that the first shielding component 404 has the same fixed potential as the initialization signal, and the positive projection of the first shielding component 404 on the substrate 50 is set, and the positive projection of the first transistor T1 on the substrate 50 is aligned with the target data line pattern (such as Figure 3 DATA2 in the target data line pattern) between the positive projections on the substrate 50, so that the first shielding component 404 can reduce the influence of the signal change transmitted on the target data line pattern on the performance of the first transistor T1, thereby reducing the influence of the coupling between the gate of the driving transistor (i.e., 203g) and the target data line pattern, weakening the problem of vertical crosstalk, so that the display substrate can obtain a better display effect when used for display.

[0184] In addition, the above-mentioned coupling of the first shielding component 404 with the initialization signal line pattern not only makes the first shielding component 404 have a fixed potential, but also strengthens the voltage of the initialization signal line pattern, so that the voltage of the initialization signal transmitted on the initialization signal line pattern is more stable, which is more conducive to the working performance of the sub-pixel driving circuit.

[0185] It is worth noting that in addition to coupling the first shielding component 404 with the initialization signal line pattern, the first shielding component 404 can also be coupled with the power signal line pattern VDD included in the sub-pixel, so that the first shielding component 404 has the same fixed potential as the power signal transmitted by the power signal line pattern VDD.

[0186] Although the above-mentioned method of coupling the first shielding component 404 with the power signal line pattern VDD can ensure that the first shielding component 404 has a fixed potential, it will increase the parasitic capacitance generated by the power signal line pattern VDD, making the RC load of the power signal line pattern VDD larger, which is not conducive to reducing the vertical crosstalk phenomenon.

[0187] like Figure 3 As shown, in some embodiments, the gate 201g of the first transistor T1 and the gate line pattern GATE are an integrated structure, and the gate 201g of the first transistor T1 is a portion of the integrated structure that can form an overlapping area with the active film layer in a direction perpendicular to the substrate.

[0188] like Figure 3 As shown, in some embodiments, the multiple sub-pixels include multiple rows of sub-pixels, each row of sub-pixels includes a plurality of sub-pixels arranged along the second direction, and the initialization signal line graphics located in the same row of sub-pixels are coupled in sequence to form the initialization signal line corresponding to the row of sub-pixels; the first shielding component 404 extends along the first direction and is coupled to at least one of the initialization signal lines.

[0189] Specifically, the multiple sub-pixels can be divided into multiple rows of sub-pixels and multiple columns of sub-pixels, each row of sub-pixels includes multiple sub-pixels arranged along the second direction, and each column of sub-pixels includes multiple sub-pixels arranged along the first direction, and the first direction intersects with the second direction; the initialization signal line graphics located in the same row of sub-pixels are coupled in sequence to form an initialization signal line corresponding to the row of sub-pixels.

[0190] The above-mentioned setting of the first shielding component 404 extending along the first direction and coupled to at least one of the initialization signal lines not only enables the first shielding component 404 to reduce the influence of the signal change transmitted on the target data line pattern on the performance of the first transistor T1, thereby reducing the influence of the coupling between the gate of the driving transistor (i.e., 203g) and the target data line pattern, and weakening the problem of vertical crosstalk, so that the display substrate can obtain a better display effect when used for display; but also realizes the enhancement of the voltage of the initialization signal line, so that the voltage of the initialization signal transmitted on the initialization signal line is more stable, which is more conducive to the working performance of the sub-pixel driving circuit.

[0191] like Fig. 9 As shown, in some embodiments, the first shielding component 404 is coupled to the two adjacent initialization signal lines.

[0192] Specifically, when the first shielding component 404 is coupled to the initialization signal line, the coupling method of the first shielding component 404 and the initialization signal line, and the specific structure and setting method of the first shielding component 404 are various, for example, Figure 3 As shown, the first shielding component 404 can be arranged to be coupled to the two adjacent initialization signal lines respectively; this arrangement makes the orthographic projection of the first shielding component 404 on the substrate 50 not only located between the orthographic projection of the first transistor T1 on the substrate 50 and the orthographic projection of the target data line pattern on the substrate 50; it also makes the orthographic projection of the first shielding component 404 on the substrate 50 be located between the orthographic projection of the connecting line 401 on the substrate 50 and the orthographic projection of the target data line pattern on the substrate 50; at the same time, it also makes the orthographic projection of the first shielding component 404 on the substrate 50 be located between the orthographic projection of the driving transistor (i.e., the third transistor T3) on the substrate 50 and the orthographic projection of the target data line pattern on the substrate 50.

[0193] The above arrangement effectively reduces the first crosstalk between the target signal line pattern and the first transistor T1, and the second crosstalk between the target signal line pattern and the connecting line 401, thereby reducing the indirect crosstalk to the driving transistor caused by the first crosstalk and the second crosstalk. In addition, the above arrangement also reduces the direct crosstalk between the target signal line pattern and the driving transistor, thereby better ensuring the working performance of the display substrate.

[0194] Please continue reading Figure 3 In some embodiments, the first shielding member 404 and the initialization signal line pattern (such as Figure 3 The VINT1 in the figure is arranged in a different layer, and the orthographic projection of the first shielding component 404 on the substrate 50 has a first overlapping area with the orthographic projection of the initialization signal line pattern on the substrate, and the first shielding component 404 is coupled to the initialization signal line pattern through a first via hole arranged in the first overlapping area.

[0195] Specifically, the first shielding component 404 can be set in the same layer or in a different layer as the initialization signal line pattern. When the first shielding component 404 and the initialization signal line pattern are set in different layers, the orthographic projection of the first shielding component 404 on the substrate 50 can be set, and there is a first overlapping area with the orthographic projection of the initialization signal line pattern on the substrate 50. In this way, by setting a first via in the first overlapping area, coupling between the first shielding component 404 and the initialization signal line can be achieved.

[0196] It should be noted that the above-mentioned "the first shielding component 404 can be set on the same layer as the initialization signal line pattern" includes: the first shielding component 404 and the initialization signal line pattern are located on the same horizontal plane; the first shielding component 404 and the initialization signal line pattern are located on the same film layer; the first shielding component 404 and the initialization signal line pattern are both arranged on the surface of the same insulating layer facing away from the substrate; and the first shielding component 404 and the initialization signal line pattern are formed by a single patterning process, etc.

[0197] The above-mentioned “the first shielding component 404 can be set in a different layer from the initialization signal line pattern” includes: the first shielding component 404 and the initialization signal line pattern are not located in the same film layer; the first shielding component 404 and the initialization signal line pattern cannot be formed by a single patterning process, etc.

[0198] In some embodiments, the first shielding member 404 and the data line pattern (eg Figure 3 DATA1) in the same material settings.

[0199] In some embodiments, the display substrate may include a first interlayer insulating layer, the first shielding member 404 and the data line pattern (eg, Figure 3 DATA1) are all located on the surface of the first interlayer insulating layer facing away from the substrate.

[0200] Specifically, the first shielding component 404 is set in the above manner, so that the first shielding component 404 and the data line pattern can be simultaneously formed on the surface of the first interlayer insulating layer facing away from the substrate through a single composition process, thereby avoiding adding an additional composition process to produce the first shielding component 404, thereby greatly simplifying the production process of the display substrate and saving production costs.

[0201] like Figure 3 As shown, in some embodiments, the sub-pixel driving circuit further includes a second transistor T2 coupled to the gate of the driving transistor, and the second transistor T2 includes:

[0202] A first semiconductor pattern, a second semiconductor pattern, and a third conductor pattern coupled to the first semiconductor pattern and the second semiconductor pattern, respectively, wherein the conductivity of the third conductor pattern is better than the conductivity of the first semiconductor pattern and the conductivity of the second semiconductor pattern;

[0203] A first gate pattern and a second gate pattern coupled to each other, wherein an orthographic projection of the first gate pattern on the substrate 50 partially overlaps with an orthographic projection of the first semiconductor pattern on the substrate 50, and an orthographic projection of the second gate pattern on the substrate 50 partially overlaps with an orthographic projection of the second semiconductor pattern on the substrate 50;

[0204] The orthographic projection of the third conductor pattern on the substrate 50 does not overlap with the orthographic projection of the first gate pattern on the substrate 50 and the orthographic projection of the second gate pattern on the substrate 50;

[0205] The orthographic projection of the third conductor pattern on the substrate 50 is the same as the initialization signal line pattern (such as Figure 3 The positive projection of VINT1) on the substrate 50 at least partially overlaps.

[0206] Specifically, Figure 7 As shown, the second transistor T2 is a dual-gate structure, wherein the first semiconductor pattern and the second semiconductor pattern formed as the channel region of the second transistor T2 (corresponding to Figure 7 The third conductor pattern 102px included therein has better conductivity than the first semiconductor pattern and the second semiconductor pattern due to doping, and the first gate pattern and the second gate pattern included in the second transistor T2 correspond to each other and cover the first semiconductor pattern and the second semiconductor pattern, and can serve as the gate 202g of the second transistor T2 together.

[0207] In the second transistor T2 of the above structure, since the third conductor pattern 102px has good conductivity and is not covered by the gate pattern, it is easy to couple with other conductive patterns nearby, resulting in crosstalk. In the technical solution provided by the above embodiment, the positive projection of the third conductor pattern on the substrate 50 is set to be aligned with the initialization signal line pattern (such as Figure 3The positive projection of VINT1) on the substrate 50 at least partially overlaps, so that the initialization signal line pattern can cover the third conductor pattern 102px. Since the initialization signal line pattern transmits an initialization signal with a fixed potential, the coupling effect between the third conductor pattern 102px and other conductive patterns nearby is better reduced, thereby making the working performance of the display substrate more stable.

[0208] like Figure 4 As shown, in some embodiments, the sub-pixel driving circuit also includes a first extension portion extending from the first semiconductor pattern, and the conductivity of the first extension portion is better than that of the first semiconductor pattern; the first extension portion includes a first part 61, a second part 62 and a third part 63, the first part 61 and the third part 63 both extend along the first direction, the second part 62 extends along the second direction, one end of the second part 62 is coupled to the first part 61, and the other end of the second part 62 is coupled to the third part 63; the end of the third part 63 away from the second part 62 is coupled to the first transistor T1.

[0209] Specifically, the first extension portion and the first semiconductor pattern can be manufactured in one patterning process, and after the first semiconductor pattern is formed, the first extension portion is doped so that the first extension portion has better conductivity than the first semiconductor pattern.

[0210] After adding the first shielding component 404, the first extension portion is set to the above-mentioned structure, so that when the second transistor T2 is coupled to the gate of the first transistor T1 and the driving transistor respectively through the first extension portion, it is more conducive to reducing the impact of the signal change transmitted on the target data line pattern on the performance of the first transistor T1 and the performance of the second transistor T2, thereby reducing the impact of the coupling between the gate of the driving transistor (i.e., 203g) and the target data line pattern, weakening the problem of vertical crosstalk, so that the display substrate can obtain a better display effect when used for display.

[0211] like Figure 3 and Figure 4 As shown, in some embodiments, the first transistor T1 includes:

[0212] a fourth semiconductor pattern, a fifth semiconductor pattern, and a sixth conductor pattern respectively coupled to the fourth semiconductor pattern and the fifth semiconductor pattern, wherein the conductivity of the sixth conductor pattern is better than the conductivity of the fourth semiconductor pattern and the conductivity of the fifth semiconductor pattern;

[0213] A third gate pattern and a fourth gate pattern coupled to each other, wherein the orthographic projection of the third gate pattern on the substrate 50 partially overlaps with the orthographic projection of the fourth semiconductor pattern on the substrate 50, and the orthographic projection of the fourth gate pattern on the substrate 50 partially overlaps with the orthographic projection of the fifth semiconductor pattern on the substrate 50;

[0214] The orthographic projection of the sixth conductor pattern on the substrate 50 does not overlap with the orthographic projection of the third gate pattern on the substrate 50 and the orthographic projection of the fourth gate pattern on the substrate 50 .

[0215] Specifically, Figure 4 As shown, the first transistor is a dual-gate structure, and the fourth semiconductor pattern and the fifth semiconductor pattern formed by the first transistor are formed into a channel region (corresponding to Figure 4 The sixth conductor pattern 101px included therein has better conductivity than the fourth semiconductor pattern and the fifth semiconductor pattern due to doping, and the third gate pattern and the fourth gate pattern included in the first transistor cover the fourth semiconductor pattern and the fifth semiconductor pattern one by one, and can serve together as the gate 201g of the first transistor T1.

[0216] like Fig.10 As shown, in some embodiments, the orthographic projection of the first shielding component 404 on the substrate 50 at least partially overlaps with the orthographic projection of the sixth conductor pattern 101px on the substrate 50 .

[0217] Specifically, in the first transistor T1 of the above structure, since the sixth conductor pattern 101px has good conductivity and is not covered by the gate pattern, it is easy to couple with other conductive patterns nearby, resulting in crosstalk. In the technical solution provided by the above embodiment, by setting the orthographic projection of the first shielding component 404 on the substrate 50 to at least partially overlap with the orthographic projection of the sixth conductor pattern 101px on the substrate 50, the first shielding component 404 can cover the sixth conductor pattern 101px, and since the first shielding component 404 has a fixed potential, the coupling effect between the sixth conductor pattern 101px and other conductive patterns nearby is better reduced, so that the working performance of the display substrate is more stable.

[0218] like Fig.11 , Fig.12 and Fig.13As shown, in some embodiments, the sub-pixel driving circuit also includes: a second shielding component 301 coupled to the first shielding component 404, and the orthographic projection of the second shielding component 301 on the substrate 50 at least partially overlaps with the orthographic projection of the sixth conductor pattern 101px on the substrate 50.

[0219] Specifically, the orthographic projection of the second shielding component 301 on the substrate 50 is at least partially overlapped with the orthographic projection of the sixth conductor pattern 101px on the substrate 50, so that the second shielding component 301 can cover the sixth conductor pattern 101px, and because the second shielding component 301 is coupled to the first shielding component 404, the second shielding component 301 has a fixed potential, thereby better reducing the coupling effect between the sixth conductor pattern 101px and other conductive patterns nearby, so that the working performance of the display substrate is more stable.

[0220] Therefore, in the display substrate provided by the above embodiment, since the first shielding component 404 and the second shielding component 301 both have a fixed potential, the parasitic capacitance formed between the first transistor T1 and the target data line pattern (such as DATA2) is better prevented or reduced, and the vertical crosstalk defect is effectively prevented or reduced.

[0221] Furthermore, the orthographic projection of the second shielding component 301 on the substrate 50 may be arranged to cover the entire orthographic projection of the sixth conductor pattern on the substrate 50 .

[0222] Specifically, the orthographic projection of the second shielding component 301 on the substrate 50 is set to cover the entire orthographic projection of the sixth conductor pattern 101px on the substrate 50, so that the second shielding component 301 can completely cover the sixth conductor pattern 101px, thereby minimizing the coupling effect between the sixth conductor pattern 101px and other conductive patterns nearby, and better improving the working stability of the display substrate.

[0223] In some embodiments, the second shielding component 301 and the first shielding component 404 are arranged in different layers, and the orthographic projection of the second shielding component 301 on the substrate 50 and the orthographic projection of the first shielding component 404 on the substrate 50 have a second overlapping area, and the second shielding component 301 and the first shielding component 404 are coupled through a second via hole arranged in the second overlapping area.

[0224] Specifically, the second shielding component 301 can be arranged on the same layer or on a different layer as the first shielding component 404. When the second shielding component 301 and the first shielding component 404 are arranged on different layers, a second overlapping area can be provided between the orthographic projection of the second shielding component 301 on the substrate 50 and the orthographic projection of the first shielding component 404 on the substrate 50. In this way, by providing a second via hole in the second overlapping area, the second shielding component 301 and the first shielding component 404 can be coupled through the second via hole.

[0225] In some embodiments, the second shielding component 301 and the initialization signal line pattern may be made of the same material.

[0226] In some embodiments, the display substrate may further include a second interlayer insulating layer, and the second shielding member 301 and the initialization signal line pattern (eg, Figure 3 VINT1) in the figure are all located on the surface of the second interlayer insulating layer facing away from the substrate.

[0227] Specifically, the second shielding member 301 and the initialization signal line pattern are made of the same material, and the second shielding member 301 and the initialization signal line pattern (such as Figure 3 VINT1 in the figure is located on the surface of the second interlayer insulating layer facing away from the substrate, so that the second shielding component 301 can be formed simultaneously with the initialization signal line pattern in the same composition process, avoiding the addition of an additional production process specifically for producing the second shielding component 301, thereby greatly simplifying the production process of the display substrate and saving production costs.

[0228] like Figure 3 As shown, in some embodiments, the sub-pixel also includes a power signal line pattern VDD, the power signal line pattern VDD includes a portion extending along the first direction, the sub-pixel driving circuit also includes a storage capacitor Cst, the first electrode Cst1 in the storage capacitor Cst is reused as the gate of the driving transistor, the second electrode Cst2 in the storage capacitor Cst is coupled to the power signal line pattern VDD, and the second electrode Cst2 in the storage capacitor Cst is located on the surface of the second interlayer insulating layer facing away from the substrate.

[0229] Specifically, the storage capacitor Cst included in the sub-pixel driving circuit has a first plate Cst1 and a second plate Cst2, the first plate Cst1 and the second plate Cst2 are arranged opposite to each other, and the first plate Cst1 is coupled to the gate of the driving transistor, and the second plate Cst2 is coupled to the power signal line pattern VDD. When laying out the storage capacitor Cst, the first plate Cst1 can be directly reused as the gate of the driving transistor, which not only ensures that the storage capacitor Cst is coupled to the gate of the driving transistor, but also reduces the space occupied by the sub-pixel driving circuit, which is more conducive to improving the resolution of the display substrate. In addition, the second plate Cst2 in the storage capacitor Cst is arranged to be located on the surface of the second interlayer insulating layer facing away from the substrate, so that the second plate Cst2 in the storage capacitor Cst can be formed simultaneously with the second shielding component 301 and the initialization signal line pattern in the same patterning process, thereby greatly simplifying the manufacturing process of the display substrate and saving production costs.

[0230] like Fig.14 As shown, in some embodiments, the sub-pixel further includes: a reset signal line pattern extending along a second direction intersecting the first direction (such as Figure 3 RST1 in the figure), the sub-pixel driving circuit further includes:

[0231] A first conductive connection portion 405, wherein the orthographic projection of the first conductive connection portion 405 on the substrate 50 covers at least a portion of the orthographic projection of the sixth conductor pattern 101px on the substrate 50;

[0232] The second transistor T2, the first electrode (such as the source S2) of the second transistor T2 is coupled to the initialization signal line pattern (such as VINT1) through the first conductive connection portion 405, the second electrode (such as the drain D2) of the second transistor T2 is coupled to the gate of the driving transistor, and the gate 202g of the second transistor T2 is coupled to the reset signal line pattern (such as RST1).

[0233] Specifically, the first conductive connection portion 405 can be made of a metal material, and can be formed in the same patterning process as the data line pattern.

[0234] The above-mentioned setting of the first conductive connection part 405 on the substrate 50 covers at least a part of the orthographic projection of the sixth conductor pattern 101px on the substrate 50, so that the first conductive connection part 405 can cover the sixth conductor pattern 101px, and because the first conductive connection part 405 is coupled to the initialization signal line pattern, the first conductive connection part 405 has a fixed potential, thereby better reducing the coupling effect between the sixth conductor pattern 101px and other conductive patterns nearby, so that the working performance of the display substrate is more stable.

[0235] like Figure 3 As shown, in some embodiments, the sub-pixel further includes: a gate line pattern GATE, a light emitting control signal line pattern EM, a reset signal line pattern (such as Figure 3 RST1) and the power signal line pattern VDD; the gate line pattern GATE, the light emitting control signal line pattern EM and the reset signal line pattern all extend along the second direction, and the power signal line pattern VDD includes a portion extending along the first direction;

[0236] The sub-pixel driving circuit further includes: a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7;

[0237] The gate of the driving transistor (such as the gate 203g of the third transistor T3) is coupled to the second electrode of the first transistor T1, the first electrode of the driving transistor is coupled to the second electrode of the fifth transistor T5, and the second electrode of the driving transistor is coupled to the first electrode of the first transistor T1;

[0238] The gate 201g of the first transistor T1 is coupled to the gate line pattern GATE;

[0239] The gate 202g of the second transistor T2 is coupled to the reset signal line pattern, the first electrode of the second transistor T2 is coupled to the initialization signal line pattern, and the second electrode of the second transistor T2 is coupled to the gate of the driving transistor;

[0240] The gate electrode 204g of the fourth transistor T4 is coupled to the gate line pattern GATE, and the first electrode of the fourth transistor T4 is coupled to the data line pattern (eg Figure 3 The second electrode of the fourth transistor T4 is coupled to the first electrode of the driving transistor;

[0241] The gate 205g of the fifth transistor T5 is coupled to the light emitting control signal line pattern EM, and the first electrode of the fifth transistor T5 is coupled to the power signal line pattern VDD;

[0242] The gate 206g of the sixth transistor T6 is coupled to the light emitting control signal line pattern EM, the first electrode of the sixth transistor T6 is coupled to the second electrode of the driving transistor, and the second electrode of the sixth transistor T6 is coupled to the light emitting element in the sub-pixel;

[0243] The gate 207g of the seventh transistor T7 is coupled to the reset signal line pattern (such as RST2) included in the next sub-pixel adjacent along the first direction, the first electrode of the seventh transistor T7 is coupled to the initialization signal line pattern (such as VINT2) included in the next sub-pixel, and the second electrode of the seventh transistor T7 is coupled to the light-emitting element in the sub-pixel.

[0244] Specifically, in the above-mentioned display substrate, the multiple sub-pixels included can be distributed in an array, and the multiple sub-pixels can be divided into multiple rows of sub-pixels and multiple columns of sub-pixels, each row of sub-pixels includes multiple sub-pixels arranged along the second direction, and each column of sub-pixels includes multiple sub-pixels arranged along the first direction, and the first direction intersects with the second direction.

[0245] It should be noted that the next adjacent sub-pixel along the first direction is the next adjacent sub-pixel located in the same column as the seventh transistor T7.

[0246] The sub-pixel and the sub-pixel driving circuit included therein are arranged as the above-mentioned structure, which can effectively reduce the layout space occupied by the sub-pixel driving circuit while ensuring the working performance of the sub-pixel driving circuit, and is conducive to improving the resolution of the display substrate.

[0247] It should be noted that the gates of each transistor included in the sub-pixel driving circuit and the functional graphics coupled thereto can form an integrated structure. For example, the gate of the first transistor and the gate of the fourth transistor are both integrated with the corresponding coupled gate line graphics, the gate of the fifth transistor and the gate of the sixth transistor are both integrated with the corresponding coupled light-emitting control signal line graphics, and the gate of the second transistor and the gate of the seventh transistor are both integrated with the corresponding coupled reset signal line graphics.

[0248] In addition, the first transistor T1 is used to perform threshold compensation on the driving transistor (such as the third transistor T3), the second transistor T2 is used to reset the gate of the driving transistor, the fourth transistor T4 is used to write the data signal transmitted by the data line pattern, the fifth transistor T5 is used to write the power signal transmitted by the power signal line pattern to the first electrode of the driving transistor, the sixth transistor T6 is used to control whether the corresponding light-emitting element emits light, and the seventh transistor T7 is used to reset the anode of the light-emitting element.

[0249] In some embodiments, the sub-pixel also includes: a gate line graphic GATE, a light-emitting control signal line graphic EM, a reset signal line graphic RST and a power signal line graphic VDD; the gate line graphic GATE, the light-emitting control signal line graphic EM and the reset signal line graphic RST all extend along the second direction, and the power signal line graphic VDD includes a portion extending along the first direction; the orthographic projection of the first shielding component 404 on the substrate 50 overlaps with the orthographic projection of the gate line graphic GATE on the substrate 50 and the orthographic projection of the light-emitting control signal line graphic EM on the substrate 50, respectively.

[0250] Specifically, the first shielding component 404 is arranged in the above manner so that the first shielding component 404 can isolate the first transistor T1 and the driving transistor from the target data line pattern (such as DATA2), thereby being more conducive to reducing the crosstalk caused by changes in the data signal on the target data line pattern to the first transistor T1 and the driving transistor.

[0251] In some embodiments, the second electrode of the seventh transistor T7 is coupled to the light-emitting element in the sub-pixel in various ways. For example, the positive projection of the anode of the light-emitting element on the substrate overlaps with the positive projection of the second electrode of the seventh transistor T7 on the substrate, and the anode of the light-emitting element can be coupled to the second electrode of the seventh transistor T7 through a via hole provided at the overlap; or, the positive projection of the anode of the light-emitting element on the substrate does not overlap with the positive projection of the second electrode of the seventh transistor T7 on the substrate, and the sub-pixel driving circuit further includes a second conductive connecting portion 406 and a third conductive connecting portion 407, and the positive projection of the anode of the light-emitting element on the substrate overlaps with the positive projection of the first end of the third conductive connecting portion 407 on the substrate. , the anode of the light-emitting element is coupled to the first end of the third conductive connection part 407 through the via hole at the overlap, the second end of the third conductive connection part 407 overlaps with the first end of the second conductive connection part 406, the second end of the third conductive connection part 407 is coupled to the first end of the second conductive connection part 406 through the via hole at the overlap, the orthographic projection of the second electrode of the seventh transistor T7 on the substrate overlaps with the orthographic projection of the second end of the second conductive connection part 406 on the substrate, and the second electrode of the seventh transistor T7 is coupled to the second end of the second conductive connection part 406 through the via hole at the overlap, so that the anode of the light-emitting element can be coupled to the second electrode of the seventh transistor T7 through the second conductive connection part 406 and the third conductive connection part 407.

[0252] When the anode of the light-emitting element is coupled to the second electrode of the seventh transistor T7 through the second conductive connection portion 406 and the third conductive connection portion 407, the second conductive connection portion 406 may include a portion extending along the first direction, the anode of the light-emitting element may be located on the upper side of the light-emitting control signal line pattern in its corresponding sub-pixel, and the second electrode of the seventh transistor T7 may be located on the lower side of the light-emitting control signal line pattern in its corresponding sub-pixel.

[0253] like Fig.15 and Fig.24 As shown, taking the sub-pixels of three colors shown in the figure as an example, the structures of the sub-pixels of the three colors are explained.

[0254] The light-emitting element in the first color sub-pixel includes a first anode 601, a first organic light-emitting material layer and a first cathode which are stacked in sequence in a direction away from the substrate; the orthographic projection of the first anode 601 on the substrate partially overlaps with the orthographic projection of the second electrode of the corresponding seventh transistor T7 on the substrate, and the first anode 601 is coupled to the second electrode of the corresponding seventh transistor T7 through a via hole at the overlapping portion.

[0255] The light-emitting element in the second color sub-pixel includes a second anode 602, a second organic light-emitting material layer and a second cathode which are stacked in sequence in a direction away from the substrate; the positive projection of the second anode 602 on the substrate does not overlap with the positive projection of the second electrode of the corresponding seventh transistor T7 on the substrate, and the sub-pixel driving circuit in the second color sub-pixel also includes a second conductive connection part 406 and a third conductive connection part 407, and the second anode 602 is coupled to the second electrode of the corresponding seventh transistor T7 through the second conductive connection part 406 and the third conductive connection part 407.

[0256] The light-emitting element in the third color sub-pixel includes a third anode 603, a third organic light-emitting material layer and a third cathode which are stacked in sequence in a direction away from the substrate; the orthographic projection of the third anode 603 on the substrate partially overlaps with the orthographic projection of the second electrode of the corresponding seventh transistor T7 on the substrate, and the third anode 603 is coupled to the second electrode of the corresponding seventh transistor T7 through a via hole at the overlapping portion.

[0257] For example, Fig.15 As shown, the anode of the organic light-emitting element of each color sub-pixel includes a main electrode and a connecting electrode, and the shape of the main electrode is a hexagon.

[0258] like Fig.15As shown, the first anode 601 of the first color sub-pixel includes a first main electrode 6011 and a first connection electrode 6012, the first main electrode 6011 and the first connection electrode 6012 can be an integral structure, and the first connection electrode 6012 is connected to the second electrode of the seventh transistor T7 of the first color sub-pixel through a connection hole. The second anode 602 of the second color sub-pixel includes a second main electrode 6021 and a second connection electrode 6022, the second main electrode 6021 and the second connection electrode 6022 can be an integral structure, and the second connection electrode 6022 is connected to the second electrode of the seventh transistor T7 of the second color sub-pixel through a second conductive connection portion 406 and a third conductive connection portion 407. The third anode 603 of the third color sub-pixel includes a third main electrode 6031 and a third connection electrode 6032, the third main electrode 6031 and the third connection electrode 6032 can be an integral structure, and the third connection electrode 6032 is connected to the second electrode of the seventh transistor T7 of the third color sub-pixel through a connection hole.

[0259] For example, the first connection electrode 6012 of the first color sub-pixel is located at the side of the data line pattern of the center of the first main electrode 6011 away from the sub-pixel pixel circuit in the X direction, and is located at the side of the center of the first main electrode 6011 away from the light-emitting control signal line of the sub-pixel pixel circuit in the Y direction. For example, the first connection electrode 6012 of the first color sub-pixel and the first main electrode 6011 are arranged in the Y direction, and the first connection electrode 6012 is located at the lower right corner of the first main electrode 6011. For example, the second connection electrode 6022 of the second color sub-pixel is located at the side of the center of the second main electrode 6021 away from the data line of the sub-pixel pixel circuit in the X direction, and is located at the side of the center of the second main electrode 6021 close to the light-emitting control signal line of the sub-pixel pixel circuit in the Y direction. For example, the second connection electrode 6022 of the second color sub-pixel and the second main electrode 6021 are arranged in the Y direction, and the second connection electrode 6022 is located at the lower right corner of the first main electrode 1231. For example, the third connection electrode 6032 of the third color sub-pixel and the third main electrode 6031 are arranged in the X direction, and the third connection electrode 6032 is located on the right side of the third main electrode 6031, that is, close to the side of the sub-pixel circuit close to the shielding line.

[0260] like Fig.15 As shown, the first main electrode 6011 of the first anode 601 of the first color sub-pixel covers the driving transistor of the first color sub-pixel, the second main electrode 6021 of the second anode 602 of the second color sub-pixel has basically no overlap or partially overlaps with the driving transistor of the second color sub-pixel, and the third main electrode 6031 of the third anode 603 of the third color sub-pixel has no overlap with the driving transistor of the third color sub-pixel.

[0261] like Fig.15 As shown, the first main electrode 6011 of the first color sub-pixel 601 (for example, the blue sub-pixel) overlaps with the gate line pattern and the light-emitting control signal line pattern; the second main electrode 6021 of the second color sub-pixel (for example, the red sub-pixel) overlaps with the gate line pattern and the reset signal line pattern; the third main electrode 6031 of the third color sub-pixel (for example, the green sub-pixel) overlaps with the light-emitting control signal line pattern, the reset signal line pattern of the next row of sub-pixel driving circuits, and the initialization signal line pattern of the next row of sub-pixel driving circuits. For example, the third main electrode 6031 of the third color sub-pixel (for example, the green sub-pixel) overlaps with the pixel driving circuit area of ​​the first color sub-pixel (for example, the blue sub-pixel) adjacent to it in the next row.

[0262] For example, the first main electrode 6011 of the first color sub-pixel 601 overlaps part of the driving transistor of the adjacent third color sub-pixel, and the first main electrode 6011 of the first color sub-pixel 601 overlaps with the data line pattern in its sub-pixel driving circuit, the first shielding component 404, and the data line pattern in the sub-pixel driving circuit of the adjacent second color sub-pixel. The second main electrode 6021 of the second color sub-pixel does not overlap with the data line pattern in its sub-pixel driving circuit, and overlaps with the power signal line pattern in its sub-pixel driving circuit and the power signal line pattern and data line pattern in the sub-pixel driving circuit of the adjacent third color sub-pixel. The third main electrode 6031 of the third color sub-pixel overlaps with the data line pattern and the power signal line pattern in its sub-pixel driving circuit, and overlaps with the power signal line pattern in the sub-pixel driving circuit of the adjacent second color sub-pixel.

[0263] For example, Fig.15 As shown, the first main electrode 6011 of the first color sub-pixel 601 is provided with a first connection electrode 6012 connected thereto on a side close to the next row of reset signal line patterns; the second main electrode 6021 of the second color sub-pixel is provided with a second connection electrode 6022 connected thereto on a side close to the next row of reset signal line patterns; the third main electrode 6031 of the third color sub-pixel is provided with a third connection electrode 6032 connected thereto on a side close to its seventh transistor T7.

[0264] For example, Fig.15As shown, the first connection electrode 6012 of the first color sub-pixel 601 overlaps with the second electrode of the seventh transistor T7 in its sub-pixel driving circuit. The second connection electrode 6022 of the second color sub-pixel does not overlap with the second electrode of the seventh transistor T7 in its sub-pixel driving circuit, while the second electrode of the seventh transistor T7 of the second color sub-pixel overlaps with the third main electrode 6031 of the third color sub-pixel. The third connection electrode 6032 of the third color sub-pixel overlaps with the second electrode of the seventh transistor T7 in its sub-pixel driving circuit.

[0265] like Fig.26 As shown, the embodiment of the present disclosure further provides a display substrate, comprising: a substrate 50 and a plurality of sub-pixels distributed in an array on the substrate 50; the sub-pixels include:

[0266] A data line pattern extending along a first direction (eg, DATA1);

[0267] An initialization signal line pattern (eg, VINT1), wherein the initialization signal line pattern includes a portion extending along a second direction, the second direction intersecting the first direction, and the initialization signal line pattern is used to transmit an initialization signal having a fixed potential;

[0268] A sub-pixel driving circuit, the sub-pixel driving circuit comprising: a driving transistor (such as: a third transistor T3), a first transistor T1 coupled to the gate of the driving transistor, and a first shielding component 404 coupled to the initialization signal line pattern, the first shielding component 404 is used to form a coupling capacitor with the first electrode (i.e., the source S1) of the first transistor T1, the first shielding component 404 is projected on the substrate 50 and the target data line pattern (such as DATA2) is not overlapped on the substrate 50, and the next sub-pixel adjacent to the sub-pixel along the second direction includes the target data line pattern.

[0269] Specifically, the display substrate generally includes a plurality of sub-pixels distributed in an array, and each sub-pixel includes: a data line pattern extending along a first direction (eg Figure 3 DATA1 in ), and an initialization signal line pattern extending at least partially along the second direction (such as Figure 3 VINT1 in the figure); the data line pattern is used to transmit a data signal, and the initialization signal line pattern is used to transmit an initialization signal with a fixed potential; exemplarily, the first direction includes a Y direction, and the second direction includes an X direction.

[0270] The target data line pattern is: a data line pattern included in a next sub-pixel adjacent to the current sub-pixel along the second direction.

[0271] Each sub-pixel also includes a sub-pixel driving circuit and a light-emitting element corresponding to the sub-pixel driving circuit one by one, the light-emitting element includes a stacked anode, an organic light-emitting material layer and a cathode, wherein the anode of the light-emitting element is coupled to the corresponding sub-pixel driving circuit, and the light-emitting element emits light under the drive signal provided by the sub-pixel driving circuit.

[0272] In more detail, Figure 1 , Figure 3 and Figure 4 As shown, taking the sub-pixel driving circuit including the above 7T1C as an example, the gate 203g of the third transistor T3 (i.e., the driving transistor) is coupled to the drain D1 of the first transistor T1 through the connecting line 401, and the drain D3 of the third transistor T3 is coupled to the source S1 of the first transistor T1. Along the X direction, the positive projection of the first channel region 101pg of the first transistor T1 on the substrate 50 is aligned with the target data line pattern (e.g., Figure 3 The minimum distance between the orthographic projections of the first channel region 101pg and the third channel region 103pg of the third transistor T3 on the substrate 50 and the orthographic projections of the target data line pattern on the substrate 50 is smaller than the minimum distance between the orthographic projections of the third channel region 103pg of the third transistor T3 on the substrate 50 and the orthographic projections of the target data line pattern on the substrate 50. It is worth noting that the orthographic projections of the above-mentioned channel regions (such as the first channel region 101pg and the third channel region 103pg) on ​​the substrate 50 and the orthographic projections of the target data line pattern (such as Figure 3 The minimum distance between the orthographic projections of the channel region on the substrate 50 is: the boundary of the orthographic projection of the channel region on the substrate 50 that is closest to the target data line pattern and the target data line pattern (such as Figure 3 DATA2 in (the minimum distance between the orthographic projections on the substrate 50).

[0273] In the sub-pixel driving circuit of the above structure, when the data signal transmitted by the target data line pattern changes, the performance of the first transistor T1 will be affected. Since the first transistor T1 is coupled to the third transistor T3 through the connecting line 401, the working performance of the third transistor T3 will be affected.

[0274] In the embodiment of the present disclosure, a sub-pixel driving circuit is provided with a signal line pattern (such as Figure 3The first shielding component 404 is coupled to the VINT1 in the target data line pattern, so that the first shielding component 404 has the same fixed potential as the initialization signal, and the first shielding component 404 is set to form a coupling capacitor with the first electrode (i.e., the source S1) of the first transistor T1, so that the first shielding component 404 can reduce the influence of the signal change transmitted on the target data line pattern on the performance of the first transistor T1, thereby reducing the influence of the coupling between the gate (i.e., 203g) of the driving transistor and the target data line pattern, weakening the problem of vertical crosstalk, so that the display substrate can obtain a better display effect when used for display.

[0275] In addition, the above-mentioned coupling of the first shielding component 404 with the initialization signal line pattern not only makes the first shielding component 404 have a fixed potential, but also strengthens the voltage of the initialization signal line pattern, so that the voltage of the initialization signal transmitted on the initialization signal line pattern is more stable, which is more conducive to the working performance of the sub-pixel driving circuit.

[0276] It is worth noting that in addition to coupling the first shielding component 404 with the initialization signal line pattern, the first shielding component 404 can also be coupled with the power signal line pattern VDD included in the sub-pixel, so that the first shielding component 404 has the same fixed potential as the power signal transmitted by the power signal line pattern VDD.

[0277] Although the above-mentioned method of coupling the first shielding component 404 with the power signal line pattern VDD can ensure that the first shielding component 404 has a fixed potential, it will increase the parasitic capacitance generated by the power signal line pattern VDD, making the RC load of the power signal line pattern VDD larger, which is not conducive to reducing the vertical crosstalk phenomenon.

[0278] like Figure 3 As shown, in some embodiments, the gate 201g of the first transistor T1 and the gate line pattern GATE are an integrated structure, and the gate 201g of the first transistor T1 is a portion of the integrated structure that can form an overlapping area with the active film layer in a direction perpendicular to the substrate.

[0279] like Figure 3 As shown, in some embodiments, the multiple sub-pixels include multiple rows of sub-pixels, each row of sub-pixels includes a plurality of sub-pixels arranged along the second direction, and the initialization signal line graphics located in the same row of sub-pixels are coupled in sequence to form the initialization signal line corresponding to the row of sub-pixels; the first shielding component 404 extends along the first direction and is coupled to at least one of the initialization signal lines.

[0280] Specifically, the multiple sub-pixels can be divided into multiple rows of sub-pixels and multiple columns of sub-pixels, each row of sub-pixels includes multiple sub-pixels arranged along the second direction, and each column of sub-pixels includes multiple sub-pixels arranged along the first direction, and the first direction intersects with the second direction; the initialization signal line graphics located in the same row of sub-pixels are coupled in sequence to form an initialization signal line corresponding to the row of sub-pixels.

[0281] The above-mentioned setting of the first shielding component 404 extending along the first direction and coupled to at least one of the initialization signal lines not only enables the first shielding component 404 to reduce the influence of the signal change transmitted on the target data line pattern on the performance of the first transistor T1, thereby reducing the influence of the coupling between the gate of the driving transistor (i.e., 203g) and the target data line pattern, and weakening the problem of vertical crosstalk, so that the display substrate can obtain a better display effect when used for display; but also realizes the enhancement of the voltage of the initialization signal line, so that the voltage of the initialization signal transmitted on the initialization signal line is more stable, which is more conducive to the working performance of the sub-pixel driving circuit.

[0282] like Fig. 9 As shown, in some embodiments, the first shielding component 404 is coupled to the two adjacent initialization signal lines.

[0283] Specifically, when the first shielding component 404 is coupled to the initialization signal line, the coupling method of the first shielding component 404 and the initialization signal line, and the specific structure and setting method of the first shielding component 404 are various, for example, Figure 3 As shown, the first shielding component 404 can be arranged to be coupled to the two adjacent initialization signal lines respectively; this arrangement makes the orthographic projection of the first shielding component 404 on the substrate 50 not only located between the orthographic projection of the first transistor T1 on the substrate 50 and the orthographic projection of the target data line pattern on the substrate 50; it also makes the orthographic projection of the first shielding component 404 on the substrate 50 be located between the orthographic projection of the connecting line 401 on the substrate 50 and the orthographic projection of the target data line pattern on the substrate 50; at the same time, it also makes the orthographic projection of the first shielding component 404 on the substrate 50 be located between the orthographic projection of the driving transistor (i.e., the third transistor T3) on the substrate 50 and the orthographic projection of the target data line pattern on the substrate 50.

[0284] The above arrangement effectively reduces the first crosstalk between the target signal line pattern and the first transistor T1, and the second crosstalk between the target signal line pattern and the connecting line 401, thereby reducing the indirect crosstalk to the driving transistor caused by the first crosstalk and the second crosstalk. In addition, the above arrangement also reduces the direct crosstalk between the target signal line pattern and the driving transistor, thereby better ensuring the working performance of the display substrate.

[0285] Please continue reading Figure 3 In some embodiments, the first shielding member 404 and the initialization signal line pattern (such as Figure 3 The VINT1 in the figure is arranged in a different layer, and the orthographic projection of the first shielding component 404 on the substrate 50 has a first overlapping area with the orthographic projection of the initialization signal line pattern on the substrate, and the first shielding component 404 is coupled to the initialization signal line pattern through a first via hole arranged in the first overlapping area.

[0286] Specifically, the first shielding component 404 can be set in the same layer or in a different layer as the initialization signal line pattern. When the first shielding component 404 and the initialization signal line pattern are set in different layers, the orthographic projection of the first shielding component 404 on the substrate 50 can be set, and there is a first overlapping area with the orthographic projection of the initialization signal line pattern on the substrate 50. In this way, by setting a first via in the first overlapping area, coupling between the first shielding component 404 and the initialization signal line can be achieved.

[0287] It should be noted that the above-mentioned "the first shielding component 404 can be set on the same layer as the initialization signal line pattern" includes: the first shielding component 404 and the initialization signal line pattern are located on the same horizontal plane; the first shielding component 404 and the initialization signal line pattern are located on the same film layer; the first shielding component 404 and the initialization signal line pattern are both arranged on the surface of the same insulating layer facing away from the substrate; and the first shielding component 404 and the initialization signal line pattern are formed by a single patterning process, etc.

[0288] The above-mentioned “the first shielding component 404 can be set in a different layer from the initialization signal line pattern” includes: the first shielding component 404 and the initialization signal line pattern are not located in the same film layer; the first shielding component 404 and the initialization signal line pattern cannot be formed by a single patterning process, etc.

[0289] In some embodiments, the first shielding member 404 and the data line pattern (eg Figure 3 DATA1) in the same material settings.

[0290] In some embodiments, the display substrate may include a first interlayer insulating layer, the first shielding member 404 and the data line pattern (eg, Figure 3 DATA1) are all located on the surface of the first interlayer insulating layer facing away from the substrate.

[0291] Specifically, the first shielding component 404 is set in the above manner, so that the first shielding component 404 and the data line pattern can be simultaneously formed on the surface of the first interlayer insulating layer facing away from the substrate through a single composition process, thereby avoiding adding an additional composition process to produce the first shielding component 404, thereby greatly simplifying the production process of the display substrate and saving production costs.

[0292] like Figure 3 As shown, in some embodiments, the sub-pixel driving circuit further includes a second transistor T2 coupled to the gate of the driving transistor, and the second transistor T2 includes:

[0293] A first semiconductor pattern, a second semiconductor pattern, and a third conductor pattern coupled to the first semiconductor pattern and the second semiconductor pattern, respectively, wherein the conductivity of the third conductor pattern is better than the conductivity of the first semiconductor pattern and the conductivity of the second semiconductor pattern;

[0294] A first gate pattern and a second gate pattern coupled to each other, wherein an orthographic projection of the first gate pattern on the substrate 50 partially overlaps with an orthographic projection of the first semiconductor pattern on the substrate 50, and an orthographic projection of the second gate pattern on the substrate 50 partially overlaps with an orthographic projection of the second semiconductor pattern on the substrate 50;

[0295] The orthographic projection of the third conductor pattern on the substrate 50 does not overlap with the orthographic projection of the first gate pattern on the substrate 50 and the orthographic projection of the second gate pattern on the substrate 50;

[0296] The orthographic projection of the third conductor pattern on the substrate 50 is the same as the initialization signal line pattern (such as Figure 3 The positive projection of VINT1) on the substrate 50 at least partially overlaps.

[0297] Specifically, Figure 7 As shown, the second transistor T2 is a dual-gate structure, wherein the first semiconductor pattern and the second semiconductor pattern formed as the channel region of the second transistor T2 (corresponding to Figure 7The third conductor pattern 102px included therein has better conductivity than the first semiconductor pattern and the second semiconductor pattern due to doping, and the first gate pattern and the second gate pattern included in the second transistor T2 correspond to each other and cover the first semiconductor pattern and the second semiconductor pattern, and can serve as the gate 202g of the second transistor T2 together.

[0298] In the second transistor T2 of the above structure, since the third conductor pattern 102px has good conductivity and is not covered by the gate pattern, it is easy to couple with other conductive patterns nearby, resulting in crosstalk. In the technical solution provided by the above embodiment, the positive projection of the third conductor pattern on the substrate 50 is set to be aligned with the initialization signal line pattern (such as Figure 3 The positive projection of VINT1) on the substrate 50 at least partially overlaps, so that the initialization signal line pattern can cover the third conductor pattern 102px. Since the initialization signal line pattern transmits an initialization signal with a fixed potential, the coupling effect between the third conductor pattern 102px and other conductive patterns nearby is better reduced, thereby making the working performance of the display substrate more stable.

[0299] like Figure 4 As shown, in some embodiments, the sub-pixel driving circuit also includes a first extension portion extending from the first semiconductor pattern, and the conductivity of the first extension portion is better than that of the first semiconductor pattern; the first extension portion includes a first part 61, a second part 62 and a third part 63, the first part 61 and the third part 63 both extend along the first direction, the second part 62 extends along the second direction, one end of the second part 62 is coupled to the first part 61, and the other end of the second part 62 is coupled to the third part 63; the end of the third part 63 away from the second part 62 is coupled to the first transistor T1.

[0300] Specifically, the first extension portion and the first semiconductor pattern can be manufactured in one patterning process, and after the first semiconductor pattern is formed, the first extension portion is doped so that the first extension portion has better conductivity than the first semiconductor pattern.

[0301] After adding the first shielding component 404, the first extension portion is set to the above-mentioned structure, so that when the second transistor T2 is coupled to the gate of the first transistor T1 and the driving transistor respectively through the first extension portion, it is more conducive to reducing the impact of the signal change transmitted on the target data line pattern on the performance of the first transistor T1 and the performance of the second transistor T2, thereby reducing the impact of the coupling between the gate of the driving transistor (i.e., 203g) and the target data line pattern, weakening the problem of vertical crosstalk, so that the display substrate can obtain a better display effect when used for display.

[0302] like Figure 3 and Figure 4 As shown, in some embodiments, the first transistor T1 includes:

[0303] a fourth semiconductor pattern, a fifth semiconductor pattern, and a sixth conductor pattern respectively coupled to the fourth semiconductor pattern and the fifth semiconductor pattern, wherein the conductivity of the sixth conductor pattern is better than the conductivity of the fourth semiconductor pattern and the conductivity of the fifth semiconductor pattern;

[0304] A third gate pattern and a fourth gate pattern coupled to each other, wherein the orthographic projection of the third gate pattern on the substrate 50 partially overlaps with the orthographic projection of the fourth semiconductor pattern on the substrate 50, and the orthographic projection of the fourth gate pattern on the substrate 50 partially overlaps with the orthographic projection of the fifth semiconductor pattern on the substrate 50;

[0305] The orthographic projection of the sixth conductor pattern on the substrate 50 does not overlap with the orthographic projection of the third gate pattern on the substrate 50 and the orthographic projection of the fourth gate pattern on the substrate 50 .

[0306] Specifically, Figure 4 As shown, the first transistor is a dual-gate structure, and the fourth semiconductor pattern and the fifth semiconductor pattern formed by the first transistor are formed into a channel region (corresponding to Figure 4 The sixth conductor pattern 101px included therein has better conductivity than the fourth semiconductor pattern and the fifth semiconductor pattern due to doping, and the third gate pattern and the fourth gate pattern included in the first transistor cover the fourth semiconductor pattern and the fifth semiconductor pattern one by one, and can serve together as the gate 201g of the first transistor T1.

[0307] like Fig.10 As shown, in some embodiments, the orthographic projection of the first shielding component 404 on the substrate 50 at least partially overlaps with the orthographic projection of the sixth conductor pattern 101px on the substrate 50 .

[0308] Specifically, in the first transistor T1 of the above structure, since the sixth conductor pattern 101px has good conductivity and is not covered by the gate pattern, it is easy to couple with other conductive patterns nearby, resulting in crosstalk. In the technical solution provided by the above embodiment, by setting the orthographic projection of the first shielding component 404 on the substrate 50 to at least partially overlap with the orthographic projection of the sixth conductor pattern 101px on the substrate 50, the first shielding component 404 can cover the sixth conductor pattern 101px, and since the first shielding component 404 has a fixed potential, the coupling effect between the sixth conductor pattern 101px and other conductive patterns nearby is better reduced, so that the working performance of the display substrate is more stable.

[0309] like Fig.11 , Fig.12 and Fig.13 As shown, in some embodiments, the sub-pixel driving circuit also includes: a second shielding component 301 coupled to the first shielding component 404, and the orthographic projection of the second shielding component 301 on the substrate 50 at least partially overlaps with the orthographic projection of the sixth conductor pattern 101px on the substrate 50.

[0310] Specifically, the orthographic projection of the second shielding component 301 on the substrate 50 is at least partially overlapped with the orthographic projection of the sixth conductor pattern 101px on the substrate 50, so that the second shielding component 301 can cover the sixth conductor pattern 101px, and because the second shielding component 301 is coupled to the first shielding component 404, the second shielding component 301 has a fixed potential, thereby better reducing the coupling effect between the sixth conductor pattern 101px and other conductive patterns nearby, so that the working performance of the display substrate is more stable.

[0311] Therefore, in the display substrate provided by the above embodiment, since the first shielding component 404 and the second shielding component 301 both have a fixed potential, the parasitic capacitance formed between the first transistor T1 and the target data line pattern (such as DATA2) is better prevented or reduced, and the vertical crosstalk defect is effectively prevented or reduced.

[0312] Furthermore, the orthographic projection of the second shielding component 301 on the substrate 50 may be arranged to cover the entire orthographic projection of the sixth conductor pattern on the substrate 50 .

[0313] Specifically, the orthographic projection of the second shielding component 301 on the substrate 50 is set to cover the entire orthographic projection of the sixth conductor pattern 101px on the substrate 50, so that the second shielding component 301 can completely cover the sixth conductor pattern 101px, thereby minimizing the coupling effect between the sixth conductor pattern 101px and other conductive patterns nearby, and better improving the working stability of the display substrate.

[0314] In some embodiments, the second shielding component 301 and the first shielding component 404 are arranged in different layers, and the orthographic projection of the second shielding component 301 on the substrate 50 and the orthographic projection of the first shielding component 404 on the substrate 50 have a second overlapping area, and the second shielding component 301 and the first shielding component 404 are coupled through a second via hole arranged in the second overlapping area.

[0315] Specifically, the second shielding component 301 can be arranged on the same layer or on a different layer as the first shielding component 404. When the second shielding component 301 and the first shielding component 404 are arranged on different layers, a second overlapping area can be provided between the orthographic projection of the second shielding component 301 on the substrate 50 and the orthographic projection of the first shielding component 404 on the substrate 50. In this way, by providing a second via hole in the second overlapping area, the second shielding component 301 and the first shielding component 404 can be coupled through the second via hole.

[0316] In some embodiments, the second shielding component 301 and the initialization signal line pattern may be made of the same material.

[0317] In some embodiments, the display substrate may further include a second interlayer insulating layer, and the second shielding member 301 and the initialization signal line pattern (eg, Figure 3 VINT1) in the figure are all located on the surface of the second interlayer insulating layer facing away from the substrate.

[0318] Specifically, the second shielding member 301 and the initialization signal line pattern are made of the same material, and the second shielding member 301 and the initialization signal line pattern (such as Figure 3 VINT1 in the figure is located on the surface of the second interlayer insulating layer facing away from the substrate, so that the second shielding component 301 can be formed simultaneously with the initialization signal line pattern in the same composition process, avoiding the addition of an additional production process specifically for producing the second shielding component 301, thereby greatly simplifying the production process of the display substrate and saving production costs.

[0319] like Figure 3As shown, in some embodiments, the sub-pixel also includes a power signal line pattern VDD, the power signal line pattern VDD includes a portion extending along the first direction, the sub-pixel driving circuit also includes a storage capacitor Cst, the first electrode Cst1 in the storage capacitor Cst is reused as the gate of the driving transistor, the second electrode Cst2 in the storage capacitor Cst is coupled to the power signal line pattern VDD, and the second electrode Cst2 in the storage capacitor Cst is located on the surface of the second interlayer insulating layer facing away from the substrate.

[0320] Specifically, the storage capacitor Cst included in the sub-pixel driving circuit has a first plate Cst1 and a second plate Cst2, the first plate Cst1 and the second plate Cst2 are arranged opposite to each other, and the first plate Cst1 is coupled to the gate of the driving transistor, and the second plate Cst2 is coupled to the power signal line pattern VDD. When laying out the storage capacitor Cst, the first plate Cst1 can be directly reused as the gate of the driving transistor, which not only ensures that the storage capacitor Cst is coupled to the gate of the driving transistor, but also reduces the space occupied by the sub-pixel driving circuit, which is more conducive to improving the resolution of the display substrate. In addition, the second plate Cst2 in the storage capacitor Cst is arranged to be located on the surface of the second interlayer insulating layer facing away from the substrate, so that the second plate Cst2 in the storage capacitor Cst can be formed simultaneously with the second shielding component 301 and the initialization signal line pattern in the same patterning process, thereby greatly simplifying the manufacturing process of the display substrate and saving production costs.

[0321] like Fig.14 As shown, in some embodiments, the sub-pixel further includes: a reset signal line pattern extending along a second direction intersecting the first direction (such as Figure 3 RST1 in the figure), the sub-pixel driving circuit further includes:

[0322] A first conductive connection portion 405, wherein the orthographic projection of the first conductive connection portion 405 on the substrate 50 covers at least a portion of the orthographic projection of the sixth conductor pattern 101px on the substrate 50;

[0323] The second transistor T2, the first electrode (such as the source S2) of the second transistor T2 is coupled to the initialization signal line pattern (such as VINT1) through the first conductive connection portion 405, the second electrode (such as the drain D2) of the second transistor T2 is coupled to the gate of the driving transistor, and the gate 202g of the second transistor T2 is coupled to the reset signal line pattern (such as RST1).

[0324] Specifically, the first conductive connection portion 405 can be made of a metal material, and can be formed in the same patterning process as the data line pattern.

[0325] The above-mentioned setting of the first conductive connection part 405 on the substrate 50 covers at least a part of the orthographic projection of the sixth conductor pattern 101px on the substrate 50, so that the first conductive connection part 405 can cover the sixth conductor pattern 101px, and because the first conductive connection part 405 is coupled to the initialization signal line pattern, the first conductive connection part 405 has a fixed potential, thereby better reducing the coupling effect between the sixth conductor pattern 101px and other conductive patterns nearby, so that the working performance of the display substrate is more stable.

[0326] like Figure 3 As shown, in some embodiments, the sub-pixel further includes: a gate line pattern GATE, a light emitting control signal line pattern EM, a reset signal line pattern (such as Figure 3 RST1) and the power signal line pattern VDD; the gate line pattern GATE, the light emitting control signal line pattern EM and the reset signal line pattern all extend along the second direction, and the power signal line pattern VDD includes a portion extending along the first direction;

[0327] The sub-pixel driving circuit further includes: a second transistor T2, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6 and a seventh transistor T7;

[0328] The gate of the driving transistor (such as the gate 203g of the third transistor T3) is coupled to the second electrode of the first transistor T1, the first electrode of the driving transistor is coupled to the second electrode of the fifth transistor T5, and the second electrode of the driving transistor is coupled to the first electrode of the first transistor T1;

[0329] The gate 201g of the first transistor T1 is coupled to the gate line pattern GATE;

[0330] The gate 202g of the second transistor T2 is coupled to the reset signal line pattern, the first electrode of the second transistor T2 is coupled to the initialization signal line pattern, and the second electrode of the second transistor T2 is coupled to the gate of the driving transistor;

[0331] The gate electrode 204g of the fourth transistor T4 is coupled to the gate line pattern GATE, and the first electrode of the fourth transistor T4 is coupled to the data line pattern (eg Figure 3 The second electrode of the fourth transistor T4 is coupled to the first electrode of the driving transistor;

[0332] The gate 205g of the fifth transistor T5 is coupled to the light emitting control signal line pattern EM, and the first electrode of the fifth transistor T5 is coupled to the power signal line pattern VDD;

[0333] The gate 206g of the sixth transistor T6 is coupled to the light emitting control signal line pattern EM, the first electrode of the sixth transistor T6 is coupled to the second electrode of the driving transistor, and the second electrode of the sixth transistor T6 is coupled to the light emitting element in the sub-pixel;

[0334] The gate 207g of the seventh transistor T7 is coupled to the reset signal line pattern (such as RST2) included in the next sub-pixel adjacent along the first direction, the first electrode of the seventh transistor T7 is coupled to the initialization signal line pattern (such as VINT2) included in the next sub-pixel, and the second electrode of the seventh transistor T7 is coupled to the light-emitting element in the sub-pixel.

[0335] Specifically, in the above-mentioned display substrate, the multiple sub-pixels included can be distributed in an array, and the multiple sub-pixels can be divided into multiple rows of sub-pixels and multiple columns of sub-pixels, each row of sub-pixels includes multiple sub-pixels arranged along the second direction, and each column of sub-pixels includes multiple sub-pixels arranged along the first direction, and the first direction intersects with the second direction.

[0336] It should be noted that the next adjacent sub-pixel along the first direction is the next adjacent sub-pixel located in the same column as the seventh transistor T7.

[0337] The sub-pixel and the sub-pixel driving circuit included therein are arranged as the above-mentioned structure, which can effectively reduce the layout space occupied by the sub-pixel driving circuit while ensuring the working performance of the sub-pixel driving circuit, and is conducive to improving the resolution of the display substrate.

[0338] It should be noted that the gates of each transistor included in the sub-pixel driving circuit and the functional graphics coupled thereto can form an integrated structure. For example, the gate of the first transistor and the gate of the fourth transistor are both integrated with the corresponding coupled gate line graphics, the gate of the fifth transistor and the gate of the sixth transistor are both integrated with the corresponding coupled light-emitting control signal line graphics, and the gate of the second transistor and the gate of the seventh transistor are both integrated with the corresponding coupled reset signal line graphics.

[0339] In addition, the first transistor T1 is used to perform threshold compensation on the driving transistor (such as the third transistor T3), the second transistor T2 is used to reset the gate of the driving transistor, the fourth transistor T4 is used to write the data signal transmitted by the data line pattern, the fifth transistor T5 is used to write the power signal transmitted by the power signal line pattern to the first electrode of the driving transistor, the sixth transistor T6 is used to control whether the corresponding light-emitting element emits light, and the seventh transistor T7 is used to reset the anode of the light-emitting element.

[0340] In some embodiments, the sub-pixel also includes: a gate line graphic GATE, a light-emitting control signal line graphic EM, a reset signal line graphic RST and a power signal line graphic VDD; the gate line graphic GATE, the light-emitting control signal line graphic EM and the reset signal line graphic RST all extend along the second direction, and the power signal line graphic VDD includes a portion extending along the first direction; the orthographic projection of the first shielding component 404 on the substrate 50 overlaps with the orthographic projection of the gate line graphic GATE on the substrate 50 and the orthographic projection of the light-emitting control signal line graphic EM on the substrate 50, respectively.

[0341] Specifically, the first shielding component 404 is arranged in the above manner so that the first shielding component 404 can isolate the first transistor T1 and the driving transistor from the target data line pattern (such as DATA2), thereby being more conducive to reducing the crosstalk caused by changes in the data signal on the target data line pattern to the first transistor T1 and the driving transistor.

[0342] In some embodiments, the second electrode of the seventh transistor T7 is coupled to the light-emitting element in the sub-pixel in various ways. For example, the positive projection of the anode of the light-emitting element on the substrate overlaps with the positive projection of the second electrode of the seventh transistor T7 on the substrate, and the anode of the light-emitting element can be coupled to the second electrode of the seventh transistor T7 through a via hole provided at the overlap; or, the positive projection of the anode of the light-emitting element on the substrate does not overlap with the positive projection of the second electrode of the seventh transistor T7 on the substrate, and the sub-pixel driving circuit further includes a second conductive connecting portion 406 and a third conductive connecting portion 407, and the positive projection of the anode of the light-emitting element on the substrate overlaps with the positive projection of the first end of the third conductive connecting portion 407 on the substrate. , the anode of the light-emitting element is coupled to the first end of the third conductive connection part 407 through the via hole at the overlap, the second end of the third conductive connection part 407 overlaps with the first end of the second conductive connection part 406, the second end of the third conductive connection part 407 is coupled to the first end of the second conductive connection part 406 through the via hole at the overlap, the orthographic projection of the second electrode of the seventh transistor T7 on the substrate overlaps with the orthographic projection of the second end of the second conductive connection part 406 on the substrate, and the second electrode of the seventh transistor T7 is coupled to the second end of the second conductive connection part 406 through the via hole at the overlap, so that the anode of the light-emitting element can be coupled to the second electrode of the seventh transistor T7 through the second conductive connection part 406 and the third conductive connection part 407.

[0343] When the anode of the light-emitting element is coupled to the second electrode of the seventh transistor T7 through the second conductive connection portion 406 and the third conductive connection portion 407, the second conductive connection portion 406 may include a portion extending along the first direction, the anode of the light-emitting element may be located on the upper side of the light-emitting control signal line pattern in its corresponding sub-pixel, and the second electrode of the seventh transistor T7 may be located on the lower side of the light-emitting control signal line pattern in its corresponding sub-pixel.

[0344] like Fig.15 As shown, taking the sub-pixels of three colors shown in the figure as an example, the structures of the sub-pixels of the three colors are explained.

[0345] The light-emitting element in the first color sub-pixel includes a first anode 601, a first organic light-emitting material layer and a first cathode which are stacked in sequence in a direction away from the substrate; the orthographic projection of the first anode 601 on the substrate partially overlaps with the orthographic projection of the second electrode of the corresponding seventh transistor T7 on the substrate, and the first anode 601 is coupled to the second electrode of the corresponding seventh transistor T7 through a via hole at the overlapping portion.

[0346] The light-emitting element in the second color sub-pixel includes a second anode 602, a second organic light-emitting material layer and a second cathode which are stacked in sequence in a direction away from the substrate; the positive projection of the second anode 602 on the substrate does not overlap with the positive projection of the second electrode of the corresponding seventh transistor T7 on the substrate, and the sub-pixel driving circuit in the second color sub-pixel also includes a second conductive connection part 406 and a third conductive connection part 407, and the second anode 602 is coupled to the second electrode of the corresponding seventh transistor T7 through the second conductive connection part 406 and the third conductive connection part 407.

[0347] The light-emitting element in the third color sub-pixel includes a third anode 603, a third organic light-emitting material layer and a third cathode which are stacked in sequence in a direction away from the substrate; the orthographic projection of the third anode 603 on the substrate partially overlaps with the orthographic projection of the second electrode of the corresponding seventh transistor T7 on the substrate, and the third anode 603 is coupled to the second electrode of the corresponding seventh transistor T7 through a via hole at the overlapping portion.

[0348] For example, Fig.15 As shown, the anode of the organic light-emitting element of each color sub-pixel includes a main electrode and a connecting electrode, and the shape of the main electrode is a hexagon.

[0349] like Fig.15 As shown, the first anode 601 of the first color sub-pixel includes a first main electrode 6011 and a first connection electrode 6012, the first main electrode 6011 and the first connection electrode 6012 can be an integral structure, and the first connection electrode 6012 is connected to the second electrode of the seventh transistor T7 of the first color sub-pixel through a connection hole. The second anode 602 of the second color sub-pixel includes a second main electrode 6021 and a second connection electrode 6022, the second main electrode 6021 and the second connection electrode 6022 can be an integral structure, and the second connection electrode 6022 is connected to the second electrode of the seventh transistor T7 of the second color sub-pixel through a second conductive connection portion 406 and a third conductive connection portion 407. The third anode 603 of the third color sub-pixel includes a third main electrode 6031 and a third connection electrode 6032, the third main electrode 6031 and the third connection electrode 6032 can be an integral structure, and the third connection electrode 6032 is connected to the second electrode of the seventh transistor T7 of the third color sub-pixel through a connection hole.

[0350] For example, the first connection electrode 6012 of the first color sub-pixel is located at the side of the data line pattern of the center of the first main electrode 6011 away from the sub-pixel pixel circuit in the X direction, and is located at the side of the center of the first main electrode 6011 away from the light-emitting control signal line of the sub-pixel pixel circuit in the Y direction. For example, the first connection electrode 6012 of the first color sub-pixel and the first main electrode 6011 are arranged in the Y direction, and the first connection electrode 6012 is located at the lower right corner of the first main electrode 6011. For example, the second connection electrode 6022 of the second color sub-pixel is located at the side of the center of the second main electrode 6021 away from the data line of the sub-pixel pixel circuit in the X direction, and is located at the side of the center of the second main electrode 6021 close to the light-emitting control signal line of the sub-pixel pixel circuit in the Y direction. For example, the second connection electrode 6022 of the second color sub-pixel and the second main electrode 6021 are arranged in the Y direction, and the second connection electrode 6022 is located at the lower right corner of the first main electrode 1231. For example, the third connection electrode 6032 of the third color sub-pixel and the third main electrode 6031 are arranged in the X direction, and the third connection electrode 6032 is located on the right side of the third main electrode 6031, that is, close to the side of the sub-pixel circuit close to the shielding line.

[0351] like Fig.15 As shown, the first main electrode 6011 of the first anode 601 of the first color sub-pixel covers the driving transistor of the first color sub-pixel, the second main electrode 6021 of the second anode 602 of the second color sub-pixel has basically no overlap or partially overlaps with the driving transistor of the second color sub-pixel, and the third main electrode 6031 of the third anode 603 of the third color sub-pixel has no overlap with the driving transistor of the third color sub-pixel.

[0352] like Fig.15 As shown, the first main electrode 6011 of the first color sub-pixel 601 (for example, the blue sub-pixel) overlaps with the gate line pattern and the light-emitting control signal line pattern; the second main electrode 6021 of the second color sub-pixel (for example, the red sub-pixel) overlaps with the gate line pattern and the reset signal line pattern; the third main electrode 6031 of the third color sub-pixel (for example, the green sub-pixel) overlaps with the light-emitting control signal line pattern, the reset signal line pattern of the next row of sub-pixel driving circuits, and the initialization signal line pattern of the next row of sub-pixel driving circuits. For example, the third main electrode 6031 of the third color sub-pixel (for example, the green sub-pixel) overlaps with the pixel driving circuit area of ​​the first color sub-pixel (for example, the blue sub-pixel) adjacent to it in the next row.

[0353] For example, the first main electrode 6011 of the first color sub-pixel 601 overlaps part of the driving transistor of the adjacent third color sub-pixel, and the first main electrode 6011 of the first color sub-pixel 601 overlaps with the data line pattern in its sub-pixel driving circuit, the first shielding component 404, and the data line pattern in the sub-pixel driving circuit of the adjacent second color sub-pixel. The second main electrode 6021 of the second color sub-pixel does not overlap with the data line pattern in its sub-pixel driving circuit, and overlaps with the power signal line pattern in its sub-pixel driving circuit and the power signal line pattern and data line pattern in the sub-pixel driving circuit of the adjacent third color sub-pixel. The third main electrode 6031 of the third color sub-pixel overlaps with the data line pattern and the power signal line pattern in its sub-pixel driving circuit, and overlaps with the power signal line pattern in the sub-pixel driving circuit of the adjacent second color sub-pixel.

[0354] For example, Fig.15 As shown, the first main electrode 6011 of the first color sub-pixel 601 is provided with a first connection electrode 6012 connected thereto on a side close to the next row of reset signal line patterns; the second main electrode 6021 of the second color sub-pixel is provided with a second connection electrode 6022 connected thereto on a side close to the next row of reset signal line patterns; the third main electrode 6031 of the third color sub-pixel is provided with a third connection electrode 6032 connected thereto on a side close to its seventh transistor T7.

[0355] For example, Fig.15 As shown, the first connection electrode 6012 of the first color sub-pixel 601 overlaps with the second electrode of the seventh transistor T7 in its sub-pixel driving circuit. The second connection electrode 6022 of the second color sub-pixel does not overlap with the second electrode of the seventh transistor T7 in its sub-pixel driving circuit, while the second electrode of the seventh transistor T7 of the second color sub-pixel overlaps with the third main electrode 6031 of the third color sub-pixel. The third connection electrode 6032 of the third color sub-pixel overlaps with the second electrode of the seventh transistor T7 in its sub-pixel driving circuit.

[0356] An embodiment of the present disclosure further provides a display device, comprising the display substrate provided by the above embodiment.

[0357] Since the display substrate provided in the above embodiment can reduce the influence of the signal change transmitted on the target data line pattern on the performance of the first transistor T1 by setting the first shielding component 404, thereby reducing the influence of the coupling between the gate of the driving transistor (i.e., 203g) and the target data line pattern, and weakening the problem of vertical crosstalk, the display substrate can obtain a better display effect when used for display. In addition, in the display substrate provided in the above embodiment, the first shielding component 404 is coupled to the initialization signal line pattern, which not only makes the first shielding component 404 have a fixed potential, but also strengthens the voltage of the initialization signal line pattern, so that the voltage of the initialization signal transmitted on the initialization signal line pattern is more stable, which is more conducive to the working performance of the sub-pixel driving circuit.

[0358] Therefore, when the display device provided by the embodiment of the present disclosure includes the above-mentioned display substrate, it also has the above-mentioned beneficial effects, which will not be described in detail here.

[0359] It should be noted that the display device may be any product or component with a display function, such as a television, a monitor, a digital photo frame, a mobile phone, and a tablet computer.

[0360] The present disclosure also provides a method for manufacturing a display substrate, which is used to manufacture the display substrate provided in the above embodiment. The manufacturing method includes:

[0361] A plurality of sub-pixels distributed in an array are manufactured on a substrate 50; the sub-pixels include:

[0362] The data line pattern extending along the first direction (such as Figure 3 DATA1 in );

[0363] Initialize the signal line graphics (such as Figure 3 The initialization signal line pattern includes a portion extending along a second direction, the second direction intersects the first direction, and the initialization signal line pattern is used to transmit an initialization signal having a fixed potential;

[0364] A sub-pixel driving circuit, the sub-pixel driving circuit comprising: a driving transistor (such as Figure 3 T3 in the figure), a first transistor T1 coupled to the gate of the driving transistor, and a first shielding component 404 coupled to the initialization signal line pattern, wherein the positive projection of the first shielding component 404 on the substrate 50 is located between the positive projection of the first transistor T1 on the substrate 50 and the target data line pattern (such as Figure 3 DATA2 in the sub-pixel) between the positive projections on the substrate 50; the next sub-pixel adjacent to the sub-pixel along the second direction includes the target data line pattern.

[0365] When the display substrate is manufactured by the manufacturing method provided by the embodiment of the present disclosure, a signal line pattern (such as Figure 3 The first shielding component 404 is coupled to the VINT1 in the substrate 50, so that the first shielding component 404 has the same fixed potential as the initialization signal, and the positive projection of the first shielding component 404 on the substrate 50 is set, and the positive projection of the first transistor T1 on the substrate 50 is aligned with the target data line pattern (such as Figure 3 DATA2 in the target data line pattern) between the positive projections on the substrate 50, so that the first shielding component 404 can reduce the influence of the signal change transmitted on the target data line pattern on the performance of the first transistor T1, thereby reducing the influence of the coupling between the gate of the driving transistor (i.e., 203g) and the target data line pattern, weakening the problem of vertical crosstalk, so that the display substrate can obtain a better display effect when used for display.

[0366] In addition, when the above-mentioned display substrate is manufactured by the manufacturing method provided by the embodiment of the present disclosure, the first shielding component 404 is coupled to the initialization signal line pattern. In addition to making the first shielding component 404 have a fixed potential, the voltage of the initialization signal line pattern is also enhanced, so that the voltage of the initialization signal transmitted on the initialization signal line pattern is more stable, which is more conducive to the working performance of the sub-pixel driving circuit.

[0367] like Fig.16 As shown, the embodiment of the present disclosure further provides a display substrate, comprising: a substrate 50 and a plurality of sub-pixels distributed in an array on the substrate 50; the sub-pixels include:

[0368] A data line pattern (such as DATA1) extending along a first direction;

[0369] a power signal line pattern VDD, wherein the power signal line pattern VDD includes a portion extending along the first direction;

[0370] A sub-pixel driving circuit, the sub-pixel driving circuit comprising: two switching transistors (such as a fourth transistor T4 and a fifth transistor T5), a driving transistor (such as a third transistor T3) and a storage capacitor Cst; a first electrode Cst1 of the storage capacitor Cst is coupled to a gate of the driving transistor (such as a gate 203g of the third transistor T3), and a second electrode Cst2 of the storage capacitor Cst is coupled to the power signal line pattern VDD; the second electrodes of the two switching transistors (such as a drain electrode D4 of the fourth transistor T4 and a drain electrode D5 of the fifth transistor T5) are both coupled to the first electrode of the driving transistor (such as a source electrode S3 of the third transistor T3), and the orthographic projection of the second electrode of at least one of the two switching transistors on the substrate 50 at least partially overlaps with the orthographic projection of the power signal line pattern VDD on the substrate 50, and at least partially overlaps with the orthographic projection of the second electrode Cst2 of the storage capacitor Cst on the substrate 50.

[0371] Specifically, the above-mentioned display substrate generally includes a plurality of sub-pixels distributed in an array, and each sub-pixel includes: a data line pattern (such as DATA1) extending along a first direction, and a power signal line pattern VDD extending at least partially along the first direction; illustratively, the first direction includes the Y direction, and the second direction includes the X direction.

[0372] It is worth noting that the specific structure of the power signal line pattern VDD is varied. Exemplarily, the power signal line pattern VDD is a grid structure, and the grid structure of the power signal line pattern VDD includes a portion extending along the first direction.

[0373] Each sub-pixel also includes a sub-pixel driving circuit and a light-emitting element corresponding to the sub-pixel driving circuit one by one, the light-emitting element includes a stacked anode, an organic light-emitting material layer and a cathode, wherein the anode of the light-emitting element is coupled to the corresponding sub-pixel driving circuit, and the light-emitting element emits light under the drive signal provided by the sub-pixel driving circuit.

[0374] In more detail, Fig.16As shown, taking the sub-pixel driving circuit including the above-mentioned 7T1C as an example, the gate 203g of the third transistor T3 (i.e., the driving transistor) is reused as the first plate Cst1 of the storage capacitor Cst, and the second plate Cst2 of the storage capacitor Cst is located on the side of the first plate Cst1 facing away from the substrate, and the orthographic projection of the first plate Cst1 on the substrate at least partially overlaps with the orthographic projection of the second plate Cst2 on the substrate, and the orthographic projection of the second plate Cst2 on the substrate at least partially overlaps with the orthographic projection of the second electrode of at least one of the fourth transistor T4 and the fifth transistor T5 on the substrate 50, and with the orthographic projection of the power signal line pattern VDD on the substrate 50.

[0375] According to the specific structure of the display substrate described above, in the display substrate provided by the embodiment of the present disclosure, the second plate Cst2 of the storage capacitor Cst is coupled to the power signal line pattern VDD, so that the second plate Cst2 of the storage capacitor Cst has the same fixed potential as the power signal transmitted on the power signal line pattern VDD; at the same time, the second electrodes of the two switching transistors are coupled to the first electrode of the driving transistor, and the orthographic projection of the second electrode of at least one of the two switching transistors on the substrate 50 at least partially overlaps with the orthographic projection of the power signal line pattern VDD on the substrate 50, and at least partially overlaps with the orthographic projection of the second plate Cst2 of the storage capacitor Cst on the substrate 50, so that the second plate Cst2 of the storage capacitor Cst and the power signal line pattern VDD can both shield the second electrode of at least one of the two switching transistors, thereby reducing the crosstalk phenomenon caused by the signal on other conductive patterns (such as signal line patterns) located around at least one of the two switching transistors to the second electrode of at least one of the two switching transistors, thereby reducing the crosstalk phenomenon caused to the first electrode of the driving transistor.

[0376] like Fig.16 As shown, in some embodiments, the second electrodes of the two switching transistors (such as the fourth transistor T4 and the fifth transistor T5) and the first electrode of the driving transistor (such as the third transistor T3) are an integrated structure, and the integrated structure includes a first conductive portion 108 extending along the first direction, and the orthographic projection of the first conductive portion 108 on the substrate, the orthographic projection of the power signal line pattern VDD on the substrate, and the orthographic projection of the second electrode plate Cst2 of the storage capacitor Cst on the substrate 50 have a first overlapping area, and the first overlapping area does not overlap with the orthographic projection of the data line pattern (such as DATA1) on the substrate 50.

[0377] Specifically, the second electrodes of the two switch transistors and the first electrode of the driving transistor are formed into an integrated structure, so that the second electrodes of the two switch transistors and the first electrode of the driving transistor can be formed through a single patterning process.

[0378] In the display substrate provided in the above embodiment, the integrated structure is provided to include a first conductive portion 108 extending along the first direction, the orthographic projection of the data line pattern on the substrate is located on a side of the orthographic projection of the first conductive portion 108 on the substrate away from the orthographic projection of the driving transistor on the substrate, and the orthographic projection of the first conductive portion 108 on the substrate, the orthographic projection of the power signal line pattern VDD on the substrate, and the orthographic projection of the second electrode plate Cst2 of the storage capacitor Cst on the substrate 50 have a first overlapping area, so that the second electrode plate Cst2 of the storage capacitor Cst and the power signal line pattern VDD can both shield the first conductive portion 108, thereby reducing the signal transmitted on the data line pattern, generating crosstalk to the first conductive portion 108, and thereby reducing the crosstalk phenomenon generated to the first electrode of the driving transistor.

[0379] like Fig.16 As shown, in some embodiments, the orthographic projection of the first electrode of the driving transistor on the substrate 50 may be arranged to be located inside the orthographic projection of the second electrode plate Cst2 of the storage capacitor Cst on the substrate.

[0380] The above configuration enables the second electrode Cst2 of the storage capacitor Cst to completely cover the first electrode of the driving transistor, thereby more effectively reducing the crosstalk phenomenon caused by the signal transmitted on the data line pattern to the first electrode of the driving transistor.

[0381] like Fig.16 and Fig.17 As shown, in some embodiments, the sub-pixel further includes: a gate line pattern GATE and a light emitting control signal line pattern EM both extending along a second direction, and the second direction intersects the first direction;

[0382] The sub-pixel driving circuit further includes: a first transistor T1 and a sixth transistor T6; the two switch transistors include a fourth transistor T4 and a fifth transistor T5;

[0383] The gate 204g of the fourth transistor T4 is coupled to the gate line pattern GATE, the first electrode of the fourth transistor T4 is coupled to the data line pattern (such as DATA1), the second electrode of the fourth transistor T4 is coupled to the second electrode of the fifth transistor T5, the gate 205g of the fifth transistor T5 is coupled to the light emitting control signal line pattern EM, and the first electrode of the fifth transistor T5 is coupled to the power signal line pattern VDD;

[0384] The gate 201g of the first transistor T1 is coupled to the gate line pattern GATE, the second electrode of the first transistor T1 is coupled to the gate of the driving transistor, the first electrode of the first transistor T1, the first electrode of the sixth transistor T6 and the second electrode of the driving transistor form an integrated structure, the integrated structure includes a second conductive portion 109 extending along the first direction, the gate 206g of the sixth transistor T6 is coupled to the light emitting control signal line pattern EM, and the second electrode of the sixth transistor T6 is coupled to the light emitting element in the sub-pixel;

[0385] The channel region of the driving transistor (such as Fig.18 103pg) in the orthographic projection on the substrate is located between the orthographic projection of the first conductive portion 108 on the substrate 50 and the orthographic projection of the second conductive portion 109 on the substrate 50; and along the second direction, the minimum distance between the orthographic projection of the channel region of the driving transistor on the substrate and the orthographic projection of the first conductive portion 108 on the substrate is smaller than the minimum distance between the orthographic projection of the channel region on the substrate 50 and the orthographic projection of the second conductive portion 109 on the substrate.

[0386] Specifically, in the above-mentioned display substrate, the plurality of sub-pixels included may be distributed in an array, and the plurality of sub-pixels may be divided into a plurality of rows of sub-pixels and a plurality of columns of sub-pixels, each row of sub-pixels includes a plurality of sub-pixels arranged along a second direction, and each column of sub-pixels includes a plurality of sub-pixels arranged along a first direction, and the first direction intersects with the second direction. The sub-pixel driving circuit included in each column of sub-pixels is located between the data line pattern included in the column of sub-pixels and the data line pattern included in the next column of sub-pixels adjacent to the column of sub-pixels.

[0387] It should be noted that the minimum distance between the orthographic projection of the channel region of the driving transistor on the substrate and the orthographic projection of the first conductive portion 108 on the substrate along the second direction refers to: along the second direction, the distance between the boundary of the orthographic projection of the channel region of the driving transistor on the substrate that is closest to the orthographic projection of the first conductive portion 108 on the substrate and the orthographic projection of the first conductive portion 108 on the substrate; the minimum distance between the orthographic projection of the channel region on the substrate 50 and the orthographic projection of the second conductive portion 109 on the substrate along the second direction refers to: along the second direction, the distance between the boundary of the orthographic projection of the channel region of the driving transistor on the substrate that is closest to the orthographic projection of the second conductive portion 109 on the substrate and the orthographic projection of the second conductive portion 109 on the substrate.

[0388] In more detail, the sub-pixel driving circuit included in each sub-pixel is located between two adjacent data line patterns (such as DATA1 and DATA2). Since the data transmitted on the two data line patterns will change, and when the data changes, it is easy to generate crosstalk to the gate of the driving transistor in the sub-pixel driving circuit. Fig.25 As shown, the working stability of the driving transistor is affected.

[0389] In the technical solution provided by the above embodiment, the fourth transistor T4, the fifth transistor T5, the first transistor T1 and the sixth transistor T6 are all arranged in the peripheral area of ​​the driving transistor, and one of the two data line patterns (such as DATA1) is arranged to be located on the side of the fourth transistor T4 and the fifth transistor T5 away from the driving transistor, and the other of the two data line patterns (such as DATA2) is arranged to be located on the side of the first transistor T1 and the sixth transistor T6 away from the driving transistor; at the same time, by setting the channel region of the driving transistor (such as Fig.18 103pg) in the orthographic projection on the substrate is located between the orthographic projection of the first conductive portion 108 on the substrate 50 and the orthographic projection of the second conductive portion 109 on the substrate 50, and the minimum distance between the orthographic projection of the channel region of the driving transistor on the substrate and the orthographic projection of the first conductive portion 108 on the substrate is smaller than the minimum distance between the orthographic projection of the channel region on the substrate and the orthographic projection of the second conductive portion 109 on the substrate; the channel region of the driving transistor can maximize the distance between the channel region of the driving transistor and DATA2 while ensuring that the appropriate distance with DATA1 is met, thereby better reducing the crosstalk caused by DATA2 to the driving transistor.

[0390] Moreover, since the portion of the channel region of the driving transistor close to DATA1 can be covered by the power signal line pattern VDD, the crosstalk caused by DATA1 to the channel region of the driving transistor can be effectively reduced. Therefore, in the technical solution provided in the above embodiment, even if the channel region of the driving transistor is close to DATA, the crosstalk effect is small.

[0391] In addition, since the second plate Cst2 of the storage capacitor Cst has the same fixed potential as the power signal transmitted on the power signal line pattern VDD, and the orthographic projection of the first conductive portion 108 on the substrate, the orthographic projection of the power signal line pattern VDD on the substrate, and the orthographic projection of the second plate Cst2 of the storage capacitor Cst on the substrate 50 have a first overlapping area, the second plate Cst2 of the storage capacitor Cst and the power signal line pattern VDD can both shield the first conductive portion 108, thereby reducing the signal transmitted on DATA1, causing crosstalk to the first conductive portion 108, and thereby reducing the crosstalk phenomenon caused to the first pole and channel region of the driving transistor.

[0392] like Fig.16 As shown, in some embodiments, the sub-pixel further includes: a gate line pattern GATE and a light emitting control signal line pattern EM both extending along a second direction, and the second direction intersects the first direction;

[0393] The sub-pixel driving circuit further includes: a first transistor T1 and a sixth transistor T6; the two switch transistors include a fourth transistor T4 and a fifth transistor T5;

[0394] The gate 204g of the fourth transistor T4 is coupled to the gate line pattern GATE, the first electrode of the fourth transistor T4 is coupled to the data line pattern (such as DATA1), the second electrode of the fourth transistor T4 is coupled to the second electrode of the fifth transistor T5, the gate 205g of the fifth transistor T5 is coupled to the light emitting control signal line pattern EM, and the first electrode of the fifth transistor T5 is coupled to the power signal line pattern VDD;

[0395] The gate 201g of the first transistor T1 is coupled to the gate line pattern GATE, the second electrode of the first transistor T1 is coupled to the gate of the driving transistor, the first electrode of the first transistor T1, the first electrode of the sixth transistor T6 and the second electrode of the driving transistor form an integrated structure, the integrated structure includes a second conductive portion 109 extending along the first direction, the gate 206g of the sixth transistor T6 is coupled to the light emitting control signal line pattern EM, and the second electrode of the sixth transistor T6 is coupled to the light emitting element in the sub-pixel;

[0396] The channel region of the driving transistor (such as Fig.18 103pg) is located between the orthographic projection of the first conductive portion 108 on the substrate and the orthographic projection of the second conductive portion 109 on the substrate; the first pole and the second pole of the driving transistor both include a first part extending along the second direction, and the length of the first part of the first pole along the second direction is different from the length of the first part of the second pole extending along the second direction.

[0397] Specifically, the first electrode and the second electrode of the driving transistor are both provided to include a first portion extending along the second direction, and the length of the first portion of the first electrode along the second direction is different from the length of the first portion of the second electrode along the second direction, specifically including the following two situations:

[0398] In the first case, the length H1 of the first portion of the first electrode along the second direction is smaller than the length H2 of the first portion of the second electrode extending along the second direction, so that the channel region (eg Fig.18 103pg) is close to the data line pattern (such as DATA1) included in the sub-pixel where it is located, and away from the data line pattern (such as DATA2) included in the next sub-pixel adjacent to the sub-pixel where it is located along the second direction, so that the channel region of the driving transistor can maximize the distance between the channel region of the driving transistor and DATA2 while ensuring that the channel region of the driving transistor meets the appropriate distance with DATA1, thereby better reducing the crosstalk generated by the DATA2 to the driving transistor. At the same time, since the second electrode Cst2 of the storage capacitor Cst and the power signal line pattern VDD can shield the first conductive part 108, the signal transmitted on DATA1 is reduced, and the crosstalk generated to the first conductive part 108 is reduced, thereby reducing the crosstalk phenomenon generated to the first electrode and channel region of the driving transistor.

[0399] In the second case, the length of the first portion of the first electrode along the second direction is greater than the length of the first portion of the second electrode extending along the second direction, so that the channel region of the driving transistor (such as Fig.18103pg) is far away from the data line pattern (such as DATA1) included in the sub-pixel where it is located, and close to the data line pattern (such as DATA2) included in the next sub-pixel adjacent to the sub-pixel where it is located along the second direction, so that the channel region of the driving transistor can maximize the distance between the channel region of the driving transistor and DATA1 while ensuring that the channel region of the driving transistor meets the appropriate distance with DATA2, thereby better reducing the crosstalk generated by the DATA1 to the driving transistor. Moreover, when the display substrate includes a first shielding component, and the first shielding component can completely block DATA2 from the second conductive portion 109, it can reduce the signal transmitted on DATA2, and the crosstalk generated to the second conductive portion 109, thereby reducing the crosstalk phenomenon generated to the second pole and channel region of the driving transistor.

[0400] like Fig.16 As shown, in some embodiments, the sub-pixel further includes an initialization signal line pattern (such as VINT1), the initialization signal line pattern includes a portion extending along a second direction, the second direction intersects the first direction, and the initialization signal line pattern is used to transmit an initialization signal with a fixed potential;

[0401] The sub-pixel driving circuit further includes a second transistor T2 coupled to the gate of the driving transistor, wherein the second transistor T2 includes:

[0402] A first semiconductor pattern, a second semiconductor pattern, and a third conductor pattern coupled to the first semiconductor pattern and the second semiconductor pattern, respectively, wherein the conductivity of the third conductor pattern is better than the conductivity of the first semiconductor pattern and the conductivity of the second semiconductor pattern;

[0403] A first gate pattern and a second gate pattern coupled to each other, wherein an orthographic projection of the first gate pattern on the substrate at least partially overlaps with an orthographic projection of the first semiconductor pattern on the substrate, and an orthographic projection of the second gate pattern on the substrate at least partially overlaps with an orthographic projection of the second semiconductor pattern on the substrate;

[0404] The orthographic projection of the third conductor pattern on the substrate does not overlap with the orthographic projection of the first gate pattern on the substrate, and the orthographic projection of the second gate pattern on the substrate;

[0405] The orthographic projection of the third conductor pattern on the substrate at least partially overlaps with the orthographic projection of the initialization signal line pattern on the substrate.

[0406] Specifically, Fig.16As shown, the second transistor T2 is a dual-gate structure, wherein the first semiconductor pattern and the second semiconductor pattern formed as the channel region of the second transistor T2 (corresponding to Fig.18 The third conductor pattern 102px included therein has better conductivity than the first semiconductor pattern and the second semiconductor pattern due to doping, and the first gate pattern and the second gate pattern included in the second transistor T2 correspond to each other and cover the first semiconductor pattern and the second semiconductor pattern, and can serve as the gate 202g of the second transistor T2 together.

[0407] In the second transistor T2 of the above structure, since the third conductor pattern 102px has good conductivity and is not covered by the gate pattern, it is easy to couple with other conductive patterns nearby, resulting in crosstalk. In the technical solution provided by the above embodiment, by setting the positive projection of the third conductor pattern on the substrate 50 to at least partially overlap with the positive projection of the initialization signal line pattern on the substrate 50, the initialization signal line pattern can cover the third conductor pattern 102px. Since the initialization signal line pattern transmits an initialization signal with a fixed potential, the coupling effect between the third conductor pattern 102px and other conductive patterns nearby is better reduced, thereby making the working performance of the display substrate more stable.

[0408] like Fig.16 and Fig.18 As shown, in some embodiments, the sub-pixel driving circuit also includes a first extension portion extending from the first semiconductor pattern, and the conductivity of the first extension portion is better than that of the first semiconductor pattern; the first extension portion includes a first part 61, a second part 62 and a third part 63, the first part 61 and the third part 63 both extend along the first direction, the second part 62 extends along the second direction, one end of the second part 62 is coupled to the first part 61, and the other end of the second part 62 is coupled to the third part 63; the end of the third part 63 away from the second part 62 is coupled to the first transistor T1.

[0409] Specifically, the first extension portion and the first semiconductor pattern can be manufactured in one patterning process, and after the first semiconductor pattern is formed, the first extension portion is doped so that the first extension portion has better conductivity than the first semiconductor pattern.

[0410] After adding the first shielding component 404, the first extension portion is set to the above-mentioned structure, so that when the second transistor T2 is coupled to the gate of the first transistor T1 and the driving transistor respectively through the first extension portion, it is more conducive to reducing the impact of the signal change transmitted on the target data line pattern on the performance of the first transistor T1 and the performance of the second transistor T2, thereby reducing the impact of the coupling between the gate of the driving transistor (i.e., 203g) and the target data line pattern, weakening the problem of vertical crosstalk, so that the display substrate can obtain a better display effect when used for display.

[0411] In some embodiments, the first transistor comprises:

[0412] a fourth semiconductor pattern, a fifth semiconductor pattern, and a sixth conductor pattern respectively coupled to the fourth semiconductor pattern and the fifth semiconductor pattern, wherein the conductivity of the sixth conductor pattern is better than the conductivity of the fourth semiconductor pattern and the conductivity of the fifth semiconductor pattern;

[0413] A third gate pattern and a fourth gate pattern coupled to each other, wherein the orthographic projection of the third gate pattern on the substrate partially overlaps with the orthographic projection of the fourth semiconductor pattern on the substrate, and the orthographic projection of the fourth gate pattern on the substrate partially overlaps with the orthographic projection of the fifth semiconductor pattern on the substrate;

[0414] The orthographic projection of the sixth conductor pattern on the substrate does not overlap with the orthographic projection of the third gate pattern on the substrate, and the orthographic projection of the fourth gate pattern on the substrate.

[0415] Specifically, Fig.16 As shown, the first transistor is a dual-gate structure, and the fourth semiconductor pattern and the fifth semiconductor pattern formed by the first transistor are formed into a channel region (corresponding to Fig.18 The sixth conductor pattern 101px included therein has better conductivity than the fourth semiconductor pattern and the fifth semiconductor pattern due to doping, and the third gate pattern and the fourth gate pattern included in the first transistor cover the fourth semiconductor pattern and the fifth semiconductor pattern one by one, and can serve together as the gate 201g of the first transistor T1.

[0416] like Fig.19 As shown, in some embodiments, the sub-pixel further includes an initialization signal line pattern (such as VINT1), the initialization signal line pattern includes a portion extending along a second direction, the second direction intersects the first direction, and the initialization signal line pattern is used to transmit an initialization signal with a fixed potential;

[0417] The sub-pixel driving circuit further includes: a first shielding component 404 coupled to the initialization signal line pattern, wherein an orthographic projection of the first shielding component 404 on the substrate 50 at least partially overlaps with an orthographic projection of the sixth conductor pattern 101px on the substrate 50 .

[0418] In the technical solution provided in the above embodiment, the orthographic projection of the first shielding component 404 on the substrate 50 is set to at least partially overlap with the orthographic projection of the sixth conductor pattern 101px on the substrate 50, so that the first shielding component 404 can cover the sixth conductor pattern 101px, and because the first shielding component 404 has a fixed potential, the coupling effect between the sixth conductor pattern 101px and other conductive patterns nearby is better reduced, so that the working performance of the display substrate is more stable.

[0419] like Fig. 20 As shown, in some embodiments, the sub-pixel further includes an initialization signal line pattern (such as VINT1), the initialization signal line pattern includes a portion extending along a second direction, the second direction intersects the first direction, and the initialization signal line pattern is used to transmit an initialization signal with a fixed potential;

[0420] The sub-pixel driving circuit also includes: a first shielding component 404 coupled to the initialization signal line pattern, and a second shielding component 301 coupled to the first shielding component 404, wherein the orthographic projection of the second shielding component 301 on the substrate at least partially overlaps with the orthographic projection of the sixth conductor pattern on the substrate.

[0421] Specifically, the orthographic projection of the second shielding component 301 on the substrate 50 is at least partially overlapped with the orthographic projection of the sixth conductor pattern 101px on the substrate 50, so that the second shielding component 301 can cover the sixth conductor pattern 101px, and because the second shielding component 301 is coupled to the first shielding component 404, the second shielding component 301 has a fixed potential, thereby better reducing the coupling effect between the sixth conductor pattern 101px and other conductive patterns nearby, so that the working performance of the display substrate is more stable.

[0422] Therefore, in the display substrate provided by the above embodiment, since the first shielding component 404 and the second shielding component 301 both have a fixed potential, the parasitic capacitance formed between the first transistor T1 and the target data line pattern (such as DATA2) is better prevented or reduced, and the vertical crosstalk defect is effectively prevented or reduced.

[0423] like Fig.21 and Fig. 22As shown, in some embodiments, the multiple sub-pixels include multiple rows of sub-pixels, each row of sub-pixels includes a plurality of sub-pixels arranged along the second direction, and the initialization signal line graphics located in the same row of sub-pixels are coupled in sequence to form an initialization signal line corresponding to the row of sub-pixels; the first shielding component 404 extends along the first direction, and the first shielding component 404 is coupled to the two adjacent initialization signal lines.

[0424] In some embodiments, the shape of the power signal line pattern can be laid out according to actual needs. For example, along the second direction, the width of the power signal line pattern near the channel region of the driving transistor is smaller than its width near the channel region away from the driving transistor, so that the influence of the power signal line pattern on the gate of the driving transistor can be reduced near the channel region of the driving transistor.

[0425] In some embodiments, Fig.23 As shown, a compensation pattern 408 can be provided in the display substrate, and the compensation pattern 408 can be connected in parallel with the power signal line pattern to improve the transmission performance of the power signal line pattern. It is worth noting that the compensation pattern 408 can be provided in the same layer and material as the third conductive connection portion, so that the compensation pattern 408 can be formed in the same patterning process as the third conductive connection portion.

[0426] In some embodiments, in a sub-pixel, the orthographic projection of the power signal line pattern VDD on the substrate completely covers the orthographic projection of the first conductive portion 108 on the substrate.

[0427] In some embodiments, in a sub-pixel, the orthographic projection of the power signal line pattern VDD on the substrate covers the orthographic projections of the first semiconductor pattern, the second semiconductor pattern and the third conductor pattern of the second transistor T2 on the substrate, and also covers at least part of the orthographic projection of the first electrode of the second transistor T2 on the substrate, and at least part of the orthographic projection of the second electrode of the second transistor T2 on the substrate.

[0428] In some embodiments, the first shielding component 404 is an extension structure extending from the initialization signal line pattern.

[0429] Specifically, the first shielding component 404 is configured as an extended structure extending from the initialization signal line pattern, so that the first shielding component 404 and the initialization signal line pattern can be formed in the same patterning process, thereby better simplifying the manufacturing process of the display substrate.

[0430] like Fig. 20As shown, in some embodiments, the first shielding component 404 and the initialization signal line pattern are arranged in different layers, and the orthographic projection of the first shielding component 404 on the substrate 50 and the orthographic projection of the initialization signal line pattern on the substrate 50 have a first overlapping area, and the first shielding component is coupled to the initialization signal line pattern through a first via hole arranged in the first overlapping area;

[0431] The second shielding component 301 and the first shielding component 404 are arranged in different layers, and the orthographic projection of the second shielding component 301 on the substrate 50 and the orthographic projection of the first shielding component 404 on the substrate 50 have a second overlapping area, and the second shielding component 301 and the first shielding component 404 are coupled through a second via hole arranged in the second overlapping area.

[0432] Specifically, the first shielding component 404 can be arranged in the same layer or in a different layer as the initialization signal line pattern. When the first shielding component 404 and the initialization signal line pattern are arranged in different layers, the orthographic projection of the first shielding component 404 on the substrate 50 can be arranged, and there is a first overlapping area with the orthographic projection of the initialization signal line pattern on the substrate 50. In this way, by setting a first via in the first overlapping area, the coupling between the first shielding component 404 and the initialization signal line can be achieved. Similarly, the second shielding component 301 can be arranged in the same layer or in a different layer as the first shielding component 404. When the second shielding component 301 and the first shielding component 404 are arranged in different layers, it can be arranged that there is a second overlapping area with the orthographic projection of the second shielding component 301 on the substrate 50 and the orthographic projection of the first shielding component 404 on the substrate 50. In this way, by setting a second via in the second overlapping area, the second shielding component 301 and the first shielding component 404 can be coupled through the second via.

[0433] In some embodiments, the first shielding component 404 and the data line pattern are made of the same material.

[0434] In some embodiments, the display substrate includes a first interlayer insulating layer, and the first shielding component 404 and the data line pattern are both located on a surface of the first interlayer insulating layer facing away from the base.

[0435] Specifically, the first shielding component 404 is set in the above manner, so that the first shielding component 404 and the data line pattern can be simultaneously formed on the surface of the first interlayer insulating layer facing away from the substrate through a single composition process, thereby avoiding adding an additional composition process to produce the first shielding component 404, thereby greatly simplifying the production process of the display substrate and saving production costs.

[0436] In some embodiments, the second shielding component 301 and the initialization signal line pattern are made of the same material.

[0437] In some embodiments, the display substrate further includes a second interlayer insulating layer, and the second shielding component 301 and the initialization signal line pattern are both located on a surface of the second interlayer insulating layer facing away from the base.

[0438] Specifically, the second shielding member 301 and the initialization signal line pattern are made of the same material, and the second shielding member 301 and the initialization signal line pattern (such as Figure 3 VINT1 in the figure is located on the surface of the second interlayer insulating layer facing away from the substrate, so that the second shielding component 301 can be formed simultaneously with the initialization signal line pattern in the same composition process, avoiding the addition of an additional production process specifically for producing the second shielding component 301, thereby greatly simplifying the production process of the display substrate and saving production costs.

[0439] In some embodiments, the first plate Cst1 of the storage capacitor Cst is reused as the gate of the driving transistor, the second plate Cst2 of the storage capacitor Cst is made of the same material as the second shielding component 301, and the second plate Cst2 of the storage capacitor Cst is located on the surface of the second interlayer insulating layer facing away from the substrate 50.

[0440] Specifically, the storage capacitor Cst included in the sub-pixel driving circuit has a first plate Cst1 and a second plate Cst2, the first plate Cst1 and the second plate Cst2 are arranged opposite to each other, and the first plate Cst1 is coupled to the gate of the driving transistor, and the second plate Cst2 is coupled to the power signal line pattern VDD. When laying out the storage capacitor Cst, the first plate Cst1 can be directly reused as the gate of the driving transistor, which not only ensures that the storage capacitor Cst is coupled to the gate of the driving transistor, but also reduces the space occupied by the sub-pixel driving circuit, which is more conducive to improving the resolution of the display substrate. In addition, the second plate Cst2 in the storage capacitor Cst is arranged to be located on the surface of the second interlayer insulating layer facing away from the substrate, so that the second plate Cst2 in the storage capacitor Cst can be formed simultaneously with the second shielding component 301 and the initialization signal line pattern in the same patterning process, thereby greatly simplifying the manufacturing process of the display substrate and saving production costs.

[0441] In some embodiments, the sub-pixel further includes: a reset signal line pattern (such as RST1) extending along a second direction intersecting the first direction, and the sub-pixel driving circuit further includes:

[0442] A first conductive connection portion 405, wherein the orthographic projection of the first conductive connection portion 405 on the substrate 50 covers at least a portion of the orthographic projection of the sixth conductor pattern 101px on the substrate 50;

[0443] The second transistor T2, the first electrode (such as the source S2) of the second transistor T2 is coupled to the initialization signal line pattern (such as VINT1) through the first conductive connection portion 405, the second electrode (such as the drain D2) of the second transistor T2 is coupled to the gate of the driving transistor, and the gate 202g of the second transistor T2 is coupled to the reset signal line pattern (such as RST1).

[0444] Specifically, the first conductive connection portion 405 can be made of a metal material, and can be formed in the same patterning process as the data line pattern.

[0445] The above-mentioned setting of the first conductive connection part 405 on the substrate 50 covers at least a part of the orthographic projection of the sixth conductor pattern 101px on the substrate 50, so that the first conductive connection part 405 can cover the sixth conductor pattern 101px, and because the first conductive connection part 405 is coupled to the initialization signal line pattern, the first conductive connection part 405 has a fixed potential, thereby better reducing the coupling effect between the sixth conductor pattern 101px and other conductive patterns nearby, so that the working performance of the display substrate is more stable.

[0446] like Fig.16 As shown, in some embodiments, the sub-pixel further includes: a gate line pattern GATE, a light emitting control signal line pattern EM, a reset signal line pattern (such as RST1) and an initialization signal line pattern (such as VINT1); the gate line pattern GATE, the light emitting control signal line pattern EM, the reset signal line pattern and the initialization signal line pattern all extend along a second direction, and the second direction intersects with the first direction;

[0447] The two switch transistors include a fourth transistor T4 and a fifth transistor T5;

[0448] The sub-pixel driving circuit further includes: a first transistor T1, a second transistor T2, a sixth transistor T6 and a seventh transistor T7;

[0449] The gate of the driving transistor (such as the gate 203g of the third transistor T3) is coupled to the second electrode of the first transistor T1, the first electrode of the driving transistor is coupled to the second electrode of the fifth transistor T5, and the second electrode of the driving transistor is coupled to the first electrode of the first transistor T1;

[0450] The gate 201g of the first transistor T1 is coupled to the gate line pattern GATE;

[0451] The gate 202g of the second transistor T2 is coupled to the reset signal line pattern, the first electrode of the second transistor T2 is coupled to the initialization signal line pattern, and the second electrode of the second transistor T2 is coupled to the gate of the driving transistor;

[0452] The gate 204g of the fourth transistor T4 is coupled to the gate line pattern GATE, the first electrode of the fourth transistor T4 is coupled to the data line pattern (such as DATA1 in FIG. (), and the second electrode of the fourth transistor T4 is coupled to the first electrode of the driving transistor;

[0453] The gate 205g of the fifth transistor T5 is coupled to the light emitting control signal line pattern EM, and the first electrode of the fifth transistor T5 is coupled to the power signal line pattern VDD;

[0454] The gate 206g of the sixth transistor T6 is coupled to the light emitting control signal line pattern EM, the first electrode of the sixth transistor T6 is coupled to the second electrode of the driving transistor, and the second electrode of the sixth transistor T6 is coupled to the light emitting element in the sub-pixel;

[0455] The gate 207g of the seventh transistor T7 is coupled to the reset signal line pattern (such as RST2) included in the next sub-pixel adjacent along the first direction, the first electrode of the seventh transistor T7 is coupled to the initialization signal line pattern (such as VINT2) included in the next sub-pixel, and the second electrode of the seventh transistor T7 is coupled to the light-emitting element in the sub-pixel.

[0456] Specifically, in the above-mentioned display substrate, the multiple sub-pixels included can be distributed in an array, and the multiple sub-pixels can be divided into multiple rows of sub-pixels and multiple columns of sub-pixels, each row of sub-pixels includes multiple sub-pixels arranged along the second direction, and each column of sub-pixels includes multiple sub-pixels arranged along the first direction, and the first direction intersects with the second direction.

[0457] It should be noted that the next adjacent sub-pixel along the first direction is the next adjacent sub-pixel located in the same column as the seventh transistor T7.

[0458] The sub-pixel and the sub-pixel driving circuit included therein are arranged as the above-mentioned structure, which can effectively reduce the layout space occupied by the sub-pixel driving circuit while ensuring the working performance of the sub-pixel driving circuit, and is conducive to improving the resolution of the display substrate.

[0459] An embodiment of the present disclosure further provides a display device, comprising the display substrate provided by the above embodiment.

[0460] Since in the display substrate provided by the above embodiment, the second plate Cst2 of the storage capacitor Cst is coupled to the power signal line pattern VDD, so that the second plate Cst2 of the storage capacitor Cst has the same fixed potential as the power signal transmitted on the power signal line pattern VDD; at the same time, the second electrodes of the two switching transistors are coupled to the first electrode of the driving transistor, and the orthographic projection of the second electrode of at least one of the two switching transistors on the substrate 50 at least partially overlaps with the orthographic projection of the power signal line pattern VDD on the substrate 50, and at least partially overlaps with the orthographic projection of the second plate Cst2 of the storage capacitor Cst on the substrate 50, so that the second plate Cst2 of the storage capacitor Cst and the power signal line pattern VDD can both shield the second electrode of at least one of the two switching transistors, thereby reducing the crosstalk phenomenon caused by signals on other conductive patterns (such as signal line patterns) located around at least one of the two switching transistors to the second electrode of at least one of the two switching transistors, thereby reducing the crosstalk phenomenon caused to the first electrode of the driving transistor.

[0461] Therefore, when the display device provided by the embodiment of the present disclosure includes the above-mentioned display substrate, it also has the above-mentioned beneficial effects, which will not be described in detail here.

[0462] The disclosed embodiment also provides a method for manufacturing a display substrate, the manufacturing method comprising: manufacturing a plurality of sub-pixels distributed in an array on a substrate; the sub-pixels comprising: a data line pattern extending along a first direction; a power signal line pattern, the power signal line pattern comprising a portion extending along the first direction; a sub-pixel driving circuit, the sub-pixel driving circuit comprising: two switching transistors, a driving transistor and a storage capacitor; the first electrode of the storage capacitor is coupled to the gate of the driving transistor, and the second electrode of the storage capacitor is coupled to the power signal line pattern; the second electrodes of the two switching transistors are both coupled to the first electrode of the driving transistor, and the orthographic projection of the second electrode of at least one of the two switching transistors on the substrate at least partially overlaps with the orthographic projection of the power signal line pattern on the substrate, and at least partially overlaps with the orthographic projection of the second electrode of the storage capacitor on the substrate.

[0463] In the display substrate manufactured by the manufacturing method provided by the embodiment of the present disclosure, the second plate Cst2 of the storage capacitor Cst is arranged to be coupled with the power signal line pattern VDD, so that the second plate Cst2 of the storage capacitor Cst has the same fixed potential as the power signal transmitted on the power signal line pattern VDD; at the same time, the second electrodes of the two switching transistors are arranged to be coupled with the first electrode of the driving transistor, and the orthographic projection of the second electrode of at least one of the two switching transistors on the substrate 50 at least partially overlaps with the orthographic projection of the power signal line pattern VDD on the substrate 50, and at least partially overlaps with the orthographic projection of the second plate Cst2 of the storage capacitor Cst on the substrate 50, so that the second plate Cst2 of the storage capacitor Cst and the power signal line pattern VDD can both shield the second electrode of at least one of the two switching transistors, thereby reducing the crosstalk phenomenon caused by the signal on other conductive patterns (such as signal line patterns) located around at least one of the two switching transistors to the second electrode of at least one of the two switching transistors, thereby reducing the crosstalk phenomenon caused to the first electrode of the driving transistor.

[0464] It should be noted that each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method embodiment, since it is basically similar to the product embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the product embodiment.

[0465] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. "Include" or "comprise" and similar words mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. "Connect" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0466] It will be understood that when an element such as a layer, film, region, or substrate is referred to as being “on” or “under” another element, it can be “directly on” or “under” the other element or intervening elements may be present.

[0467] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0468] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A display substrate, characterized in that: include: A substrate and a plurality of sub-pixels distributed in an array on the substrate; The sub-pixel comprises: A data line pattern extending along a first direction; a power signal line pattern, the power signal line pattern including a portion extending along the first direction; A sub-pixel driving circuit, the sub-pixel driving circuit comprising: two switching transistors, a driving transistor and a storage capacitor; the first plate of the storage capacitor is coupled to the gate of the driving transistor, and the second plate of the storage capacitor is coupled to the power signal line pattern; the second electrodes of the two switching transistors are coupled to the first electrode of the driving transistor, and the orthographic projection of the second electrode of at least one of the two switching transistors on the substrate at least partially overlaps with the orthographic projection of the power signal line pattern on the substrate, and at least partially overlaps with the orthographic projection of the second plate of the storage capacitor on the substrate, Among them, the sub-pixel also includes a third initialization signal line graphic extending along a first direction, and a first initialization signal line graphic coupled to the third initialization signal line graphic, the first initialization signal line graphic extends along a second direction, the second direction intersects with the first direction, and the first initialization signal line graphic and the third initialization signal line graphic are used to transmit an initialization signal with a fixed potential.

2. The display substrate according to claim 1, characterized in that: The second electrodes of the two switching transistors and the first electrode of the driving transistor are an integrated structure, and the integrated structure includes a first conductive portion extending along the first direction, and the orthographic projection of the first conductive portion on the substrate, the orthographic projection of the power signal line pattern on the substrate, and the orthographic projection of the second electrode plate of the storage capacitor on the substrate have a first overlapping area, and the first overlapping area does not overlap with the orthographic projection of the data line pattern on the substrate.

3. The display substrate according to claim 1, characterized in that: The orthographic projection of the first electrode of the driving transistor on the substrate is located inside the orthographic projection of the second electrode plate of the storage capacitor on the substrate.

4. The display substrate according to claim 2, characterized in that: The sub-pixel further includes: a gate line pattern and a light emitting control signal line pattern both extending along the second direction; The sub-pixel driving circuit further includes: a first transistor and a sixth transistor; the two switch transistors include a fourth transistor and a fifth transistor; The gate of the fourth transistor is coupled to the gate line pattern, the first electrode of the fourth transistor is coupled to the data line pattern, the second electrode of the fourth transistor is coupled to the second electrode of the fifth transistor, the gate of the fifth transistor is coupled to the light emitting control signal line pattern, and the first electrode of the fifth transistor is coupled to the power signal line pattern; The gate of the first transistor is coupled to the gate line pattern, the second electrode of the first transistor is coupled to the gate of the driving transistor, the first electrode of the first transistor, the first electrode of the sixth transistor and the second electrode of the driving transistor form an integrated structure, the integrated structure includes a second conductive portion extending along the first direction, the gate of the sixth transistor is coupled to the light emitting control signal line pattern, and the second electrode of the sixth transistor is coupled to the light emitting element in the sub-pixel; The orthographic projection of the channel region of the driving transistor on the substrate is located between the orthographic projection of the first conductive portion on the substrate and the orthographic projection of the second conductive portion on the substrate; and along the second direction, the minimum distance between the orthographic projection of the gate of the driving transistor on the substrate and the orthographic projection of the first conductive portion on the substrate is smaller than the minimum distance between the orthographic projection of the gate of the driving transistor on the substrate and the orthographic projection of the second conductive portion on the substrate.

5. The display substrate according to claim 1, characterized in that: The sub-pixel driving circuit further includes a second transistor coupled to a gate of the driving transistor, wherein the second transistor includes: A first semiconductor pattern, a second semiconductor pattern, and a third conductor pattern coupled to the first semiconductor pattern and the second semiconductor pattern, respectively, wherein the conductivity of the third conductor pattern is better than the conductivity of the first semiconductor pattern and the conductivity of the second semiconductor pattern; a first gate pattern and a second gate pattern, wherein an orthographic projection of the first gate pattern on the substrate at least partially overlaps with an orthographic projection of the first semiconductor pattern on the substrate, and an orthographic projection of the second gate pattern on the substrate at least partially overlaps with an orthographic projection of the second semiconductor pattern on the substrate; The orthographic projection of the third conductor pattern on the substrate does not overlap with the orthographic projection of the first gate pattern on the substrate, and the orthographic projection of the second gate pattern on the substrate; An orthographic projection of the third conductor pattern on the substrate at least partially overlaps with an orthographic projection of the first initialization signal line pattern on the substrate.

6. The display substrate according to claim 1, characterized in that: The sub-pixel driving circuit further includes: a first transistor and a sixth transistor; the first transistor includes: a fourth semiconductor pattern, a fifth semiconductor pattern, and a sixth conductor pattern respectively coupled to the fourth semiconductor pattern and the fifth semiconductor pattern, wherein the conductivity of the sixth conductor pattern is better than the conductivity of the fourth semiconductor pattern and the conductivity of the fifth semiconductor pattern; A third gate pattern and a fourth gate pattern coupled to each other, wherein the orthographic projection of the third gate pattern on the substrate partially overlaps with the orthographic projection of the fourth semiconductor pattern on the substrate, and the orthographic projection of the fourth gate pattern on the substrate partially overlaps with the orthographic projection of the fifth semiconductor pattern on the substrate; The orthographic projection of the sixth conductor pattern on the substrate does not overlap with the orthographic projection of the third gate pattern on the substrate, and the orthographic projection of the fourth gate pattern on the substrate.

7. The display substrate according to claim 6, characterized in that: The sub-pixel driving circuit further includes: A first shielding component is used to receive a fixed potential, and an orthographic projection of the first shielding component on the substrate at least partially overlaps with an orthographic projection of the sixth conductor pattern on the substrate.

8. The display substrate according to claim 6, characterized in that: The sub-pixel driving circuit further includes: A second shielding component is used for receiving a constant voltage signal; an orthographic projection of the second shielding component on the substrate at least partially overlaps with an orthographic projection of the sixth conductor pattern on the substrate.

9. The display substrate according to claim 8, characterized in that: The sub-pixel driving circuit further includes: The first shielding component is an integrated structure with the third initialization signal line pattern.

10. The display substrate according to claim 9, characterized in that: The third initialization signal line pattern is arranged in a different layer from the first initialization signal line pattern, an orthographic projection of the third initialization signal line pattern on the substrate and an orthographic projection of the first initialization signal line pattern on the substrate have a first overlapping area, and the third initialization signal line pattern is coupled to the first initialization signal line pattern through a first via hole arranged in the first overlapping area; The second shielding component and the third initialization signal line pattern are arranged in different layers, and an orthographic projection of the second shielding component on the substrate and an orthographic projection of the first shielding component on the substrate have a second overlapping area.

11. The display substrate according to claim 10, characterized in that: The second shielding component does not overlap with the data line pattern.

12. The display substrate according to claim 7, characterized in that: The third initialization signal line pattern and the data line pattern are made of the same material.

13. The display substrate according to claim 12, characterized in that: The third initialization signal line pattern is arranged in the same layer as the power signal line pattern; The third initialization signal line pattern and the power signal line pattern are located at two sides of the driving transistor.

14. The display substrate according to claim 7, characterized in that: The display substrate comprises a first interlayer insulating layer, and the third initialization signal line pattern and the data line pattern are both located on a surface of the first interlayer insulating layer facing away from the base.

15. The display substrate according to claim 8, characterized in that: The second shielding component is made of the same material as the first initialization signal line pattern.

16. The display substrate according to claim 15, characterized in that: The second shielding component and the first initialization signal line pattern are arranged in the same layer as the second electrode plate in the storage capacitor.

17. The display substrate according to claim 8, characterized in that: The display substrate further includes a second interlayer insulating layer, and the second shielding member and the first initialization signal line pattern and the third initialization signal line pattern are all located on a surface of the second interlayer insulating layer facing away from the base.

18. The display substrate according to claim 17, characterized in that: The first plate in the storage capacitor is reused as the gate of the driving transistor, the second plate in the storage capacitor is made of the same material as the second shielding component, and the second plate in the storage capacitor is located on the surface of the second interlayer insulating layer facing away from the substrate.

19. The display substrate according to claim 1, characterized in that: The sub-pixel further includes: a gate line pattern, a light emitting control signal line pattern, and a reset signal line pattern; the gate line pattern, the light emitting control signal line pattern, and the reset signal line pattern all extend along the second direction; The two switch transistors include a fourth transistor and a fifth transistor; The sub-pixel driving circuit further includes: a first transistor, a second transistor, a sixth transistor and a seventh transistor; The gate of the driving transistor is coupled to the second electrode of the first transistor, the first electrode of the driving transistor is coupled to the second electrode of the fifth transistor, and the second electrode of the driving transistor is coupled to the first electrode of the first transistor; The gate of the first transistor is coupled to the gate line pattern; The gate of the second transistor is coupled to the reset signal line pattern, the first electrode of the second transistor is coupled to the first initialization signal line pattern, and the second electrode of the second transistor is coupled to the gate of the driving transistor; The gate electrode of the fourth transistor is coupled to the gate line pattern, the first electrode of the fourth transistor is coupled to the data line pattern, and the second electrode of the fourth transistor is coupled to the first electrode of the driving transistor; The gate electrode of the fifth transistor is coupled to the light emitting control signal line pattern, and the first electrode of the fifth transistor is coupled to the power supply signal line pattern; The gate of the sixth transistor is coupled to the light emitting control signal line pattern, the first electrode of the sixth transistor is coupled to the second electrode of the driving transistor, and the second electrode of the sixth transistor is coupled to the corresponding light emitting element in the sub-pixel; The gate of the seventh transistor is coupled to the reset signal line pattern included in the next sub-pixel adjacent to the first direction, the first electrode of the seventh transistor is coupled to the second initialization signal line pattern included in the next sub-pixel, and the second electrode of the seventh transistor is coupled to the light-emitting element in the sub-pixel.

20. A display device, characterized in that: The invention comprises the display substrate according to any one of claims 1 to 19.

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