Display device and mobile electronic device including the same

Abstract

A display device and a mobile electronic device including the same are provided. The display device includes a pixel defining layer, a first electrode positioned in an opening of the pixel defining layer, a wiring including a first wiring extending in a first direction and having a first length in a display area and a second wiring having a second length shorter than the first length, an intermediate layer, a second electrode, and a pattern wiring, the intermediate layer covers the first electrode at the opening, a portion of the intermediate layer is disconnected at the upper portion of the wiring, and the second electrode covers the intermediate layer in the opening. The pattern wiring is connected to the wiring in the non-display area and includes a third wiring connected to the first wiring and having a third length and a fourth wiring connected to the second wiring and having a fourth length longer than the third length.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0117137 filed in the Korean Intellectual Property Office on September 4, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Aspects of embodiments of the present disclosure relate to a display device and a mobile electronic device including the display device. Background Art

[0004] Wearable devices in the form of glasses or helmets are being developed to form a focal point close to the user's eyes at a distance. For example, the wearable device may be a head mounted display (HMD) device or augmented reality (AR) glasses. Such wearable devices provide the user with an augmented reality screen or a virtual reality (VR) screen.

[0005] Wearable devices developed in the form of HMD devices or AR glasses may use a display specification of at least 2000 pixels per inch (PPI) to allow users to use the device for a long time without feeling dizzy. As such, organic light emitting diode on silicon (OLEDoS) technology, i.e., a small organic light emitting display device with high resolution, is emerging. OLEDoS is a technology in which an organic light emitting diode (OLED) is arranged on a semiconductor wafer substrate on which a complementary metal oxide semiconductor (CMOS) is arranged.

[0006] The above information disclosed in this Background section is for enhancement of understanding of the background of the disclosure and therefore it may contain information that does not constitute prior art. Summary of the invention

[0007] As the pitch between pixels in a display panel to which OLEDoS technology is applied becomes narrower, unexpected leakage current may occur between adjacent pixels. The leakage current may occur through some conductive layers among the intermediate layers arranged between the pixel electrode (e.g., anode) and the common electrode (e.g., cathode), and may cause color crosstalk between adjacent pixels.

[0008] One or more embodiments of the present disclosure may relate to a display device and a mobile electronic device including the display device, which is capable of preventing or substantially preventing leakage current and / or color crosstalk by disconnecting at least a portion of an intermediate layer arranged between a pixel electrode and a common electrode located between adjacent pixels using wiring.

[0009] One or more embodiments of the present disclosure may relate to a display device and a mobile electronic device including the display device, wherein the display device includes a disconnected portion of an intermediate layer having a uniform or substantially uniform width and height (e.g., where the intermediate layer is disconnected) by compensating for a resistance deviation or variation caused by a length deviation or variation of wiring, and is capable of reducing product defects caused by process deviations of the disconnected portion.

[0010] According to one or more embodiments of the present disclosure, a display device includes a substrate, a driving element layer located on the substrate, and a light-emitting element layer located on the driving element layer, the light-emitting element layer including: a pixel defining layer that divides a plurality of sub-pixels, a first electrode of a sub-pixel among the plurality of sub-pixels, a wiring, an intermediate layer, a second electrode, and a pattern wiring, the first electrode being positioned in an opening of the pixel defining layer, the wiring including a first wiring that extends in a first direction while crossing between the first electrodes on the pixel defining layer and having a first length in a display region, and a second wiring having a second length shorter than the first length in the display region, the intermediate layer covering the first electrode at the opening and covering the pixel defining layer, a portion of the intermediate layer being disconnected at an upper portion of the wiring, the second electrode covering the intermediate layer in the opening and continuously covering the intermediate layer and the wiring between sub-pixels adjacent to each other among the plurality of sub-pixels, the pattern wiring being connected to the wiring in a non-display region and including a third wiring and a fourth wiring. The third wiring is connected to the first wiring and has a third length, and the fourth wiring is connected to the second wiring and has a fourth length longer than the third length.

[0011] In an implementation, the fourth wiring may have a zigzag shape to have a fourth length longer than the third length.

[0012] In an embodiment, a first total length obtained by adding a first length of the first wiring and a third length of the third wiring to each other may be equal to a second total length obtained by adding a second length of the second wiring and a fourth length of the fourth wiring to each other.

[0013] In an embodiment, the first wiring may be an odd-numbered wiring among the wirings, and the second wiring may be an even-numbered wiring among the wirings.

[0014] In an embodiment, the power supply pad may be positioned at one end of the non-display area adjacent to one end of the wiring, and the other end of the non-display area adjacent to the other end of the wiring may include a first ground wiring and a second ground wiring connecting the ground pad and the wiring to each other. The first ground wiring may be connected to the first wiring and may extend straight. The second ground wiring may be connected to the second wiring and may have a zigzag shape.

[0015] In an implementation, a ground pad may be positioned at the other end of the non-display area.

[0016] In an implementation, the first electrode may have a hexagonal shape in a plan view, and may include a protrusion protruding in a direction of the first wiring.

[0017] In an embodiment, the plurality of sub-pixels may include a first light emitting region of a first sub-pixel, a second light emitting region of a second sub-pixel, and a third light emitting region of a third sub-pixel. The first light emitting region and the second light emitting region may be alternately positioned along the first direction in odd-numbered rows among the plurality of sub-pixels, and the third light emitting region may be positioned at intervals along the first direction in even-numbered rows among the plurality of sub-pixels. The length of the third light emitting region in the first direction may be greater than the sum of the length of the first light emitting region in the first direction and the length of the second light emitting region in the first direction.

[0018] In an embodiment, the first wiring may include a first portion located between the first light emitting region and the third light emitting region, a second portion extending from the first portion and located between the first light emitting region and the second light emitting region, and a third portion extending from the second portion and located between the second light emitting region and the third light emitting region. The second wiring may include a fourth portion located between the third light emitting region and the first and second light emitting regions, and a fifth portion located between two third light emitting regions adjacent to each other.

[0019] In an embodiment, the display device may further include a plurality of fan-out wirings connected between the pattern wiring and the power supply pad. The plurality of fan-out wirings may all have the same length as each other by including a length deviation compensation portion, and the length deviation compensation portion of each of the fan-out wirings may include a zigzag wiring of a different length from the length deviation compensation portion of other fan-out wirings in the fan-out wirings.

[0020] According to one or more embodiments of the present disclosure, a mobile electronic device includes a display panel including a light-emitting element layer. The light-emitting element layer includes a pixel defining layer that divides a plurality of sub-pixels, a first electrode of a sub-pixel among the plurality of sub-pixels, a wiring, an intermediate layer, a second electrode, and a pattern wiring, wherein the first electrode is positioned in an opening of the pixel defining layer, the wiring includes a first wiring that extends in a first direction while crossing between the first electrodes on the pixel defining layer and has a first length in the display area, and a second wiring that has a second length shorter than the first length in the display area, the intermediate layer covers the first electrode at the opening and covers the pixel defining layer, a portion of the intermediate layer is disconnected at the upper portion of the wiring, the second electrode covers the intermediate layer in the opening and continuously covers the intermediate layer and wiring between the sub-pixels arranged adjacent to each other among the plurality of sub-pixels, and the pattern wiring is connected to the wiring in the non-display area and includes a third wiring and a fourth wiring. The third wiring is connected to the first wiring and has a third length. The fourth wiring is connected to the second wiring and has a fourth length longer than the third length.

[0021] In an implementation, the fourth wiring may have a zigzag shape to have a fourth length longer than the third length.

[0022] In an embodiment, a first total length obtained by adding a first length of the first wiring and a third length of the third wiring to each other may be equal to a second total length obtained by adding a second length of the second wiring and a fourth length of the fourth wiring to each other.

[0023] In an embodiment, the first wiring may be an odd-numbered wiring among the wirings, and the second wiring may be an even-numbered wiring among the wirings.

[0024] In an embodiment, the power supply pad may be positioned at one end of the non-display area adjacent to one end of the wiring, and the other end of the non-display area adjacent to the other end of the wiring may include a first ground wiring and a second ground wiring connecting the ground pad and the wiring to each other. The first ground wiring may be connected to the first wiring and may extend straight, and the second ground wiring may be connected to the second wiring and may have a zigzag shape.

[0025] In an implementation, a ground pad may be positioned at the other end of the non-display area.

[0026] In an implementation, the first electrode may have a hexagonal shape in a plan view, and may include a protrusion protruding in a direction of the first wiring.

[0027] In an embodiment, the plurality of sub-pixels may include a first light emitting region of a first sub-pixel, a second light emitting region of a second sub-pixel, and a third light emitting region of a third sub-pixel. The first light emitting region and the second light emitting region may be alternately positioned along the first direction in odd-numbered rows among the plurality of sub-pixels. The third light emitting region may be positioned at intervals along the first direction in even-numbered rows among the plurality of sub-pixels. The length of the third light emitting region in the first direction may be greater than the sum of the length of the first light emitting region in the first direction and the length of the second light emitting region in the first direction.

[0028] In an embodiment, the first wiring may include a first portion located between the first light emitting region and the third light emitting region, a second portion extending from the first portion and located between the first light emitting region and the second light emitting region, and a third portion extending from the second portion and located between the second light emitting region and the third light emitting region. The second wiring may include a fourth portion located between the third light emitting region and the first and second light emitting regions, and a fifth portion located between two third light emitting regions adjacent to each other.

[0029] In an embodiment, the mobile electronic device may further include a plurality of fan-out wirings connected between the pattern wiring and the power pad. The plurality of fan-out wirings may all have the same length as each other by including a length deviation compensation portion, and the length deviation compensation portion of each of the fan-out wirings may include a zigzag wiring of a different length from the length deviation compensation portion of the other fan-out wirings in the fan-out wirings.

[0030] According to one or more embodiments of the present disclosure, leakage current and color crosstalk phenomena in a display device and a mobile device including the display device can be prevented or substantially prevented by disconnecting at least a portion of an intermediate layer arranged between a pixel electrode and a common electrode located between adjacent pixels using wiring.

[0031] According to one or more embodiments of the present disclosure, by compensating for resistance deviations or changes caused by length deviations or changes in wiring, the width and height of the disconnected portion of the middle layer (e.g., where the middle layer is disconnected) can be uniformized (e.g., can be formed uniformly or substantially uniformly), and product defects caused by process deviations or changes in the disconnected portion can be reduced.

[0032] However, the aspects and features of the present disclosure are not limited to those described above. The above and other aspects and features of the present disclosure will become more apparent to those of ordinary skill in the art through the following detailed description of the present disclosure with reference to the accompanying drawings, or can be learned by practicing one or more of the presented embodiments of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The above and other aspects and features of the present disclosure will be more clearly understood from the following detailed description of illustrative non-limiting embodiments with reference to the accompanying drawings, in which:

[0034] Figure 1 is a perspective view showing a head mounted display device according to an embodiment;

[0035] Figure 2 yes Figure 1 An exploded perspective view of a head mounted display device;

[0036] Figure 3 is a perspective view showing a head mounted display device according to an embodiment;

[0037] Figure 4 is an exploded perspective view showing a display device according to an embodiment;

[0038] Figure 5 It is shown Figure 4 A layout diagram of a display panel;

[0039] Figure 6 is a block diagram showing a display device according to an embodiment;

[0040] Figure 7 is an equivalent circuit diagram of a first sub-pixel according to an embodiment;

[0041] Figure 8 is a layout diagram showing pixels of a display area according to an embodiment;

[0042] Fig. 9 is a cross-sectional view showing an example in which a portion of a display panel is cut according to an embodiment;

[0043] Fig.10 is a plan view showing the arrangement of first electrodes of sub-pixels according to an embodiment;

[0044] Fig.11 is a cross-sectional view schematically showing connection between a reference wiring and a pad portion of a display panel according to an embodiment;

[0045] Fig.12 is a layout diagram showing a pad portion and a fan-out line arranged in a non-display area of ​​a display panel according to an embodiment;

[0046] Fig.13 It is shown Fig.12 An enlarged view of more details of the wiring between the power pad and the reference wiring shown in FIG.

[0047] Fig.14 is a flowchart illustrating a method of manufacturing a display device according to an embodiment; and

[0048] Figures 15 to 18 The following are cross-sectional views showing respective processes of a method for manufacturing a display device. DETAILED DESCRIPTION

[0049] Hereinafter, embodiments will be described in more detail with reference to the accompanying drawings, in which the same reference numerals always indicate the same elements. However, the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments shown herein. On the contrary, these embodiments are provided as examples so that the present disclosure will be thorough and complete, and the aspects and features of the present disclosure will be fully communicated to those skilled in the art. Accordingly, processes, elements and techniques that are not necessary for a complete understanding of the aspects and features of the present disclosure by those of ordinary skill in the art may not be described. Unless otherwise stated, the same reference numerals represent the same elements throughout the drawings and written descriptions, and therefore their redundant descriptions may not be repeated.

[0050] When a specific embodiment can be implemented differently, the specific process order may be different from the described order. For example, two processes described in succession may be performed simultaneously or substantially simultaneously, or may be performed in the reverse order of the described order.

[0051] In the accompanying drawings, for the sake of clarity, the relative size, thickness and ratio of elements, layers and zones can be enlarged and / or simplified. Spatial relative terms, such as "below", "below", "below", "above", "on", etc., can be used in this article for the convenience of explanation, to describe the relationship between an element or feature as shown in the figure and another (some) element or feature. It should be understood that, in addition to the orientation depicted in the figure, spatial relative terms are intended to also cover the different orientations of the device in use or in operation. For example, if the device in the figure is turned over, the element described as "below", "below" or "below" of other elements or features will be subsequently oriented to "above" other elements or features. Therefore, the example terms "below" and "below" can cover both the orientations of above and below. The device can be oriented in other ways (for example, rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein should be interpreted accordingly.

[0052] In the figure, the X-axis, Y-axis and Z-axis are not limited to the three axes of the rectangular coordinate system, and can be interpreted in a broader sense. For example, the X-axis, Y-axis and Z-axis may be perpendicular or substantially perpendicular to each other, or may represent different directions that are not perpendicular to each other.

[0053] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, the first element, component, region, layer or part described below may be referred to as a second element, component, region, layer or part without departing from the spirit and scope of the present disclosure.

[0054] It should be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on, directly connected to, or coupled to the other element or layer, or there may be one or more intervening elements or layers. Similarly, when a layer, region, or element is referred to as being "electrically connected" to another layer, region, or element, it can be directly electrically connected to the other layer, region, or element, or it can be indirectly electrically connected with one or more intervening layers, regions, or elements interposed therebetween. In addition, it should be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or there may also be one or more intervening elements or layers.

[0055] The terms used herein are for the purpose of describing specific embodiments and are not intended to limit the present disclosure. Unless the context clearly indicates otherwise, the singular forms "one" and "an" as used herein are also intended to include the plural forms. It should also be understood that the terms "comprises", "comprising", "includes", "including", "has", "have" and "having" when used in this specification specify the presence of stated features, wholes, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, parts and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the relevant listed items. For example, the expression "A and / or B" means A, B, or A and B. Expressions such as "at least one of..." when following a column of elements, modify the entire column of elements rather than modifying the individual elements in the column. For example, the expressions "at least one of a, b, and c" and "at least one selected from the group consisting of a, b, and c" mean only a, only b, only c, both a and b, both a and c, both b and c, all of a, b, and c, or variations thereof.

[0056] As used herein, the terms "substantially," "about," and similar terms are used as terms of approximation rather than terms of degree, and are intended to take into account the inherent deviations in measurements or calculations recognized by those of ordinary skill in the art. In addition, the use of "may" when describing embodiments of the present disclosure refers to "one or more embodiments of the present disclosure." As used herein, the terms "use," "using," and "used" may be considered synonymous with the terms "utilize," "utilizing," and "utilized," respectively.

[0057] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It should also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having the same meaning as they have in the context of the relevant technology and / or this specification, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0058] Figure 1 is a perspective view showing a head mounted display device according to an embodiment. Figure 2 yes Figure 1 An exploded perspective view of a head mounted display device.

[0059] Reference Figure 1 and Figure 2 According to the embodiment, the head-mounted display device 1 includes a first display device 10_1, a second display device 10_2, a display device accommodating portion 110, a accommodating portion cover 120, a first eyepiece 131, a second eyepiece 132, a head mounting band 140, an intermediate frame 160, a first optical member 151, a second optical member 152, a control circuit board 170 and a connector.

[0060] The first display device 10_1 provides an image to the left eye of the user, and the second display device 10_2 provides an image to the right eye of the user. Each of the first display device 10_1 and the second display device 10_2 is similar to the following reference Figures 4 to 18 The display device 10 described in more detail is the same or substantially the same.

[0061] The first optical member 151 may be disposed between the first display device 10_1 and the first eyepiece 131. The second optical member 152 may be disposed between the second display device 10_2 and the second eyepiece 132. Each of the first optical member 151 and the second optical member 152 may include at least one convex lens.

[0062] The middle frame 160 may be disposed between the first display device 10_1 and the control circuit board 170, and may be disposed between the second display device 10_2 and the control circuit board 170. The middle frame 160 serves to support the first display device 10_1, the second display device 10_2, and the control circuit board 170 and fix them to each other.

[0063] The control circuit board 170 may be disposed between the middle frame 160 and the display device receiving portion 110. The control circuit board 170 may be connected to the first display device 10_1 and the second display device 10_2 through a connector. The control circuit board 170 may convert an image source input from the outside into digital video data DATA (see Figure 6), and the digital video data DATA may be transmitted to the first display device 10_1 and the second display device 10_2 through the connector.

[0064] The control circuit board 170 may transmit digital video data DATA corresponding to a left-eye image optimized for the user's left eye to the first display device 10_1, and may transmit digital video data DATA corresponding to a right-eye image optimized for the user's right eye to the second display device 10_2. As another example, the control circuit board 170 may transmit the same digital video data DATA to the first display device 10_1 and the second display device 10_2.

[0065] The display device receiving portion 110 is used to receive the first display device 10_1, the second display device 10_2, the middle frame 160, the first optical member 151, the second optical member 152, the control circuit board 170, and the connector. The receiving portion cover 120 is arranged to cover one open surface of the display device receiving portion 110. The receiving portion cover 120 may include a first eyepiece 131 to be arranged for the left eye of the user and a second eyepiece 132 to be arranged for the right eye of the user. Although Figure 1 and Figure 2 It is shown that the first eyepiece 131 and the second eyepiece 132 are separately arranged, but the present disclosure is not limited thereto. In some embodiments, the first eyepiece 131 and the second eyepiece 132 may be integrated together into one.

[0066] The first eyepiece 131 may be aligned with the first display device 10_1 and the first optical member 151. The second eyepiece 132 may be aligned with the second display device 10_2 and the second optical member 152. Therefore, the user may view the image of the first display device 10_1 magnified into a virtual image by the first optical member 151 through the first eyepiece 131, and may view the image of the second display device 10_2 magnified into a virtual image by the second optical member 152 through the second eyepiece 132.

[0067] The head mounting band 140 is used to fix the display device housing 110 to the user's head so that the first eyepiece 131 and the second eyepiece 132 of the housing cover 120 are arranged on the left eye and the right eye of the user, respectively. When the display device housing 110 is implemented in a lightweight and small size, the head mounted display device 1 may include, for example, Figure 3 , rather than the head mounting strap 140 .

[0068] In addition, the head mounted display device 1 may further include a battery for supplying power, an external memory slot for accommodating an external memory, and an external connection port and a wireless communication module for receiving an image source. The external connection port may be a universal serial bus (USB) terminal, a display port, or a high-definition multimedia interface (HDMI) terminal. The wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0069] Figure 3 is a perspective view showing a head mounted display device according to an embodiment.

[0070] Reference Figure 3 The head mounted display device 1_1 according to the embodiment may be a glasses type display device including a display device housing 120_1 implemented with a relatively light weight and a small size. The head mounted display device 1_1 according to the embodiment may include a display device 10_3, a left eye lens 311, a right eye lens 312, a support frame 350, glasses frame legs 341 and 342, an optical member 320, an optical path conversion member 330, and a display device housing 120_1.

[0071] Figure 3 The display device 10_3 shown in FIG. 1 can be used with reference to the following Figures 4 to 18 The display device 10 described in more detail is the same or substantially the same.

[0072] The display device housing portion 120_1 is used to house the display device 10_3, the optical member 320, and the optical path conversion member 330. When the image displayed on the display device 10_3 is magnified by the optical member 320 and the optical path thereof is converted by the optical path conversion member 330, the image can be provided to the right eye of the user through the right eye lens 312. Therefore, the user can view an augmented reality image in which a virtual image displayed on the display device 10_3 and a real image viewed through the right eye lens 312 are combined with each other through the right eye.

[0073] Figure 3 The display device housing 120_1 is shown to be arranged at the right distal end of the support frame 350, but the present disclosure is not limited thereto. For example, the display device housing 120_1 may be arranged at the left distal end of the support frame 350, and in this case, the image of the display device 10_3 may be provided to the left eye of the user. As another example, the display device housing 120_1 may be arranged at both the left distal end and the right distal end of the support frame 350. In this case, the user can view the image displayed on the display device 10_3 through both the left eye and the right eye of the user.

[0074] Figure 4 is an exploded perspective view showing a display device according to an embodiment. Figure 5 It is shown Figure 4 Layout diagram of the display panel. Figure 6 is a block diagram showing a display device according to an embodiment.

[0075] Reference Figure 4 and Figure 5 , the display device 10 according to the embodiment is a device for displaying moving images and / or still images. The display device 10 according to the embodiment can be applied to various suitable portable electronic devices, such as mobile phones, smart phones, tablet personal computers (PCs), mobile communication terminals, electronic notepads, electronic books, portable multimedia players (PMPs), navigation devices, and ultra-mobile PCs (UMPCs). For example, the display device 10 can be applied to a display unit of a television, a laptop computer, a monitor, a billboard, or an Internet of Things (IOT) device. As another example, the display device 10 can be applied to a smart watch, a watch phone, and / or a head-mounted display (HMD) for realizing virtual reality and / or augmented reality.

[0076] The display device 10 according to the embodiment includes a display panel 410 , a heat dissipation layer 420 , a circuit board 430 , a driving circuit 440 , and a power supply circuit 450 .

[0077] The display panel 410 may be formed in a planar shape similar to a planar shape of a quadrilateral or in a substantially planar shape. For example, the display panel 410 may have a planar shape similar to a planar shape of a quadrilateral having short sides extending in a first direction DR1 and long sides extending in a second direction DR2 that crosses or intersects the first direction DR1 or in a substantially planar shape. In the display panel 410, the corners where the short sides extending in the first direction DR1 and the long sides extending in the second direction DR2 intersect with each other may be rounded to have a suitable curvature (e.g., a predetermined curvature), or may form a right angle. The planar shape of the display panel 410 is not limited to a quadrilateral, and may be formed to be similar to other suitable polygons, circles, or ellipses. The planar shape of the display device 10 may follow the planar shape of the display panel 410, but the present disclosure is not limited thereto.

[0078] like Figure 5 As shown in FIG. 4 , the display panel 410 includes a display area DAA for displaying an image and a non-display area NDA where no image is displayed.

[0079] like Figure 6 As shown in FIG. 1 , the display area DAA includes a plurality of pixels PX, a plurality of scan lines SL, a plurality of emission control lines EL, and a plurality of data lines DL.

[0080] The plurality of pixels PX include a light emitting element LE (see Figure 7). A plurality of pixels PX may be arranged in a matrix along a first direction DR1 and a second direction DR2. A plurality of scan lines SL and a plurality of emission control lines EL may extend in the first direction DR1 and may be arranged along the second direction DR2. A plurality of data lines DL may extend in the second direction DR2 and may be arranged along the first direction DR1.

[0081] The plurality of scan lines SL include a plurality of write scan lines GWL, a plurality of control scan lines GCL, and a plurality of bias scan lines EBL. The plurality of emission control lines EL include a plurality of first emission control lines EL1 and a plurality of second emission control lines EL2.

[0082] Each of the plurality of pixels PX includes a plurality of sub-pixels SP, for example, a plurality of sub-pixels SP1, SP2, and SP3. The plurality of sub-pixels SP1, SP2, and SP3 may include Figure 7 The plurality of pixel transistors shown in FIG. The plurality of pixel transistors may be formed by a semiconductor process and may be arranged on a semiconductor substrate (eg, Fig. 9 For example, a plurality of pixel transistors may be formed by a complementary metal oxide semiconductor (CMOS).

[0083] Each of the plurality of sub-pixels SP1, SP2, and SP3 may be connected to one write scan line GWL among the plurality of write scan lines GWL, one control scan line GCL among the plurality of control scan lines GCL, one bias scan line EBL among the plurality of bias scan lines EBL, one first emission control line EL1 among the plurality of first emission control lines EL1, one second emission control line EL2 among the plurality of second emission control lines EL2, and one data line DL among the plurality of data lines DL. Each of the plurality of sub-pixels SP1, SP2, and SP3 may receive a data voltage of a corresponding data line DL according to a write scan signal of the corresponding write scan line GWL, and may emit light from a corresponding light emitting element according to the data voltage.

[0084] The non-display area NDA includes a scan driving area SDA, a data driving area DDA, and a pad area PDA.

[0085] The scan driving area SDA may be a region in which the scan driver 510 and the emission driver 520 are arranged. Figure 5 The scan driver 510 is shown to be arranged on the left side of the display area DAA, and the emission driver 520 is arranged on the right side of the display area DAA, but the present disclosure is not limited thereto. For example, the scan driver 510 and the emission driver 520 may each be arranged on both the left and right sides of the display area DAA.

[0086] The scan driver 510 includes a plurality of scan transistors, and the emission driver 520 includes a plurality of light emitting transistors. The plurality of scan transistors and the plurality of light emitting transistors may be formed by a semiconductor process and may be formed on a semiconductor substrate (eg, Fig. 9 For example, a plurality of scanning transistors and a plurality of light emitting transistors may be formed by CMOS.

[0087] The scan driver 510 may include a write scan signal output unit (e.g., a write scan signal output circuit) 511, a control scan signal output unit (e.g., a control scan signal output circuit) 512, and a bias scan signal output unit (e.g., a bias scan signal output circuit) 513. Each of the write scan signal output unit 511, the control scan signal output unit 512, and the bias scan signal output unit 513 may receive a scan timing control signal SCS from a timing control circuit (e.g., a timing controller) 610. The write scan signal output unit 511 may generate a write scan signal according to the scan timing control signal SCS of the timing control circuit 610, and sequentially output the write scan signal to the write scan line GWL. The control scan signal output unit 512 may generate a control scan signal according to the scan timing control signal SCS, and sequentially output the control scan signal to the control scan line GCL. The bias scan signal output unit 513 may generate a bias scan signal according to the scan timing control signal SCS, and sequentially output the bias scan signal to the bias scan line EBL.

[0088] The emission driver 520 includes a first emission control driver 521 and a second emission control driver 522. Each of the first emission control driver 521 and the second emission control driver 522 may receive an emission timing control signal ECS from the timing control circuit 610. The first emission control driver 521 may generate a first emission control signal according to the emission timing control signal ECS, and sequentially output the first emission control signal to the first emission control line EL1. The second emission control driver 522 may generate a second emission control signal according to the emission timing control signal ECS, and sequentially output the second emission control signal to the second emission control line EL2.

[0089] The data driving area DDA may be an area in which the data driver 530 is arranged. The data driver 530 may include a plurality of data transistors. The plurality of data transistors may be formed by a semiconductor process and may be formed on a semiconductor substrate (eg, Fig. 9 For example, the plurality of data transistors may be formed by CMOS.

[0090] The data driver 530 may receive the digital video data DATA and the data timing control signal DCS from the timing control circuit 610. The data driver 530 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS, and outputs the converted analog data voltage to the data line DL. In this case, the sub-pixels SP1, SP2, and SP3 may be selected by the scan write signal of the scan driver 510, and the data voltage may be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0091] The pad area PDA includes a plurality of pads PD arranged along the first direction DR1. Each of the plurality of pads PD may be exposed without being covered by a cover layer (eg, Fig. 9 CVL) and polarizing plate covering.

[0092] The heat dissipation layer 420 may overlap the display panel 410 in the third direction DR3, which is the thickness direction of the display panel 410. The heat dissipation layer 420 may be arranged on one surface of the display panel 410, such as, for example, on the rear surface of the display panel 410. The heat dissipation layer 420 is used to dissipate heat generated from the display panel 410. The heat dissipation layer 420 may include a graphite layer having high thermal conductivity or a metal layer such as silver (Ag), copper (Cu), or aluminum (Al).

[0093] The circuit board 430 may be electrically connected to the plurality of pads PD of the pad area PDA of the display panel 410 by using a conductive adhesive member such as an anisotropic conductive film. The circuit board 430 may be a flexible printed circuit board or a flexible film having a flexible material. Figure 4 The circuit board 430 is shown to be unfolded, but the circuit board 430 may be bent. In this case, one end of the circuit board 430 may be arranged on the rear surface of the display panel 410. The one end of the circuit board 430 may be an opposite end of one end of the circuit board 430 connected to the plurality of pads PD of the pad area PDA of the display panel 410 by using a conductive adhesive member.

[0094] The timing control circuit 610 (which can be implemented as Figure 4 The driving circuit 440 (part of the driving circuit 440 in the display panel 410) can receive digital video data DATA and timing signals from the outside. The driving circuit 440 / timing control circuit 610 can generate a scan timing control signal SCS, an emission timing control signal ECS, and a data timing control signal DCS for controlling the display panel 410 according to the timing signals. The driving circuit 440 / timing control circuit 610 can output the scan timing control signal SCS to the scan driver 510, and can output the emission timing control signal ECS to the emission driver 520. The driving circuit 440 / timing control circuit 610 can output the digital video data DATA and the data timing control signal DCS to the data driver 530.

[0095] The power supply circuit 450 may generate a plurality of panel driving voltages according to an external power supply voltage. For example, the power supply circuit 450 may generate a first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT and supply them to the display panel 410. Figure 7 The first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT are described in more detail.

[0096] Each of the driving circuit 440 / timing control circuit 610 and the power supply circuit 450 may be formed as an integrated circuit (IC) and may be attached to one surface of the circuit board 430. The scan timing control signal SCS, the emission timing control signal ECS, the digital video data DATA, and the data timing control signal DCS of the driving circuit 440 / timing control circuit 610 may be supplied to the display panel 410 through the circuit board 430. The first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT of the power supply circuit 450 may be supplied to the display panel 410 through the circuit board 430.

[0097] Figure 7 is an equivalent circuit diagram of a first sub-pixel according to an embodiment.

[0098] Reference Figure 7 , the first sub-pixel SP1 may be connected to the write scan line GWL, the control scan line GCL, the bias scan line EBL, the first emission control line EL1, the second emission control line EL2, and the data line DL. In addition, the first sub-pixel SP1 may be connected to a first drive voltage VSS (see Figure 6 ) and a first driving voltage line VSL to which a second driving voltage VDD corresponding to a high potential voltage is applied (see Figure 6 ) and a second driving voltage line VDL to which a third driving voltage VINT corresponding to the initialization voltage is applied (see Figure 6 ). In other words, the first driving voltage line VSL may be a low potential voltage line, the second driving voltage line VDL may be a high potential voltage line, and the third driving voltage line VIL may be an initialization voltage line. In this case, the first driving voltage VSS may be a voltage lower than the third driving voltage VINT. The second driving voltage VDD may be a voltage higher than the third driving voltage VINT.

[0099] The first sub-pixel SP1 includes a light emitting element LE and a pixel driving circuit PC connected to the light emitting element LE. The pixel driving circuit PC includes a plurality of transistors T1 to T6, a first capacitor C1, and a second capacitor C2.

[0100] The light emitting element LE emits light according to the driving current Ids flowing through the channel of the first transistor T1. The amount of light emitted from the light emitting element LE may be proportional to the driving current Ids. The light emitting element LE may be arranged between the fourth transistor T4 and the first driving voltage line VSL. The first electrode of the light emitting element LE may be connected to the drain electrode of the fourth transistor T4, and the second electrode of the light emitting element LE may be connected to the first driving voltage line VSL. The first electrode of the light emitting element LE may be an anode (e.g., a pixel electrode), and the second electrode of the light emitting element LE may be a cathode (e.g., a common electrode). The light emitting element LE may be an organic light emitting diode including a first electrode, a second electrode, and an organic light emitting layer arranged between the first electrode and the second electrode, but the present disclosure is not limited thereto. For example, the light emitting element LE may be an inorganic light emitting device including a first electrode, a second electrode, and an inorganic semiconductor arranged between the first electrode and the second electrode. In this case, the light emitting element LE may be a micro light emitting diode.

[0101] The first transistor T1 may be a driving transistor that controls a source-drain current (hereinafter referred to as a "driving current" Ids) flowing between its source electrode and drain electrode according to a voltage applied to its gate electrode. The first transistor T1 includes a gate electrode connected to the first node N1, a source electrode connected to the drain electrode of the sixth transistor T6, and a drain electrode connected to the second node N2.

[0102] The second transistor T2 may be arranged between one electrode of the first capacitor C1 and the data line DL. The second transistor T2 may be turned on by a write scan signal of the write scan line GWL, and connects one electrode of the first capacitor C1 to the data line DL. Therefore, a data voltage of the data line DL may be applied to one electrode of the first capacitor C1. The second transistor T2 includes a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to one electrode of the first capacitor C1.

[0103] The third transistor T3 may be arranged between the first node N1 and the second node N2. The third transistor T3 may be turned on by a control scan signal of the control scan line GCL to connect the first node N1 to the second node N2. Therefore, since the gate electrode and the drain electrode of the first transistor T1 are connected to each other through the third transistor T3, the first transistor T1 may operate like a diode. In other words, when the third transistor T3 is turned on, the first transistor T1 may be connected in a diode manner. The third transistor T3 includes a gate electrode connected to the control scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0104] The fourth transistor T4 may be arranged between the second node N2 and the third node N3. The fourth transistor T4 may be turned on by the first emission control signal of the first emission control line EL1, and connects the second node N2 to the third node N3. Therefore, the driving current Ids of the first transistor T1 may be supplied to the light emitting element LE. The fourth transistor T4 includes a gate electrode connected to the first emission control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0105] The fifth transistor T5 may be arranged between the third node N3 and the third driving voltage line VIL. The fifth transistor T5 may be turned on by the bias scan signal of the bias scan line EBL, and connects the third node N3 to the third driving voltage line VIL. Therefore, the third driving voltage VINT of the third driving voltage line VIL may be applied to the first electrode of the light emitting element LE. The fifth transistor T5 includes a gate electrode connected to the bias scan line EBL, a source electrode connected to the third node N3, and a drain electrode connected to the third driving voltage line VIL.

[0106] The sixth transistor T6 may be arranged between the source electrode of the first transistor T1 and the second driving voltage line VDL. The sixth transistor T6 may be turned on by the second emission control signal of the second emission control line EL2, and connects the source electrode of the first transistor T1 to the second driving voltage line VDL. Therefore, the second driving voltage VDD of the second driving voltage line VDL may be applied to the source electrode of the first transistor T1. The sixth transistor T6 includes a gate electrode connected to the second emission control line EL2, a source electrode connected to the second driving voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0107] The first capacitor C1 is formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor C1 includes one electrode connected to the drain electrode of the second transistor T2 and the other electrode connected to the first node N1.

[0108] The second capacitor C2 is formed between the gate electrode of the first transistor T1 and the second driving voltage line VDL. The second capacitor C2 includes one electrode connected to the gate electrode of the first transistor T1 and another electrode connected to the second driving voltage line VDL.

[0109] The first node N1 may be a contact point of the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor C1, and one electrode of the second capacitor C2. The second node N2 may be a contact point of the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 may be a contact point of the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light emitting element LE.

[0110] Each of the first transistor T1 to the sixth transistor T6 may be a metal oxide semiconductor field effect transistor (MOSFET). For example, each of the first transistor T1 to the sixth transistor T6 may be a P-type MOSFET (PMOS), but the present disclosure is not limited thereto. As another example, each of the first transistor T1 to the sixth transistor T6 may be an N-type MOSFET (NMOS). As another example, each of some of the first transistor T1 to the sixth transistor T6 may be a P-type MOSFET (PMOS), and each of the remaining other transistors may be an N-type MOSFET (NMOS).

[0111] Figure 7 The first sub-pixel SP1 is shown to include six transistors T1 to T6 and two capacitors C1 and C2, but the present disclosure is not limited thereto. For example, the number of transistors and the number of capacitors of the first sub-pixel SP1 are not limited to Figure 7 , and various modifications may be made as needed or desired.

[0112] In addition, the equivalent circuit diagram of the second sub-pixel SP2 and the equivalent circuit diagram of the third sub-pixel SP3 can be compared with the above reference. Figure 7 The described equivalent circuit diagram of the first sub-pixel SP1 is the same or substantially the same. Therefore, redundant descriptions of the equivalent circuit diagram of the second sub-pixel SP2 and the equivalent circuit diagram of the third sub-pixel SP3 may not be repeated.

[0113] Figure 8 is a diagram showing a layout of pixels of a display area according to an embodiment.

[0114] Reference Figure 8 Each of the plurality of pixels PX includes a first light emitting area EA1 as a light emitting area of ​​a corresponding first sub-pixel SP1, a second light emitting area EA2 as a light emitting area of ​​a corresponding second sub-pixel SP2, and a third light emitting area EA3 as a light emitting area of ​​a corresponding third sub-pixel SP3.

[0115] Each of the first, second, and third light emitting areas EA1, EA2, and EA3 may have a quadrilateral plane shape such as a rectangle, a square, or a rhombus.

[0116] In the odd-numbered row R_ODD in which some of the plurality of sub-pixels SP1 , SP2 , and SP3 are arranged, the first light emitting areas EA1 and the second light emitting areas EA2 may be alternately arranged along the first direction DR1 .

[0117] In the even-numbered rows R_EVEN in which some of the plurality of sub-pixels SP1, SP2, and SP3 are arranged, the third light-emitting regions EA3 may be arranged at appropriate intervals along the first direction DR1. The length of the third light-emitting regions EA3 in the first direction DR1 may be greater than the sum of the length of the first light-emitting regions EA1 in the first direction DR1 and the length of the second light-emitting regions EA2 in the first direction DR1. For example, in the example shown, the first direction DR1 may be a horizontal direction.

[0118] According to an embodiment, the display panel 410 (see Figure 4 ) may include a reference wiring 1010 extending in the first direction DR1 while surrounding the emission areas EA1, EA2, and EA3 (eg, around the periphery of the emission areas EA1, EA2, and EA3). The reference wiring 1010 is used to connect the intermediate layer IL (see FIG. 1 ) to the display panel 410 during the manufacturing process of the display panel 410. Fig. 9 ) is partially disconnected between the sub-pixels SP1, SP2 and SP3 that are arranged adjacent to each other. Figures 14 to 18 A method of disconnecting the intermediate layer IL using the reference wiring 1010 will be described in more detail. Hereinafter, the reference wiring may also be referred to as a "wiring," "heating wiring," "traversing wiring," or "dummy wiring."

[0119] According to an embodiment, a reference wiring (eg, wiring) 1010 may be included in the display area DAA (see Figure 5 ) and a second reference wiring (e.g., second wiring) 1012 having a second length in the display area DAA. In this case, the first length may be longer than the second length. Therefore, the resistance of the first reference wiring 1011 in the display area DAA may be greater than the resistance of the second reference wiring 1012 because the length of the first reference wiring 1011 may be longer than the length of the second reference wiring 1012.

[0120] The first reference wiring 1011 may be arranged to extend in the first direction DR1 while surrounding the first and second light emitting areas EA1 and EA2 (e.g., around the peripheries of the first and second light emitting areas EA1 and EA2). The second reference wiring 1012 may be arranged to extend in the first direction DR1 while surrounding the third light emitting area EA3 (e.g., around the periphery of the third light emitting area EA3). Since the length of one third light emitting area EA3 in the first direction DR1 may be substantially the same as the sum of the length of the first light emitting area EA1 in the first direction DR1 and the length of the second light emitting area EA2 in the first direction DR1, the first reference wiring 1011 may be longer than the second reference wiring 1012.

[0121] In more detail, the first reference wiring 1011 may include a first portion 811 disposed between the first light emitting area EA1 and the third light emitting area EA3, a second portion 812 extending from the first portion 811 and disposed between the first light emitting area EA1 and the second light emitting area EA2, and a third portion 813 extending from the second portion 812 and disposed between the second light emitting area EA2 and the third light emitting area EA3. The second reference wiring 1012 may include a fourth portion 814 disposed between the third light emitting area EA3 and the first and second light emitting areas EA1 and EA2, and a fifth portion 815 disposed between the third light emitting areas EA3 disposed adjacent to each other.

[0122] The length deviation or variation between the first reference wiring 1011 and the second reference wiring 1012 may be a cause of the resistance deviation or variation between the first reference wiring 1011 and the second reference wiring 1012. The resistance deviation or variation between the first reference wiring 1011 and the second reference wiring 1012 may cause the width and height of the disconnected portion of the intermediate layer IL (e.g., where the intermediate layer IL is disconnected) to be uneven.

[0123] According to an embodiment of the present disclosure, a metal pattern wiring (eg, pattern wiring) connected to a reference wiring (eg, see Fig.10 1040) and the length deviation compensation section (see, for example, Fig.13 The metal pattern wiring 1040 and the length deviation compensation portion 1111 may be arranged in the non-display area to compensate for the length deviation or change between the first reference wiring 1011 and the second reference wiring 1012 in the display area. For example, when the resistance deviation or change between the first reference wiring 1011 and the second reference wiring 1012 occurs in the display area DAA, since the metal pattern wiring 1040 and the length deviation compensation portion 1111 may be arranged in the non-display area NDA (see Figure 5 ) to compensate for resistance deviation or variation, so from each reference wiring 1010 to the power supply pad (for example, see Fig.10 The total length and total resistance of 1030) can be made uniform or substantially uniform. Fig.10 The metal pattern wiring 1040 will be described in more detail. Fig.12 and Fig.13 The length deviation compensating portion 1111 will be described in more detail. Hereinafter, the metal pattern wiring may be referred to as "pattern wiring", "compensation wiring" or "extension wiring".

[0124] Figure 8It is shown that each of the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 has a quadrilateral plane shape, but the present disclosure is not limited thereto. For example, each of the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3 may have a polygonal plane shape other than a quadrilateral shape, a circular plane shape, or an elliptical plane shape.

[0125] The first light emitting area EA1 may emit light of a first color, the second light emitting area EA2 may emit light of a second color, and the third light emitting area EA3 may emit light of a third color. For example, the first color light may be light in a red wavelength band, the second color light may be light in a green wavelength band, and the third color light may be light in a blue wavelength band.

[0126] Figure 8 It is shown that each of the plurality of pixels PX includes three light emitting areas EA1, EA2, and EA3, but the present disclosure is not limited thereto. In other words, in some embodiments, each of the plurality of pixels PX may include four light emitting areas.

[0127] In addition, the arrangement of the light emitting regions of the plurality of pixels PX is not limited to Figure 8 For example, the light emitting regions of the plurality of pixels PX may be arranged in a stripe structure in which the light emitting regions are arranged along the first direction DR1, an RGBG structure in which the light emitting regions have a diamond arrangement (eg, structure, is an officially registered trademark of Samsung Display Co., Ltd.), or a hexagonal structure in which a plurality of light-emitting areas having a hexagonal planar shape are arranged.

[0128] Fig. 9 is a cross-sectional view illustrating an example in which a portion of a display panel is cut according to an embodiment.

[0129] Reference Fig. 9 , display panel 410 (see Figure 4 ) includes a semiconductor backplane SBP, a light emitting element backplane EBP, a light emitting element layer EML, an encapsulation layer TFE, an optical layer OPL, a cover layer CVL and a polarizing plate.

[0130] The semiconductor backplane SBP includes: a semiconductor substrate SSUB including a plurality of pixel transistors PTR, a plurality of semiconductor insulating films covering the plurality of pixel transistors PTR, and a plurality of contact terminals CTE electrically connected to the plurality of pixel transistors PTR. The plurality of pixel transistors PTR may be Figure 7 The first transistor T1 to the sixth transistor T6 are described.

[0131] The semiconductor substrate SSUB may be a silicon substrate, a germanium substrate, or a silicon germanium substrate. The semiconductor substrate SSUB may be a substrate doped with a first type of impurity. A plurality of well regions WA may be arranged at (e.g., in or on) the upper surface of the semiconductor substrate SSUB. The plurality of well regions WA may be regions doped with a second type of impurity. The second type of impurity may be different from the first type of impurity described above. For example, when the first type of impurity is a p-type impurity, the second type of impurity may be an n-type impurity. As another example, when the first type of impurity is an n-type impurity, the second type of impurity may be a p-type impurity.

[0132] Each of the plurality of well regions WA includes a source region SA corresponding to a source electrode of the pixel transistor PTR, a drain region DA corresponding to a drain electrode of the pixel transistor PTR, and a channel region CH disposed between the source region SA and the drain region DA.

[0133] Each of the source region SA and the drain region DA may be a region doped with first type impurities. The gate electrode GE of the pixel transistor PTR may overlap the well region WA in the third direction DR3. The channel region CH may overlap the gate electrode GE in the third direction DR3. The source region SA may be arranged on one side of the gate electrode GE, and the drain region DA may be arranged on the other side (e.g., the opposite side) of the gate electrode GE.

[0134] Each of the plurality of well regions WA further includes a first low-concentration impurity region disposed between the channel region CH and the source region SA and a second low-concentration impurity region disposed between the channel region CH and the drain region DA. The first low-concentration impurity region may be a region having an impurity concentration lower than that of the source region SA. The second low-concentration impurity region may be a region having an impurity concentration lower than that of the drain region DA. The distance between the source region SA and the drain region DA may be increased by the first low-concentration impurity region and the second low-concentration impurity region. Therefore, since the length of the channel region CH of each of the pixel transistors PTR may be increased, a punch-through phenomenon and a hot carrier phenomenon that may be caused by a shorter channel may be prevented or substantially prevented.

[0135] A first semiconductor insulating film SINS1 may be disposed on the semiconductor substrate SSUB. The first semiconductor insulating film SINS1 may be formed of silicon carbon nitride (SiCN) or silicon oxide (SiO x )-based inorganic film, but the present disclosure is not limited thereto.

[0136] A second semiconductor insulating film SINS2 may be disposed on the first semiconductor insulating film SINS1. The second semiconductor insulating film SINS2 may be formed of silicon oxide (SiO x )-based inorganic film, but the present disclosure is not limited thereto.

[0137] A plurality of contact terminals CTE may be arranged on the second semiconductor insulating film SINS2. Each of the plurality of contact terminals CTE may be connected to one of the gate electrode GE, the source region SA, and the drain region DA of each of the plurality of pixel transistors PTR through a corresponding hole penetrating the first semiconductor insulating film SINS1 and the second semiconductor insulating film SINS2. The plurality of contact terminals CTE may be formed of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or a suitable alloy including at least one of them.

[0138] A third semiconductor insulating film SINS3 may be arranged on a side surface of each of the plurality of contact terminals CTE. An upper surface of each of the plurality of contact terminals CTE may be exposed without being covered by the third semiconductor insulating film SINS3. The third semiconductor insulating film SINS3 may be formed of silicon oxide (SiO x )-based inorganic film, but the present disclosure is not limited thereto.

[0139] The semiconductor substrate SSUB may be replaced with a glass substrate or a polymer resin substrate such as polyimide. In this case, the thin film transistor may be arranged on the glass substrate or the polymer resin substrate. The glass substrate may be a rigid substrate that is not bent, and the polymer resin substrate may be a flexible substrate that can be bent or folded.

[0140] The light emitting element backplane EBP includes first to eighth metal layers ML1 to ML8, reflective metal layers RL1 to RL4, a plurality of through holes VA1 to VA10, and a step layer STPL. In addition, the light emitting element backplane EBP includes a plurality of interlayer insulating films INS1 to INS10 arranged between the semiconductor backplane SBP, the first to eighth metal layers ML1 to ML8, the reflective electrodes RL1 to RL4, and the light emitting element layer EML.

[0141] The first metal layer ML1 to the eighth metal layer ML8 are used to realize the Figure 7 . In other words, the first to sixth transistors T1 to T6 are formed only at (e.g., in or on) the semiconductor backplane SBP, and the first to sixth transistors T1 to T6 and the first capacitor C1 and the second capacitor C2 are connected through the first to eighth metal layers ML1 to ML8. In addition, the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5, and the first electrode of the light emitting element LE are also connected through the first to eighth metal layers ML1 to ML8.

[0142] The first interlayer insulating film INS1 may be disposed on the semiconductor backplane SBP. Each of the first vias VA1 may penetrate the first interlayer insulating film INS1 and be connected to a corresponding contact terminal CTE exposed from the semiconductor backplane SBP. Each of the first metal layers ML1 may be disposed on the first interlayer insulating film INS1 and may be connected to a corresponding first via VA1.

[0143] The second interlayer insulating film INS2 may be disposed on the first interlayer insulating film INS1 and the first metal layer ML1. Each of the second vias VA2 may be connected to the exposed corresponding first metal layer ML1 by penetrating the second interlayer insulating film INS2. Each of the second metal layers ML2 may be disposed on the second interlayer insulating film INS2 and may be connected to the corresponding second via VA2.

[0144] The third interlayer insulating film INS3 may be disposed on the second interlayer insulating film INS2 and the second metal layer ML2. Each of the third vias VA3 may be connected to the exposed corresponding second metal layer ML2 by penetrating the third interlayer insulating film INS3. Each of the third metal layers ML3 may be disposed on the third interlayer insulating film INS3 and may be connected to the corresponding third via VA3.

[0145] The fourth interlayer insulating film INS4 may be disposed on the third interlayer insulating film INS3 and the third metal layer ML3. Each of the fourth vias VA4 may be connected to the exposed corresponding third metal layer ML3 by penetrating the fourth interlayer insulating film INS4. Each of the fourth metal layers ML4 may be disposed on the fourth interlayer insulating film INS4 and may be connected to the corresponding fourth via VA4.

[0146] The fifth interlayer insulating film INS5 may be disposed on the fourth interlayer insulating film INS4 and the fourth metal layer ML4. Each of the fifth vias VA5 may be connected to the exposed corresponding fourth metal layer ML4 by penetrating the fifth interlayer insulating film INS5. Each of the fifth metal layers ML5 may be disposed on the fifth interlayer insulating film INS5 and may be connected to the corresponding fifth via VA5.

[0147] The sixth interlayer insulating film INS6 may be disposed on the fifth interlayer insulating film INS5 and the fifth metal layer ML5. Each of the sixth vias VA6 may be connected to the exposed corresponding fifth metal layer ML5 by penetrating the sixth interlayer insulating film INS6. Each of the sixth metal layers ML6 may be disposed on the sixth interlayer insulating film INS6 and may be connected to the corresponding sixth via VA6.

[0148] The seventh interlayer insulating film INS7 may be disposed on the sixth interlayer insulating film INS6 and the sixth metal layer ML6. Each of the seventh vias VA7 may be connected to the exposed corresponding sixth metal layer ML6 by penetrating the seventh interlayer insulating film INS7. Each of the seventh metal layers ML7 may be disposed on the seventh interlayer insulating film INS7 and may be connected to the corresponding seventh via VA7.

[0149] The eighth interlayer insulating film INS8 may be disposed on the seventh interlayer insulating film INS7 and the seventh metal layer ML7. Each of the eighth vias VA8 may be connected to the exposed corresponding seventh metal layer ML7 by penetrating the eighth interlayer insulating film INS8. Each of the eighth metal layers ML8 may be disposed on the eighth interlayer insulating film INS8 and may be connected to the corresponding eighth via VA8.

[0150] The first metal layer ML1 to the eighth metal layer ML8 and the first through hole VA1 to the eighth through hole VA8 may be formed of the same or substantially the same material as each other. The first metal layer ML1 to the eighth metal layer ML8 and the first through hole VA1 to the eighth through hole VA8 may be formed of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and neodymium (Nd) or a suitable alloy including at least one of them. The first through hole VA1 to the eighth through hole VA8 may be formed of the same or substantially the same material as each other. The first interlayer insulating film INS1 to the eighth interlayer insulating film INS8 may be formed of silicon oxide (SiO x )-based inorganic film, but the present disclosure is not limited thereto.

[0151] The thickness of the first metal layer ML1, the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be respectively greater than the thickness of the first through hole VA1, the thickness of the second through hole VA2, the thickness of the third through hole VA3, the thickness of the fourth through hole VA4, the thickness of the fifth through hole VA5, and the thickness of the sixth through hole VA6. Each of the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be greater than the thickness of the first metal layer ML1. The thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be the same or substantially the same as each other. For example, the thickness of the first metal layer ML1 may be about Each of the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be about 100 Å. And each of the thickness of the first through hole VA1, the thickness of the second through hole VA2, the thickness of the third through hole VA3, the thickness of the fourth through hole VA4, the thickness of the fifth through hole VA5, and the thickness of the sixth through hole VA6 may be

[0152] Each of the thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be greater than each of the thickness of the first metal layer ML1, the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6. Each of the thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be greater than each of the thickness of the seventh through hole VA7 and the thickness of the eighth through hole VA8. Each of the thickness of the seventh through hole VA7 and the thickness of the eighth through hole VA8 may be greater than each of the thickness of the first through hole VA1, the thickness of the second through hole VA2, the thickness of the third through hole VA3, the thickness of the fourth through hole VA4, the thickness of the fifth through hole VA5, and the thickness of the sixth through hole VA6. The thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be the same or substantially the same as each other. For example, each of the thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be about Each of the thickness of the seventh through hole VA7 and the thickness of the eighth through hole VA8 may be about 100 Å.

[0153] The ninth interlayer insulating film INS9 may be disposed on the eighth interlayer insulating film INS8 and the eighth metal layer ML8. The ninth interlayer insulating film INS9 may be formed of silicon oxide (SiO x )-based inorganic film, but the present disclosure is not limited thereto.

[0154] Each of the ninth through holes VA9 may be connected to the corresponding exposed eighth metal layer ML8 by penetrating the ninth interlayer insulating film INS9. The ninth through hole VA9 may be formed of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or a suitable alloy including at least one of them. The thickness of the ninth through hole VA9 may be about

[0155] Each of the first reflective electrodes RL1 may be disposed on the ninth interlayer insulating film INS9 and may be connected to the corresponding ninth via VA9. The first reflective electrode RL1 may be formed of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or a suitable alloy including at least one of them.

[0156] Each of the second reflective electrodes RL2 may be disposed on the corresponding first reflective electrode RL1. The second reflective electrode RL2 may be formed of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or a suitable alloy including at least one of them. For example, the second reflective electrode RL2 may be formed of titanium nitride (TiN).

[0157] In the first sub-pixel SP1, the step layer STPL may be arranged on the second reflective electrode RL2. The step layer STPL may not be arranged in each of the second sub-pixel SP2 and the third sub-pixel SP3. The thickness of the step layer STPL may be determined (e.g., may be set) in consideration of the wavelength of the light of the first color and the distance from the first light emitting layer to the corresponding fourth reflective electrode RL4, so that the light of the first color emitted from the first light emitting layer of the first sub-pixel SP1 may be reflected. The step layer STPL may be made of silicon carbon nitride (SiCN) or silicon oxide (SiO x )-based inorganic film is formed, but the present disclosure is not limited thereto. The thickness of the step layer STPL may be about

[0158] In the first subpixel SP1, the third reflective electrode RL3 may be disposed on the second reflective electrode RL2 and the step layer STPL. In the second subpixel SP2 and the third subpixel SP3, the third reflective electrode RL3 may be disposed on the second reflective electrode RL2. The third reflective electrode RL3 may be formed of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or a suitable alloy including at least one of them.

[0159] As needed or desired, at least one of the first reflective electrode RL1, the second reflective electrode RL2, and the third reflective electrode RL3 may be omitted.

[0160] Each of the fourth reflective electrodes RL4 may be arranged on the corresponding third reflective electrode RL3. The fourth reflective electrode RL4 may be a layer that reflects light from the first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3. The fourth reflective electrode RL4 may include a suitable metal with high reflectivity for reflecting light. The fourth reflective electrode RL4 may be formed of aluminum (Al); a stacked structure of aluminum and titanium (Ti / Al / Ti); a stacked structure of aluminum and ITO (ITO / Al / ITO); an APC alloy that is an alloy of silver (Ag), palladium (Pd), and copper (Cu); and / or a stacked structure of an APC alloy and ITO (ITO / APC / ITO), but the present disclosure is not limited thereto. The thickness of each of the fourth reflective electrodes RL4 may be about 100 Å.

[0161] The tenth interlayer insulating film INS10 may be disposed on the ninth interlayer insulating film INS9 and the fourth reflective electrode RL4. The tenth interlayer insulating film INS10 may be formed of silicon oxide (SiO x )-based inorganic film, but the present disclosure is not limited thereto.

[0162] Each of the tenth through holes VA10 may be connected to the exposed corresponding ninth metal layer ML9 by penetrating the tenth interlayer insulating film INS10. The tenth through hole VA10 may be formed of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or a suitable alloy including at least one of them. Due to the step layer STPL, the thickness of the tenth through hole VA10 in the first sub-pixel SP1 may be less than the thickness of the tenth through hole VA10 in each of the second sub-pixel SP2 and the third sub-pixel SP3. For example, the thickness of the tenth through hole VA10 in the first sub-pixel SP1 may be about And the thickness of the tenth through hole VA10 in each of the second sub-pixel SP2 and the third sub-pixel SP3 may be about 100 mm.

[0163] The light emitting element layer EML may be disposed on the light emitting element backplane EBP. The light emitting element layer EML may include a plurality of light emitting elements LE (see Figure 7 ) and a pixel defining layer PDL, each of the light emitting elements LE includes a first electrode AND, an intermediate layer IL and a second electrode CAT.

[0164] The first electrode AND of each of the light emitting elements LE may be arranged on the tenth interlayer insulating film INS10 and may be connected to the corresponding tenth through hole VA10. The first electrode AND of each of the light emitting elements LE may be connected to the drain area DA or the source area SA of the corresponding pixel transistor PTR through the corresponding tenth through hole VA10, the corresponding first to fourth reflective electrodes RL1 to RL4, the corresponding first to ninth through holes VA1 to VA9, the corresponding first to eighth metal layers ML1 to ML8, and the corresponding contact terminal CTE. The first electrode AND of each of the light emitting elements LE may be formed of one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or a suitable alloy including at least one of them. For example, the first electrode AND of each of the light emitting elements LE may be formed of titanium nitride (TiN).

[0165] The pixel defining layer PDL may be disposed on a partial area of ​​the first electrode AND of each of the light emitting elements LE. The pixel defining layer PDL may cover an edge of the first electrode AND of each of the light emitting elements LE. The pixel defining layer PDL is used to divide the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3.

[0166] The first light emitting area EA1 may be defined as an area where the first electrode AND, the intermediate layer IL, and the second electrode CAT are sequentially stacked with each other in the first sub-pixel SP1 to emit light. The second light emitting area EA2 may be defined as an area where the first electrode AND, the intermediate layer IL, and the second electrode CAT are sequentially stacked with each other in the second sub-pixel SP2 to emit light. The third light emitting area EA3 may be defined as an area where the first electrode AND, the intermediate layer IL, and the second electrode CAT are sequentially stacked with each other in the third sub-pixel SP3 to emit light.

[0167] The pixel defining layer PDL may include a first pixel defining layer PDL1, a second pixel defining layer PDL2, and a third pixel defining layer PDL3. The first pixel defining layer PDL1 may be arranged on the edge of the first electrode AND of each of the light emitting elements LE. The second pixel defining layer PDL2 may be arranged on the first pixel defining layer PDL1. The third pixel defining layer PDL3 may be arranged on the second pixel defining layer PDL2. The first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may be formed of silicon oxide (SiO x )-based inorganic film, but the present disclosure is not limited thereto. Each of the thickness of the first pixel defining layer PDL1, the thickness of the second pixel defining layer PDL2, and the thickness of the third pixel defining layer PDL3 may be about

[0168] The intermediate layer IL may include a first intermediate layer IL1 , a second intermediate layer IL2 , and a third intermediate layer IL3 .

[0169] The intermediate layer IL may have a series structure including a plurality of intermediate layers IL1, IL2, and IL3 for emitting light different from each other. For example, the intermediate layer IL may include a first intermediate layer IL1 for emitting light of a first color, a second intermediate layer IL2 for emitting light of a third color, and a third intermediate layer IL3 for emitting light of a second color. The first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 may be sequentially stacked on each other.

[0170] The charge generation layer may be disposed between the first intermediate layer IL1 and the second intermediate layer IL2. In addition, the charge generation layer may be disposed between the second intermediate layer IL2 and the third intermediate layer IL3. The charge generation layer may include a negative charge generation layer and a positive charge generation layer.

[0171] The first intermediate layer IL1 may have a structure in which a first hole transport layer, a first organic light emitting layer for emitting light of a first color, and a first electron transport layer are sequentially stacked on each other. The second intermediate layer IL2 may have a structure in which a second hole transport layer, a second organic light emitting layer for emitting light of a third color, and a second electron transport layer are sequentially stacked on each other. The third intermediate layer IL3 may have a structure in which a third hole transport layer, a third organic light emitting layer for emitting light of a second color, and a third electron transport layer are sequentially stacked on each other.

[0172] The intermediate layer IL covers the first electrode AND located at the opening of the pixel defining layer PDL, and covers the pixel defining layer PDL located between the sub-pixels SP1, SP2, and SP3 arranged adjacent to each other. Part of the intermediate layer IL may be disconnected. The disconnected part of the intermediate layer IL may be, for example, a charge generation layer arranged between the first intermediate layer IL1 and the second intermediate layer IL2, and a part of the intermediate layer IL arranged below the charge generation layer. In addition, the disconnected part of the intermediate layer IL may be, for example, a charge generation layer arranged between the second intermediate layer IL2 and the third intermediate layer IL3, and a part of the intermediate layer IL arranged below the charge generation layer. However, the disconnected part of the intermediate layer IL is not limited to the above example, and the intermediate layer IL may be disconnected in a part of a layer arranged on the charge generation layer.

[0173] In an embodiment, during a process of manufacturing a display panel, the intermediate layer IL may be disconnected between mutually adjacent sub-pixels SP1, SP2, and SP3 using a reference wiring. According to such an embodiment, leakage current between mutually adjacent sub-pixels SP1, SP2, and SP3 may be prevented or substantially prevented, and color crosstalk may be prevented or substantially prevented. Color crosstalk refers to, for example, a phenomenon in which a red sub-pixel adjacent to a blue sub-pixel is accidentally turned on while the blue sub-pixel emits blue light. Color crosstalk may occur due to leakage current, and may occur when a blue sub-pixel and a red sub-pixel having a large difference in voltage for driving the pixel are adjacent to each other. For example, leakage current may be a phenomenon in which a portion of a driving current is transmitted to a red sub-pixel through at least a portion of a conductive layer of the intermediate layer IL, while a driving current is supplied to a light-emitting element LE of the blue sub-pixel to turn on the blue sub-pixel. When leakage current occurs, the red sub-pixel may be accidentally turned on while the blue sub-pixel is turned on.

[0174] The number of the intermediate layers IL1, IL2, and IL3 for emitting light of different colors from each other is not limited to Fig. 9For example, the intermediate layer IL may include two intermediate layers. In this case, one of the two intermediate layers may be the same as or substantially the same as the first intermediate layer IL1, and the other of them may include a second hole transport layer, a second organic light emitting layer, a third organic light emitting layer, and a second electron transport layer. In this case, a charge generation layer for supplying electrons to one intermediate layer and holes to the other intermediate layer may be arranged between the two intermediate layers.

[0175] also, Fig. 9 It is shown that the first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 are all arranged in each of the first light emitting area EA1, the second light emitting area EA2, and the third light emitting area EA3, but the present disclosure is not limited thereto. For example, the first intermediate layer IL1 may be arranged in the first light emitting area EA1, and may not be arranged in the second light emitting area EA2 and the third light emitting area EA3. In addition, the second intermediate layer IL2 may be arranged in the second light emitting area EA2, and may not be arranged in the first light emitting area EA1 and the third light emitting area EA3. In addition, the third intermediate layer IL3 may be arranged in the third light emitting area EA3, and may not be arranged in the first light emitting area EA1 and the second light emitting area EA2. In this case, the first color filter CF1, the second color filter CF2, and the third color filter CF3 of the optical layer OPL described in more detail below may be omitted.

[0176] The second electrode CAT may be arranged on the third intermediate layer IL3. The second electrode CAT may be arranged on the third intermediate layer IL3 in each of the plurality of grooves. The second electrode CAT may be formed of a transparent conductive material (TCO) such as ITO or IZO capable of transmitting light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag). When the second electrode CAT is formed of a semi-transmissive conductive material, the light emission efficiency in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be improved through the microcavity.

[0177] The encapsulation layer TFE may be arranged on the light emitting element layer EML. The encapsulation layer TFE may include one or more inorganic films TFE1 and TFE3 to prevent or substantially prevent oxygen and / or moisture from penetrating into the light emitting element layer EML. In addition, the encapsulation layer TFE may include at least one organic film TFE2 to protect the light emitting element layer EML from foreign matter such as dust. For example, the encapsulation layer TFE may include a first encapsulation inorganic film TFE1, an encapsulation organic film TFE2, and a second encapsulation inorganic film TFE3.

[0178] The first encapsulating inorganic film TFE1 may be disposed on the second electrode CAT. The encapsulating organic film TFE2 may be disposed on the first encapsulating inorganic film TFE1, and the second encapsulating inorganic film TFE3 may be disposed on the encapsulating organic film TFE2. The first encapsulating inorganic film TFE1 and the second encapsulating inorganic film TFE3 may be formed in which silicon nitride (SiN x ) layer, silicon oxynitride (SiON) layer, silicon oxide (SiO x ) layer, titanium oxide (TiO x ) layer and aluminum oxide (AlO x ) layers. The encapsulating organic film TFE2 may be a monomer. As another example, the encapsulating organic film TFE2 may be an organic film including (eg, made of) acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0179] The adhesive layer ADL may be a layer for bonding the encapsulation layer TFE and the optical layer OPL to each other. The adhesive layer ADL may be a double-sided adhesive member. In addition, the adhesive layer ADL may be a transparent adhesive member such as a transparent adhesive or a transparent adhesive resin.

[0180] The optical layer OPL includes a plurality of color filters CF1, CF2, and CF3, a plurality of lenses LNS, and a filling layer FIL. The plurality of color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. The first color filter CF1, the second color filter CF2, and the third color filter CF3 may be arranged on the adhesive layer ADL.

[0181] The first color filter CF1 may overlap the first emission area EA1 of the first subpixel SP1. The first color filter CF1 may transmit light of the first color, or in other words, transmit light in a blue wavelength band. The blue wavelength band may be about 370nm to 460nm. Therefore, the first color filter CF1 may transmit light of the first color among the light emitted from the first emission area EA1.

[0182] The second color filter CF2 may overlap with the second emission area EA2 of the second sub-pixel SP2. The second color filter CF2 may transmit light of the second color, or in other words, transmit light in a green wavelength band. The green wavelength band may be about 480nm to 560nm. Therefore, the second color filter CF2 may transmit light of the second color among the light emitted from the second emission area EA2.

[0183] The third color filter CF3 may overlap with the third light emitting area EA3 of the third sub-pixel SP3. The third color filter CF3 may transmit light of a third color, or in other words, transmit light in a red wavelength band. The red wavelength band may be about 600nm to 750nm. Therefore, the third color filter CF3 may transmit light of a third color among the light emitted from the third light emitting area EA3.

[0184] Each of the plurality of lenses LNS may be disposed on a corresponding one of the first color filter CF1, the second color filter CF2, and the third color filter CF3. Each of the plurality of lenses LNS may be used to increase the pointing display device 10 (see Figure 4 Each of the plurality of lenses LNS may have a cross-sectional shape convex in an upward direction.

[0185] The filling layer FIL may be arranged on the plurality of lenses LNS. The filling layer FIL may have a suitable refractive index (e.g., a predetermined refractive index) so that light travels in the third direction DR3 at the interface between the plurality of lenses LNS and the filling layer FIL. In addition, the filling layer FIL may be a planarization layer. The filling layer FIL may be an organic film including (e.g., made of) acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0186] The cover layer CVL may be arranged on the filling layer FIL. The cover layer CVL may be a glass substrate or a polymer resin. When the cover layer CVL is a glass substrate, the cover layer CVL may be attached to the filling layer FIL. In this case, the filling layer FIL may be used for bonding to the cover layer CVL. When the cover layer CVL is a glass substrate, the cover layer CVL may be used as a packaging substrate. When the cover layer CVL is a polymer resin, the cover layer CVL may be directly applied to the filling layer FIL.

[0187] The polarizing plate may be arranged on one surface of the cover layer CVL. The polarizing plate may be a structure for preventing or substantially preventing degradation of visibility due to reflection of external light. The polarizing plate may include a linear polarizing plate and a phase retardation film. For example, the phase retardation film may be a λ / 4 (quarter wavelength) wave plate, but the present disclosure is not limited thereto. However, when degradation of visibility due to reflection of external light is sufficiently improved by the first color filter CF1, the second color filter CF2, and the third color filter CF3, the polarizing plate may be omitted.

[0188] Fig.10 is a plan view showing the arrangement of first electrodes of sub-pixels according to an embodiment.

[0189] Reference Fig.10 , a plurality of sub-pixels SP1, SP2 and SP3 (see Fig. 9) may have a hexagonal shape in a plan view. For example, each of the first electrodes AND may have a hexagonal shape and be arranged at appropriate intervals along the first direction DR1.

[0190] The display panel 410 may include a reference wiring 1010 including a first reference wiring 1011 and a second reference wiring 1012. The first reference wiring 1011 may extend in a first direction DR1 while crossing between the first electrodes AND and may have a first length in the display area DAA. The second reference wiring 1012 may have a second length in the display area DAA.

[0191] The first reference wiring 1011 may be arranged to cross between the first electrode AND of the 2n-1th row R_2n-1 and the first electrode AND of the 2nth row R_2n in the first direction DR1, where n is a natural number greater than 0. For example, the first reference wiring 1011 may be an odd-numbered wiring among the reference wirings 1010 .

[0192] The second reference wiring 1012 may be arranged to cross between the first electrode AND of the 2nth row R_2n and the first electrode AND of the 2n+1th row R_2n+1 in the first direction DR1 . For example, the second reference wiring 1012 may be an even-numbered wiring among the reference wirings 1010 .

[0193] According to an embodiment, each of the first electrodes AND has a hexagonal shape and may include a protrusion AND_P protruding in the direction of the first reference wiring 1011. The protrusion AND_P of the first electrode AND may be a portion in which a connection to the light emitting element back plate EBP (see Fig. 9 ) of the contact hole.

[0194] Since the first reference wiring 1011 may be arranged to cross between the first electrode AND of the 2n-1th row R_2n-1 and the first electrode AND of the 2nth row R_2n in the first direction DR1, the first electrodes AND of the odd-numbered rows R_2n-1 and R_2n+1 may have protrusions AND_P formed in the second direction DR2 perpendicular or substantially perpendicular to the first direction DR1, and the first electrodes AND of the even-numbered rows R_2n may have protrusions AND_P formed in the fourth direction DR4 opposite to the second direction DR2. Since the first reference wiring 1011 extends in the first direction DR1 while crossing between the protrusions AND_P, the length of the first reference wiring 1011 may be longer than that of the second reference wiring 1012.

[0195] According to an embodiment, a metal pattern wiring 1040 connecting the reference wiring 1010 and the power supply pad 1030 to each other is arranged in the non-display area NDA. The metal pattern wiring 1040 may be used to convert the Joule heating voltage V applied to the power supply pad 1030 to Heat or Joule heating current I Heat The metal pattern wiring 1040 may include a first metal pattern wiring (eg, a third wiring) 1041 connected to the first reference wiring 1011 and a second metal pattern wiring (eg, a fourth wiring) 1042 connected to the second reference wiring 1012 .

[0196] The first metal pattern wiring 1041 may extend to have a straight line or a substantially straight line in a plan view.

[0197] Since at least a portion of the second metal pattern wiring 1042 may have a zigzag shape in a plan view, the length of the second metal pattern wiring 1042 may be longer than the length of the first metal pattern wiring 1041. For example, the first metal pattern wiring 1041 may have a third length, and the second metal pattern wiring 1042 may have a fourth length longer than the third length. Since at least a portion of the second metal pattern wiring 1042 may be arranged in a zigzag shape in a plan view, the second metal pattern wiring 1042 may have a fourth length longer than the third length.

[0198] However, the shape of the portion of the second metal pattern wiring 1042 having a zigzag shape in a plan view is provided as an example, and the shape of the second metal pattern wiring 1042 may be variously modified as needed or desired. For example, at least a portion of the second metal pattern wiring 1042 may be arranged to have a specific pattern in a plan view, and the specific pattern may be variously modified to various suitable shapes as needed or desired. In other words, the zigzag shape of the second metal pattern wiring 1042 is provided only as an example of a specific pattern, and the present disclosure is not limited thereto.

[0199] A first total length obtained by adding the first length of the first reference wiring 1011 and the third length of the first metal pattern wiring 1041 to each other may be equal to or substantially equal to a second total length obtained by adding the second length of the second reference wiring 1012 and the fourth length of the second metal pattern wiring 1042 to each other. Therefore, a resistance deviation or change between the first reference wiring 1011 and the second reference wiring 1012 that may occur in the display area DAA may be compensated.

[0200] According to an embodiment, one end of the reference wiring 1010 may be connected to the power pad 1030 through the metal pattern wiring 1040, and the other end (e.g., the opposite end) of the reference wiring 1010 may be connected to the ground pad 1050 through the ground wiring 1060. For example, the power pad 1030 may be arranged at one end of the non-display area NDA, and the ground pad 1050 may be arranged at the other end of the non-display area NDA. Like the metal pattern wiring 1040, the ground wiring 1060 may be arranged in a zigzag shape to compensate for the resistance deviation or change between the first reference wiring 1011 and the second reference wiring 1012. In more detail, the power pad 1030 may be arranged at one end of the non-display area NDA adjacent to one end of the reference wiring 1010. The other end of the non-display area NDA adjacent to the other end of the reference wiring 1010 may include a first ground wiring 1061 and a second ground wiring 1062 connecting the ground pad 1050 and the reference wiring 1010 to each other.

[0201] The first ground wiring 1061 may be connected to the first reference wiring 1011 and may extend in a straight line or substantially in a straight line. The second ground wiring 1062 may be connected to the second reference wiring 1012 and may extend in a zigzag shape. Unlike the first ground wiring 1061, since the second ground wiring 1062 may be arranged in a zigzag shape, its resistance may be relatively high. The resistance deviation or change between the first ground wiring 1061 and the second ground wiring 1062 may be designed to compensate for the resistance deviation or change between the first reference wiring 1011 and the second reference wiring 1012.

[0202] Fig.11 is a cross-sectional view schematically showing connection between a reference wiring and a pad portion of a display panel according to an embodiment.

[0203] Reference Fig.11 , the reference wiring 1010 arranged in the display area DAA may be electrically connected to the power supply pad 1030 through the metal pattern wiring 1040 and the fan-out wiring 1110 arranged in the non-display area NDA. As in the example shown, the metal pattern wiring 1040 and the fan-out wiring 1110 may be arranged at the same layer as the layer of the reference wiring 1010 (e.g., in the middle or on), and the distal end of the fan-out wiring 1110 may be connected to the pad electrode 1031 of the power supply pad 1030 through the contact hole CT1030 penetrating a portion of the display panel 410. For example, the pad electrode 1031 of the power supply pad 1030 may be arranged at the first metal layer ML1 to the eighth metal layer ML8 (see Fig. 9 ) is at the same layer as one of the layers (e.g., in the middle or above), but the present disclosure is not limited thereto.

[0204] Fig.11The reference symbol EBP shown in the figure may represent the above reference Fig. 9 Described light emitting element backplane EBP.

[0205] Fig.11 The reference symbol TFE shown in the figure may represent the above reference Fig. 9 The encapsulation layer TFE is described.

[0206] Fig.12 is a layout diagram showing a pad portion and a fan-out line (also referred to as a fan-out wiring) arranged in a non-display area of ​​a display panel according to an embodiment. Fig.13 It is shown Fig.12 An enlarged view of more details of the wiring between the power pad and the reference wiring is shown in FIG.

[0207] Reference Fig.12 and Fig.13 , a plurality of pads may be arranged on the outside of the display area DAA. The plurality of pads may include a power pad 1030, a pad connected to the second electrode CAT (see Fig. 9 ) common voltage pad 1210 and ground pad 1050. In some embodiments, in addition to power pad 1030, common voltage pad 1210 and ground pad 1050, the pad portion may further include a device for driving display panel 410 (see Figure 4 ) of multiple pads for signals and voltages.

[0208] According to an embodiment, the metal pattern wiring 1040 and the fan-out wiring 1110 connecting the reference wiring 1010 and the power supply pad 1030 may be arranged in the non-display area NDA of the display panel 410. For example, the Joule heating voltage V input to the power supply pad 1030 Heat (See Fig.10 ) may be supplied to the reference wiring 1010 arranged in the display area DAA via the fan-out wiring 1110 and the metal pattern wiring 1040 arranged in the non-display area NDA.

[0209] exist Fig.13 , a first region 1301 in which the metal pattern wiring 1040 is arranged and a second region 1302 in which the fan-out wiring 1110 is arranged are shown. Fig.10 As described above, the metal pattern wiring 1040 arranged in the first region 1301 may include a first metal pattern wiring 1041 arranged in a straight line or substantially a straight line and having a third length and a second metal pattern wiring 1042 arranged in a zigzag shape and having a fourth length.

[0210] Unlike the metal pattern wirings 1040 arranged to extend in the first direction DR1 or substantially in the first direction DR1, the fan-out wirings 1110 arranged in the second region 1302 may be arranged to converge toward the direction of the power supply pad 1030. For example, in order to connect to the metal pattern wirings 1040 arranged at appropriate intervals, the fan-out wirings 1110 connected from one power supply pad 1030 may extend in inclined directions at different angles, and their lengths may be designed to be different.

[0211] According to an embodiment, in order to compensate for the resistance deviation or change caused by the length deviation or change of the fan-out wiring 1110 having a differently increased or decreased length between the power supply pad 1030 and the metal pattern wiring 1040, the fan-out wiring 1110 may include a length deviation compensating portion 1111. For example, a plurality of fan-out wirings 1110 according to an embodiment may all have the same or substantially the same length as each other by including the length deviation compensating portion 1111. The length deviation compensating portion 1111 of each fan-out wiring 1110 may include a zigzag wiring of a suitable length (e.g., a specified or predetermined length) of different designs.

[0212] However, at least a portion of the length deviation compensating portion 1111 having a sawtooth shape in a plan view is provided only as an example, and the shape of the length deviation compensating portion 1111 may be variously modified as needed or desired. For example, at least a portion of the length deviation compensating portion 1111 may be arranged to have a specific pattern in a plan view, and the specific pattern may be variously modified to various suitable shapes. In other words, the sawtooth shape of the length deviation compensating portion 1111 is provided only as an example of a specific pattern, and the present disclosure is not limited thereto.

[0213] Fig.14 is a flowchart illustrating a method of manufacturing a display device according to an embodiment. Figures 15 to 18 The following are cross-sectional views showing respective processes of a method for manufacturing a display device.

[0214] In the following, reference will be made to Figures 14 to 18 The manufacturing method of the display panel 410 according to the embodiment is described in more detail (see Figure 4 ) method. Only a portion of the various processes for manufacturing the display panel 410 is described below, and additional processes for forming one or more of the above components may be performed before or after each process described in more detail below. In addition, various suitable processes for manufacturing the display panel 410 known to those of ordinary skill in the art may be additionally performed before or after each process described in more detail below.

[0215] Reference Fig.14 In block 1410, a driving element layer may be formed on a substrate SSUB. For example, the substrate SSUB may be Fig. 9 The semiconductor substrate SSUB described above. The driving element layer can be Fig. 9 The remaining parts of the semiconductor back plate SBP except the semiconductor substrate SSUB are described.

[0216] In block 1420, a wiring layer EBP may be formed on the driving element layer. For example, the wiring layer EBP may be Fig. 9 The wiring layer EBP may include the light emitting element backplane EBP described above. Fig. 9 The first to eighth metal layers ML1 to ML8 , the reflective metal layers RL1 to RL4 , the plurality of vias VA1 to VA10 , and the step layer STPL are described.

[0217] In block 1430, a first electrode AND of each sub-pixel SP1, SP2, and SP3 and a pixel defining layer PDL (see FIG. 1 ) dividing the sub-pixels SP1, SP2, and SP3 may be formed on the wiring layer EBP. Fig. 9 ). A portion of the first electrode AND may be exposed through the opening in the pixel defining layer PDL.

[0218] Reference Fig.14 and Fig.15 In block 1440, a reference wiring 1010 may be formed on a pixel definition layer PDL between sub-pixels SP1, SP2, and SP3 disposed adjacent to each other. As described above, the reference wiring 1010 may include a first reference wiring 1011 and a second reference wiring 1012 (see Fig.10 ).

[0219] Reference Fig.14 and Fig.16 , in block 1450, an intermediate layer IL may be deposited. The intermediate layer IL may be deposited on the opening of the pixel defining layer PDL and on the upper portion of the pixel defining layer PDL disposed between the sub-pixels SP1, SP2, and SP3 adjacent to each other using an open mask. Thus, the intermediate layer IL may cover a portion of the first electrode AND at the opening of the pixel defining layer PDL, and may also cover the reference wiring 1010 disposed on the pixel defining layer PDL.

[0220] Reference Fig.14 and Fig.17 In block 1460, at least a portion of the intermediate layer IL disposed between the adjacent sub-pixels SP1, SP2, and SP3 may be removed using the reference wiring 1010. For example, the Joule heating voltage V Heat (See Fig.10 ) is applied to the power supply pad 1030, and the applied Joule heating voltage V Heat The fan-out wiring 1110 and the metal pattern wiring 1040 (see Fig.12) is transmitted to the reference wiring 1010. The reference wiring 1010 can be heated by the input Joule heating voltage V Heat The reference wiring 1010 is heated to a high temperature of about 400° C. or higher. Due to the high temperature of the reference wiring 1010 , all or at least a portion of the intermediate layer IL deposited on the reference wiring 1010 may be removed.

[0221] The disconnected portion of the intermediate layer IL may be, for example, a portion disposed between the first intermediate layer IL1 and the second intermediate layer IL2 (see Fig. 9 ) between the charge generation layer and the portion of the intermediate layer IL arranged below the charge generation layer. In addition, the disconnected portion of the intermediate layer IL may be, for example, arranged between the second intermediate layer IL2 and the third intermediate layer IL3 (see Fig. 9 ) and a portion of the intermediate layer IL disposed below the charge generation layer. However, the disconnected portion of the intermediate layer IL is not limited to the above example, and the intermediate layer IL may be disconnected in a portion of a layer disposed on the charge generation layer.

[0222] Reference Fig.14 and Fig.18 , in block 1470, the second electrode CAT may be deposited. For example, the second electrode CAT may be deposited on the opening of the pixel defining layer PDL and on the upper portion of the pixel defining layer PDL arranged between the sub-pixels SP1, SP2, and SP3 adjacent to each other using an opening mask. Therefore, the second electrode CAT may cover the intermediate layer IL at each opening of the pixel defining layer PDL, and may cover the intermediate layer IL and the reference wiring 1010 arranged on the pixel defining layer PDL.

[0223] According to one or more embodiments of the present disclosure, in a display device and a mobile electronic device including the display device, leakage current and color crosstalk can be prevented or substantially prevented by disconnecting at least a portion of an intermediate layer arranged between a pixel electrode and a common electrode located between adjacent pixels using a reference wiring.

[0224] According to one or more embodiments of the present disclosure, in a display device and a mobile electronic device including the display device, by compensating for a resistance deviation or variation caused by a length deviation or variation of a reference wiring, the width and height of a disconnected portion of an intermediate layer that disconnects the intermediate layer can be uniformized, and product defects caused by process deviations or variations of the disconnected portion can be reduced.

[0225] The foregoing is an explanation of some embodiments of the present disclosure and should not be interpreted as limiting it. Although some embodiments have been described, it will be readily understood by those skilled in the art that various modifications can be made in the embodiments without departing from the spirit and scope of the present disclosure. It will be understood that the description of the features or aspects within each embodiment should generally be considered as other similar features or aspects that can be used in other embodiments. Therefore, as is apparent to those of ordinary skill in the art, unless otherwise specifically indicated, the features, characteristics and / or elements described in conjunction with a specific embodiment may be used alone or in combination with the features, characteristics and / or elements described in conjunction with other embodiments. Therefore, it should be understood that the foregoing is an explanation of various example embodiments and should not be interpreted as being limited to the specific embodiments disclosed herein, and various modifications to the disclosed embodiments and other example embodiments are intended to be included in the spirit and scope of the present disclosure as defined in the accompanying claims and their equivalents.

Claims

1. A display device, comprising: substrate; A driving element layer, wherein the driving element layer is located on the substrate; as well as A light emitting element layer, the light emitting element layer is located on the driving element layer, and the light emitting element layer includes: A pixel defining layer, wherein the pixel defining layer is divided into a plurality of sub-pixels; a first electrode of a sub-pixel among the plurality of sub-pixels, the first electrode being positioned in an opening of the pixel defining layer; A plurality of wirings, the plurality of wirings comprising: A first wiring is formed on the pixel defining layer. The first electrodes extend in a first direction while crossing each other and have a first length in the display area; and a second wiring having a second length in the display area that is shorter than the first length; an intermediate layer, the intermediate layer covering the first electrode and the pixel defining layer at the opening, and a portion of the intermediate layer being disconnected at upper portions of the plurality of wirings; a second electrode covering the intermediate layer in the opening, and continuously covering the intermediate layer and the plurality of wirings between sub-pixels adjacent to each other among the plurality of sub-pixels; and a plurality of pattern wirings connected to the plurality of wirings in a non-display area and including a third wiring and a fourth wiring, wherein the third wiring is connected to the first wiring and has a third length, and The fourth wiring is connected to the second wiring and has a fourth length longer than the third length.

2. The display device according to claim 1, wherein: The fourth wiring has a zigzag shape to have the fourth length longer than the third length.

3. The display device according to claim 2, wherein: A first total length obtained by adding the first length of the first wiring and the third length of the third wiring to each other is equal to a second total length obtained by adding the second length of the second wiring and the fourth length of the fourth wiring to each other.

4. The display device according to claim 3, wherein: The first wiring is an odd-numbered wiring among the plurality of wirings, and The second wiring is an even-numbered wiring among the plurality of wirings.

5. The display device according to claim 1, wherein: a power supply pad positioned at one end of the non-display area adjacent to one end of the plurality of wirings, The other end of the non-display area adjacent to the other end of the plurality of wirings includes a first ground wiring and a second ground wiring that connect the ground pad and the plurality of wirings to each other. wherein the first ground wiring is connected to the first wiring and extends in a straight line, and The second ground wiring is connected to the second wiring and has a zigzag shape.

6. The display device according to claim 5, wherein: The ground pad is positioned at the other end of the non-display area.

7. The display device according to claim 1, wherein: The first electrode has a hexagonal shape in a plan view, and includes a protrusion protruding in a direction of the first wiring.

8. The display device according to claim 1, wherein: The plurality of sub-pixels include: a first light emitting region of a first sub-pixel; a second light emitting region of a second sub-pixel; and a third light emitting region of the third sub-pixel, wherein, in odd-numbered rows among the plurality of sub-pixels, the first light-emitting regions and the second light-emitting regions are alternately positioned along the first direction, wherein, in even-numbered rows among the plurality of sub-pixels, the third light emitting regions are positioned at intervals along the first direction, and The length of the third light emitting area in the first direction is greater than the sum of the length of the first light emitting area in the first direction and the length of the second light emitting area in the first direction.

9. The display device according to claim 8, wherein: The first wiring comprises: a first portion, the first portion being located between the first light emitting area and the third light emitting area; a second portion extending from the first portion and positioned between the first light emitting area and the second light emitting area; and a third portion extending from the second portion and positioned between the second light emitting area and the third light emitting area, and Wherein, the second wiring comprises: a fourth portion, the fourth portion being located between the third light emitting area and the first light emitting area and the second light emitting area; and The fifth portion is located between two adjacent third light-emitting areas.

10. The display device according to claim 5, further comprising: a plurality of fan-out wirings connected between the plurality of pattern wirings and the power supply pad, wherein the plurality of fan-out wirings all have the same length as each other by including a length deviation compensation portion, and The length deviation compensation portion of each of the plurality of fan-out wirings and the length deviation compensation portion of other fan-out wirings in the plurality of fan-out wirings include zigzag wirings of different lengths.

11. A mobile electronic device, comprising: A display panel, the display panel comprising a light emitting element layer, Wherein, the light emitting element layer comprises: A pixel defining layer, wherein the pixel defining layer is divided into a plurality of sub-pixels; a first electrode of a sub-pixel among the plurality of sub-pixels, the first electrode being positioned in an opening of the pixel defining layer; A plurality of wirings, the plurality of wirings comprising: A first wiring is formed on the pixel defining layer. The first electrodes extend in a first direction while crossing each other and have a first length in the display area; and a second wiring having a second length in the display area that is shorter than the first length; an intermediate layer, the intermediate layer covering the first electrode and the pixel defining layer at the opening, and a portion of the intermediate layer being disconnected at upper portions of the plurality of wirings; a second electrode covering the intermediate layer in the opening, and continuously covering the intermediate layer and the plurality of wirings between sub-pixels arranged adjacent to each other among the plurality of sub-pixels; and a plurality of pattern wirings connected to the plurality of wirings in a non-display area and including a third wiring and a fourth wiring, wherein the third wiring is connected to the first wiring and has a third length, and The fourth wiring is connected to the second wiring and has a fourth length longer than the third length.

12. The mobile electronic device according to claim 11, wherein: The fourth wiring has a zigzag shape to have the fourth length longer than the third length.

13. The mobile electronic device according to claim 12, wherein: A first total length obtained by adding the first length of the first wiring and the third length of the third wiring to each other is equal to a second total length obtained by adding the second length of the second wiring and the fourth length of the fourth wiring to each other.

14. The mobile electronic device according to claim 13, wherein: The first wiring is an odd-numbered wiring among the plurality of wirings, and The second wiring is an even-numbered wiring among the plurality of wirings.

15. The mobile electronic device according to claim 11, wherein: a power supply pad positioned at one end of the non-display area adjacent to one end of the plurality of wirings, The other end of the non-display area adjacent to the other end of the plurality of wirings includes a first ground wiring and a second ground wiring that connect the ground pad and the plurality of wirings to each other. wherein the first ground wiring is connected to the first wiring and extends in a straight line, and The second ground wiring is connected to the second wiring and has a zigzag shape.

16. The mobile electronic device according to claim 15, wherein: The ground pad is positioned at the other end of the non-display area.

17. The mobile electronic device according to claim 11, wherein: The first electrode has a hexagonal shape in a plan view, and includes a protrusion protruding in a direction of the first wiring.

18. The mobile electronic device according to claim 11, wherein: The plurality of sub-pixels include: a first light emitting region of a first sub-pixel; a second light emitting region of a second sub-pixel; and a third light emitting region of the third sub-pixel, wherein, in odd-numbered rows among the plurality of sub-pixels, the first light-emitting regions and the second light-emitting regions are alternately positioned along the first direction, wherein, in even-numbered rows among the plurality of sub-pixels, the third light emitting regions are positioned at intervals along the first direction, and The length of the third light emitting area in the first direction is greater than the sum of the length of the first light emitting area in the first direction and the length of the second light emitting area in the first direction.

19. The mobile electronic device according to claim 18, wherein: The first wiring comprises: a first portion, the first portion being located between the first light emitting area and the third light emitting area; a second portion extending from the first portion and positioned between the first light emitting area and the second light emitting area; and a third portion extending from the second portion and positioned between the second light emitting area and the third light emitting area, and Wherein, the second wiring comprises: a fourth portion, the fourth portion being located between the third light emitting area and the first light emitting area and the second light emitting area; and The fifth portion is located between two adjacent third light-emitting areas.

20. The mobile electronic device according to claim 15, further comprising: a plurality of fan-out wirings connected between the plurality of pattern wirings and the power supply pad, wherein the plurality of fan-out wirings all have the same length as each other by including a length deviation compensation portion, and The length deviation compensation portion of each of the plurality of fan-out wirings and the length deviation compensation portion of other fan-out wirings in the plurality of fan-out wirings include zigzag wirings of different lengths.

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