Display device

Abstract

A display device may include: a display panel having a plurality of pixels; and a data driver circuit configured to provide a data signal to the plurality of pixels via the data lines. A gate driver circuit is provided in the display panel, the gate driver circuit configured to provide a gate signal to the plurality of pixels via a gate line. The display panel includes: a driving layer including a gate region having the gate driver circuit; and a pixel circuit layer including an active region having a pixel region in which each of the plurality of pixels is disposed, and a non-active region around the active region. The pixel circuit layer includes a light emitting diode, a clock line configured to provide a clock signal to the gate driver circuit, and a shielding pattern located between the light emitting diode and the clock line.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0115320 filed on August 31, 2023 in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The invention relates to a display device. Background Art

[0004] With the advent of the information age, the display field that visually presents electrical information signals has been rapidly developed, and in response thereto, various display devices having excellent properties such as thin thickness, light weight, and low power consumption have been developed. Examples of such display devices may include liquid crystal display (LCD) devices, organic light emitting display (OLED) devices, and the like.

[0005] Such a display device may include a display panel in which pixels for displaying an image are arranged, and a driving circuit. The driving circuit includes: a data driver configured to provide a data signal to the pixel via a data line; a gate driver configured to provide a gate signal to the pixel via a gate line; and a timing controller that controls the data driver and the gate driver. Summary of the invention

[0006] Accordingly, embodiments of the present invention are directed to a display device that substantially obviates one or more problems due to limitations and disadvantages of the related art.

[0007] One aspect of the present invention is to provide a display device that minimizes or at least reduces a bezel area.

[0008] Another aspect of the present invention is to provide a display device implemented to have high resolution and a large area.

[0009] Still another aspect of the present invention is to provide a display device in which a spacing between each signal line and / or power supply line connected to a pixel is minimized or at least reduced, ensuring ease of design.

[0010] Additional features and advantages of the present invention will be set forth in the following description, and in part will be apparent from the description, or may be learned from the practice of the inventive concept provided herein. Other features and aspects of the inventive concept may be realized or obtained by the structures specifically pointed out in the written description or their derivatives, its claims, and the accompanying drawings.

[0011] To achieve these and other aspects of the inventive concept, as embodied and broadly described herein, a display device may include: a display panel having a plurality of pixels; and a data driver circuit, the data driver circuit being configured to provide data signals to the plurality of pixels via data lines, wherein a gate driver circuit is provided in the display panel, the gate driver circuit being configured to provide gate signals to the plurality of pixels via gate lines, wherein the display panel includes: a driving layer, the driving layer including a gate region having the gate driver circuit; and a pixel circuit layer, the pixel circuit layer including an active region having a pixel region and an inactive region around the active region, each of the plurality of pixels being provided in the pixel region, wherein the pixel circuit layer includes a light emitting diode, a clock line configured to provide a clock signal to the gate driver circuit, and a shielding pattern located between the light emitting diode and the clock line.

[0012] Additional specific details of example embodiments are included in the detailed description and the accompanying drawings.

[0013] In a display device according to an exemplary embodiment of the present invention, a display panel may include: a pixel circuit layer in which pixels are arranged; and a driving layer in which a gate driver is arranged. Here, the gate region of each element in which the gate driver is arranged may be arranged to overlap at least a portion of the active region of each element in which the pixel is arranged. For example, the transistors included in the driving layer may be arranged on the same layer as at least some of the transistors included in the pixel circuit layer. For example, the gate driver is arranged on the same layer as the pixel circuit layer in which the pixels are arranged in a gate-in-array (GIA) manner and is formed on the gate region overlapping the active region, thereby minimizing or at least reducing the border area of ​​the display device.

[0014] Compared to a gate-in-panel (GIP) method in which a gate driver is formed outside an active region to provide a gate signal to a pixel, in a display device according to an exemplary embodiment of the present invention, a gate driver is disposed in at least a portion of an active region, for example, on a gate region, in a gate-in-array (GIA) method. Therefore, a gate signal delay based on a relative position of a pixel is minimized or at least reduced to improve brightness uniformity of the entire active region, so that a display device having a high resolution and a large area can be implemented at low power.

[0015] In addition, in the display device according to the exemplary embodiment of the present invention, the seventh conductive layer disposed above the second planarization layer is disposed in a portion of the fifth conductive layer constituting a clock line for providing a clock signal to the gate driver and an anode of the light emitting diode to perform a function as a shielding pattern for shielding a signal. Therefore, the display quality can be improved.

[0016] In addition, the pixel included in the display device according to the exemplary embodiment of the present invention has a vertical flip structure. Therefore, a space for setting transistors, capacitors, etc. constituting a gate driver can be ensured on the gate region of the driving layer overlapping the central region of the pixel circuit layer.

[0017] In addition, in the display device according to the exemplary embodiment of the present invention, the third power line, the second scan line and the light emitting line included in the first conductive layer and the fourth scan line, the first scan line and the third scan line included in the fourth conductive layer formed of a different metal material from the first conductive layer are alternately arranged along one direction (the second direction). Therefore, the spacing between each signal line and / or power line can be minimized or at least reduced. Therefore, the ease of design can be ensured.

[0018] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the inventive concepts as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings are included to provide a further understanding of the present invention, and are incorporated in and constitute a part of this application, and illustrate embodiments of the present invention and together with the description serve to explain the principles. In the drawings:

[0020] Figure 1 is a block diagram illustrating a display device according to an exemplary embodiment of the present invention;

[0021] Figure 2A It is illustrated in Figure 1 A view of an example of a gate driver included in a display device of FIG. 1 ;

[0022] Figure 2B It is illustrated in Figure 1 A view of another example of a gate driver included in a display device of FIG. 1 ;

[0023] Figure 3 It is illustrated in Figure 1 A circuit diagram of an example of a gate driver included in a display device;

[0024] Figure 4 It is illustrated in Figure 1 A circuit diagram of an example of a pixel included in a display device of;

[0025] Figure 5 is a plan view illustrating a display device according to an exemplary embodiment of the present invention;

[0026] Fig. 6A is used to explain Figure 5 A view of an example of an active region and a gate region included in a display device of FIG. 1 ;

[0027] Figure 6B is used to explain Figure 5 A view of another example of an active region and a gate region included in a display device of FIG. 1 ;

[0028] Figure 7 is a schematic diagram in Figure 5 A cross-sectional view of an example of a display panel included in a display device;

[0029] Figure 8 It is a graphic Figure 7 A cross-sectional view of an example of a display panel;

[0030] Fig. 9 It is illustrated in Figure 5 Layout of an example of pixels included in a display device;

[0031] Fig.10 It is a diagram along Fig. 9 A cross-sectional view of the example taken along line II'. DETAILED DESCRIPTION

[0032] The advantages and features of the present invention and the method for achieving these advantages and features are described in detail below and in the accompanying drawings. Figure 1 The exemplary embodiments described in detail will be clear. However, the present invention is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided only by way of example so that those skilled in the art can fully understand the disclosure of the present invention and the scope of the present invention.

[0033] The shapes, sizes, proportions, angles, quantities, etc. shown in the accompanying drawings for describing exemplary embodiments of the present invention are merely examples, and the present invention is not limited thereto. Similar reference numerals generally represent similar elements throughout the application. In addition, in the following description of the present invention, detailed explanations of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present invention. Terms such as "including", "having" and "comprising" used herein are generally intended to allow the addition of other components unless these terms are used together with the term "only". Any singular reference may include plural numbers unless otherwise expressly indicated.

[0034] Even if not expressly stated, the components are to be construed as containing ordinary margins of error.

[0035] When terms such as "on", "over", "below", and "after" are used to describe the positional relationship between two parts, one or more parts may be placed between the two parts unless these terms are used together with the terms "immediately" or "directly".

[0036] When an element or layer is referred to as being “on” another element or layer, it can be directly on the other element or layer, or other layers or other elements may be interposed therebetween.

[0037] Although the terms "first", "second", etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, within the technical concept of the present invention, the first component mentioned below may be the second component.

[0038] Like reference numbers generally refer to like elements throughout the application.

[0039] For convenience of description, the size and thickness of each component shown in the drawings are exemplified, and the present invention is not limited to the size and thickness of the illustrated components.

[0040] The features of the various embodiments of the present invention may be combined or combined with each other in part or in whole, and may be technically interlocked and operated in various ways, and the embodiments may be implemented independently of each other, or in association with each other.

[0041] Hereinafter, a display device according to an exemplary embodiment of the present invention will be described in detail with reference to the accompanying drawings.

[0042] Figure 1 is a block diagram illustrating a display device according to an exemplary embodiment of the present invention.

[0043] Reference Figure 1 , a display device 1000 according to an exemplary embodiment of the present invention may include a pixel unit 100, a gate driver GD (e.g., a gate driver circuit), a data driver 400 (e.g., a data driver circuit), and a timing controller 500. In an exemplary embodiment, the gate driver GD may include a scan driver 200 and a light emitting driver 300.

[0044] The display device 1000 can display images at various frame rates (refresh rates, driving frequencies, or screen refresh rates) according to driving conditions. The frame rate is the frequency at which the data voltage is actually written in the driving transistor of the pixel PX within one second. For example, the frame rate is also called a screen scan rate or a screen refresh rate, and indicates the frequency at which the display screen is refreshed within one second.

[0045] In one exemplary embodiment, the output frequency of the scan signal (e.g., the second scan signal) provided to the scan line (e.g., the second scan line) to provide the data signal output frequency and / or the data signal to the data driver 400 may be changed in response to the frame rate. For example, when the frame rate is 120 Hz, the second signal may be provided to each horizontal line (pixel line) 120 times per second.

[0046] In an exemplary embodiment, the display device 1000 may adjust the output frequency of the scan driver 200 and the light emitting driver 300 and the output frequency of the data driver 400 corresponding thereto according to the driving conditions. For example, the display device 1000 may display images according to various frame rates from 1 Hz to 120 Hz. Here, the frame rate may be set by a maximum frequency divisor based on the maximum frequency at which the scan signal is provided, excluding the maximum frequency. For example, the scan signal may be provided at a maximum of 240 Hz, and therefore, the display device 1000 may display images at a frame rate corresponding to a divisor of 240 Hz (excluding 240 Hz). However, this is exemplary, and the display device 100 may also display images at a frame rate of 120 Hz or higher (e.g., 240 Hz or 480 Hz).

[0047] Meanwhile, the display device 1000 can be operated at various frame rates. In the case of low-frequency driving, image defects such as flickering may be visible due to current leakage in the pixel. In addition, afterimages such as image dragging may be visible due to changes in the bias state of the drive transistor caused by driving at various frame rates or changes in response speed due to threshold voltage shifts caused by changes in hysteresis characteristics.

[0048] In order to improve the image quality, one frame period may include a plurality of non-luminous periods and luminous periods according to the frame rate. For example, the first non-luminous period and luminous period of one frame may be defined as a first driving period, and the subsequent non-luminous period and luminous period may be defined as a second driving period. For example, in the first driving period, a data signal for substantially displaying an image may be written into the pixel PX in the first driving period, and an on-bias may be applied to the driving transistor of the pixel PX in the second driving period.

[0049] The pixel unit 100 may include scan lines S11 to S1n, S21 to S2n, S31 to S3n, and S41 to S4n; light emission control lines E1 to En; and data lines D1 to Dm, and the pixel unit 100 includes pixels PX connected to the scan lines S11 to S1n, S21 to S2n, S31 to S3n, and S41 to S4n; the light emission control lines E1 to En; and the data lines D1 to Dm, where m and n are integers greater than 0. Each pixel PX may include a driving transistor and a plurality of switching transistors.

[0050] The pixel PX arranged in the i-th row and j-th column among the pixels PX can be connected to the corresponding first scan line among the first scan lines S11 to S1n (for example, the i-th first scan line S1i), the corresponding second scan line among the second scan lines S21 to S2n (for example, the i-th second scan line S2i), the corresponding third scan line among the third scan lines S31 to S3n (for example, the i-th third scan line S3i), the corresponding fourth scan line among the fourth scan lines S41 to S4n (for example, the i-th fourth scan line S4i), the corresponding light-emitting control line among the light-emitting control lines E1 to En (for example, the i-th light-emitting control line Ei), and the corresponding data line among the data lines D1 to Dm (for example, the j-th data line Dj), where i and j are integers greater than 0.

[0051] The pixel PX may be provided with a first power voltage VDD, a second power voltage VSS, a third power voltage VINIT (eg, a first initialization voltage), a fourth power voltage VAR (eg, a second initialization voltage), and a fifth power voltage VOBS (eg, a bias voltage).

[0052] The voltage level of the second power supply voltage VSS may be lower than the voltage level of the first power supply voltage VDD. For example, the first power supply voltage VDD may be a positive voltage, and the second power supply voltage VSS may be a negative voltage.

[0053] The third power supply voltage VINIT (eg, first initialization voltage) and the fourth power supply voltage VAR (eg, second initialization voltage) are initialization voltages for initializing the pixel PX. For example, a driving transistor and / or a light emitting diode included in the pixel PX may be initialized by the initialization voltages.

[0054] The fifth power supply voltage VOBS (e.g., bias voltage) may be a voltage for providing a predetermined bias to the source and / or drain of the driving transistor included in the pixel PX. For example, the fifth power supply voltage VOBS may be a positive voltage. However, the voltage level of the fifth power supply voltage VOBS is not limited thereto, and the fifth power supply voltage VOBS may be set to a negative voltage. In an exemplary embodiment of the present invention, the signal line connected to the pixel PX may be arranged in various forms according to the circuit structure of the pixel PX.

[0055] The first data DATA1 (eg, input image data) and the input control signal CS may be provided from the host system via a predetermined interface to the timing controller 500. The timing controller 500 may control driving timings of the scan driver 200, the light emitting driver 300, and the data driver 400.

[0056] The timing controller 500 may generate a first control signal SCS, a second control signal ECS, and a third control signal DCS based on the first data DATA1 and the input control signal CS. For example, the input control signal CS may include a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a clock signal. The first control signal SCS may be provided to the scan driver 200, the second control signal ECS may be provided to the light emitting driver 300, and the third control signal DCS may be provided to the data driver 400. The timing controller 500 rearranges the first data DATA1 to generate the second data DATA2 and provides the second data to the data driver 400.

[0057] The scan driver 200 receives a first control signal SCS (e.g., a scan control signal) from the timing controller 500. The scan driver 200 may provide first, second, third, and fourth scan signals to the first, second, third, and fourth scan lines S11 to S1n, S21 to S2n, S31 to S3n, and S41 to S4n, respectively, based on the first control signal SCS.

[0058] The first to fourth scan signals may be set to a gate-on voltage (e.g., a low voltage or a high voltage) corresponding to the type of transistor to which the corresponding scan signal is provided. When the scan signal is provided, the transistor receiving the scan signal may be set to an on state. For example, the gate-on voltage of the scan signal provided to a P-channel metal oxide semiconductor (PMOS) transistor may be a logic low level, and the gate-on voltage of the scan signal provided to an N-channel metal oxide semiconductor (NMOS) transistor may be a logic high level. Hereinafter, the meaning of "providing a scan signal" is understood as: providing a scan signal at a logic level that turns on the transistor controlled by the scan signal.

[0059] The light emitting driver 300 may provide a light emitting control signal to the light emitting control lines E1 to En based on the second control signal ECS (eg, a light emitting driving control signal). For example, the light emitting control signal may be sequentially provided to the light emitting control lines E1 to En.

[0060] The light emitting control signal may be set to a gate cut-off voltage (e.g., a high voltage). The transistor receiving the light emitting control signal may be turned off when the light emitting control signal is provided, and may be set to a conducting state in other cases. Hereinafter, the meaning of "providing a light emitting control signal" is understood as: providing the light emitting control signal at a logic level that turns off the transistor controlled by the light emitting control signal.

[0061] At the same time, for the convenience of description, Figure 1, the scanning driver 200 and the light emitting driver 300 are shown as a single structure, but the present invention is not limited thereto. According to the design, the scanning driver 200 may include a plurality of scanning transistors configured to provide at least one of the first to fourth scanning signals, respectively. In addition, at least some of the scanning driver 200 and the light emitting driver 300 may be integrated into one driving circuit or module.

[0062] The data driver 400 may receive a third control signal DCS (e.g., a data control signal) and second data DATA2 (e.g., image data) from the timing controller 500. The data driver 400 may convert the digital type second data DATA2 into an analog data signal (e.g., a data voltage). The data driver 400 may provide data signals to the data lines D1 to Dm in response to the third control signal DCS. At this time, the data signals provided to the data lines D1 to Dm may be provided synchronously with the second scan signals provided to the second scan lines S21 to S2n.

[0063] Meanwhile, a normal gate driver is formed independently of the display panel to be electrically connected to the display panel in various ways. However, in the display device according to the exemplary embodiment, the gate driver GD, such as the scanning driver 200 and the light emitting driver 300, is formed in the form of a thin film pattern during the manufacture of the substrate of the display panel to be formed in the active area AA of the display panel in an array gate manner (see FIG. Figure 5 ) at least a portion of the region (eg, gate region GIA (see Figure 5 ))superior.

[0064] The following will refer to Figures 1 to 5 This is described in more detail.

[0065] Figure 2A It is illustrated in Figure 1 FIG. 1 is a diagram showing an example of a gate driver included in a display device of FIG. Figure 2B It is illustrated in Figure 1 FIG. 1 is a view of another example of a gate driver included in a display device of FIG.

[0066] Reference Figure 1 and 2A The gate driver GD may include a scan driver 200 and a light emitting driver 300, and the scan driver 200 may include a first scan driver 210, a second scan driver 220, a third scan driver 230, and a fourth scan driver 240. The first control signal SCS (e.g., a scan control signal) may include first to fourth scan start signals SST1 to SST4. The first to fourth scan start signals SST1 to SST4 may be provided to the first to fourth scan drivers 210, 220, 230, and 240, respectively.

[0067] The width and supply timing of the first to fourth scan start signals SST1 to SST4 may be determined according to the driving conditions and frame frequency of the pixel PX. The first to fourth scan signals may be output based on the first to fourth scan start signals SST1 to SST4. For example, the signal width of at least one of the first to fourth scan signals may be different from the signal widths of the other scan signals.

[0068] The first scan driver 210 may sequentially provide the first scan signal to the first scan lines S11 to S1n in response to the first scan start signal SST1. The second scan driver 220 may sequentially provide the second scan signal to the second scan lines S21 to S2n in response to the second scan start signal SST2. The third scan driver 230 may sequentially provide the third scan signal to the third scan lines S31 to S3n in response to the third scan start signal SST3. The fourth scan driver 240 may sequentially provide the fourth scan signal to the fourth scan lines S41 to S4n in response to the fourth scan start signal SST4.

[0069] In addition, the second control signal ECS (eg, light emitting driving control signal) may include a light emitting start signal EST. The light emitting start signal EST may be provided to the light emitting driver 300.

[0070] The width and supply timing of the light emission start signal EST may be determined according to the driving conditions and frame rate of the pixel PX. The light emission signal may be output based on the light emission start signal EST. The light emission driver 300 may sequentially supply light emission signals to the light emission control lines E1 to En in response to the light emission start signal EST.

[0071] At the same time, even in Figure 2A 1 and 2 , one second scan driver 220 is shown to provide the second scan signal via the second scan lines S21 to S2n connected to the corresponding pixels PX disposed in all rows (or all horizontal rows), but exemplary embodiments of the present invention are not limited thereto.

[0072] For example, refer to Figure 2B , the pixels PX_1 included in the pixel unit 100_11 are divided into pixels PX_Odd disposed in odd rows, for example, the i-th row, and pixels PX_Even disposed in even rows, for example, the i+1-th row, where i is an odd natural number.

[0073] Here, among the pixels PX_Odd arranged in odd rows, such as the i-th row, the pixel PX_Odd arranged in the j-th column can be connected to the corresponding first scan line among the first scan lines S11 to S1n (for example, the i-th first scan line S1i), the corresponding first sub-scan line among the first sub-scan lines S21a to S2pa (for example, the k-th first sub-scan line S2ka), the corresponding third scan line among the third scan lines S31 to S3n (for example, the i-th third scan line S3i), the corresponding fourth scan line among the fourth scan lines S41 to S4n (for example, the i-th fourth scan line S4i), the corresponding light-emitting control line among the light-emitting control lines E1 to En (for example, the i-th light-emitting control line Ei), and the corresponding data line among the data lines D1 to Dm (for example, the j-th data line Dj), and in this case, 2p is n and 2k is i+1.

[0074] In addition, among the pixels PX_Even arranged in an even row, such as the i+1th row, the pixel PX_Even arranged in the jth column can be connected to the corresponding first scan line among the first scan lines S11 to S1n (for example, the i+1th first scan line S1i+1), the corresponding second sub-scan line among the second sub-scan lines S21b to S2pb (for example, the kth second sub-scan line S2kb), the corresponding third scan line among the third scan lines S31 to S3n (for example, the i+1th third scan line S3i+1), the corresponding fourth scan line among the fourth scan lines S41 to S4n (for example, the i+1th fourth scan line S4i+1), the corresponding light-emitting control line among the light-emitting control lines E1 to En (for example, the i+1th light-emitting control line Ei+1), and the corresponding data line among the data lines D1 to Dm (for example, the jth data line Dj).

[0075] The first control signal SCS (e.g., scan control signal) may include first to fourth scan start signals SST1, SST2, SST3, and SST4. The first to fourth scan start signals SST1, SST2, SST3, and SST4 may be provided to the first to fourth scan drivers 210, 220_1, 230, and 240, respectively. Meanwhile, the second scan start signal SST2 may include a first sub-scan start signal SST2a and a second sub-scan start signal SST2b.

[0076] The gate driver GD may include a scan driver 200_1 and a light emitting driver 300. The scan driver 200_1 may include first, second, third, and fourth scan drivers 210, 220_1, 230, and 240. In one exemplary embodiment, the second scan driver 220_1 may include first and second sub-scan drivers 221 and 222.

[0077] The first sub-scanning driver 221 of the second scan driver 220_1 may sequentially provide the first sub-scanning signal to the first sub-scanning lines S21a to S2pa in response to the first sub-scanning start signal SST2a. In addition, the second sub-scanning driver 222 of the second scan driver 220_1 may sequentially provide the second sub-scanning signal to the second sub-scanning lines S21b to S2pb in response to the second sub-scanning start signal SST2b.

[0078] As described above, in the display device 1000 according to the exemplary embodiment of the present invention, the second scan driver 220_1 included in the scan driver 200_1 may also be configured to be divided into a first sub-scan driver 221 and a second sub-scan driver 222. The first sub-scan driver 221 provides a second scan signal (e.g., a first sub-scan signal) to the pixels PX_Odd disposed in the odd-numbered rows, and the second sub-scan driver 222 provides a second scan signal (e.g., a second sub-scan signal) to the pixels PX_Even disposed in the even-numbered rows.

[0079] Meanwhile, for the convenience of description, unless otherwise mentioned, the following description will be based on one second scan driver 220 providing the second scan signal via the second scan lines S21 to S2n connected to each pixel PX disposed in each row (or each horizontal row), such as Figure 2A shown.

[0080] Figure 3 It is illustrated in Figure 1 A circuit diagram of an example of a gate driver included in a display device.

[0081] at the same time, Figure 3 A circuit diagram is shown, which illustrates an example of a light-emitting stage included in a scanning driver 200 included in a gate driver GD and a light-emitting driver 300 configured to provide a light-emitting control signal (e.g., an i-th light-emitting control signal EMi) to a pixel PX set in an i-th row.

[0082] Reference Figure 1 and 3 The light-emitting stage included in the light-emitting driver 300 can receive an input signal INP (for example, a light-emitting start signal EST or a previous light-emitting control signal (for example, the i-1th light-emitting control signal EMi-1) and a light-emitting clock signal ECLK. The light-emitting stage can receive a first driving power supply voltage VEH and a second driving power supply voltage VEL.

[0083] The voltage level of the second driving power supply voltage VEL may be lower than the voltage level of the first driving power supply voltage VEH. For example, the first driving power supply voltage VEH may be a positive voltage and the second driving power supply voltage VEL may be a negative voltage, but these are exemplary and the exemplary embodiments of the present invention are not limited thereto.

[0084] In one exemplary embodiment, the light emitting stage may generate and output an i-th light emitting control signal EMi based on the input signal INP, the light emitting clock signal ECLK, the first driving power voltage VEH, and the second driving power voltage VEL.

[0085] To this end, the light emitting stage may include first to seventh stage transistors M1 to M7 , a first capacitor CB, a second capacitor CQB, and a third capacitor C_ON.

[0086] Meanwhile, a transistor is a three-electrode element including a gate, a source and a drain. The source is an electrode configured to provide carriers to the transistor. In a transistor, carriers begin to flow from the source. The drain is an electrode from which carriers are output from the transistor to the outside. Therefore, carriers in a MOSFET flow from the source to the drain. In the case of an n-type MOSFET (NMOS), since the carriers are electrons, in order to allow electrons to flow from the source to the drain, the voltage of the source is lower than the voltage of the drain. In an n-type MOSFET, since electrons flow from the source to the drain, current flows from the drain to the source. In the case of a p-type MOSFET (PMOS), since the carriers are holes, in order to allow holes to flow from the source to the drain, the voltage of the source is higher than the voltage of the drain. In a p-type MOSFET, since holes flow from the source to the drain, current flows from the source to the drain. However, it should be noted that the source and drain of a MOSFET are not fixed. For example, the source and drain of a MOSFET may change according to an applied voltage. In the following exemplary embodiments, the present invention should not be limited by the source and drain of the transistor.

[0087] In an exemplary embodiment, the stage transistors constituting the gate driver GD may be p-type MOSFET transistors (PMOS transistors) or low temperature polycrystalline silicon (LTPS) thin film transistors. Each of the plurality of transistors included in the gate driver GD may include a polycrystalline silicon semiconductor layer. For example, the first to seventh stage transistors M1 to M7 constituting the light emitting stage included in the light emitting driver 300 may be PMOS LTPS thin film transistors.

[0088] The first-stage transistor M1 is connected between a power terminal (hereinafter referred to as a second power terminal) to which the second driving power voltage VEL is supplied and an output terminal to which the i-th light emitting control signal EMi is output, and may include a gate connected to the Q node Q. The first-stage transistor M1 may be turned on or off based on the voltage of the Q node Q.

[0089] For example, when the voltage of the Q node Q has a gate-on level (e.g., a low level), the first-stage transistor M1 is turned on to electrically connect the second power terminal to which the second driving power voltage VEL is provided to the output terminal to which the i-th light emitting control signal EMi is output. For example, in a section in which the first-stage transistor M1 is turned on, the i-th light emitting control signal EMi may have a turn-on level (e.g., a low level).

[0090] The second-stage transistor M2 is connected between a power terminal (hereinafter referred to as a first power terminal) to which the first driving power voltage VEH is provided and an output terminal to which the i-th light emitting control signal EMi is output, and may include a gate connected to the QB node QB. The second-stage transistor M2 may be turned on or off based on the voltage of the QB node QB.

[0091] For example, when the voltage of the QB node QB has a gate-on level (e.g., a low level), the second-stage transistor M2 is turned on to electrically connect the first power terminal to which the first driving power voltage VEH is provided with the output terminal to which the i-th light-emitting control signal EMi is output. For example, in a section in which the second-stage transistor M2 is turned on, the i-th light-emitting control signal EMi may have a cut-off level (e.g., a high level).

[0092] As described above, the first-stage transistor M1 of the light emitting stage may perform a pull-up function, and the second-stage transistor M2 may perform a pull-down function.

[0093] The third-stage transistor M3 is connected between an input terminal (hereinafter referred to as the first input terminal) to which an input signal INP is input and a second control node Q2. The third-stage transistor M3 may include a gate connected to an input terminal (hereinafter referred to as the second input terminal) to which a light emitting clock signal ECLK is provided. When the light emitting clock signal ECLK provided via the second input terminal has a gate-on level (e.g., a low level), the third-stage transistor M3 is turned on to electrically connect the first input terminal to the second control node Q2. When the third-stage transistor M3 is turned on, the input signal INP provided via the first input terminal may be provided to the second control node Q2.

[0094] The fourth-stage transistor M4 is connected between the first power supply terminal to which the first driving power supply voltage VEH is provided and the first control node Q1, and may include a gate connected to the first input terminal to which the input signal INP is input. When the input signal INP provided via the first input terminal has a gate-on level (e.g., a low level), the fourth-stage transistor M4 is turned on to electrically connect the first power supply terminal and the first control node Q1. When the fourth-stage transistor M4 is turned on, the first driving power supply voltage VEH having a high level provided via the first power supply terminal may be provided to the first control node Q1.

[0095] The third capacitor C_ON may be connected between the second input terminal to which the emission clock signal ECLK is provided and the first control node Q1. For example, the third capacitor C_ON may include a first electrode connected to the second input terminal and a second electrode connected to the first control node Q1.

[0096] The third capacitor C_ON may maintain a voltage between the second input terminal and the first control node Q1. Therefore, the third capacitor C_ON may boost a voltage level of the first control node Q1 in response to a voltage level change of the emission clock signal ECLK provided through the second input terminal.

[0097] The fifth-stage transistor M5 is connected between the second input terminal to which the emission clock signal ECLK is provided and the QB node QB, and may include a gate connected to the first control node Q1. The fifth-stage transistor M5 may be turned on or off in response to the voltage level of the first control node Q1. When the fifth-stage transistor M5 is turned on, the emission clock signal ECLK provided via the second input terminal may be provided to the QB node QB.

[0098] The sixth-stage transistor M6 is connected between the first input terminal to which the first driving power supply voltage VEH is provided and the QB node QB, and may include a gate connected to the second control node Q2. The sixth-stage transistor M6 may be turned on or off in response to the voltage level of the second control node Q2. When the sixth-stage transistor M6 is turned on, the first driving power supply voltage VEH having a high level provided via the first power supply terminal may be provided to the QB node QB.

[0099] The seventh-stage transistor M7 is connected between the second control node Q2 and the Q-node Q, and may include a gate connected to a second power supply terminal to which a second driving power supply voltage VEL is supplied. Here, the second driving power supply voltage VEL has a low-level voltage level so that the seventh-stage transistor M7 can always maintain a turned-on state and the second control node Q2 and the Q-node Q can maintain an electrically connected state.

[0100] The first capacitor CB (or boost capacitor) may be connected between the Q node Q and the output terminal. For example, the first capacitor QB may include a first electrode connected to the Q node Q and a second electrode connected to the output terminal.

[0101] The second capacitor CQB may be connected between the first power supply terminal and the QB node QB. For example, the second capacitor CQB may include a first electrode connected to the first power supply terminal and a second electrode connected to the QB node QB. Here, one electrode (e.g., the first electrode) of the second capacitor CQB is connected to the first power supply terminal of the first driving power supply voltage VEH provided as a constant power supply, so that the second capacitor CQB can charge the voltage applied to the QB node QB and stably maintain the voltage of the QB node QB.

[0102] Figure 4 It is illustrated in Figure 1 A circuit diagram of an example of a pixel included in a display device.

[0103] exist Figure 4 In the figure, for the convenience of description, the pixel PX located in the i-th horizontal line (or the i-th pixel row) and connected to the j-th data line Dj is illustrated, where i and j are integers greater than 0. At the same time, Figure 4 The pixel PX shown can be compared with the reference Figure 1 The pixels PX described are substantially the same.

[0104] Reference Figure 1 and 4 , the pixel PX may include a light emitting diode LD, a driving transistor DT, first to seventh transistors T1 to T7 , and a storage capacitor Cst.

[0105] A first electrode (e.g., an anode) of the light emitting diode LD may be connected to the fourth node N4 (or the second electrode of the fourth transistor T4), and a second electrode (e.g., a cathode) may be connected to the second power line PL2 transmitting the second power voltage VSS. The light emitting diode LD may generate light having a predetermined brightness in response to the amount of current (driving current) provided from the driving transistor DT.

[0106] The second power line PL2 may be a line type, but is not limited thereto. For example, the second power line PL2 may be a conductive plate type of a conductive layer.

[0107] In one exemplary embodiment, the light emitting diode LD may be an organic light emitting diode including an organic light emitting layer. In another exemplary embodiment, the light emitting diode LD may be an inorganic light emitting diode formed using an inorganic material, such as a micro light emitting diode (LED) or a quantum dot light emitting diode. In yet another exemplary embodiment, the light emitting diode LD may be a light emitting diode in which an organic material and an inorganic material are mixed.

[0108] Despite Figure 4 , the pixel PX includes a single light emitting diode LD, but according to another exemplary embodiment, the pixel PX includes a plurality of light emitting diodes, and the plurality of light emitting diodes may be connected to each other in series, in parallel, or in series and in parallel. For example, in the light emitting diode LD, a plurality of light emitting diodes (e.g., organic light emitting diodes and / or inorganic light emitting diodes) may be connected in series, in parallel, or in series and in parallel between the second power line PL2 and the fourth node N4.

[0109] The first electrode (e.g., source) of the driving transistor DT may be connected to the first node N1, and the second electrode (e.g., drain) may be connected to the second node N2. The gate of the driving transistor DT may be connected to the third node N3. The driving transistor DT may control the driving current (e.g., the amount of driving current) flowing from the first power line PL1 configured to provide the first power supply voltage VDD to the second power line PL2 configured to provide the second power supply voltage VSS via the light emitting diode LD in response to the voltage of the third node N3, e.g., the voltage of the gate. To this end, the first power supply voltage VDD may be set to be higher than the second power supply voltage VSS. For example, the first power supply voltage VDD may be a positive voltage, and the second power supply voltage VSS may be a negative voltage.

[0110] The first transistor T1 may be connected between the second electrode (e.g., the second node N2) and the gate (e.g., the third node N3) of the driving transistor DT. For example, the first electrode (e.g., the drain) of the first transistor T1 may be connected to the second node N2, and the second electrode (e.g., the source) may be connected to the third node N3. The gate of the first transistor T1 may be connected to the i-th first scan line S1i. When the first scan signal is provided to the i-th first scan line S1i, the first transistor T1 is turned on to electrically connect the second electrode and the gate (e.g., the second node N2 and the third node N3) of the driving transistor DT. For example, the connection time of the second electrode (e.g., the drain) and the gate of the driving transistor DT may be controlled by the first scan signal SC1i. When the first transistor T1 is turned on, the driving transistor DT may be connected in the form of a diode.

[0111] The second transistor T2 may be connected between the j-th data line Dj and the first node N1. For example, a first electrode (e.g., a source) of the second transistor T2 may be connected to the j-th data line Dj, and a second electrode (e.g., a drain) may be connected to the first node N1. A gate of the second transistor T2 may be connected to the i-th second scan line S2i. When the second scan signal is provided to the i-th second scan line S2i, the second transistor T2 is turned on to electrically connect the j-th data line Dj and the first node N1.

[0112] The third transistor T3 may be connected between the first power line PL1 and the first node N1. For example, a first electrode (e.g., a source) of the third transistor T3 may be connected to the first power line PL1, and a second electrode (e.g., a drain) may be connected to the first node N1. A gate of the third transistor T3 may be connected to the i-th light emission control line Ei. When the light emission control signal is provided to the i-th light emission control line Ei, the third transistor T3 may be turned off; otherwise, the third transistor T3 may be turned on. When the third transistor T3 is turned on, the first node N1 may be electrically connected to the first power line PL1.

[0113] The fourth transistor T4 may be connected between the second electrode (e.g., the second node N2) of the driving transistor DT and the first electrode (e.g., the fourth node N4) of the light emitting diode LD. For example, the first electrode (e.g., the source) of the fourth transistor T4 may be connected to the second node N2, and the second electrode (e.g., the drain) may be connected to the fourth node N4. The gate of the fourth transistor T4 may be connected to the i-th light emission control line Ei. The fourth transistor T4 may be controlled in substantially the same manner as the third transistor T3. When the fourth transistor T4 is turned on, the second node N2 and the fourth node N4 may be electrically connected.

[0114] exist Figure 4 , the third transistor T3 and the fourth transistor T4 are shown to be connected to the same light emitting control line (e.g., the i-th light emitting control line Ei), but this is exemplary and the present invention is not limited thereto. For example, the third transistor T3 and the fourth transistor T4 may be connected to separate light emitting control lines provided with different light emitting control signals, respectively.

[0115] The fifth transistor T5 may be connected between the third node N3 (e.g., the gate of the driving transistor DT) and the third power line PL3 configured to provide a third power supply voltage VINIT (hereinafter referred to as the first initialization voltage). For example, the first electrode (e.g., the drain) of the fifth transistor T5 may be connected to the third power supply line PL3, and the second electrode (e.g., the source) may be connected to the third node N3. The gate of the fifth transistor T5 may be connected to the i-th fourth scan line S4i. When the fourth scan signal is supplied to the i-th fourth scan line S4i, the fifth transistor T5 is turned on to supply the first initialization voltage VINIT to the third node N3. Here, the first initialization voltage VINIT may be set to be lower than the lowest level of the data signal DATA supplied to the j-th data line Dj. The fifth transistor T5 is turned on by supplying the fourth scan signal SC4i to initialize the voltage of the gate (or the third node N3) of the driving transistor DT to the first initialization voltage VINIT.

[0116] The sixth transistor T6 may be connected between the first electrode (or fourth node N4) of the light emitting diode LD and the fourth power line PL4 configured to provide a fourth power supply voltage VAR (hereinafter referred to as the second initialization voltage). For example, the first electrode (e.g., source) of the sixth transistor T6 may be connected to the fourth power supply line PL4, and the second electrode (e.g., drain) may be connected to the fourth node N4. The gate of the sixth transistor T6 may be connected to the i-th third scan line S3i. When the third scan signal SC3i is provided to the i-th third scan line S3i, the sixth transistor T6 is turned on to provide the second initialization voltage VAR to the fourth node N4 (e.g., the first electrode of the light emitting diode LD).

[0117] In an exemplary embodiment, when the third scan signal is provided, the second initialization voltage VAR may be provided to the first electrode of the light emitting diode LD through the turned-on sixth transistor T6. In this case, the parasitic capacitor of the light emitting diode LD may be discharged. As described above, since the residual voltage charged in the parasitic capacitor of the light emitting diode LD is discharged (removed), undesirable micro-light emission may be suppressed. Therefore, the black performance capability of the pixel PX may be improved.

[0118] Meanwhile, the voltage levels of the first initialization voltage VINIT and the second initialization voltage VAR may be different from each other. For example, a voltage at which the third node N3 is initialized and a voltage at which the fourth node N4 is initialized may be set to be different from each other.

[0119] When the first initialization voltage VINIT supplied to the third node N3 is significantly lower in low-frequency driving with an increased length of one frame period, a stronger on-bias voltage is applied to the driving transistor DT, so that the threshold voltage of the driving transistor DT in the corresponding frame period may be shifted. This hysteresis characteristic may cause a flickering phenomenon during low-frequency driving. Therefore, in a display device driven at a low frequency, a first initialization voltage VINIT higher than the second power supply voltage VSS may be required.

[0120] However, when the voltage level of the second initialization voltage VAR supplied to the fourth node N4 to initialize the light emitting diode LD is higher than a predetermined reference value, the voltage of the parasitic capacitor of the light emitting diode LD may not be discharged but may be charged. Therefore, the voltage level of the second initialization voltage VAR should be sufficiently low so as to discharge the voltage of the parasitic capacitor of the light emitting diode LD. For example, considering the threshold voltage of the light emitting diode LD, the voltage level of the second initialization voltage VAR may be set to be lower than the sum of the threshold voltage of the light emitting diode LD and the second power supply voltage VSS.

[0121] However, this is exemplary, and the voltage level of the first initialization voltage VINIT and the voltage level of the second initialization voltage VAR may be set to various levels. For example, the voltage level of the first initialization voltage VINIT and the voltage level of the second initialization voltage VAR may be substantially the same.

[0122] The seventh transistor T7 may be connected between the first node N1 (or the first electrode of the driving transistor DT) and a fifth power line PL5 configured to provide a fifth power voltage VOBS (hereinafter referred to as a bias voltage). For example, a first electrode (e.g., a source) of the seventh transistor T7 may be connected to the fifth power line PL5, and a second electrode (e.g., a drain) may be connected to the first node N1. A gate of the seventh transistor T7 may be connected to the i-th third scan line S3i.

[0123] When the third scan signal SC3i is supplied to the i-th third scan line S3i, the seventh transistor T7 is turned on to supply the bias voltage VOBS to the first node N1. In an exemplary embodiment, the bias voltage VOBS may have a level similar to the voltage level of the black grayscale data signal DATA. For example, the bias voltage VOBS may have a voltage level close to 5 to 7V, but this is exemplary and the voltage level of the bias voltage VOBS is not limited thereto.

[0124] Therefore, the seventh transistor T7 is turned on to apply a predetermined high voltage to the first electrode (eg, source) of the driving transistor DT. At this time, when the first transistor T1 is in the on state, the driving transistor DT may be in the on bias state (to be turned on state) (eg, to be turned on bias).

[0125] Here, since the bias voltage VOBS is periodically supplied to the first node N1, the bias state of the driving transistor DT is periodically changed, and the threshold voltage characteristics of the driving transistor DT may be changed. Therefore, the characteristics of the driving transistor DT may be suppressed from being fixed to a specific state at low frequency driving and deteriorating.

[0126] The storage capacitor Cst may be connected between the first power line PL1 and the third node N3. One electrode of the storage capacitor Cst is connected to the first power line PL1, so that the first power supply voltage VDD as a constant voltage may be continuously supplied to one electrode of the storage capacitor Cst. Therefore, the voltage of the third node N3 may not be affected by other parasitic capacitors and may be maintained at a voltage level of the voltage directly supplied to the third node N3. For example, the storage capacitor Cst may store the voltage applied to the third node N3.

[0127] In one exemplary embodiment, the pixel PX may include four p-type transistors PMOS including a polysilicon semiconductor layer and four n-type transistors NMOS including an oxide semiconductor layer.

[0128] For example, the driving transistor DT, the second transistor T2, the third transistor T3 and the fourth transistor T4 may be formed by polysilicon semiconductor transistors. For example, the transistor DT, the second transistor T2, the third transistor T3 and the fourth transistor T4 may include a polysilicon semiconductor layer formed by a low temperature polysilicon (LTPS) process as an active layer (channel). In addition, the driving transistor DT, the second transistor T2, the third transistor T3 and the fourth transistor T4 may be polysilicon semiconductor transistors. Therefore, the gate-on voltage that turns on the driving transistor DT, the second transistor T2, the third transistor T3 and the fourth transistor T4 may be a logic low level.

[0129] Polycrystalline silicon semiconductor transistors have the advantage of fast response speed, so they can be applied to switching elements that require fast switching.

[0130] The first transistor T1, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be formed by oxide semiconductor transistors. For example, the first transistor T1, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be n-type oxide semiconductor transistors (e.g., NMOS transistors) and may include an oxide semiconductor layer as an active layer. Therefore, the gate-on voltage that turns on the first transistor T1, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be a logic high level.

[0131] Oxide semiconductor transistors can be processed at low temperatures and have lower charge mobility than polysilicon semiconductor transistors. For example, oxide semiconductor transistors have excellent off-current characteristics.

[0132] However, the driving transistor DT and the first to seventh transistors T1 to T7 are not limited thereto. Therefore, at least one of the driving transistor DT, the second transistor T2, the third transistor T3, and the fourth transistor T4 may be formed as an oxide semiconductor transistor. In addition, at least one of the first transistor T1, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 may be formed as a polysilicon semiconductor transistor.

[0133] Figure 5 is a plan view illustrating a display device according to an exemplary embodiment of the present invention. Fig. 6A is used to explain Figure 5 FIG. 1 is a view of an example of an active region and a gate region included in a display device of FIG. Figure 6B is used to explain Figure 5 FIG. 1 is a view of another example of an active region and a gate region included in a display device of FIG. Figure 7 is a schematic diagram in Figure 5A cross-sectional view of an example of a display panel included in a display device.

[0134] To avoid redundant descriptions, separate the main description from the reference Figures 1 to 4 Parts that are not described in detail follow the description of the above exemplary embodiments, and the same reference numerals refer to the same elements, and similar reference numerals refer to similar elements.

[0135] Reference Figure 5 , the display device 1000 according to an exemplary embodiment of the present invention may include a display panel DP, a plurality of pixels PX, a gate driver GD, and a data driver (DD) 400. In an exemplary embodiment, the display device 1000 may further include a printed circuit board PCB and a connection film COF.

[0136] The display panel DP may include an active area AA and a non-active area NA surrounding or around the active area AA. For example, the display panel DP may include a substrate divided into the active area AA and the non-active area NA.

[0137] The active area AA may be an area where an image is displayed. A plurality of pixels PX may be arranged on the active area AA. Each pixel PX may include a display element and various driving elements for driving the display element. For example, the various driving elements may include at least one thin film transistor TFT and a capacitor. In addition, the pixels PX may be connected to various wirings, respectively. For example, each pixel PX may be connected to various wirings such as a gate line (e.g., a scan signal line or a light emitting signal line), a data line, and a power supply voltage line.

[0138] The active area AA may be provided in various shapes. For example, the active area AA of the display device 1000 may be provided in a rectangular shape having two pairs of parallel sides, but the exemplary embodiment of the present invention is not limited thereto. According to the exemplary embodiment, the active area AA provided in a rectangular shape may have a rounded corner in which one long side and one short side contact each other. However, the exemplary embodiment is not limited thereto, and the active area AA may have a square shape, a polygonal shape, or a circular shape.

[0139] At the same time, for the sake of convenience, although in Figure 5 , the active area AA has a rectangular shape with rounded corners, a direction parallel to a pair of sides of the active area AA is a first direction DR1, and a direction parallel to the other pair of sides is a second direction DR2. A normal direction of the active area AA, for example, a thickness direction of the display device 1000, may be defined as a third direction DR3, but exemplary embodiments of the present invention are not limited thereto.

[0140] The front surface (or top surface) and the rear surface (or bottom surface) of the components or units of the display device 1000 described below can be distinguished by the third direction DR3. However, the first to third directions DR1, DR2, and DR3 shown in the specification are exemplary, and the first to third directions DR1, DR2, and DR3 are relative concepts that can be converted into other directions. Hereinafter, for the convenience of description, the same reference numerals refer to the first to third directions DR1, DR2, and DR3.

[0141] Meanwhile, when “overlap” is expressed in the present invention, it means that two components overlap in the thickness direction (eg, the third direction DR3 ) of the display device 1000 , unless otherwise defined.

[0142] The non-active area NA may be an area in which an image is not displayed. The non-active area NA may be disposed adjacent to the active area AA. For example, the non-active area NA may be an area surrounding the active area AA. However, without limitation thereto, the non-active area NA corresponds to an area excluding the active area AA from the display panel DP, and may be modified and / or separated into various forms. Components for driving the pixels PX disposed in the active area AA may be disposed on the non-active area NA. For example, a plurality of pads connected to the data driver (DD) 400 may be disposed on the non-active area NA, and each pad may be connected to a plurality of pixels PX of the active area AA via a data line extending from the non-active area NA to the active area AA.

[0143] In addition, the display panel DP may include a gate area GIA. The gate area GIA may overlap at least a portion of the active area AA.

[0144] The gate driver GD may be disposed on the gate area GIA. For example, the gate driver GD may be formed on the gate area GIA overlapping at least a portion of the active area AA in a gate-in-array (GIA) manner.

[0145] For a more detailed description, refer to Fig. 6A The gate area GIA may overlap at least a portion of the active area AA. For example, it may be defined that a portion of the active area AA overlaps the gate area GIA.

[0146] The gate area GIA may be divided into a plurality of blocks Block1 to Block5. For example, the gate area GIA may be divided into a plurality of blocks Block1 to Block5 sequentially disposed along the first direction DR1.

[0147] At the same time, despite Fig. 6A It is shown that the gate area GIA is divided into five blocks Block1 to Block5, but this is exemplary and exemplary embodiments of the present invention are not limited thereto. For example, the gate area GIA may be divided into four or less blocks or six or more blocks.

[0148] In each of the blocks Block1 to Block5 of the gate area GIA, the scan driver 200 and the light emitting driver 300 included in the gate driver GD may be disposed.

[0149] For example, in each of the blocks Block1 to Block5 of the gate area GIA, the first scan driver 210, the third scan driver 230, the second scan driver 220, the fourth scan driver 240, the light emitting driver 300, and the second scan driver 220 may be sequentially arranged along the first direction DR1. Components (e.g., transistors, capacitors, and various connection signal lines) included in the first scan driver 210, components (e.g., transistors, capacitors, and various connection signal lines) included in the third scan driver 230, components (e.g., transistors, capacitors, and various connection signal lines) included in the second scan driver 220, components (e.g., transistors, capacitors, and various connection signal lines) included in the fourth scan driver 240, components (e.g., transistors, capacitors, and various connection signal lines) included in the light emitting driver 300, and components (e.g., transistors, capacitors, and various connection signal lines) included in the second scan driver 220 may be sequentially arranged along the first direction DR1 in each of the blocks Block1 to Block5 of the gate area GIA.

[0150] However, this is exemplary, and the arrangement order of the drivers is not limited thereto.

[0151] At the same time, as reference Figure 2B As described above, when the second scan driver 220_1 included in the scan driver 200_1 of the gate driver GD includes two sub-scan drivers 221 and 222, in each of the blocks Block1 to Block5 of the gate area GIA_1, the first scan driver 210, the third scan driver 230, the first sub-scan driver 221, the second sub-scan driver 222, the fourth scan driver 240, the light emitting driver 300, the first sub-scan driver 221 and the second sub-scan driver 222 can be arranged in sequence along the first direction DR1.

[0152] Refer again Figure 5 In an exemplary embodiment, the display panel DP may include: a driving layer DRL on which a gate driver GD and a signal line connected thereto are disposed; and a pixel circuit layer DSL on which pixels PX and a signal line connected thereto are disposed. For example, further referring to Figure 7 , the display panel DP may include a driving layer DRL and a pixel circuit layer DSL.

[0153] On the driving layer DRL, various elements (such as transistors and capacitors) and signal lines constituting the gate driver GD may be disposed. For example, various elements (such as transistors and capacitors) and signal lines constituting the gate driver GD may be disposed on an area defined as the above-mentioned gate area GIA in the area of ​​the driving layer DRL. For example, it can be understood that the above-mentioned gate area GIA in the area of ​​the display panel DP is defined on the driving layer DRL on which the gate driver GD is disposed, but is not limited thereto.

[0154] On the pixel circuit layer DSL, various elements (such as transistors, capacitors, and light-emitting diodes) and signal lines constituting the pixel PX may be disposed. For example, the pixel circuit layer DSL may include: a display element layer DPL on which display elements such as first-type transistors and second-type transistors and capacitors are disposed; and a light-emitting diode layer EPL, which is disposed on the display element layer DPL and includes light-emitting diodes. For example, the display element included in the display element layer DPL and the light-emitting diode included in the light-emitting diode layer EPL may be disposed on the active area AA. For example, it will be understood that the active area AA (or the active area AA and the non-active area NA) in the above-mentioned area of ​​the display panel DP is defined on the pixel circuit layer DSL on which the light-emitting diodes and display elements included in the pixel PX are disposed, but is not limited thereto. At least some of the plurality of first-type transistors may be included in the pixel circuit layer DSL, and the rest of the plurality of first-type transistors may be included in the drive layer DRL.

[0155] In an exemplary embodiment, the driving layer DRL may be disposed on the same layer as the pixel circuit layer DSL. For example, the driving layer DRL may be disposed on the same layer as the display element layer DPL of the pixel circuit layer DSL. With respect to the above description, further, various elements (such as transistors and capacitors) constituting the gate driver GD may be disposed on the driving layer DRL, and various elements (such as transistors and capacitors) constituting the pixel PX may be disposed on the display element layer DPL. As shown in FIG. Figure 3 As described above, the transistors constituting the gate driver GD can be configured by PMOS LTPS thin film transistors. Figure 4 As described above, the transistors constituting the pixel PX may be configured by a PMOS LTPS thin film transistor or an NMOS oxide thin film transistor. Figure 8As described, among the transistors constituting the pixel PX, the PMOS LTPS thin film transistor is arranged in the lower part, and the NMOS oxide thin film transistor is arranged in the upper part. For example, the PMOS LTPS thin film transistor included in the gate driver GD of the driving layer DRL may be arranged on the same layer as the layer on which the PMOS LTPS thin film transistor included in the pixel PX in the pixel circuit layer DSL, such as the display element layer, is arranged. For example, the PMOS LTPS thin film transistor included in the pixel circuit layer DSL, such as the display element layer DPL, and the PMOS LTPS thin film transistor included in the driving layer DRL may be arranged on the same layer.

[0156] As described above, in the case of the display device 1000 according to the exemplary embodiment of the present invention, the display panel DP includes a driving layer DRL on which various elements constituting the gate driver GD are disposed, and a pixel circuit layer DSL on which various elements constituting the pixel PX are disposed. The gate area GIA on which the various elements constituting the gate driver GD are disposed may be disposed to overlap at least a portion of the active area AA on which the various elements constituting the pixel PX are disposed. For example, the transistors (e.g., PMOS LTPS transistors) included in the driving layer DRL may be disposed on the same layer as at least a portion of the transistors (e.g., PMOS LTPS transistors) included in the pixel circuit layer DSL. For example, the gate driver GD is disposed on the same layer as the pixel circuit layer DSL on which the pixel PX is disposed, and is disposed in an array gate manner and formed on the gate area GIA overlapping the active area AA, so that the border area of ​​the display device 1000 can be minimized or at least reduced.

[0157] In addition, compared to a gate-in-panel (GIP) method in which a gate driver is formed outside the active area to provide a gate signal to the pixel, in the display device 1000 according to the exemplary embodiment of the present invention, the gate driver GD is disposed in at least a partial region of the active area AA, for example, on the gate area GIA, in a gate-in-array (GIA) method. Therefore, a gate signal delay based on a relative position of the pixel PX is minimized or at least reduced to improve the brightness uniformity of the entire active area AA, thereby realizing a display device 1000 having a high resolution and a large area.

[0158] Refer again Figure 5 The printed circuit board PCB can transmit the signal and voltage for driving the display element from the controller to the display element. Therefore, the printed circuit board PCB can also be called a driving substrate. A controller such as an IC chip or a circuit unit can be mounted on the printed circuit board PCB. In addition, a memory, a processor, etc. can also be mounted on the printed circuit board PCB.

[0159] The data driver (DD) 400 may provide data signals to the pixels PX disposed in the active area AA. For example, the data driver (DD) 400 may provide data signals to the pixels PX via data lines.

[0160] In one exemplary embodiment, the data driver (DD) 400 is configured as an integrated circuit chip (IC chip), referred to as a data integrated circuit. The data driver (DD) 400 may be mounted in the form of an IC chip on a connection film COF. Figure 5 4 shows that the data driver (DD) 400 is mounted in a chip on film (COF) manner, but the exemplary embodiment of the present invention is not limited thereto. For example, the data driver (DD) 400 may also be mounted in a chip on board (COB), a chip on glass (COG), or a tape carrier package (TCP) manner.

[0161] In the following, reference will be made to Figure 8 A detailed cross-sectional structure of the pixel circuit layer DSL included in the display panel DP is described. Figure 8 It is a graphic Figure 7 A cross-sectional view of an example display panel.

[0162] Reference Figure 5 , 7 8, at least one transistor TR_P and TR_O and a light emitting diode LD may be disposed on a substrate SUB. Meanwhile, the first type transistor TR_P among the transistors disposed on the substrate SUB may be a polycrystalline silicon semiconductor transistor. For example, the first type transistor TR_P may be a p-type MOSFET transistor (PMOS transistor) including a polycrystalline silicon semiconductor layer formed by a low temperature polycrystalline silicon (LTPS) process as an active layer (channel).

[0163] In an exemplary embodiment, Figure 8 As shown, the second type transistor TR_O may be disposed on the first type transistor TR_P. In an exemplary embodiment, the first type transistor TR_P may be disposed on the first type transistor TR_P. Figure 4 The pixel PX described herein includes at least one of the driving transistor DT, the second transistor T2, the third transistor T3, and the fourth transistor T4.

[0164] In addition, in one exemplary embodiment, the transistors of the gate driver GD (eg, PMOS LTPS transistors) are disposed on the same layer as the PMOS LTPS transistors in the transistors constituting the pixel PX. Figure 3 At least one of the first to seventh stage transistors M1 to M7 included in the described gate driver GD.

[0165] In addition, the second type transistor TR_O among the transistors provided on the substrate SUB may be an oxide semiconductor transistor. For example, the second type transistor TR_O may be an n-type MOSFET transistor (NMOS transistor) including an oxide semiconductor layer as an active layer (channel). For example, the second type transistor TR_O may be a reference Figure 4 The pixel PX described herein includes at least one of a first transistor T1, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7.

[0166] The substrate SUB is a basic component of the pixel circuit layer DSL and may be a transparent and transmissive substrate in nature. The substrate SUB may be a flexible substrate formed of a plastic material. Here, the flexible property may be interpreted as having the same meaning as bendable, unbreakable, rollable, and foldable properties.

[0167] For example, the substrate SUB may include plastic, and in this case, the substrate SUB may be referred to as a plastic film or a plastic substrate. For example, the substrate SUB may include at least one selected from the group consisting of polyester-based polymers, silicon-based polymers, acrylic polymers, polyolefin-based polymers, and polymers thereof. For example, the substrate SUB may include polyimide (PI).

[0168] Meanwhile, when the substrate SUB includes polyimide (PI), moisture passes through the substrate SUB formed of polyimide (PI) and penetrates a thin film transistor or the like included in the pixel PX, thereby reducing reliability of the pixel PX, thereby degrading performance of the display device 1000 .

[0169] Therefore, in an exemplary embodiment, the substrate SUB may include double polyimide (PI). In addition, the substrate SUB further includes an inorganic film formed between the double polyimide (PI) to block moisture components from penetrating the lower polyimide (PI), thereby further improving the reliability of product performance. In addition, the inorganic film is formed between the double polyimide (PI) to block the charge charged in the lower polyimide (PI), thereby further improving the reliability of the product.

[0170] For example, Figure 8 As shown, the substrate SUB may include: a first sub-substrate SUBa including polyimide (PI); a second substrate SUBb disposed on the first sub-substrate SUBa and including an inorganic insulating material; and a third sub-substrate SUBc disposed on the second sub-substrate SUBb and including polyimide PI.

[0171] The inorganic insulating material included in the second sub-substrate SUBb may be formed by a single layer or a multilayer of silicon nitride (SiNx) or silicon oxide (SiOx). However, this is exemplary, and the exemplary embodiments of the present invention are not limited thereto. For example, the inorganic insulating material included in the second sub-substrate SUBb may include a silicon oxide (SiOx) material. For example, the inorganic insulating material included in the second sub-substrate SUBb may include silicon dioxide (silica, SiO2). As another example, the inorganic insulating material included in the second sub-substrate SUBb may be formed by a double layer of silicon dioxide (SiO2) and silicon nitride (SiNx).

[0172] At the same time, although not Figure 8 Although shown separately in the figure, the black plate and the metal plate may be further disposed under the substrate SUB.

[0173] A shielding metal layer including at least one shielding metal pattern BSM may be disposed on the substrate SUB. The shielding metal pattern BSM included in the shielding metal layer may be formed by a single layer or multiple layers formed of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0174] According to example embodiments, the shielding metal pattern BSM may be defined as a component included in the first type transistor TR_P. For example, the shielding metal pattern BSM may constitute a lower gate of the first type transistor TR_P.

[0175] The first buffer layer BUF1 may be disposed on the substrate SUB. For example, the first buffer layer BUF1 may be disposed on the substrate SUB to cover the shielding metal pattern BSM.

[0176] In an exemplary embodiment, the first buffer layer BUF1 may include a multi-buffer layer BUF1a disposed on the substrate SUB and an active buffer layer BUF1b disposed on the multi-buffer layer BUF1a.

[0177] The first type transistor TR_P may be disposed on the first buffer layer BUF1. The first type transistor TR_P may include a first semiconductor pattern ACT_P, a first gate G1, a source SE1, and a drain DE1. According to an exemplary embodiment, as described above, the first type transistor TR_P may further include a shielding metal pattern BSM disposed between the first buffer layer BUF1 and the substrate SUB. The first semiconductor layer including at least one first semiconductor pattern ACT_P may be disposed on the first buffer layer BUF1.

[0178] For example, a first semiconductor pattern ACT_P of a first semiconductor layer included in the first type transistor TR_P may be disposed on the first buffer layer BUF1. The first semiconductor pattern ACT_P may include a first region S1 (or source or source region), a second region D1 (or drain or drain region), and a channel region A1 between the first region S1 and the second region D1. In addition, as described above, the first semiconductor pattern ACT_P may include a polycrystalline silicon semiconductor layer formed by a low temperature polysilicon (LTPS) process.

[0179] For example, the first gate insulating layer GI1 may be disposed on the first semiconductor layer, for example, the first semiconductor pattern ACT_P. For example, the first gate insulating layer GI1 is disposed to cover the first semiconductor layer, for example, the first semiconductor pattern ACT_P, to insulate the first semiconductor pattern ACT_P of the first type transistor TR_P from the first gate G1.

[0180] For example, the first gate insulating layer GI1 may be configured by a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multi-layer thereof, but is not limited thereto.

[0181] The first conductive layer GAT1 may be disposed on the first gate insulating layer GI1. The first conductive layer GAT1 may constitute at least a portion of the light emitting control line Ei, the third power line PL3 configured to provide the first initialization voltage VINIT, or the second scan line S2i. Here, the first conductive layer GAT1 constitutes at least a portion of the third power line PL3 configured to provide the first initialization voltage VINIT, so that the first conductive layer GAT1 may include a material having high conductivity, such as a metal or a conductive oxide. For example, the first conductive layer GAT1 may be formed by a single layer or multiple layers including aluminum (Al), copper (Cu), or titanium (Ti). In some exemplary embodiments, the first conductive layer GAT1 may be provided as three layers of titanium, aluminum, and titanium (Ti / Al / Ti) disposed in sequence.

[0182] The first gate G1 of the first type transistor TR_P constituting at least a portion of the light emission control line (eg, Ei) or the scan line (eg, S2i) of the first conductive layer GAT1 may be disposed on the first gate insulating layer GI1.

[0183] The first gate G1 of the first type transistor TR_P may be disposed to at least partially overlap the first semiconductor pattern ACT_P.

[0184] The first insulating layer ILD1 may be disposed on the first conductive layer GAT1, for example, the first gate G1 of the first type transistor TR_P. For example, the first insulating layer ILD1 may be disposed to cover the first conductive layer GAT1, for example, the first gate G1 of the first type transistor TR_P. The first insulating layer ILD1 may be configured by a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multilayer thereof, but is not limited thereto.

[0185] The second conductive layer TM1 may be disposed on the first insulating layer ILD1. The second conductive layer TM1 includes at least one of molybdenum (Mo), copper (Cu), and titanium (Ti), and may be formed by a single layer or a multilayer.

[0186] The second insulating layer ILD2 may be disposed on the second conductive layer TM1. For example, the second insulating layer ILD2 may be disposed to cover the second conductive layer TM1.

[0187] The second insulating layer ILD2 may be configured by a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multi-layer thereof, but is not limited thereto.

[0188] The third conductive layer TM2 may be disposed on the second insulating layer ILD2. The third conductive layer TM2 includes at least one of molybdenum (Mo), copper (Cu), and titanium (Ti), and may be formed by a single layer or a multilayer.

[0189] For example, the first source SE1 and the first drain DE1 of the first type transistor TR_P of the third conductive layer TM2 may be disposed on the second insulating layer ILD2. The first source SE1 of the first type transistor TR_P of the third conductive layer TM2 may contact the first region S1 of the first semiconductor pattern ACT_P via a contact hole passing through the second insulating layer ILD2, the first insulating layer ILD1, and the first gate insulating layer GI1. The first drain DE1 of the first type transistor TR_P of the third conductive layer TM2 may contact the second region D1 of the first semiconductor pattern ACT_P via a contact hole passing through the second insulating layer ILD2, the first insulating layer ILD1, and the first gate insulating layer GI1.

[0190] The third insulating layer ILD3 may be disposed on the third conductive layer TM2, for example, the first source SE1 and the first drain DE1 of the first type transistor TR_P. For example, the third insulating layer ILD3 may be disposed to cover the third conductive layer TM2.

[0191] The third insulating layer ILD3 may be configured by a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multi-layer thereof, but is not limited thereto.

[0192] The second buffer layer BUF2 may be disposed on the third insulating layer ILD3 .

[0193] The second buffer layer BUF2 may be configured by a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multi-layer thereof, but is not limited thereto.

[0194] A second semiconductor layer including at least one second semiconductor pattern ACT_O may be disposed on the second buffer layer BUF2 .

[0195] For example, the second semiconductor pattern ACT_O of the second semiconductor layer included in the second type transistor TR_O may be disposed on the second buffer layer BUF2. The second semiconductor pattern ACT_O may include a first region S2 (or source or source region), a second region D2 (or drain or drain region), and a channel region A2 between the first region S2 and the second region D2. In addition, as described above, the second semiconductor pattern ACT_O may include an oxide semiconductor layer.

[0196] The second gate insulating layer GI2 may be disposed on the second semiconductor layer, for example, the second semiconductor pattern ACT_O. The second gate insulating layer GI2 may be configured by a single layer of silicon nitride (SiNx) or silicon oxide (SiOx) or a multi-layer thereof, but is not limited thereto.

[0197] The fourth conductive layer GAT2 may be disposed on the second gate insulating layer GI2. The fourth conductive layer GAT2 includes at least one of molybdenum (Mo), copper (Cu), and titanium (Ti), and may be formed by a single layer or a multilayer.

[0198] For example, the second gates G2 of the second type transistors TR_O of at least some of the scan lines (eg, S1i, S3i, and S4i) constituting the fourth conductive layer GAT2 may be disposed on the second gate insulating layer GI2.

[0199] The second gate G2 of the second type transistor TR_O may be disposed to at least partially overlap the second semiconductor pattern ACT_O.

[0200] The fourth insulating layer ILD4 may be disposed on the fourth conductive layer GAT2, for example, the second gate G2 of the second type transistor TR_O. For example, the fourth insulating layer ILD4 may be disposed to cover the fourth conductive layer GAT2, for example, the second gate G2 of the second type transistor TR_O.

[0201] The fifth conductive layer SD1 may be disposed on the fourth insulating layer ILD4. The fifth conductive layer SD1 may constitute a reference Figure 4The fourth power line PL4 configured to provide the second initialization voltage VAR or the fifth power line PL5 configured to provide the bias voltage VOBS is at least a portion of the fourth power line PL4 configured to provide the second initialization voltage VAR or the fifth power line PL5 configured to provide the bias voltage VOBS. Here, the fifth conductive layer SD1 constitutes at least a portion of the fourth power line PL4 configured to provide the second initialization voltage VAR or the fifth power line PL5 configured to provide the bias voltage VOBS, so that the fifth conductive layer SD1 may include a material with high conductivity, such as a metal or a conductive oxide. For example, the fifth conductive layer SD1 may be formed by a single layer or multiple layers containing aluminum (Al), copper (Cu), or titanium (Ti). In some exemplary embodiments, the fifth conductive layer SD1 may be provided as three layers of titanium, aluminum, and titanium (Ti / Al / Ti) disposed in sequence.

[0202] In addition, at least a portion of the fifth conductive layer SD1 may be used as a connection electrode. For example, at least a portion of the fifth conductive layer SD1 is connected to the source SE1 and / or drain DE1 of the first type transistor TR_P of the third conductive layer TM2 via a contact hole passing through the fourth insulating layer ILD4, the second gate insulating layer GI2, the second buffer layer BUF2, and the third insulating layer ILD3. Alternatively, at least a portion of the fifth conductive layer SD1 may contact a portion of the fourth conductive layer GAT2 via a contact hole passing through the fourth insulating layer ILD4.

[0203] In addition, at least a portion of the fifth conductive layer SD1 may constitute a second source SE2 and a second drain DE2 of the second type transistor TR_O. For example, the second source SE2 of the second type transistor TR_O of the fifth conductive layer SD1 may contact the first region S2 of the second semiconductor pattern ACT_O via a contact hole passing through the fourth insulating layer ILD4 and the second gate insulating layer GI2. The second drain DE2 of the second type transistor TR_O of the fifth conductive layer SD1 may contact the second region D2 of the second semiconductor pattern ACT_O via a contact hole passing through the fourth insulating layer ILD4 and the second gate insulating layer GI2.

[0204] In one exemplary embodiment, at least a portion of the fifth conductive layer SD1 may constitute a Figures 5 to 7The clock line CLK connected to the driving layer DRL of the display panel DP described above. For example, at least a portion of the fifth conductive layer SD1 may constitute the clock line CLK for transmitting a clock signal as an input signal of each stage included in the gate driver GD (e.g., the scanning driver 200 and / or the light emitting driver 300). For example, the clock line CLK of the fifth conductive layer SD1 for transmitting the clock signal may be electrically connected to each stage of the gate driver GD provided on the driving layer DRL (e.g., at least a portion of the transistors constituting each stage) through a line jumping structure. For example, as described above, at least some of the first type transistors TR_P constitute at least some of the stage transistors M1 to M7 of the gate driver GD, so that at least a portion of the fifth conductive layer SD1 constituting the clock line CLK may be electrically connected to any one of the first type transistors TR_P.

[0205] The first planarization layer PNL1 may be disposed on the fifth conductive layer SD1. The first planarization layer PNL1 may be an organic layer that planarizes the upper portion and protects components disposed thereunder. For example, the first planarization layer PNL1 may include an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0206] The sixth conductive layer SD2 may be disposed on the first planarization layer PNL1.

[0207] The sixth conductive layer SD2 may constitute a reference Figure 4 The data line Dj is at least a portion of the first power line PL1 configured to provide the first power supply voltage VDD. Here, the sixth conductive layer SD2 constitutes at least a portion of the first power line PL1 configured to provide the first power supply voltage VDD, so that the sixth conductive layer SD2 may include a material having high conductivity, such as a metal or a conductive oxide. For example, the sixth conductive layer SD2 may be formed by a single layer or multiple layers including aluminum (Al), copper (Cu), or titanium (Ti). In some exemplary embodiments, the sixth conductive layer SD2 may be provided as three layers of titanium, aluminum, and titanium (Ti / Al / Ti) provided in sequence.

[0208] In addition, at least a portion of the sixth conductive layer SD2 may be used as a connection electrode. For example, at least a portion of the sixth conductive layer SD2 may be connected to at least a portion of the fifth conductive layer SD1 via a contact hole passing through the first planarization layer PLN1.

[0209] The second planarization layer PNL2 may be disposed on the sixth conductive layer SD2. The second planarization layer PNL2 may be an organic layer that planarizes the upper portion and protects components disposed thereunder. For example, the second planarization layer PNL2 may include an organic material such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, or a polyimide resin.

[0210] The seventh conductive layer SD3 may be disposed on the second planarization layer PNL2. The seventh conductive layer SD3 may be formed of a single layer or multiple layers formed of any one of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), and neodymium (Nd), or an alloy thereof.

[0211] In an exemplary embodiment, at least a portion of the seventh conductive layer SD3 may be used as a shielding pattern SM. For example, as described above, at least a portion of the fifth conductive layer SD1 constitutes at least a portion of a clock line CLK for transmitting a clock signal to the gate driver GD of the driving layer DRL. Therefore, there may be signal interference between the clock line CLK of the fifth conductive layer SD1 and the anode AND of the light emitting diode LD of the light emitting diode layer EPL disposed above the display element layer DPL. In this case, the voltage of the anode AND of the light emitting diode LD (for example, referring to Figure 4 The voltage of the fourth node N4 described above) is unstable, which may degrade the display quality of the desired pixel PX. Therefore, in the case of the display device 1000 according to the exemplary embodiment of the present invention, the seventh conductive layer SD3 disposed above the second planarization layer PNL2 serves as a shielding pattern SM, which is located between the clock line CLK and the light emitting diode LD, and shields a signal between at least a portion of the fifth conductive layer SD1 (e.g., the clock line CLK) and the anode AND of the light emitting diode LD of the light emitting diode layer EPL. Therefore, the display quality can be improved.

[0212] According to an exemplary embodiment, for the shielding function, the shielding pattern SM of the seventh conductive layer SD3 may have a width greater than that of the anode AND of the light emitting diode LD. In addition, at least a portion of the seventh conductive layer SD3 may be connected to at least a portion of the sixth conductive layer SD2 via a contact hole passing through the second planarization layer PNL2.

[0213] The third planarization layer PNL3 may be disposed on the seventh conductive layer SD3. The third planarization layer PNL3 may be an organic layer that planarizes the upper portion and protects components disposed thereunder. For example, the third planarization layer PNL3 may include an organic material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, or polyimide resin.

[0214] The light emitting diode LD may be disposed on the third planarization layer PNL3. The light emitting diode LD may include an anode AND (or first electrode), a cathode CAD (or second electrode), and a light emitting layer EML formed between the anode AND and the cathode CAD. The anode AND may be disposed on the third planarization layer PNL3.

[0215] Meanwhile, when the display device 1000 is a top emission type (in which light emitted from the light emitting diode LD is emitted above the substrate SUB in which the light emitting diode LD is disposed), the anode AND may further include a transparent conductive layer and a reflective layer on the transparent conductive layer. The transparent conductive layer may be formed of a transparent conductive oxide such as ITO or IZO; for example, the reflective layer may include silver (Ag), aluminum (Al), gold (Au), molybdenum (Mo), tungsten (W), chromium (Cr), or an alloy thereof.

[0216] The bank layer BNK is provided to cover at least a portion of the anode AND, and the rest of the anode AND may be opened. For example, the bank layer BNK may be provided to open a portion corresponding to the light emitting region of the pixel PX. Therefore, a portion of the anode AND may be exposed through the opening of the bank layer BNK. The bank layer BNK may include an inorganic insulating material such as silicon nitride (SiNx) or silicon oxide (SiOx) or an organic insulating material such as a benzocyclobutene resin, an acrylic resin, or an imide resin, but is not limited thereto.

[0217] The light emitting layer EML may be disposed on the entire surface of the pixel PX on the top surfaces of the bank layer BNK and the anode AND. Meanwhile, a portion of the light emitting layer EML may contact the exposed portion of the anode AND through the opening of the bank layer BNK. According to an exemplary embodiment, the light emitting layer EML may include a plurality of organic films.

[0218] The cathode CAD may be disposed on the light emitting layer EML. For example, the cathode CAD may be disposed on the front surface of the pixel PX. The light emitting diode LD may be formed by the anode AND, the light emitting layer EML, and the cathode CAD.

[0219] Meanwhile, a spacer SPC may be provided to prevent a screen mask and a substrate from contacting each other during a process of depositing the light emitting area EML. The spacer SPC is provided on the bank layer BNK, and the light emitting layer EML and the cathode CAD may be coated to pass over the spacer SPC provided in the active area AA.

[0220] According to exemplary embodiments, the light emitting layer EML and / or the cathode CAD may not cross the spacer SPC. The spacer SPC is disposed only in a portion of the bank layer BNK in the active area AA, so that the cathode CAD may be connected while covering the entire active area AA even if the cathode CAD does not cross the spacer SPC.

[0221] The encapsulation layer may be disposed above the light emitting diode LD. For example, the encapsulation layer may include a first inorganic encapsulation layer PAS1, an organic encapsulation layer PCL on the first inorganic encapsulation layer PAS1, and a second inorganic encapsulation layer PAS2 on the organic encapsulation layer PCL. The first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 may be used to block the penetration of moisture or oxygen. For example, the first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 may be formed of an inorganic material such as silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, or titanium nitride. The first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2 may be formed by a chemical vapor deposition process or an atomic layer deposition process.

[0222] The organic encapsulation layer PCL may be disposed between the first inorganic encapsulation layer PAS1 and the second inorganic encapsulation layer PAS2. The organic encapsulation layer PCL may be formed to have a thickness greater than that of the first inorganic encapsulation layer PAS1 and / or the second inorganic encapsulation layer PAS2 to adsorb and / or block particles that may be generated during the manufacturing process. The organic encapsulation layer PCL may be formed of an organic material such as silicon carbide SiOCz acryl or epoxy resin. The organic encapsulation layer PCL may be formed by a coating process such as an inkjet coating process or a slit coating process.

[0223] Fig. 9 It is illustrated in Figure 5 Layout of an example of pixels included in a display device. Fig.10 It is a diagram along Fig. 9 A cross-sectional view of the example taken along line II'.

[0224] To avoid redundant descriptions, separate the main description from the reference Figures 1 to 8 Parts that are not described in detail follow the description of the above exemplary embodiments, and the same reference numerals refer to the same elements, and similar reference numerals refer to similar elements.

[0225] At the same time, Fig. 9 , a first pixel PX1, a second pixel PX2, a third pixel PX3 and a fourth pixel PX4 are shown, which are similar to those in the reference Figure 4 The described pixels PX are substantially the same and are disposed in the first pixel area PXA1 , the second pixel area PXA2 , the third pixel area PXA3 , and the fourth pixel area PXA4 , respectively.

[0226] at the same time, Fig. 9 The pixels PX1 to PX4 shown can be compared with the reference Figures 1 to 8 The pixels PX disposed on the display panel DP (eg, the pixel circuit layer DSL) of the display device 1000 described above are substantially the same. Figures 1 to 9The display panel DP, for example, the pixel circuit layer DSL may include a pixel area PXA in which the pixels PX are arranged. Fig. 9 As shown, the pixel area PXA may include a first pixel area PXA1, a second pixel area PXA2, a third pixel area PXA3, and a fourth pixel area PXA4. The first pixel PX1 is disposed in the first pixel area PXA1, the second pixel PX2 is disposed in the second pixel area PXA2, the third pixel PX3 is disposed in the third pixel area PXA3, and the fourth pixel PX4 is disposed in the fourth pixel area PXA4. The first pixel PX1 and the second pixel PX2 may be symmetrical to each other with respect to the second direction DR2, the third pixel PX3 and the fourth pixel PX4 may be symmetrical to each other with respect to the second direction DR2, the first pixel PX1 and the third pixel PX3 may be symmetrical to each other with respect to the first direction DR1, and the second pixel PX2 and the fourth pixel PX4 may be symmetrical to each other with respect to the first direction DR1.

[0227] In an exemplary embodiment, the pixel PX (or pixel region PXA) may have a vertical flip structure. For example, the first pixel region PXA1 and the second pixel region PXA2 are disposed adjacent to each other along the first direction DR1 and may be symmetrical to each other about the first power line PL1 extending along the second direction DR2.

[0228] In addition, the third pixel region PXA3 and the fourth pixel region PXA4 are disposed adjacent to each other along the first direction DR1, and may be symmetrical to each other about the first power line PL1 extending along the second direction DR2. In addition, the first pixel region PXA1 and the third pixel region PXA3 are disposed adjacent to each other along the second direction DR2, and may be symmetrical to each other about the fourth power line PL4 and / or the fifth power line PL5 extending along the first direction DR1. In addition, the second pixel region PXA2 and the fourth pixel region PXA4 are disposed adjacent to each other along the second direction DR2, and may be symmetrical to each other about the fourth power line PL4 and / or the fifth power line PL5 extending along the first direction DR1. The third pixel region PXA3 may be spaced apart from the first pixel region PXA1 by a predetermined interval along the second direction DR2. The fourth pixel region PXA4 may be spaced apart from the second pixel region PXA2 by a predetermined interval along the second direction DR2.

[0229] Therefore, the first pixel PX1, the second pixel PX2, the third pixel PX3, and the fourth pixel PX4 may include substantially similar or identical configurations. Therefore, hereinafter, one pixel PX disposed in one pixel area PXA will be described with respect to the first pixel PX1 disposed in the first pixel area PXA1. For the second pixel PX2, the third pixel PX3, and the fourth pixel PX4 disposed in the second pixel area PXA2, the third pixel area PXA3, and the fourth pixel area PXA4, respectively, redundant descriptions will not be repeated.

[0230] In an exemplary embodiment, the pixel area PXA may include a central area CA disposed between the first pixel area PXA1 and the second pixel area PXA2 and between the third pixel area PXA3 and the fourth pixel area PXA4. Here, the central area CA may be Figures 5 to 7 For example, in the central area CA of the pixel area PXA of the pixel circuit layer DSL, a gate driver GD located on the gate area GIA of the driving layer DRL may be provided. In other words, transistors, capacitors, and signal lines constituting the gate driver GD may be provided on the central area CA of the pixel area PXA of the pixel circuit layer DSL.

[0231] According to an exemplary embodiment, the central area CA extends along the first direction DR1 to be disposed on the entire active area AA. For example, the central area CA may be responsive to the reference Figure 5 In addition, according to an exemplary embodiment, the width of the central area CA along the second direction DR2 may be smaller than the width of each pixel area PXA1, PXA2, PXA3 or PXA4 along the second direction DR2. However, this is exemplary and the exemplary embodiments of the present invention are not limited thereto.

[0232] Further references Fig.10 , the substrate SUB and the first buffer layer BUF1 may be sequentially disposed on the pixel area PXA. According to example embodiments, a shielding metal layer including a shielding metal pattern BSM may be disposed between the substrate SUB and the first buffer layer BUF1.

[0233] A first semiconductor layer including at least one first semiconductor pattern ACT_P may be disposed on the first buffer layer BUF1. Fig.10 As shown, a first semiconductor pattern ACT_P of the second transistor T2 and a first semiconductor pattern ACT_P of the third transistor T3 may be provided.

[0234] The first gate insulating layer GI1 may be disposed on the first semiconductor layer, and the first conductive layer GAT1 may be disposed on the first gate insulating layer GI1. Fig.10 As shown, the first gate G1_T2 of the second transistor T2 constituting at least a portion of the second scan line S2i of the first conductive layer GAT1 may be disposed on the first gate insulating layer GI1.

[0235] In addition, if Fig. 9As shown, the first conductive layer GAT1 extends along the first direction DR1 with respect to the first pixel area PXA1 and the second pixel area PXA2, and may include a third power line PL3, a second scan line S2i, and a light emission control line Ei sequentially disposed along the second direction DR2. On the first pixel area PXA1 and the second pixel area PXA2, the third power line PL3, the fourth scan line, the second scan line, the first scan line, the light emission control line, and the third scan line may be sequentially disposed along the second direction DR2 and spaced apart from each other.

[0236] Meanwhile, as described above, the pixel PX (or pixel area PXA) has a vertical flip structure (for example, the first pixel area PXA1 and the third pixel area PXA3 are symmetrical to each other, and the second pixel area PXA2 and the fourth pixel area PXA4 are symmetrical to each other). With respect to the third pixel area PXA3 and the fourth pixel area PXA4, the light emission control line Ei+1, the second scan line S2i+1, and the third power supply line PL3 included in the first conductive layer GAT1 extend along the first direction DR1. The light emission control line Ei+1, the second scan line S2i+1, and the third power supply line PL3 may be sequentially arranged in this order along the second direction DR2.

[0237] For example, the arrangement order of the third power line PL3, the second scan line S2i, and the light emission control line Ei included in the first conductive layer GAT1 in the first pixel area PXA1 and the second pixel area PXA2 along the second direction DR2 may be opposite to the arrangement order of the light emission control line Ei+1, the second scan line S2i+1, and the third power line PL3 included in the first conductive layer GAT1 in the third pixel area PXA3 and the fourth pixel area PXA4 along the second direction DR2. In the third pixel area PXA3 and the fourth pixel area PXA4, the third scan line, the light emission control line, the first scan line, the second scan line, the fourth scan line, and the third power line PL3 may be sequentially arranged spaced apart from each other along the second direction DR2.

[0238] A first insulating layer ILD1 , a second conductive layer TM1 , and a second insulating layer ILD2 may be sequentially disposed on the first conductive layer GAT1 .

[0239] The third conductive layer TM2 may be disposed on the second insulating layer ILD2. Fig.10 As shown, a portion of the third conductive layer TM2 may constitute the drain DE1_T2 of the second transistor T2, and another portion may constitute the source SE1_T3 of the third transistor T3.

[0240] A third insulating layer ILD3 , a second buffer layer BUF2 , a second semiconductor layer, and a second gate insulating layer GI2 may be sequentially disposed on the third conductive layer TM2 .

[0241] The fourth conductive layer GAT2 may be disposed on the second gate insulating layer GI2. Fig.10 As shown, at least a portion of the fourth conductive layer GAT2 may constitute a first scan line S1i, and at least another portion of the fourth conductive layer GAT2 may constitute a third scan line S3i.

[0242] In addition, if Fig. 9 As shown, the fourth conductive layer GAT2 extends along the first direction DR1 with respect to the first pixel region PXA1 and the second pixel region PXA2, and may include a fourth scan line S4i, a first scan line S1i, and a third scan line S3i sequentially disposed along the second direction DR2.

[0243] Meanwhile, as described above, the pixel PX (or the pixel area PXA) has a vertical flip structure (for example, the first pixel area PXA1 and the third pixel area PXA3 are symmetrical to each other, and the second pixel area PXA2 and the fourth pixel area PXA4 are symmetrical to each other). With respect to the third pixel area PXA3 and the fourth pixel area PXA4, the third scan line S3i+1, the first scan line S1i+1, and the fourth scan line S4i+1 included in the fourth conductive layer GAT2 extend along the first direction DR1. The third scan line S3i+1, the first scan line S1i+1, and the fourth scan line S4i+1 may be sequentially arranged in this order along the second direction DR2.

[0244] For example, the arrangement order of the fourth scan line S4i, the first scan line S1i and the third scan line S3i included in the fourth conductive layer GAT2 in the first pixel area PXA1 and the second pixel area PXA2 along the second direction DR2 and the arrangement order of the third scan line S3i+1, the first scan line S1i+1 and the fourth scan line S4i+1 included in the fourth conductive layer GAT2 in the third pixel area PXA3 and the fourth pixel area PXA4 may be opposite to each other.

[0245] According to an exemplary embodiment, Fig. 9 As shown, the first conductive layer GAT1 and the second conductive layer GAT2 may include different kinds of metal materials. For example, the first conductive layer GAT1 and the second conductive layer GAT2 may include different metal materials.

[0246] Here, the third power line PL3, the second scan line S2i, and the light emission control line Ei included in the first conductive layer GAT1, and the fourth scan line S4i, the first scan line S1i, and the third scan line S3i included in the fourth conductive layer GAT2 may be alternately arranged along the second direction DR2. For example, the third power line PL3 of the first conductive layer GAT1, the fourth scan line S4i of the fourth conductive layer GAT2, the second scan line S2i of the first conductive layer GAT1, the first scan line S1i of the fourth conductive layer GAT2, the light emission control line Ei of the first conductive layer GAT1, and the third scan line S3i of the fourth conductive layer GAT2 may be sequentially arranged with respect to the first pixel area PXA1 and the second pixel area PXA2. As another example, the third scan line S3i of the fourth conductive layer GAT2, the light emitting control line Ei of the first conductive layer GAT1, the first scan line S1i of the fourth conductive layer GAT2, the second scan line S2i of the first conductive layer GAT1, the fourth scan line S4i of the fourth conductive layer GAT2 and the third power line PL3 of the first conductive layer GAT1 can be arranged in sequence with respect to the first pixel area PXA1 and the second pixel area PXA2, and can be arranged in sequence with respect to the third pixel area PXA3 and the fourth pixel area PXA4.

[0247] As described above, the third power line PL3, the second scan line S2i, and the light emission control line Ei included in the first conductive layer GAT1, and the fourth scan line S4i, the first scan line S1i, and the third scan line S3i included in the fourth conductive layer GAT2 which may be made of a different metal material from the first conductive layer GAT1 may be alternately arranged along the second direction DR2. Therefore, the spacing between the signal lines and / or the power lines may be minimized or at least reduced. Thus, ease of design may be ensured.

[0248] The fourth insulating layer ILD4 may be disposed on the fourth conductive layer GAT2 , and the fifth conductive layer SD1 may be disposed on the fourth insulating layer ILD4 .

[0249] In addition, if Fig. 9As shown, the fifth conductive layer SD1 may include a fourth power line PL4 and a fifth power line PL5 extending along the first direction DR1 on the central area CA. According to an exemplary embodiment, the fourth power line PL4 may include a first sub-power line PL4a, a second sub-power line PL4b, and a third sub-power line PL4c; the fifth power line PL5 may include a fourth sub-power line PL5a and a fifth sub-power line PL5b. According to an exemplary embodiment, the first sub-power line PL4a and the third sub-power line PL4c may be the fourth power line PL4 that provides the second initialization voltage VAR to the red pixel and the blue pixel, and the second sub-power line PL4b may be the fourth power line PL4 that provides the second initialization voltage VAR to the green pixel. This is exemplary, and the exemplary embodiment of the present invention is not limited thereto. In addition, the fourth sub-power line PL5a may be the fifth power line PL5 configured to provide the bias voltage VOBS to the first pixel PX1 and the second pixel PX2, and the fifth sub-power line PL5b may be the fifth power line PL5 configured to provide the bias voltage VOBS to the third pixel PX3 and the fourth pixel PX4. However, this is exemplary, and the exemplary embodiment of the present invention is not limited thereto.

[0250] In an exemplary embodiment, the fourth sub-power line PL5a, the first sub-power line PL4a, the second sub-power line PL4b, the third sub-power line PL4c and the fifth sub-power line PL5b extend along the first direction DR1, respectively, and may be sequentially spaced apart from each other along the second direction DR2 on the central area CA.

[0251] Here, in addition to the vertical lines (e.g., the data line Dj included in the sixth conductive layer SD2 as a wiring extending in the second direction DR2, and the first power line PL1 configured to provide the first power supply voltage VDD), only the fourth power line PL4 and the fifth power line PL5 substantially included in the fifth conductive layer SD1 and extending in the first direction DR1 are arranged in the central area CA of the pixel area PXA except for the first to fourth pixel areas PXA1 to PXA4. Therefore, on the gate area GIA corresponding to the central area CA of the driving layer DRL arranged on the same layer as the pixel circuit layer DSL, a space for placing other elements (e.g., a stage transistor included in the gate driver GD) can be ensured. Therefore, the transistors and capacitors constituting the gate driver GD can be arranged on the gate area GIA of the driving layer DRL.

[0252] Refer again Fig.10 , the first planarization layer PNL1 may be disposed on the fifth conductive layer SD1 , and the sixth conductive layer SD2 may be disposed on the first planarization layer PNL1 .

[0253] At the same time, as reference Figure 8As mentioned above, at least a portion of the sixth conductive layer SD2 may constitute a data line Dj extending along the second direction DR2.

[0254] The second planarization layer PNL2 , the seventh conductive layer SD3 , the third planarization layer PNL3 , the light emitting diode LD, and the encapsulation layer may be sequentially disposed on the sixth conductive layer SD2 .

[0255] As described above, in a display device according to an exemplary embodiment of the present invention, a display panel may include: a pixel circuit layer in which pixels are arranged; and a driving layer in which a gate driver is arranged. Here, a gate region in which each element constituting the gate driver is arranged may be arranged to overlap at least a portion of an active region in which each element constituting the pixel is arranged. For example, a transistor included in the driving layer may be arranged on the same layer as at least a portion of a transistor included in the pixel circuit layer. For example, the gate driver may be arranged on the same layer as a pixel circuit layer in which pixels are arranged in a gate-in-array (GIA) manner and formed on a gate region overlapping the active region, thereby minimizing or at least reducing the border area of ​​the display device.

[0256] Compared to a gate-in-panel (GIP) method in which a gate driver is formed outside an active region to provide a gate signal to a pixel, in a display device according to an exemplary embodiment of the present invention, a gate driver is disposed in at least a portion of an active region, for example, on a gate region, in a gate-in-array (GIA) method. Therefore, a gate signal delay based on a relative position of a pixel is minimized or at least reduced to improve brightness uniformity of the entire active region, thereby enabling a display device with high resolution and a large area to be implemented.

[0257] In addition, in the display device according to the exemplary embodiment of the present invention, the seventh conductive layer disposed above the second planarization layer is disposed in a portion of the fifth conductive layer constituting a clock line for providing a clock signal to the gate driver and an anode of the light emitting diode to perform a function as a shielding pattern for shielding a signal. Therefore, the display quality can be improved.

[0258] In addition, the pixel included in the display device according to the exemplary embodiment of the present invention has a vertical flip structure. Therefore, a space for setting transistors and capacitors constituting a gate driver can be ensured on the gate region of the driving layer overlapping the central region of the pixel circuit layer.

[0259] In addition, in the display device according to the exemplary embodiment of the present invention, the third power supply line, the second scan line and the light emitting line included in the first conductive layer, and the fourth scan line, the first scan line and the third scan line included in the fourth conductive layer formed of a different metal material from the first conductive layer are alternately arranged along one direction (the second direction). Therefore, the spacing between each signal line and / or power supply line can be minimized or at least reduced, and the ease of design can be ensured.

[0260] Exemplary embodiments of the present invention can also be described as follows.

[0261] According to an embodiment of one aspect of the present invention, a display device may include: a display panel having a plurality of pixels; and a data driver circuit, the data driver circuit being configured to provide data signals to the plurality of pixels via data lines. A gate driver circuit may be provided in the display panel, the gate driver circuit being configured to provide gate signals to the plurality of pixels via gate lines. The display panel may include: a driving layer, the driving layer including a gate region having the gate driver circuit; and a pixel circuit layer, the pixel circuit layer including an active region having a pixel region and a non-active region around the active region, each of the plurality of pixels being provided in the pixel region. The pixel circuit layer may include a light emitting diode, a clock line configured to provide a clock signal to the gate driver circuit, and a shielding pattern located between the light emitting diode and the clock line.

[0262] The pixel area may include: a first pixel area in which a first pixel among the plurality of pixels is disposed; a second pixel area in which a second pixel is disposed; a third pixel area in which a third pixel is disposed; a fourth pixel area including a fourth pixel; and a central area overlapping the gate area.

[0263] The second pixel region may be adjacent to the first pixel region along a first direction, the third pixel region may be separated from the first pixel region by a predetermined interval along a second direction different from the first direction, and the fourth pixel region may be adjacent to the third pixel region along the first direction and separated from the second pixel region by the predetermined interval along the second direction.

[0264] The central area may be an area between the first pixel area and the third pixel area and an area between the second pixel area and the fourth pixel area.

[0265] At least one of the plurality of pixels may be connected to each of the first to fourth scan lines, the light emission control line, the data line, and the first to fifth power supply voltage lines. The first to fourth scan lines, the light emission control line, and the third to fifth power supply voltage lines may extend along the first direction to be spaced apart from each other. The data line and the first power supply voltage line may extend along the second direction.

[0266] In the first pixel area and the second pixel area, the third power supply voltage line, the fourth scan line, the second scan line, the first scan line, the light-emitting control line and the third scan line can be arranged in sequence along the second direction and spaced apart from each other; in the third pixel area and the fourth pixel area, the third scan line, the light-emitting control line, the first scan line, the second scan line, the fourth scan line and the third power supply voltage line can be arranged in sequence along the second direction and spaced apart from each other.

[0267] The fourth power supply voltage line may include first to third sub-power supply voltage lines, and the fifth power supply voltage line may include fourth and fifth sub-power supply voltage lines; in the central area, the fourth sub-power supply voltage line, the first sub-power supply voltage line, the second sub-power supply voltage line, the third sub-power supply voltage line and the fifth sub-power supply voltage line may be arranged in sequence along the second direction and spaced apart from each other.

[0268] The first pixel and the second pixel may be symmetrical to each other about the second direction, the third pixel and the fourth pixel may be symmetrical to each other about the second direction, the first pixel and the third pixel may be symmetrical to each other about the first direction, and the second pixel and the fourth pixel may be symmetrical to each other about the first direction.

[0269] The pixel circuit layer may include: a display element layer having at least one first type transistor, at least one second type transistor, and at least one capacitor; and a light emitting diode layer having the light emitting diode.

[0270] The first type transistor may include a polysilicon semiconductor layer, and the second type transistor may include an oxide semiconductor layer.

[0271] The display element layer may include: a first buffer layer; a first semiconductor layer on the first buffer layer and including a first semiconductor pattern of the first type transistor; a first gate insulating layer on the first semiconductor layer; a first conductive layer on the first gate insulating layer and including a first gate of the first type transistor; a first insulating layer on the first conductive layer; a second conductive layer on the first insulating layer; a second insulating layer on the second conductive layer; a third conductive layer on the second insulating layer and including a first source and a first drain of the first type transistor; and a third insulating layer on the third conductive layer.

[0272] The display element layer may also include: a second buffer layer on the third insulating layer; a second semiconductor layer on the second buffer layer and including a second semiconductor pattern of the second type transistor; a second gate insulating layer on the second semiconductor layer; a fourth conductive layer on the second gate insulating layer and including a second gate of the second type transistor; a fourth insulating layer on the fourth conductive layer; and a fifth conductive layer on the fourth insulating layer and including a second source and a second drain of the second type transistor.

[0273] The fifth conductive layer may further include the clock line.

[0274] The display element layer may further include: a first planarization layer on the fifth conductive layer; a sixth conductive layer on the first planarization layer; a second planarization layer on the sixth conductive layer; and a seventh conductive layer on the second planarization layer. The seventh conductive layer may include the shielding pattern.

[0275] The shielding pattern may have a width greater than a width of an anode electrode of the light emitting diode.

[0276] Each of the multiple pixels may include a driving transistor, a second transistor, a third transistor, and a fourth transistor, each of which includes a polysilicon semiconductor layer, and a first transistor, a fifth transistor, a sixth transistor, and a seventh transistor, each of which includes an oxide semiconductor layer, and each of the multiple transistors included in the gate driver circuit may include the polysilicon semiconductor layer.

[0277] Each of the plurality of pixels may include: a light emitting diode; a driving transistor connected between a first node and a second node and configured to generate a driving current flowing from a first power line to supply a first power supply voltage to the light emitting diode supplied with a second power supply voltage via a second power line; a first transistor connected between the second node and a third node corresponding to a gate of the driving transistor and configured to be turned on in response to a first scan signal supplied to a first scan line; a second transistor connected between a data line and the first node and configured to be turned on in response to a second scan signal supplied to a second scan line; a third transistor connected between the first power line and the first node and configured to be turned off in response to a light emitting control signal supplied to a light emitting control line; and a fourth transistor connected between the first power line and the first node and configured to be turned off in response to a light emitting control signal supplied to a light emitting control line. a transistor, the fourth transistor being connected between the second node and a fourth node corresponding to the first electrode of the light emitting diode and being configured to be turned off in response to the light emitting control signal; a fifth transistor, the fifth transistor being connected between the third node and a third power line configured to provide a third power supply voltage and being configured to be turned on in response to a fourth scan signal provided to a fourth scan line; a sixth transistor, the sixth transistor being connected between the fourth node and a fourth power line configured to provide a fourth power supply voltage and being configured to be turned on in response to a third scan signal provided to the third scan line; a seventh transistor, the seventh transistor being connected between the first node and a fifth power line configured to provide a fifth power supply voltage and being configured to be turned on in response to the third scan signal; and a storage capacitor connected between the first power line and the third node.

[0278] The driving transistor, the second transistor, the third transistor, and the fourth transistor may include a polysilicon semiconductor layer, and the first transistor, the fifth transistor, the sixth transistor, and the seventh transistor may include an oxide semiconductor layer.

[0279] The driving layer and the pixel circuit layer may be provided on the same layer.

[0280] The display panel may include a plurality of first type transistors and a plurality of second type transistors, at least some of the plurality of first type transistors may be included in the pixel circuit layer, and the rest of the plurality of first type transistors may be included in the driving layer.

[0281] In a plan view of the display panel, the plurality of pixels may be directly located on the gate driving circuit.

[0282] It will be clear to those skilled in the art that various modifications and variations can be made in the display device of the present invention without departing from the technical concept or scope of the present invention. Therefore, the present invention is intended to cover modifications and variations of the present invention that fall within the scope of the appended claims and their equivalents.

Claims

1. A display device, comprising: A display panel having a plurality of pixels; as well as a data driver circuit configured to provide data signals to the plurality of pixels via data lines, A gate driver circuit is provided in the display panel, and the gate driver circuit is configured to provide gate signals to the plurality of pixels via gate lines. The display panel comprises: a driving layer, the driving layer comprising a gate region having the gate driver circuit; as well as a pixel circuit layer, the pixel circuit layer including an active area having a pixel region and an inactive area around the active area, each of the plurality of pixels being disposed in the pixel region, The pixel circuit layer includes a light emitting diode, a clock line configured to provide a clock signal to the gate driver circuit, and a shielding pattern located between the light emitting diode and the clock line.

2. The display device according to claim 1, wherein the pixel area comprises: a first pixel region, in which a first pixel among the plurality of pixels is disposed; a second pixel region in which a second pixel is disposed; a third pixel region in which a third pixel is disposed; a fourth pixel region in which a fourth pixel is included; and a central region overlapping the gate region.

3. The display device according to claim 2, wherein the second pixel region is adjacent to the first pixel region along a first direction, the third pixel region is separated from the first pixel region by a predetermined interval along a second direction different from the first direction, and the fourth pixel region is adjacent to the third pixel region along the first direction and separated from the second pixel region by the predetermined interval along the second direction. 4 . The display device according to claim 3 , wherein the central area is an area between the first pixel area and the third pixel area and an area between the second pixel area and the fourth pixel area.

5. The display device according to claim 3, wherein at least one pixel among the plurality of pixels is connected to each of the first to fourth scan lines, the light emission control line, the data line, and the first to fifth power supply voltage lines, wherein the first to fourth scan lines, the light emitting control lines, and the third to fifth power supply voltage lines extend along the first direction to be spaced apart from each other, The data line and the first power supply voltage line extend along the second direction.

6. The display device according to claim 5, wherein on the first pixel area and the second pixel area, a third power supply voltage line, a fourth scan line, a second scan line, a first scan line, the light emitting control line and a third scan line are sequentially arranged spaced apart from each other along the second direction, Wherein, on the third pixel area and the fourth pixel area, the third scan line, the light emitting control line, the first scan line, the second scan line, the fourth scan line and the third power supply voltage line are sequentially arranged along the second direction and spaced apart from each other.

7. The display device according to claim 5, wherein the fourth power supply voltage line includes first to third sub-power supply voltage lines, the fifth power supply voltage line includes fourth and fifth sub-power supply voltage lines, Wherein, in the central area, the fourth sub-power supply voltage line, the first sub-power supply voltage line, the second sub-power supply voltage line, the third sub-power supply voltage line and the fifth sub-power supply voltage line are sequentially arranged along the second direction and spaced apart from each other.

8. The display device according to claim 3, wherein the first pixel and the second pixel are symmetrical to each other about the second direction, the third pixel and the fourth pixel are symmetrical to each other about the second direction, the first pixel and the third pixel are symmetrical to each other about the first direction, and the second pixel and the fourth pixel are symmetrical to each other about the first direction.

9. The display device according to claim 1, wherein the pixel circuit layer comprises: A display element layer having at least one first type transistor, at least one second type transistor, and at least one capacitor; as well as A light emitting diode layer having the light emitting diode. 10 . The display device according to claim 9 , wherein the first type transistor includes a polysilicon semiconductor layer, and the second type transistor includes an oxide semiconductor layer.

11. The display device according to claim 9, wherein the display element layer comprises: A first buffer layer; a first semiconductor layer on the first buffer layer and including a first semiconductor pattern of the first type transistor; a first gate insulating layer on the first semiconductor layer; a first conductive layer on the first gate insulating layer and including a first gate of the first type transistor; a first insulating layer on the first conductive layer; a second conductive layer on the first insulating layer; a second insulating layer on the second conductive layer; a third conductive layer on the second insulating layer and including a first source and a first drain of the first type transistor; as well as A third insulating layer is on the third conductive layer.

12. The display device according to claim 11, wherein the display element layer further comprises: a second buffer layer on the third insulating layer; a second semiconductor layer on the second buffer layer and including a second semiconductor pattern of the second type transistor; a second gate insulating layer on the second semiconductor layer; a fourth conductive layer on the second gate insulating layer and including a second gate of the second type transistor; a fourth insulating layer on the fourth conductive layer; as well as A fifth conductive layer is on the fourth insulating layer and includes a second source and a second drain of the second type transistor. The display device according to claim 12 , wherein the fifth conductive layer further comprises the clock line.

14. The display device according to claim 12, wherein the display element layer further comprises: a first planarization layer on the fifth conductive layer; a sixth conductive layer on the first planarization layer; a second planarization layer on the sixth conductive layer; as well as A seventh conductive layer is disposed on the second planarization layer, wherein the seventh conductive layer includes the shielding pattern. 15 . The display device of claim 14 , wherein a width of the shielding pattern is greater than a width of an anode electrode of the light emitting diode.

16. A display device according to claim 1, wherein each of the plurality of pixels includes a driving transistor, a second transistor, a third transistor and a fourth transistor each including a polycrystalline silicon semiconductor layer and a first transistor, a fifth transistor, a sixth transistor and a seventh transistor each including an oxide semiconductor layer, and each of the plurality of transistors included in the gate driver circuit includes the polycrystalline silicon semiconductor layer.

17. The display device according to claim 1, wherein each of the plurality of pixels comprises: Light Emitting Diodes; a driving transistor connected between the first node and the second node and configured to generate a driving current flowing from the first power line to supply a first power voltage to the light emitting diode supplied with a second power voltage via the second power line; a first transistor connected between the second node and a third node corresponding to the gate of the driving transistor, and configured to be turned on in response to a first scan signal supplied to a first scan line; a second transistor connected between the data line and the first node and configured to be turned on in response to a second scan signal supplied to a second scan line; a third transistor connected between the first power supply line and the first node and configured to be turned off in response to a light emission control signal supplied to a light emission control line; a fourth transistor connected between the second node and a fourth node corresponding to the first electrode of the light emitting diode, and configured to be turned off in response to the light emission control signal; a fifth transistor connected between the third node and a third power line configured to supply a third power supply voltage and configured to be turned on in response to a fourth scan signal supplied to a fourth scan line; a sixth transistor; the sixth transistor is connected between the fourth node and a fourth power line configured to provide a fourth power supply voltage, and the sixth transistor is configured to be turned on in response to a third scan signal supplied to a third scan line; a seventh transistor connected between the first node and a fifth power line configured to provide a fifth power supply voltage, and configured to be turned on in response to the third scan signal; as well as A storage capacitor is connected between the first power line and the third node. 18 . The display device according to claim 17 , wherein the driving transistor, the second transistor, the third transistor, and the fourth transistor include a polysilicon semiconductor layer, and the first transistor, the fifth transistor, the sixth transistor, and the seventh transistor include an oxide semiconductor layer.

19. The display device according to claim 1, wherein the driving layer and the pixel circuit layer are provided on the same layer.

20. The display device according to claim 1, wherein the display panel comprises a plurality of first type transistors and a plurality of second type transistors, wherein at least some of the plurality of first type transistors are included in the pixel circuit layer, and the rest of the plurality of first type transistors are included in the driving layer.

Images