Integrated circuit device

Abstract

The integrated circuit device includes: a lower electrode; a dielectric film covering the lower electrode; an upper electrode covering the dielectric film; and a multilayer interface structure between the dielectric film and the upper electrode, in which the multilayer interface structure includes: a transition metal-aluminum (Al) composite oxide layer including a transition metal oxide layer in which Al atoms are dispersed, the transition metal-Al composite oxide layer being in contact with the dielectric film; and an upper interface layer including a metal oxide or a metal oxynitride, the upper interface layer being in contact with the transition metal-Al composite oxide layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on and claims the benefit of priority from Korean Patent Application No. 10-2023-0116267 filed in the Korean Intellectual Property Office on September 1, 2023, the disclosure of which is incorporated herein in its entirety by reference. Technical Field

[0003] The inventive concept relates to integrated circuit (IC) devices, and more particularly, to IC devices including capacitors. Background Art

[0004] As IC devices become smaller, the space occupied by capacitors is rapidly shrinking. Therefore, it is necessary to develop a structure that can overcome space limitations and design rule limitations in capacitors and improve the capacitance of capacitors to maintain desired electrical characteristics. Summary of the invention

[0005] The inventive concept provides an integrated circuit (IC) device which may have a structure capable of maintaining desired electrical characteristics by providing a capacitor having a relatively high capacitance.

[0006] According to one aspect of the inventive concept, an IC device is provided, comprising: a lower electrode; a dielectric film (dielectric film) covering the lower electrode; an upper electrode covering the dielectric film; and a multilayer interface structure between the dielectric film and the upper electrode, wherein the multilayer interface structure comprises: a transition metal-aluminum (Al) composite oxide layer including a transition metal oxide layer in which Al atoms are dispersed, the transition metal-Al composite oxide layer being in contact with the dielectric film; and an upper interface layer including a metal oxide or a metal oxynitride, the upper interface layer being in contact with the transition metal-Al composite oxide layer.

[0007] According to another aspect of the inventive concept, an IC device is provided, comprising: a substrate including an active region; a conductive region formed on the active region; and a capacitor formed on the conductive region, wherein the capacitor comprises: a lower electrode in contact with the conductive region, a dielectric film covering the lower electrode, an upper electrode covering the dielectric film, and a multilayer interface structure between the dielectric film and the upper electrode, and wherein the multilayer interface structure comprises: a transition metal-aluminum (Al) composite oxide layer including a transition metal oxide layer in which Al atoms are dispersed, the transition metal-Al composite oxide layer in contact with the dielectric film; and an upper interface layer including a metal oxide or a metal oxynitride, the upper interface layer in contact with the transition metal-Al composite oxide layer.

[0008] According to another aspect of the inventive concept, an IC device is provided, comprising: a substrate including an active region; a plurality of conductive regions formed on the active region; an insulating pattern extending in a lateral direction on the plurality of conductive regions, the insulating pattern having a plurality of openings vertically overlapping the plurality of conductive regions; a plurality of lower electrodes extending in a vertical direction through the insulating pattern via the plurality of openings, the plurality of lower electrodes being connected to the plurality of conductive regions; an insulating support pattern extending in a lateral direction and spaced apart from the insulating pattern in a vertical direction, the insulating support pattern contacting with a partial region of each of the plurality of lower electrodes to support the plurality of lower electrodes; a support pattern covering the plurality of lower electrodes, the insulating pattern, and a dielectric film of the insulating support pattern; an upper electrode covering the dielectric film; a lower interface layer between the plurality of lower electrodes and the dielectric film, the lower interface layer being in contact with the dielectric film; and a multilayer interface structure between the dielectric film and the upper electrode, wherein the lower interface layer comprises a Ti oxide film doped with a pentavalent dopant metal, wherein the multilayer interface structure comprises: a transition metal-aluminum (Al) composite oxide layer comprising a transition metal oxide layer in which Al atoms are dispersed, the transition metal-Al composite oxide layer being in contact with the dielectric film; and an upper interface layer comprising a metal oxide or a metal oxynitride, the upper interface layer being in contact with the transition metal-Al composite oxide layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Example embodiments of the present inventive concepts will be more clearly understood from the following detailed description considered in conjunction with the accompanying drawings, in which:

[0010] Figure 1 is a cross-sectional view of major components of an integrated circuit (IC) device according to some example embodiments;

[0011] Figure 2A is a cross-sectional view of a multi-layer interface structure that may be used in an IC device according to some example embodiments;

[0012] Figure 2B is a cross-sectional view of a multi-layer interface structure that may be used in an IC device according to some example embodiments;

[0013] Figure 3 illustrates a schematic planar layout of some components of a memory cell array region of an IC device according to some example embodiments;

[0014] Figure 4A is a plan view of some components of a memory cell region of an IC device according to some example embodiments;

[0015] Figure 4B For and along Figure 4A Schematic cross-sectional views of some components corresponding to the cross-section taken along line 2X–2X′;

[0016] Figure 4C for Figure 4B an enlarged cross-sectional view of a region “EX1”;

[0017] Figures 5A to 5J is a cross-sectional view showing a process sequence of a method for manufacturing an IC device according to some example embodiments;

[0018] Fig. 6A is a graph of X-ray diffraction (XRD) measurement results showing a comparison of crystallinity of dielectric films included in capacitors of IC devices according to some example embodiments and comparative examples;

[0019] Figure 6B is a graph of measurement results showing a comparison of capacitances of capacitors of IC devices according to some example embodiments and comparative examples; and

[0020] Fig. 7A , 7B 7C are graphs of XRD measurement results showing a comparison of crystallinity of dielectric films included in capacitors of IC devices according to some example embodiments and comparative examples. DETAILED DESCRIPTION

[0021] Hereinafter, some example embodiments will be described in detail with reference to the accompanying drawings. The same reference numerals are used to denote the same elements in the accompanying drawings, and their repeated description will be omitted.

[0022] Figure 1 is a cross-sectional view of major components of an integrated circuit (IC) device 100 according to some example embodiments.

[0023] Reference Figure 1 , the IC device 100 may include a substrate 102 , a lower structure 120 formed on the substrate 102 , and a capacitor CP1 formed on the lower structure 120 .

[0024] The substrate 102 may include a semiconductor element (element) such as silicon (Si) and / or germanium (Ge), or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and / or indium phosphide (InP). The substrate 102 may include: a semiconductor substrate; and a structure including at least one insulating film and / or at least one conductive region formed on the semiconductor substrate. The at least one conductive region may include, for example, a doped well or a doped structure. In some example embodiments, the substrate 102 may include a plurality of device isolation structures, such as a shallow trench isolation (STI) structure.

[0025] In some example embodiments, the lower structure 120 may include an insulating film. In other example embodiments, the lower structure 120 may include various conductive regions such as wiring layers, contact plugs, and transistors, and an insulating film configured to electrically insulate the conductive regions from each other.

[0026] The capacitor CP1 may include a lower electrode LE1, a dielectric film 160 covering the lower electrode LE1, an upper electrode UE1 covering the dielectric film 160, and a multilayer interface structure 170 between the dielectric film 160 and the upper electrode UE1. The multilayer interface structure 170 may include a transition metal-aluminum (Al) composite oxide layer 172 and an upper interface layer 174 sequentially stacked from the dielectric film 160 toward the upper electrode UE1.

[0027] In the multi-layer interface structure 170, the transition metal-Al composite oxide layer 172 may include a transition metal oxide layer in which Al atoms are dispersed. The upper interface layer 174 may include a metal oxide or a metal oxynitride.

[0028] In some example embodiments, the transition metal-Al composite oxide layer 172 may include a first metal as a transition metal, and the upper interface layer 174 may include a second metal of a different type from the first metal. The second metal may be a transition metal or a post-transition metal. In some example embodiments, the first metal included in the transition metal-Al composite oxide layer 172 may be selected from zirconium (Zr) and / or hafnium (Hf), and the second metal included in the upper interface layer 174 may be selected from titanium (Ti), niobium (Nb), tantalum (Ta), tin (Sn), and / or molybdenum (Mo).

[0029] In some example embodiments, the transition metal-Al composite oxide layer 172 may include zirconium oxide in which Al atoms are irregularly dispersed or hafnium oxide in which Al atoms are irregularly dispersed. In some example embodiments, in the transition metal-Al composite oxide layer 172, the content ratio of Al atoms may be in a range of at least 1 atomic % (at %) and less than 40 atomic %, for example, in a range of about 1 atomic % to about 30 atomic %, based on the total number of atoms of zirconium oxide in which Al atoms are irregularly dispersed or hafnium oxide in which Al atoms are irregularly dispersed included in the transition metal-Al composite oxide layer, without being limited thereto.

[0030] In some example embodiments, the upper interface layer 174 may include an oxide of at least one metal selected from Ti, Nb, Ta, Sn, and / or Mo or an oxynitride of at least one metal selected from Ti, Nb, Ta, Sn, and Mo. For example, the upper interface layer 174 may include Ti oxide, Ti oxynitride, Nb oxide, Nb oxynitride, Ta oxide, Ta oxynitride, Sn oxide, Sn oxynitride, Mo oxide, Mo oxynitride, or a combination thereof.

[0031] Figure 2A is a cross-sectional view of a multilayer interface structure 170A according to some example embodiments, which may be used as Figure 1 The multi-layer interface structure 170 shown in FIG.

[0032] Reference Figure 2A , the multilayer interface structure 170A may include an upper interface layer 174A including components that are substantially uniformly dispersed. More specifically, when the upper interface layer 174A includes a metal oxide, the metal atoms and oxygen atoms included in the upper interface layer 174A may be substantially uniformly dispersed regardless of the position within the upper interface layer 174A. For example, when the upper interface layer 174A includes a Ti oxide, the Ti atoms and the oxygen atoms may be substantially uniformly dispersed regardless of the position within the upper interface layer 174A.

[0033] When the upper interface layer 174A includes a metal oxynitride, the metal atoms, oxygen atoms, and nitrogen atoms included in the upper interface layer 174A may be substantially uniformly dispersed regardless of the position within the upper interface layer 174A. For example, when the upper interface layer 174A includes Mo oxynitride, the Mo atoms, oxygen atoms, and nitrogen atoms may be substantially uniformly dispersed regardless of the position within the upper interface layer 174A. In the upper interface layer 174A, the content ratio of nitrogen atoms may be in the range of about 10 atomic % to about 30 atomic %, and the content ratio of oxygen atoms may be in the range of about 10 atomic % to about 30 atomic %, based on the total number of atoms of the metal oxynitride included in the upper interface layer. For example, the content ratio of nitrogen atoms in the range of about 10 atomic % to about 30 atomic % may refer to that the content of nitrogen atoms in the upper interface layer 174A is in the range of about 10 atomic % to about 30 atomic %. For example, a content ratio of oxygen atoms in the range of about 10 atomic % to about 30 atomic % may mean that the content of oxygen atoms in the upper interface layer 174A is in the range of about 10 atomic % to about 30 atomic %.

[0034] Figure 2B is a cross-sectional view of a multilayer interface structure 170B according to some example embodiments, which may be used as Figure 1 The multi-layer interface structure 170 shown in FIG.

[0035] Reference Figure 2B , the multilayer interface structure 170B may include an upper interface layer 174B including components dispersed non-uniformly according to positions. More specifically, the upper interface layer 174B may include a metal oxynitride. In the upper interface layer 174B, the content ratio of nitrogen atoms may increase toward the transition metal-Al composite oxide layer 172, and the content ratio of oxygen atoms may decrease toward the upper electrode (referring to Figure 1 In the upper interface layer 174B, the metal atoms may be substantially uniformly dispersed regardless of the position. In the upper interface layer 174B, the content ratio of nitrogen atoms and the content ratio of oxygen atoms may be in the range of about 10 atomic % to about 30 atomic %.

[0036] For example, when the upper interface layer 174B includes a Mo oxynitride layer, the content ratio of nitrogen atoms in the Mo oxynitride layer may increase toward the transition metal-Al composite oxide layer 172, and the content ratio of oxygen atoms in the Mo oxynitride layer may increase toward the upper electrode (referring to Figure 1 When the upper interface layer 174B includes a Mo oxynitride layer, the upper interface layer 174B may induce a Hf oxide film (eg, HfO 2 The dielectric film 160 of the HfO film has a tetragonal or orthorhombic crystal structure. 2 When the HfO film has a tetragonal crystal structure or an orthorhombic crystal structure, the dielectric constant of the dielectric film 160 may be higher than that when the HfO film has a tetragonal crystal structure or an orthorhombic crystal structure. 2 When the film has a monoclinic crystal structure. Therefore, since the capacitor CP1 includes the upper interface layer 174B including the Mo oxynitride layer, the capacitance of the capacitor CP1 can be further improved without increasing the leakage current in the capacitor CP1.

[0037] Refer back to Figure 1 , the transition metal-Al composite oxide layer 172 may have one surface in contact with, for example, directly in contact with, the dielectric film 160. The other surface of the transition metal-Al composite oxide layer 172 opposite to the one surface of the transition metal-Al composite oxide layer 172 may be in contact with, for example, directly in contact with, the upper interface layer 174. The upper interface layer 174 may have one surface in contact with, for example, directly in contact with, the transition metal-Al composite oxide layer 172. The other surface of the upper interface layer 174 opposite to the one surface of the upper interface layer 174 may be in contact with, for example, directly in contact with the upper electrode UE1.

[0038] like Figure 1As shown in , the capacitor CP1 may further include a lower interface layer 150 between the lower electrode LE1 and the dielectric film 160. One surface of the lower interface layer 150 may be in contact with, e.g., directly in contact with, the lower electrode LE1, and another surface of the lower interface layer 150 opposite to the one surface of the lower interface layer 150 may be in contact with, e.g., directly in contact with the dielectric film 160.

[0039] The lower interface layer 150 may include a Ti oxide film doped with a pentavalent dopant metal. In some example embodiments, the dopant metal may include niobium (Nb), tantalum (Ta), antimony (Sb), vanadium (V), and / or combinations thereof.

[0040] In the lower interface layer 150, Ti may be tetravalent, and the dopant metal may be pentavalent, and thus the lower interface layer 150 including the Ti oxide film doped with the dopant metal may include excess electrons. Therefore, the electrical conductivity of the lower interface layer 150 may be improved, and thus the capacitance of the capacitor CP1 may be improved.

[0041] In the lower interface layer 150, the content ratio of the dopant metal may be in the range of about 1 atomic % to about 10 atomic % based on the total atomic number of Ti oxide doped with the dopant metal included in the lower interface layer. For example, in the lower interface layer 150, the content ratio of the dopant metal may be in the range of about 1 atomic % to about 4 atomic %. When the content ratio of the dopant metal in the lower interface layer 150 is too low, it may be difficult to ensure conductivity. When the content ratio of the dopant metal in the lower interface layer 150 is too high, electrical characteristics required for the capacitor CP1 may be adversely affected.

[0042] In some example embodiments, the lower interface layer 150 may include a Ti oxide film doped with one type of dopant metal. For example, the lower interface layer 150 may include a Nb-doped Ti oxide film. In the Nb-doped Ti oxide film, the content ratio of Nb atoms may be in the range of about 1 atomic % to about 4 atomic %.

[0043] In other example embodiments, the lower interface layer 150 may include a Ti oxide film doped with a plurality of types of dopant metals. The plurality of types of dopant metals may include: a first dopant atom including Nb and a second dopant atom including at least one selected from Ta, Sb, and / or V. In the lower interface layer 150, a content ratio of the sum of the first dopant atom and the second dopant atom may be in a range of about 1 atomic % to about 4 atomic %.

[0044] The thickness TH1 of the lower interface layer 150 may be less than the thickness of the dielectric film 160. In some example embodiments, the thickness TH1 of the lower interface layer 150 may be about 1000 Å. to about , but not limited to this.

[0045] The thickness TH2 of the transition metal-Al composite oxide layer 172 may be about to about The thickness TH3 of the upper interface layer 174 may be in the range of about to about In some example embodiments, the thickness TH1 of the lower interface layer 150 may be smaller than the thickness TH2 of the transition metal-Al composite oxide layer 172 and the thickness TH3 of the upper interface layer 174 .

[0046] The dielectric film 160 may include a high-k dielectric film. As used herein, the term "high-k dielectric film" refers to a dielectric film having a higher dielectric constant than a silicon oxide film. In some example embodiments, the dielectric film 160 may include a metal oxide including at least one metal selected from the group consisting of hafnium (Hf), zirconium (Zr), aluminum (Al), niobium (Nb), cerium (Ce), lanthanum (La), tantalum (Ta), and / or titanium (Ti). In some example embodiments, the dielectric film 160 may have a single film structure including one high-k dielectric film. In other example embodiments, the dielectric film 160 may have a multilayer structure including a plurality of high-k dielectric films sequentially stacked on the lower electrode LE1. The high-k dielectric film may include HfO 2 Film, ZrO 2 Film, Al 2 O 3 Membrane, La 2 O 3 Film, Ta 2 O 5 Film, Nb 2 O 5 Film, CeO 2 Film, TiO 2 Film, GeO 2 In some example embodiments, the thickness TH4 of the dielectric film 160 may be about 1000 Å. to about , but not limited to this.

[0047] The surface of the dielectric film 160 facing the upper electrode UE1 may be in contact with, for example, directly in contact with, the transition metal-Al composite oxide layer 172 of the multilayer interface structure 170, and the multilayer interface structure 170 including the transition metal-Al composite oxide layer 172 and the upper interface layer 174 may improve the crystallinity of the dielectric film 160. Therefore, even when the thickness of the dielectric film 160 is reduced by reducing the space occupied by the capacitor CP1 as the IC device 100 is miniaturized, the dielectric film 160 may be sufficiently crystallized by the multilayer interface structure 170. The dielectric film 160 may have a crystal structure of a tetragonal phase, an orthorhombic phase, or a monoclinic phase.

[0048] In some example embodiments, the transition metal-Al composite oxide layer 172 may include a first metal as a transition metal, the upper interface layer 174 may include a second metal of a different type from the first metal, and the dielectric film 160 may include an oxide of the first metal. For example, the transition metal-Al composite oxide layer 172 may include a first metal selected from Zr and Hf, the upper interface layer 174 may include a second metal selected from Ti, Nb, Ta, Sn, and / or Mo, and the dielectric film 160 may include an oxide of the first metal selected from Zr and / or Hf.

[0049] The upper electrode UE1 may face the lower electrode LE1 with a lower interface layer 150, a dielectric film 160, and a multilayer interface structure 170 therebetween. In some example embodiments, the lower electrode LE1 and the upper electrode UE1 may include the same metal as each other. For example, the lower electrode LE1 and the upper electrode UE1 may each include titanium nitride (TiN). In other example embodiments, the lower electrode LE1 and the upper electrode UE1 may include different metals from each other.

[0050] The lower electrode LE1 and the upper electrode UE1 may each include a metal film, a conductive metal oxide film, a conductive metal nitride film, a conductive metal oxynitride film, or a combination thereof. In some example embodiments, the lower electrode LE1 and the upper electrode UE1 may each include niobium (Nb), Nb oxide, Nb nitride, Nb oxynitride, titanium (Ti), Ti oxide, Ti nitride, Ti oxynitride, cobalt (Co), Co oxide, Co nitride, Co oxynitride, tin (Sn), Sn oxide, Sn nitride, Sn oxynitride, and / or a combination thereof. For example, the lower electrode LE1 and the upper electrode UE1 may each include TiN, NbN, CoN, SnO 2 In other example embodiments, the lower electrode LE1 and the upper electrode UE1 may each include TaN, TiAlN, TaAlN, V, VN, Mo, MoN, W, WN, Ru, RuO 2 、SrRuO 3、Ir、IrO 2 、Pt、PtO、SRO(SrRuO 3 )、BSRO((Ba,Sr)RuO 3 )、CRO(CaRuO 3 )、LSCO((La,Sr)CoO 3 ), and / or a combination thereof. However, constituent materials of each of the lower electrode LE1 and the upper electrode UE1 are not limited thereto.

[0051] In reference Figure 1 , 2A In the IC devices 100, 100A, and 100B described in FIGS. 2B and 2B, the capacitor CP1 may include a multilayer interface structure 170, 170A, or 170B between the dielectric film 160 and the upper electrode UE1, and the multilayer interface structure 170, 170A, or 170B may include a transition metal-Al composite oxide layer 172 and an upper interface layer 174, 174A, or 174B including a metal oxide or a metal oxynitride sequentially stacked from the dielectric film 160 toward the upper electrode UE1. Even when the thickness of the dielectric film 160 is reduced by reducing the space occupied by the capacitor CP1 as the IC device 100 is miniaturized, the crystallinity of the dielectric film 160 can be improved by the multilayer interface structure 170. In addition, the capacitor CP1 of the IC device 100 may further include a lower interface layer 150 between the lower electrode LE1 and the dielectric film 160 and in contact with the dielectric film 160, and thus the crystallinity of the dielectric film 160 can be further improved. Therefore, the capacitance of the capacitor CP1 including the dielectric film 160 may increase, and the reliability of the IC device 100 may improve.

[0052] Figure 3 A schematic planar layout illustrating some components of a memory cell array area of ​​an IC device 200 according to some example embodiments.

[0053] Reference Figure 3 , the IC device 200 may include a plurality of active regions AC extending in a lateral direction at an angle relative to the X direction and the Y direction on a plane. A plurality of word lines WL may intersect the plurality of active regions AC and extend parallel to each other in the X direction. A plurality of bit lines BL may extend parallel to each other on the plurality of word lines WL and in the Y direction intersecting the X direction. Each of the plurality of bit lines BL may be connected to the active region AC via a direct contact DC.

[0054] A plurality of buried contacts BC may be formed between two adjacent bit lines of the plurality of bit lines BL. A plurality of conductive landing pads LP may be formed on the plurality of buried contacts BC. At least a portion of each of the plurality of conductive landing pads LP may overlap the buried contact BC. A plurality of lower electrodes LE2 may be formed on the plurality of conductive landing pads LP and separated from each other. The plurality of lower electrodes LE2 may be connected to the plurality of active regions AC through the plurality of buried contacts BC and the plurality of conductive landing pads LP.

[0055] Figure 4A for Figure 3 2 is a plan view of some components of IC device 200 shown in FIG. Figure 4B For and along Figure 4A The cross section taken along line 2X-2X' corresponds to a schematic cross-sectional view of some components. Figure 4C for Figure 4B An enlarged cross-sectional view of the area “EX1”.

[0056] Reference Figures 4A to 4C , the IC device 200 may include: a substrate 210 including a plurality of active regions AC and a lower structure 220 formed on the substrate 210. A plurality of conductive regions 224 may pass through the lower structure 220 and be connected to the plurality of active regions AC.

[0057] The substrate 210 may include a semiconductor element (element) such as Si and / or Ge, or a compound semiconductor such as SiC, GaAs, InAs, and / or InP. The substrate 210 may include: a semiconductor substrate; and a structure including at least one insulating film or at least one conductive region formed on the semiconductor substrate. The at least one conductive region may include, for example, a doped well or a doped structure. A device isolation film 212 defining a plurality of active regions AC may be formed in the substrate 210. The device isolation film 212 may include an oxide film, a nitride film, or a combination thereof.

[0058] In some embodiments, the lower structure 220 may include an insulating film including a silicon oxide film, a silicon nitride film, or a combination thereof. In other example embodiments, the lower structure 220 may include various conductive regions such as wiring layers, contact plugs, and transistors, and an insulating film configured to electrically insulate the conductive regions from each other. The plurality of conductive regions 224 may include polysilicon, metal, conductive metal nitride, metal silicide, or a combination thereof. The lower structure 220 may include reference Figure 3 The plurality of conductive regions 224 may each include a reference Figure 3 Described buried contact BC and conductive landing pad LP.

[0059] An insulating pattern 226P having a plurality of openings 226H may be on the lower structure 220 and the plurality of conductive regions 224. The plurality of openings 226H may be at a position overlapping the plurality of conductive regions 224 in the vertical direction (Z direction). The insulating pattern 226P may include a silicon nitride (SiN) film, a silicon carbon nitride (SiCN) film, a silicon boron nitride (SiBN) film, or a combination thereof. As used herein, the terms "SiN", "SiCN", and "SiBN" each refer to a material including elements contained therein, rather than a chemical formula representing a stoichiometric relationship.

[0060] A plurality of capacitors CP2 may be on a plurality of conductive regions 224. Each of the plurality of capacitors CP2 may include a lower electrode LE2, a dielectric film 260 covering the lower electrode LE2, an upper electrode UE2 covering the dielectric film 260, and a multilayer interface structure 270 between the dielectric film 260 and the upper electrode UE2. The multilayer interface structure 270 may include a transition metal-Al composite oxide layer 272 and an upper interface layer 274 sequentially stacked from the dielectric film 260 toward the upper electrode UE2. The capacitor CP2 may further include a lower interface layer 250 between the lower electrode LE2 and the dielectric film 260. The respective constituent materials of the lower electrode LE2, the lower interface layer 250, the dielectric film 260, the transition metal-Al composite oxide layer 272, the upper interface layer 274, and the upper electrode UE2 are the same as those already described with reference to FIG. Figure 1 , 2A The lower electrode LE1, the lower interface layer 150, the dielectric film 160, the transition metal-Al composite oxide layer 172, the upper interface layer 174, and the upper electrode UE1 described in FIG2B are substantially the same as those.

[0061] The insulating pattern 226P may be adjacent to the lower end of each of the plurality of lower electrodes LE2. Each of the plurality of lower electrodes LE2 may have a pillar shape extending from the top surface of the conductive region 224 through the opening 226H of the insulating pattern 226P in a vertical direction (Z direction) in a direction away from the substrate 210. Figure 4B An example in which the plurality of lower electrodes LE2 each have a pillar shape is described, but the inventive concept is not limited thereto. For example, the plurality of lower electrodes LE2 each may have a cup-shaped cross-sectional structure or a cylindrical cross-sectional structure having a closed bottom.

[0062] The plurality of lower electrodes LE2 may be supported by the lower insulating support pattern 242P and the upper insulating support pattern 244P. The plurality of lower electrodes LE2 and the upper electrode UE2 may face each other with the lower interface layer 250, the dielectric film 260, the transition metal-Al composite oxide layer 272, and the upper interface layer 274 therebetween.

[0063] The lower interface layer 250 may be between the lower electrode LE2 and the dielectric film 260. The lower interface layer 250 may conformally cover the outer sidewall and the uppermost surface of the lower electrode LE2. The lower interface layer 250 may not be between the lower electrode LE2 and the insulating pattern 226P, between the lower electrode LE2 and the lower insulating support pattern 242P, and between the lower electrode LE2 and the upper insulating support pattern 244P. The lower interface layer 250 may not be between the insulating pattern 226P and the dielectric film 260, between the lower insulating support pattern 242P and the dielectric film 260, and between the upper insulating support pattern 244P and the dielectric film 260.

[0064] The dielectric film 260 may cover the lower electrode LE2, the lower insulating support pattern 242P, and the upper insulating support pattern 244P. The dielectric film 260 may include portions that are in contact with, for example, directly in contact with, the insulating pattern 226P, the lower interface layer 250, the lower insulating support pattern 242P, and the upper insulating support pattern 244P, respectively. The portion of the dielectric film 260 facing the lower electrode LE2 may be separated from the lower electrode LE2 with the lower interface layer 250 therebetween. The dielectric film 260 may not include a portion that is in contact with, for example, directly in contact with the lower electrode LE2. Figure 4B As shown in , the lower interface layer 250 may be in contact with, eg, in direct contact with, the uppermost surface of the lower electrode LE2 .

[0065] The upper insulating support pattern 244P may be arranged in a lateral direction (with respect to the substrate 210) parallel to the substrate 210. Figure 4B The upper insulating support pattern 244P may extend in a direction parallel to the XY plane in the upper portion (in a direction parallel to the XY plane in the upper portion), while surrounding the upper ends of the plurality of lower electrodes LE2. A plurality of holes 244H through which the plurality of lower electrodes LE2 pass may be formed in the upper insulating support pattern 244P. The inner sidewalls of the plurality of holes 244H formed in the upper insulating support pattern 244P may be in contact with, for example, in direct contact with, the outer sidewalls of the lower electrodes LE2. The top surfaces of the plurality of lower electrodes LE2 may be on the same plane as the top surface of the upper insulating support pattern 244P, without being limited thereto.

[0066] The lower insulating support pattern 242P may be parallel to the lateral direction of the substrate 210 (with respect to Figure 4B The plurality of holes 242H through which the plurality of lower electrodes LE2 pass, and the plurality of lower holes (referring to the lower holes 242H) may be formed in the lower insulating support pattern 242P. Figure 5E The plurality of lower electrodes LE2 may pass through the plurality of holes 244H formed in the upper insulating support pattern 244P and the plurality of holes 242H formed in the lower insulating support pattern 242P, and extend in the vertical direction (Z direction).

[0067] like Figure 4A As shown in FIG. 2 , a plurality of upper holes UH may be formed in the upper insulating support pattern 244P. Figure 4A An example configuration is described in which the planar shape of each of the plurality of upper holes UH is substantially a rhombus planar shape, the vertices of which are formed by four adjacent lower electrodes LE2, respectively. However, the planar shape of each of the plurality of upper holes UH is not limited to Figure 4A , and various modifications and changes may be made within the scope of the inventive concept. A plurality of lower holes LH having a planar shape corresponding to that of the plurality of upper holes UH may be formed in the lower insulating support pattern 242P.

[0068] The lower insulating support pattern 242P and the upper insulating support pattern 244P may each include a silicon nitride (SiN) film, a silicon carbon nitride (SiCN) film, a silicon boron nitride (SiBN) film, or a combination thereof. In some example embodiments, the lower insulating support pattern 242P and the upper insulating support pattern 244P may include the same material as each other. In other example embodiments, the lower insulating support pattern 242P and the upper insulating support pattern 244P may include materials different from each other. In one example, the lower insulating support pattern 242P and the upper insulating support pattern 244P may each include a SiCN film. In another example, the lower insulating support pattern 242P may include a SiCN film, and the upper insulating support pattern 244P may include a SiBN film. However, the inventive concept is not limited to the above materials.

[0069] In reference Figure 3 and 4A In the IC device 200 described in 4C, the capacitor CP2 may include a multilayer interface structure 270 between the dielectric film 260 and the upper electrode UE2. The multilayer interface structure 270 may include a transition metal-Al composite oxide layer 272 and an upper interface layer 274 sequentially stacked from the dielectric film 260 toward the upper electrode UE2. The upper interface layer 274 may include a metal oxide or a metal oxynitride. Even when the thickness of the dielectric film 260 is reduced by reducing the space occupied by the capacitor CP2 as the IC device 200 is miniaturized, the crystallinity of the dielectric film 260 can be improved by the multilayer interface structure 270. In addition, the capacitor CP2 of the IC device 200 may further include a lower interface layer 250, which is between the lower electrode LE2 and the dielectric film 260 and in contact with the dielectric film 260, and thus the crystallinity of the dielectric film 260 can be further improved. Therefore, the capacitance of the capacitor CP2 including the dielectric film 260 can be increased, and the reliability of the IC device 200 can be improved.

[0070] Figures 5A to 5JFIG. 1 is a cross-sectional view of a process sequence of a method for manufacturing an IC device according to some example embodiments. Figures 5A to 5J In the drawings, the same reference numerals are used to denote Figure 3 and 4A to the same elements as in 4C, and their detailed description is omitted.

[0071] Reference Figure 5A , a lower structure 220 and a conductive region 224 may be formed on a substrate 210 in which an active region AC is defined by a device isolation film 212. The conductive region 224 may pass through the lower structure 220 and be connected to the active region AC. Thereafter, an insulating film 226 may be formed to cover the lower structure 220 and the conductive region 224.

[0072] The insulating film 226 may be used as an etch stop layer in subsequent processes. The insulating film 226 may include an insulating material having an etch selectivity with respect to the lower structure 220. In some example embodiments, the insulating film 226 may include a silicon nitride (SiN) film, a silicon carbon nitride (SiCN) film, a silicon boron nitride (SiBN) film, or a combination thereof.

[0073] Reference Figure 5B , a mold structure MST may be formed on the insulating film 226 .

[0074] The mold structure MST may include a plurality of mold films and a plurality of support films. For example, the mold structure MST may include a first mold film 232, a lower insulating support film 242, a second mold film 234, and an upper insulating support film 244 sequentially stacked on the insulating film 226. The first mold film 232 and the second mold film 234 may each include the following materials: 4 F), hydrofluoric acid (HF), and water have a relatively high etching rate and can be removed by a lift-off process using the etchant. In some example embodiments, the first mold film 232 and the second mold film 234 may each include an oxide film, a nitride film, or a combination thereof. For example, the first mold film 232 may include a borophosphosilicate glass (BPSG) film. The BPSG film may include at least one of the following: a first portion in which the concentration of the dopant B (boron) varies in the thickness direction of the BPSG film, and a second portion in which the concentration of the dopant P (phosphorus) varies in the thickness direction of the BPSG film. The second mold film 234 may include: a silicon nitride film; or a multilayer insulating film in which silicon oxide films and silicon nitride films, each having a relatively small thickness, are alternately and repeatedly stacked one by one multiple times. However, the constituent materials of each of the first mold film 232 and the second mold film 234 are not limited to the above examples, and various modifications and changes may be made within the scope of the inventive concept. In addition, the order of stacking of the films in the mold structure MST is not limited to Figure 5B The examples shown in the drawings are limited to the examples shown in the drawings and many modifications and variations are possible within the scope of the inventive concept.

[0075] The lower insulating support film 242 and the upper insulating support film 244 may each include a silicon nitride (SiN) film, a silicon carbon nitride (SiCN) film, a silicon boron nitride (SiBN) film, or a combination thereof. In some example embodiments, the lower insulating support film 242 and the upper insulating support film 244 may include the same material as each other. In other example embodiments, the lower insulating support film 242 and the upper insulating support film 244 may include materials different from each other. In some example embodiments, the lower insulating support film 242 and the upper insulating support film 244 may each include a silicon carbon nitride film. In other example embodiments, the lower insulating support film 242 may include a silicon carbon nitride film, and the upper insulating support film 244 may include a silicon boron nitride film. However, the constituent materials of the lower insulating support film 242 and the upper insulating support film 244 are not limited thereto, and various modifications and changes may be made within the scope of the inventive concept.

[0076] Reference Figure 5C ,exist Figure 5B In the resulting structure, a mask pattern MP may be formed on the mold structure MST. Thereafter, by using the mask pattern MP as an etching mask and by using the insulating film 226 as an etching stop layer, the mold structure MST may be anisotropically etched to form a mold structure pattern MSP defining a plurality of holes BH. The mold structure pattern MSP may include a first mold pattern 232P, a lower insulating support pattern 242P, a second mold pattern 234P, and an upper insulating support pattern 244P. The mask pattern MP may include a nitride film, an oxide film, a polysilicon film, a photoresist film, or a combination thereof.

[0077] The process of forming the plurality of holes BH may further include wet-treating the resultant structure obtained by anisotropically etching the mold structure MST. During the process of wet-treating the resultant structure obtained by anisotropically etching the mold structure MST, a portion of the insulating film 226 may be etched together, and thus, an insulating pattern 226P having a plurality of openings 226H exposing the plurality of conductive regions 224 may be obtained. An example process for wet-treating the resultant structure obtained by anisotropically etching the mold structure MST may be performed using an etchant including a dilute sulfuric acid peroxide (DSP) solution, without being limited thereto.

[0078] In the mold structure pattern MSP, a plurality of holes 242H as part of the plurality of holes BH may be formed in the lower insulating support pattern 242P, and a plurality of holes 244H as part of the plurality of holes BH may be formed in the upper insulating support pattern 244P.

[0079] Reference Figure 5D , the mask pattern MP can be obtained from Figure 5C The resulting structure is removed, and the lower electrode LE2 may be formed to fill the plurality of holes BH.

[0080] In some example embodiments, to form the lower electrode LE2, Figure 5D A conductive layer filling the plurality of holes BH and covering the top surface of the upper insulating support pattern 244P is formed on the resulting structure. To form the conductive layer, a chemical vapor deposition (CVD) process, a plasma enhanced CVD (PECVD) process, a metal organic CVD (MOCVD) process, or an atomic layer deposition (ALD) process may be used. Thereafter, the conductive layer may be partially removed using an etch-back process or a chemical mechanical polishing (CMP) process to expose the top surface of the upper insulating support pattern 244P.

[0081] Reference Figure 5E , available from Figure 5D The resulting structure may be formed by removing a portion of the upper insulating support pattern 244P to form a plurality of upper holes UH. Thereafter, the second mold pattern 234P may be wet-removed through the plurality of upper holes UH. Next, a portion of the lower insulating support pattern 242P exposed through the plurality of upper holes UH may be removed to form a plurality of lower holes LH. Thereafter, the first mold pattern 232P may be wet-removed through the plurality of lower holes LH to expose the top surface of the insulating pattern 226P. In some example embodiments, a mold including ammonium fluoride (NH 4 The second mold pattern 234P and the first mold pattern 232P are wet-removed by an etchant of hydrofluoric acid (HF), hydrofluoric acid (HF), and water, without being limited thereto.

[0082] The planar shapes of the upper holes UH and the lower holes LH are not limited to Figure 4A , and may be variously selected. After removing the first mold pattern 232P and the second mold pattern 234P, the sidewalls of the plurality of lower electrodes LE2 may be exposed.

[0083] Reference Fig. 5F ,from Figure 5E Among the exposed surfaces of the resulting structure, the lower interface layer 250 may be selectively formed only on the exposed surfaces of the plurality of lower electrodes LE2.

[0084] In some example embodiments, in order to form the lower interface layer 250, a Ti oxide film may be formed on the exposed surface of the lower electrode LE2, and then doped with a pentavalent dopant metal. In some example embodiments, the dopant metal may include Nb, Ta, Sb, V, and / or a combination thereof. In other example embodiments, when the lower electrode LE2 includes TiN, a Ti oxide film may be formed on the exposed surface of the lower electrode LE2 by oxidizing the exposed surface of the lower electrode LE2.

[0085] Reference Figure 5G ,exist Fig. 5F In the resulting structure, a dielectric film 260 may be formed to cover the exposed surface of the lower interface layer 250, the exposed surfaces of each of the lower and upper insulating support patterns 242P and 244P, and the exposed surface of the insulating pattern 226P.

[0086] The dielectric film 260 may be formed using an ALD process. The dielectric film 260 may include HfO 2 、ZrO 2 、Al 2 O 3 ,La 2 O 3 、 2 O 5 , Nb 2 O 5 、CeO 2 、TiO 2 ,GeO 2 , and / or a combination thereof, but not limited thereto.

[0087] Reference Figure 5H , available in Figure 5G A transition metal-Al composite oxide layer 272 conformally covering the dielectric film 260 is formed on the resulting structure.

[0088] In some example embodiments, in order to form the transition metal-Al composite oxide layer 272, a transition metal oxide film may be formed on the exposed surface of the dielectric film 260 and then doped with aluminum (Al). In other example embodiments, when the exposed surface of the dielectric film 260 includes a transition metal oxide film (e.g., HfO 2 Film or ZrO 2 When a transition metal-Al composite oxide layer 272 is formed, the process of forming a transition metal oxide film on the exposed surface of the dielectric film 260 may be omitted, and the exposed surface of the dielectric film 260 may be doped with Al.

[0089] Reference Fig.5I , available in Figure 5HIn the resulting structure, an upper interface layer 274 is formed that conformally covers the transition metal-Al composite oxide layer 272. The transition metal-Al composite oxide layer 272 and the upper interface layer 274 may constitute a multilayer interface structure 270.

[0090] In some example embodiments, the upper interface layer 274 may be formed by using an ALD process or a CVD process. For example, to form the upper interface layer 274, a metal oxide film including an oxide of at least one metal selected from Ti, Nb, Ta, Sn, and / or Mo, or a metal oxynitride film including an oxynitride of at least one metal selected from Ti, Nb, Ta, Sn, and / or Mo may be formed by using an ALD process or a CVD process.

[0091] In other example embodiments, to form the upper interface layer 274, a metal nitride film including a nitride of at least one metal selected from Ti, Nb, Ta, Sn, and / or Mo may be formed on the transition metal-Al composite oxide layer 272, and then a portion of the metal nitride film may be oxidized from the exposed surface of the metal nitride film. In the upper interface layer 274 obtained as a result, the content ratio of nitrogen atoms may increase toward the transition metal-Al composite oxide layer 272, and the content ratio of oxygen atoms may increase toward the exposed surface of the upper interface layer 274. For example, to form the upper interface layer 274, a Mo nitride film conformally covering the transition metal-Al composite oxide layer 272 may be formed, and a portion of the Mo nitride film may be oxidized from the exposed surface of the Mo nitride film to form a Mo oxynitride film. In the Mo oxynitride film obtained using the above method, the content ratio of nitrogen atoms may increase toward the transition metal-Al composite oxide layer 272 , and the content ratio of oxygen atoms may increase toward the exposed surface of the Mo oxynitride film.

[0092] In yet another example embodiment, in order to form the upper interface layer 274, a metal nitride film including a nitride of at least one metal selected from Ti, Nb, Ta, Sn, and / or Mo may be formed, and then a metal oxide film including an oxide of at least one metal selected from Ti, Nb, Ta, Sn, and / or Mo may be formed on the metal nitride film to form a metal oxynitride film. In the metal oxynitride film formed using the above method, the content ratio of nitrogen atoms may increase toward the transition metal-Al composite oxide layer 272, and the content ratio of oxygen atoms may increase toward the exposed surface of the metal oxynitride film. For example, in order to form the upper interface layer 274, after first forming a Mo nitride film to conformally cover the transition metal-Al composite oxide layer 272, a Mo oxide film conformally covering the Mo nitride film may be formed on the Mo nitride film to form a Mo oxynitride film.

[0093] Reference Figure 5J , the upper interface layer 274 may be formed Fig.5I The resulting structure is annealed in an inert atmosphere 290. The inert atmosphere 290 may be an atmosphere including N 2 The annealing process may be performed at a temperature of about 400° C. to about 600° C. for about 60 minutes to about 120 minutes, without being limited thereto. Due to the annealing process, the crystallinity of the dielectric film 260 may be increased. In some example embodiments, the reference to Figure 5J Describe the annealing process.

[0094] Afterwards, an upper electrode UE2 may be formed on the upper interface layer 274, and thus, Figure 4B In some example embodiments, the upper electrode UE2 may be formed by using a CVD process, a MOCVD process, a physical vapor deposition (PVD) process, or an ALD process.

[0095] In reference Figure 3 and 4A In the IC device 200 described in 4C, even when the thickness of the dielectric film 260 is reduced by reducing the space occupied by the capacitor CP2 as the IC device 200 is miniaturized, the crystallinity of the dielectric film 260 can be increased, and therefore, the capacitance of the capacitor CP2 including the dielectric film 260 can be increased, and the mass production capability and reliability of the IC device 200 can be improved.

[0096] Example Implementation 1

[0097] Fig. 6A is a graph of X-ray diffraction (XRD) measurement results showing a comparison of crystallinity of dielectric films included in capacitors of IC devices according to example embodiments and comparative examples.

[0098] exist Fig. 6A In Example 1, the crystallinity of a dielectric film included in a capacitor formed by using a method for manufacturing an IC device according to the present inventive concept is evaluated. To prepare a sample of Example 1, a lower interface layer including a Nb-doped Ti oxide film is formed on a lower electrode including TiN. The thickness of the lower interface layer will have ZrO 2 Film and Al 2 O 3 A dielectric film having a multilayer structure in which films are alternately stacked is formed. A transition metal-Al composite oxide layer including an Al-doped Zr oxide film is formed on the dielectric film to a thickness of The Al-doped Zr oxide film is obtained by forming a zirconium oxide layer using an ALD (atomic layer deposition) process, forming an aluminum oxide layer on the zirconium oxide layer using an ALD process, and annealing the resulting structure at about 350° C., and forming an upper interface layer including a Ti oxide film on the transition metal-Al composite oxide layer to a thickness of 1000 Å. Thickness. 2 The obtained resultant structure was annealed at 400° C. for 120 minutes in an atmosphere. Thereafter, an upper electrode including TiN was formed on the obtained resultant structure.

[0099] To prepare the sample of Comparative Example 1, substantially the same method as the method of preparing the sample according to Example Embodiment 1 was performed. However, the process of forming the transition metal-Al composite oxide layer was omitted, and the dielectric film was directly formed on the N 2 The structure was annealed at 400°C for 120 minutes in an atmosphere. Furthermore, an upper interface layer including a Ti oxide film was formed on the annealed structure. A thickness of , and an upper electrode including TiN is formed on the upper interface layer without annealing the resulting structure including the upper interface layer.

[0100] from Fig. 6A As a result, it can be seen that Example Embodiment 1 having a structure according to the inventive concept exhibits a higher intensity of XRD peak than Comparative Example 1. Therefore, it can be inferred that the structure of Example Embodiment 1 has improved crystallinity compared to the structure of Comparative Example 1.

[0101] Example Implementation 2

[0102] Figure 6B For use Fig. 6A Graph of capacitance measurement results of Example Embodiment 1 and Comparative Example for evaluation. Figure 6B From the results, it can be seen that the structure of Example Implementation 1 has significantly improved capacitance compared to the structure of Comparative Example 1.

[0103] Example Implementation 3

[0104] Fig. 7A , 7B 7C are graphs of XRD measurement results showing a comparison of crystallinity of dielectric films included in capacitors of IC devices according to example embodiments and comparative examples.

[0105] More specifically, Fig. 7A This is a graph for evaluating the crystallinity of the dielectric film in the sample of Comparative Example 2. Figure 7B This is a graph for evaluating the crystallinity of the dielectric film in the sample of Example Implementation 2. Figure 7CThis is a graph for evaluating the crystallinity of the dielectric film in the sample of Example 3.

[0106] To prepare the sample of Comparative Example 2, the following was performed: Fig. 6A The method of evaluating the sample of Comparative Example 1 is substantially the same as that of the sample of Comparative Example 1. However, the process of forming the upper interface layer is omitted. As the dielectric film, a film having HfO 2 Film on ZrO 2 Film and Al 2 O 3 The dielectric film of the multilayer structure between the films is formed to and an upper electrode including TiN is directly formed on the dielectric film.

[0107] To prepare the samples of Example 2, the following steps were performed: Fig. 6A The method of evaluating the sample of Example 1 is basically the same as that of Example 1. However, as the dielectric film, a layer having HfO 2 Film on ZrO 2 Film and Al 2 O 3 The dielectric film of the multilayer structure between the films is formed to and as the upper interface layer, a The thickness of the Mo nitride film is .

[0108] To prepare the samples of Example 3, the following steps were performed: Fig. 6A The method of evaluating the sample of Example 1 is basically the same as that of Example 1. However, as the dielectric film, a layer having HfO 2 Film on ZrO 2 Film and Al 2 O 3 The dielectric film of the multilayer structure between the films is formed to and as the upper interface layer, a The thickness of the Mo oxide film is .

[0109] from Fig. 7A It can be seen that the peak of the monoclinic phase is observed in the case of Comparative Example 2, and it is about 1 / 3 of the peak of the tetragonal phase. Figure 7B and 7C , when the upper interface layer includes a Mo nitride film or a Mo oxide film, the peak of the monoclinic phase is hardly seen, and only the peak of the tetragonal phase is observed. Fig. 7A , 7B 7C, it can be seen that when the upper interface layer includes a Mo nitride film or a Mo oxide film, including HfO2 The monoclinic phase of the dielectric film of the film is suppressed, and the tetragonal phase thereof is induced. As a result, an effect of improving the capacitance of a capacitor including the dielectric film while suppressing leakage current in the capacitor can be expected.

[0110] While the present inventive concept has been particularly described and illustrated with reference to example embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

Claims

1. Integrated circuit devices, including: Lower electrode; a dielectric film covering the lower electrode; an upper electrode covering the dielectric film; as well as a multilayer interface structure between the dielectric film and the upper electrode, The multi-layer interface structure comprises: a transition metal-aluminum (Al) composite oxide layer including a transition metal oxide layer in which Al atoms are dispersed, the transition metal-Al composite oxide layer being in contact with the dielectric film; and An upper interface layer comprising a metal oxide or a metal oxynitride is in contact with the transition metal-Al composite oxide layer.

2. The integrated circuit device of claim 1, wherein The transition metal-Al composite oxide layer includes a first metal as a transition metal, and The upper interface layer includes a second metal, and The second metal is a transition metal or a post-transition metal of a different type from the first metal.

3. The integrated circuit device according to claim 1, wherein the transition metal-Al composite oxide layer comprises zirconium oxide in which Al atoms are dispersed or hafnium oxide in which Al atoms are dispersed.

4. The integrated circuit device of claim 1, wherein the upper interface layer comprises an oxide of at least one metal selected from the group consisting of titanium (Ti), niobium (Nb), tantalum (Ta), tin (Sn), or molybdenum (Mo), or an oxynitride of the at least one metal.

5. The integrated circuit device of claim 1, wherein The upper interface layer includes the metal oxynitride, The content ratio of nitrogen atoms in the upper interface layer increases toward the transition metal-Al composite oxide layer, and A content ratio of oxygen atoms in the upper interface layer increases toward the upper electrode.

6. The integrated circuit device of claim 1, wherein The upper interface layer comprises a Mo oxynitride layer, The content ratio of nitrogen atoms in the Mo oxynitride layer increases toward the transition metal-Al composite oxide layer, and A content ratio of oxygen atoms in the Mo oxynitride layer increases toward the upper electrode.

7. The integrated circuit device of claim 1, further comprising: a lower interface layer between the lower electrode and the dielectric film, the lower interface layer being in contact with the dielectric film, The lower interface layer includes a Ti oxide film doped with a pentavalent dopant metal.

8. The integrated circuit device of claim 7, wherein the dopant metal comprises niobium (Nb), tantalum (Ta), antimony (Sb), vanadium (V), or a combination thereof.

9. The integrated circuit device of claim 7, wherein a thickness of the lower interface layer is smaller than a thickness of each of the transition metal-Al composite oxide layer and the upper interface layer.

10. The integrated circuit device of claim 1, wherein the dielectric film comprises: A metal oxide containing at least one metal selected from the group consisting of hafnium (Hf), zirconium (Zr), aluminum (Al), niobium (Nb), cerium (Ce), lanthanum (La), tantalum (Ta), or titanium (Ti).

11. Integrated circuit devices, including: a substrate including an active region; a conductive region formed on the active region; and a capacitor formed on the conductive region, The capacitor comprises: a lower electrode in contact with the conductive region, a dielectric film covering the lower electrode, an upper electrode covering the dielectric film, and a multilayer interface structure between the dielectric film and the upper electrode, and The multi-layer interface structure comprises: a transition metal-aluminum (Al) composite oxide layer including a transition metal oxide layer in which Al atoms are dispersed, the transition metal-Al composite oxide layer being in contact with the dielectric film; and An upper interface layer comprising a metal oxide or a metal oxynitride is in contact with the transition metal-Al composite oxide layer.

12. The integrated circuit device of claim 11, wherein The upper interface layer includes the metal oxynitride, The content ratio of nitrogen atoms in the upper interface layer increases toward the transition metal-Al composite oxide layer, The content ratio of oxygen atoms in the upper interface layer increases toward the upper electrode, and A content ratio of nitrogen atoms and a content ratio of oxygen atoms in the upper interface layer are each in a range of 10 atomic % to 30 atomic % based on the total number of atoms of the metal oxynitride included in the upper interface layer.

13. The integrated circuit device of claim 11, further comprising: a lower interface layer between the lower electrode and the dielectric film, the lower interface layer having one surface in contact with the dielectric film and another surface in contact with the lower electrode, wherein the lower interface layer comprises a Ti oxide film doped with a pentavalent dopant metal, and the dopant metal comprises Nb, Ta, Sb, V, or a combination thereof, and The lower electrode includes a titanium nitride (TiN) film.

14. Integrated circuit devices, including: a substrate including an active region; a plurality of conductive regions formed on the active region; an insulating pattern extending in a lateral direction on the plurality of conductive regions, the insulating pattern having a plurality of openings vertically overlapping the plurality of conductive regions; a plurality of lower electrodes passing through the insulating pattern via the plurality of openings and extending in a vertical direction, the plurality of lower electrodes being connected to the plurality of conductive regions; an insulating support pattern extending in a lateral direction and spaced apart from the insulating pattern in a vertical direction, the insulating support pattern contacting a partial region of each of the plurality of lower electrodes to support the plurality of lower electrodes; a dielectric film covering the plurality of lower electrodes, the insulating pattern, and the insulating support pattern; an upper electrode covering the dielectric film; a lower interface layer between the plurality of lower electrodes and the dielectric film, the lower interface layer being in contact with the dielectric film; as well as a multilayer interface structure between the dielectric film and the upper electrode, wherein the lower interface layer comprises a Ti oxide film doped with a pentavalent dopant metal, The multi-layer interface structure comprises: a transition metal-aluminum (Al) composite oxide layer including a transition metal oxide layer in which Al atoms are dispersed, the transition metal-Al composite oxide layer being in contact with the dielectric film; and An upper interface layer comprising a metal oxide or a metal oxynitride is in contact with the transition metal-Al composite oxide layer.

15. An integrated circuit device as claimed in claim 11 or 14, wherein The transition metal-Al composite oxide layer includes a first metal selected from zirconium (Zr) and hafnium (Hf), The upper interface layer includes a second metal selected from at least one of titanium (Ti), niobium (Nb), tantalum (Ta), tin (Sn), or molybdenum (Mo), and The dielectric film has a tetragonal, orthorhombic or monoclinic crystal structure.

16. An integrated circuit device as claimed in claim 11 or 14, wherein The upper interface layer comprises a Mo oxynitride layer, The content ratio of nitrogen atoms in the Mo oxynitride layer increases toward the transition metal-Al composite oxide layer, The content ratio of oxygen atoms in the Mo oxynitride layer increases toward the upper electrode, and The dielectric film has a tetragonal or orthorhombic crystal structure.

17. An integrated circuit device as claimed in claim 11 or 14, wherein The transition metal-Al composite oxide layer includes a first metal as a transition metal, The upper interface layer includes a second metal, wherein the second metal is a transition metal or a post-transition metal of a different type than the first metal, and The dielectric film includes an oxide of the first metal.

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