Semiconductor device

Abstract

The semiconductor device includes: a chip having a main surface; a trench resistor structure formed on the main surface; a resistive film electrically connected to the trench resistor structure on the main surface; a gate terminal electrode having a lower resistance value than the resistive film and electrically connected to the trench resistor structure via the resistive film on the main surface; and a gate wiring electrode having a lower resistance value than the resistive film and electrically connected to the gate terminal electrode on the main surface via the resistive film and the trench resistor structure.

Description

Technical Field

[0001] This application claims priority based on Patent Application No. 2022-111395 filed in the Japan Patent Office on Jul. 11, 2022, the entire contents of which are incorporated herein by reference. The present disclosure relates to a semiconductor device. Background Art

[0002] Patent Document 1 discloses a semiconductor device including a semiconductor substrate, a plurality of trench structures, and a gate pad portion. The plurality of trench structures are formed on the surface of the semiconductor substrate. The gate pad portion is arranged on the semiconductor substrate so as to cover the plurality of trench structures.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: U.S. Patent Application Publication No. 2017 / 0040423 Summary of the invention

[0006] Problems to be solved by the invention

[0007] The present disclosure provides a semiconductor device having a novel layout.

[0008] Solutions to Solve Problems

[0009] The present disclosure provides a semiconductor device, including: a chip, which has a main surface; a trench resistor structure, which is formed on the above-mentioned main surface; a resistor film, which is electrically connected to the above-mentioned trench resistor structure on the above-mentioned main surface; a gate terminal electrode, which has a lower resistance value than the above-mentioned resistor film, and is electrically connected to the above-mentioned trench resistor structure on the above-mentioned main surface via the above-mentioned resistor film; and a gate wiring electrode, which has a lower resistance value than the above-mentioned resistor film, and is electrically connected to the above-mentioned gate terminal electrode on the above-mentioned main surface via the above-mentioned resistor film and the above-mentioned trench resistor structure.

[0010] The above or other objects, features and effects will become clear from the accompanying drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 It is a top view showing the semiconductor device according to the first embodiment.

[0012] Figure 2 It is a plan view showing the layout of the first main surface.

[0013] Figure 3 It is an enlarged top view showing the active region and the peripheral region.

[0014] Figure 4 is along Figure 3A cross-sectional view taken along line IV-IV is shown.

[0015] Figure 5 is along Figure 3 A cross-sectional view taken along line VV is shown.

[0016] Figure 6 is along Figure 3 A cross-sectional view taken along line VI-VI is shown.

[0017] Figure 7 It is an enlarged top view showing the active region and the boundary region.

[0018] Figure 8 is along Figure 7 A cross-sectional view taken along line VIII-VIII is shown.

[0019] Fig. 9 is along Figure 7 A cross-sectional view taken along line IX-IX is shown.

[0020] Fig.10 It is a cross-sectional view showing the structure of the outer peripheral area.

[0021] Fig.11 It is an enlarged top view showing the pad area.

[0022] Fig.12 Yes means Fig.11 An enlarged top view of the gate resistor structure is shown.

[0023] Fig.13 Yes means Fig.12 An enlarged top view of the inner portion of the gate resistor structure is shown.

[0024] Fig.14 Yes means Fig.12 An enlarged top view of one end of the gate resistor structure shown.

[0025] Fig.15 Yes means Fig.12 An enlarged top view of the other end of the gate resistor structure is shown.

[0026] Fig.16 It means along Fig.13 A cross-sectional view taken along line XVI-XVI is shown.

[0027] Fig.17 is along Fig.13 A cross-sectional view taken along line XVII-XVII is shown.

[0028] Fig.18 is along Fig.13 A cross-sectional view taken along line XVIII-XVIII is shown.

[0029] Fig.19 is along Fig.13 A cross-sectional view taken along line XIX-XIX is shown.

[0030] Fig. 20 is along Fig.14 A cross-sectional view taken along line XX-XX is shown.

[0031] Fig.21 is along Fig.15 A cross-sectional view taken along line XXI-XXI is shown.

[0032] Fig. 22 is along Fig.12 A cross-sectional view along line XXII-XXII is shown.

[0033] Fig.23 It is a plan view showing the layout of the resistor film, the gate electrode film, and the gate wiring film.

[0034] Fig.24 This is a circuit diagram showing a gate resistor structure, a gate terminal electrode, and a gate wiring electrode.

[0035] Fig.25 It is an enlarged plan view showing the layout of the first main surface of the semiconductor device according to the second embodiment.

[0036] Fig.26 is along Fig.25 A cross-sectional view taken along line XXVI-XXVI is shown.

[0037] Fig. 27 FIG. 1 is a plan view showing the layout of the first main surface of the semiconductor device according to the third embodiment.

[0038] Fig.28 Yes means Fig. 27 FIG. 1 is a cross-sectional view of the structure of a semiconductor device on the boundary region side.

[0039] Fig.29 Yes means Fig. 27 2 is a cross-sectional view of the structure of the semiconductor device on the peripheral region side.

[0040] Fig.30 It is an enlarged plan view showing a first resistor connecting electrode according to a modification example.

[0041] Fig.31 1 is a cross-sectional view showing a second resistor connecting electrode according to a first modification example.

[0042] Fig.32 It is an enlarged plan view showing the second resistor connecting electrode according to the second modification example.

[0043] Fig.33 It is an enlarged plan view showing the second resistor connecting electrode according to the third modification example.

[0044] Fig.34 2 is a cross-sectional view showing a third resistor connecting electrode according to the first modification example.

[0045] Fig.35 It is an enlarged plan view showing the third resistor connecting electrode of the second modification example.

[0046] Fig.36 It is an enlarged plan view showing a third resistor connecting electrode according to a third modification example.

[0047] Fig.37 It is an enlarged plan view showing the gate resistor structure of the first modification example.

[0048] Fig.38 Yes means Fig.37 An enlarged top view of the inner portion of the gate resistor structure is shown.

[0049] Fig.39 It is an enlarged plan view showing the gate resistor structure of the second modification example.

[0050] Fig.40 It is an enlarged plan view showing a gate resistor structure according to a third modification.

[0051] Fig.41 This is a circuit diagram showing a gate resistor structure, a gate terminal electrode, and a gate wiring electrode.

[0052] Fig.42 It is a plan view showing a gate wiring electrode according to a modification and an emitter terminal electrode according to a modification.

[0053] Fig.43 It is an enlarged plan view showing a gate connection electrode of a modified example.

[0054] Fig.44 is along Fig.43 A cross-sectional view taken along line XLIV-XLIV is shown. DETAILED DESCRIPTION

[0055] The specific method is described in detail below with reference to the accompanying drawings. The accompanying drawings are schematic diagrams and are not strictly illustrated, and the scales and the like are not necessarily the same. In addition, the same reference symbols are given to corresponding structures between the drawings, and repeated descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions before the omission or simplification shall apply.

[0056] When the phrase "substantially equal" is used in the description of a comparison target, the phrase includes not only a numerical value (method) equal to the numerical value (method) of the comparison target, but also a numerical error (method error) within a range of ±10% based on the numerical value (method) of the comparison target. In the embodiments, the phrases such as "first", "second", and "third" are used, but they are symbols for the names of the structures in order to clarify the order of description, and are not intended to limit the names of the structures.

[0057] Figure 1 1 is a plan view showing a semiconductor device 1A according to a first embodiment. Figure 2 It is a plan view showing the layout of the first main surface 3 . Figure 3 It is an enlarged plan view showing the active region 6 and the peripheral region 9 . Figure 4 is along Figure 3 A cross-sectional view taken along line IV-IV is shown. Figure 5 is along Figure 3 A cross-sectional view taken along line VV is shown.

[0058] Figure 6 is along Figure 3 A cross-sectional view taken along line VI-VI is shown. Figure 7 It is an enlarged plan view showing the active region 6 and the boundary region 8 . Figure 8 is along Figure 7 A cross-sectional view taken along line VIII-VIII is shown. Fig. 9 is along Figure 7 A cross-sectional view taken along line IX-IX is shown. Fig.10 It is a cross-sectional view showing the structure of the outer peripheral region 9 .

[0059] The semiconductor device 1A is an IGBT (Insulated Gate Bipolar Transistor) semiconductor device. Figures 1 to 10 The semiconductor device 1A includes a hexahedral (specifically, a rectangular parallelepiped) chip 2. The chip 2 may also be referred to as a “semiconductor chip.” In this embodiment, the chip 2 has a single-layer structure composed of a silicon single crystal substrate (semiconductor substrate).

[0060] The chip 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting the first main surface 3 and the second main surface 4. The first main surface 3 and the second main surface 4 are formed into a quadrilateral shape when viewed from above (hereinafter referred to as "viewed from above") from their normal direction Z. The normal direction Z is also the thickness direction of the chip 2.

[0061] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and are opposed to each other in a second direction Y intersecting the first direction X along the first main surface 3. Specifically, the second direction Y is orthogonal to the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and are opposed to each other in the first direction X.

[0062] The semiconductor device 1A includes a plurality of active regions 6 arranged at intervals on the first main surface 3. The plurality of active regions 6 include a first active region 6A on one side and a second active region 6B on the other side. The first active region 6A is provided in a region on the first side surface 5A side relative to a straight line that crosses the center of the first main surface 3 in the first direction X.

[0063] The second active region 6B is provided in a region on the second side surface 5B side relative to a straight line crossing the center of the first main surface 3 in the first direction X. In this embodiment, each active region 6 is formed into a polygonal shape having four sides parallel to the periphery of the chip 2 in a plan view. The planar shape of each active region 6 is arbitrary.

[0064] The semiconductor device 1A includes an inactive region 7 provided in a region outside the plurality of active regions 6 on the first main surface 3. The inactive region 7 includes a boundary region 8 and a peripheral region 9. The boundary region 8 is provided in a band shape extending in the first direction X in a region between the first active region 6A and the second active region 6B. In this embodiment, the boundary region 8 is located on a straight line crossing the center of the first main surface 3 in the first direction X.

[0065] The boundary region 8 includes: a pad region 10 having a relatively large width in the second direction Y; and a scribeline region 11 having a width smaller than that of the pad region 10 in the second direction Y. The pad region 10 may also be referred to as a "first boundary region" or a "wide width region". The scribeline region 11 may also be referred to as a "second boundary region", a "line region" or a "narrow width region".

[0066] The pad region 10 is provided in a region on one side (the third side surface 5C side) in the first direction X. In this embodiment, the pad region 10 is located on a straight line crossing the center of the first main surface 3 in the first direction X in a plan view, and is formed into a quadrilateral shape near the center of the third side surface 5C.

[0067] The scribe line region 11 is provided in a region on the other side (the fourth side surface 5D side) relative to the pad region 10 in the first direction X. In this embodiment, the scribe line region 11 is led out in a strip shape from the pad region 10 toward the fourth side surface 5D side and is located on a straight line crossing the center of the first main surface 3 in the first direction X.

[0068] The peripheral region 9 is provided at the peripheral portion of the chip 2 in a manner of surrounding a plurality of active regions 6. The peripheral region 9 is provided in a ring shape (a four-sided ring shape in this embodiment) extending along the periphery (the first to fourth side surfaces 5A to 5D) of the chip 2. The peripheral region 9 is connected to the pad region 10 on one side (the third side surface 5C side) of the first main surface 3, and is connected to the dicing road region 11 on the other side (the fourth side surface 5D side) of the first main surface 3.

[0069] The semiconductor device 1A includes an n-type (first conductivity type) drift region 12 formed inside the chip 2. The drift region 12 is formed in the entire region inside the chip 2. In this embodiment, the chip 2 is composed of an n-type semiconductor substrate (n-type semiconductor chip), and the drift region 12 is formed using the n-type chip 2.

[0070] The semiconductor device 1A includes an n-type buffer region 13 formed in the surface portion of the second main surface 4. In this embodiment, the buffer region 13 is formed in a layer extending along the second main surface 4 in the entire region of the second main surface 4. The buffer region 13 has a higher n-type impurity concentration than the drift region 12. The presence or absence of the buffer region 13 is optional, and an embodiment without the buffer region 13 may be adopted.

[0071] The semiconductor device 1A includes a p-type (second conductivity type) collector region 14 formed on the surface portion of the second main surface 4. The collector region 14 is formed on the surface portion of the buffer region 13 on the second main surface 4 side. In this embodiment, the collector region 14 is formed in a layer extending along the second main surface 4 in the entire region of the second main surface 4. The collector region 14 is exposed from the second main surface 4 and a portion of the first to fourth side surfaces 5A to 5D.

[0072] The semiconductor device 1A includes a plurality of trench isolation structures 15 formed on the first main surface 3 in a manner of dividing a plurality of active regions 6. A gate potential is given to the plurality of trench isolation structures 15. The trench isolation structure 15 may also be referred to as a "trench gate isolation structure" or a "trench gate connection structure". The plurality of trench isolation structures 15 include a first trench isolation structure 15A on the first active region 6A side and a second trench isolation structure 15B on the second active region 6B side.

[0073] The first trench isolation structure 15A surrounds the first active region 6A and divides the first active region 6A from the boundary region 8 and the peripheral region 9. In this embodiment, the first trench isolation structure 15A is formed into a polygonal ring having four sides parallel to the periphery of the chip 2 when viewed from above. The first trench isolation structure 15A has a bent portion so as to divide the pad region 10 and the dicing street region 11 of the boundary region 8 when viewed from above.

[0074] The second trench isolation structure 15B surrounds the second active region 6B and divides the second active region 6B from the boundary region 8 and the peripheral region 9. In this embodiment, the second trench isolation structure 15B is formed into a polygonal ring having four sides parallel to the periphery of the chip 2 when viewed from above. The second trench isolation structure 15B has a bent portion so as to divide the pad region 10 and the dicing street region 11 of the boundary region 8 when viewed from above.

[0075] The trench isolation structure 15 preferably has a width smaller than the width of the street region 11. The width of the trench isolation structure 15 is a width in a direction perpendicular to the direction in which the trench isolation structure 15 extends.

[0076] The width of the trench isolation structure 15 may be greater than or equal to 0.1 μm and less than or equal to 2.5 μm. The width of the trench isolation structure 15 is preferably greater than or equal to 0.3 μm and less than or equal to 1 μm. The width of the trench isolation structure 15 is particularly preferably greater than or equal to 0.4 μm and less than or equal to 0.7 μm. The trench isolation structure 15 may also have a depth of greater than or equal to 1 μm and less than or equal to 20 μm. The depth of the trench isolation structure 15 is preferably greater than or equal to 4 μm and less than or equal to 10 μm.

[0077] The following describes the structure of a trench isolation structure 15. The trench isolation structure 15 includes a separation trench 16, a separation insulating film 17, and a separation buried electrode 18. The separation trench 16 is formed on the first main surface 3 to define the wall surface of the trench isolation structure 15. The separation insulating film 17 covers the wall surface of the separation trench 16 in a film shape. The separation insulating film 17 may also include at least one of a silicon oxide film, a silicon nitride film, and an aluminum oxide film.

[0078] The separation insulating film 17 preferably has a single-layer structure composed of a single insulating film. The separation insulating film 17 particularly preferably includes a silicon oxide film composed of an oxide of the chip 2. The separation buried electrode 18 is buried in the separation trench 16 via the separation insulating film 17. The separation buried electrode 18 may also include conductive polysilicon. A gate potential is given to the separation buried electrode 18.

[0079] The semiconductor device 1A includes an IGBT structure Tr (transistor structure) formed in each active region 6. The IGBT structure Tr is not formed in the inactive region 7. The structure on the second active region 6B side (the structure of the IGBT structure Tr) is substantially the same as the structure on the first active region 6A side (the structure of the IGBT structure Tr), so the structure on the first active region 6A side will be described below. In this embodiment, the structure on the second active region 6B side is symmetrical to the structure on the first active region 6A side across the boundary region 8. The description of the structure on the second active region 6B side is applied to the description of the structure on the first active region 6A side and is omitted.

[0080] The semiconductor device 1A includes a p-type base region 20 formed in the surface portion of the first main surface 3 in the first active region 6A. The base region 20 may also be referred to as a "body region" or a "channel region". The base region 20 extends in a layer along the first main surface 3 and is connected to the inner peripheral wall of the trench isolation structure 15. The base region 20 is formed to be shallower than the trench isolation structure 15 and has a bottom located on the first main surface 3 side relative to the bottom wall of the trench isolation structure 15. The bottom of the base region 20 is preferably located on the first main surface 3 side relative to the middle of the depth range of the trench isolation structure 15.

[0081] The semiconductor device 1A includes a plurality of first trench structures 21 formed in the first main surface 3 in the first active region 6A. A gate potential is applied to the plurality of first trench structures 21. The first trench structure 21 may also be referred to as a "trench gate structure."

[0082] The plurality of first trench structures 21 penetrate the base region 20 so as to reach the drift region 12. The plurality of first trench structures 21 are arranged at intervals in the first direction X in a plan view, and are each formed in a strip shape extending in the second direction Y. That is, the plurality of first trench structures 21 are arranged in a stripe shape extending in the second direction Y.

[0083] Each first groove structure 21 has one end on the side of the boundary region 8 and the other end on the side of the peripheral region 9 in the length direction (second direction Y). One end and the other end of the plurality of first groove structures 21 are mechanically and electrically connected to the groove separation structure 15. That is, the plurality of first groove structures 21 together with the groove separation structure 15 form a ladder-shaped groove structure. The connection between the first groove structure 21 and the groove separation structure 15 can also be regarded as a part of the groove separation structure 15 and / or a part of the first groove structure 21.

[0084] The interval between the plurality of first trench structures 21 is preferably smaller than the width of the scribe line region 11. The width of the first trench structure 21 is preferably smaller than the width of the scribe line region 11. The width of the first trench structure 21 is the width in a direction perpendicular to the direction in which the first trench structure 21 extends.

[0085] The width of the first trench structure 21 may be 0.1 μm to 2.5 μm. The width of the first trench structure 21 is preferably 0.3 μm to 1 μm. The width of the first trench structure 21 is particularly preferably 0.4 μm to 0.7 μm. The width of the first trench structure 21 is preferably substantially equal to the width of the trench isolation structure 15.

[0086] The first trench structure 21 may have a depth of 1 μm or more and 20 μm or less. The depth of the first trench structure 21 is preferably 4 μm or more and 10 μm or less. The depth of the first trench structure 21 is preferably substantially equal to the depth of the trench isolation structure 15 .

[0087] The structure of a first trench structure 21 is described below. The first trench structure 21 includes a first trench 22, a first insulating film 23, and a first buried electrode 24. The first trench 22 is formed on the first main surface 3 and defines the wall surface of the first trench structure 21. In this embodiment, the first trench 22 is connected to the separation trench 16 at both ends in the second direction Y. Specifically, the side wall of the first trench 22 is connected to the side wall of the separation trench 16, and the bottom wall of the first trench 22 is connected to the bottom wall of the separation trench 16.

[0088] The first insulating film 23 covers the wall surface of the first trench 22 in a film shape. The first insulating film 23 may include at least one of a silicon oxide film, a silicon nitride film, and an aluminum oxide film. The first insulating film 23 preferably has a single-layer structure composed of a single insulating film.

[0089] The first insulating film 23 preferably includes a silicon oxide film made of the oxide of the chip 2. In this embodiment, the first insulating film 23 is made of the same insulating film as the isolation insulating film 17. The first insulating film 23 is connected to the isolation insulating film 17 in the communicating portion between the isolation trench 16 and the first trench 22.

[0090] The first buried electrode 24 is buried in the first trench 22 via the first insulating film 23. The first buried electrode 24 may also include conductive polysilicon. A gate potential is applied to the first buried electrode 24. The first buried electrode 24 is mechanically and electrically connected to the separation buried electrode 18 in the communicating portion between the separation trench 16 and the first trench 22.

[0091] The semiconductor device 1A includes a plurality of second trench structures 25, each of which is formed in a region between adjacent first trench structures 21 in the first main surface 3 of the first active region 6A. The second trench structure 25 may also be referred to as an "emitter trench structure". Each second trench structure 25 is formed in a quadrilateral ring shape extending in the second direction Y, spaced apart from the plurality of first trench structures 21X in a first direction when viewed from above.

[0092] The width of the second trench structure 25 is preferably smaller than the width of the scribe line region 11. The width of the second trench structure 25 is the width in a direction perpendicular to the direction in which the second trench structure 25 extends.

[0093] The width of the second groove structure 25 may be 0.1 μm to 2.5 μm. The width of the second groove structure 25 is preferably 0.3 μm to 1 μm. The width of the second groove structure 25 is particularly preferably 0.4 μm to 0.7 μm. The width of the second groove structure 25 is preferably substantially equal to the width of the first groove structure 21.

[0094] The second trench structure 25 may have a depth of 1 μm to 20 μm. The depth of the second trench structure 25 is preferably 4 μm to 10 μm. The depth of the second trench structure 25 is preferably substantially equal to the depth of the first trench structure 21 .

[0095] The following describes the structure of one second trench structure 25. The second trench structure 25 includes a second trench 26, a second insulating film 27, and a second embedded electrode 28. The second trench 26 is formed in the first main surface 3, and defines a wall surface of the second trench structure 25.

[0096] The second insulating film 27 covers the wall surface of the second trench 26 in a film shape. The second insulating film 27 may also include at least one of a silicon oxide film, a silicon nitride film, and an aluminum oxide film. The second insulating film 27 preferably has a single-layer structure composed of a single insulating film. The second insulating film 27 particularly preferably includes a silicon oxide film composed of an oxide of the chip 2. In this embodiment, the second insulating film 27 is composed of the same insulating film as the first insulating film 23.

[0097] The second embedded electrode 28 is embedded in the second trench 26 via the second insulating film 27. The second embedded electrode 28 may include conductive polysilicon. The second embedded electrode 28 is given an emitter potential.

[0098] The semiconductor device 1A includes a plurality of n-type emitter regions 29 formed in the first active region 6A in the surface layer portion of the base region 20. The plurality of emitter regions 29 each have a higher n-type impurity concentration than the drift region 12. The plurality of emitter regions 29 are formed on both sides of the plurality of first trench structures 21, respectively.

[0099] The plurality of emitter regions 29 are formed in a strip shape extending along the plurality of first trench structures 21 in a plan view. Of course, the plurality of emitter regions 29 may be formed at intervals along the plurality of first trench structures 21 in a plan view.

[0100] In this embodiment, a plurality of emitter regions 29 are formed in the region between the first trench structure 21 and the second trench structure 25 so as to be connected to the first trench structure 21 and the second trench structure 25. The emitter region 29 is preferably not formed in the region between the trench isolation structure 15 and the outermost first trench structure 21.

[0101] The semiconductor device 1A includes a plurality of contact holes 30 formed in the first main surface 3 in the first active region 6A so as to expose the emitter region 29. The plurality of contact holes 30 are formed on both sides of the plurality of first trench structures 21 at intervals from the plurality of first trench structures 21. The plurality of contact holes 30 may be formed in a tapered shape in which the opening width becomes narrower from the opening toward the bottom wall.

[0102] The plurality of contact holes 30 may be separated from the bottom of the emitter region 29 toward the first main surface 3 so as not to reach the base region 20 . Of course, the plurality of contact holes 30 may penetrate the emitter region 29 so as to reach the base region 20 .

[0103] The contact holes 30 are formed in a strip shape extending along the first trench structures 21 in a plan view. The contact holes 30 are preferably shorter than the first trench structures 21 in the length direction (second direction Y). The contact holes 30 are particularly preferably shorter than the second trench structures 25.

[0104] The semiconductor device 1A includes a plurality of p-type contact regions 31 formed in a region different from the plurality of emitter regions 29 in the surface layer portion of the base region 20 of the first active region 6A. The plurality of contact regions 31 have a higher p-type impurity concentration than the base region 20. The plurality of contact regions 31 are formed in a strip shape extending along the corresponding contact holes 30 in a plan view. The bottoms of the plurality of contact regions 31 are formed in a region between the bottom wall of the corresponding contact hole 30 and the bottom of the base region 20.

[0105] The semiconductor device 1A includes a plurality of p-type floating regions 32, each of which is formed in a region surrounded by a plurality of second trench structures 25 in the surface layer portion of the first main surface 3 of the first active region 6A. The plurality of floating regions 32 are formed in an electrically floating state. Of course, an emitter potential may be given to the plurality of floating regions 32. The plurality of floating regions 32 preferably have a higher p-type impurity concentration than the base region 20.

[0106] Each floating region 32 extends in a layered manner along the first main surface 3 and is connected to the inner peripheral wall of each second groove structure 25. Each floating region 32 is preferably formed deeper than the middle portion of the depth range of the second groove structure 25. In this embodiment, each floating region 32 is formed deeper than the second groove structure 25 and has a portion covering the bottom wall of the second groove structure 25.

[0107] Thus, the first active region 6A includes, as the IGBT structure Tr, the base region 20 , the plurality of first trench structures 21 , the plurality of second trench structures 25 , the plurality of emitter regions 29 , the plurality of contact holes 30 , the plurality of contact regions 31 , and the plurality of floating regions 32 .

[0108] In addition, similar to the first active region 6A, the second active region 6B includes a base region 20 , a plurality of first trench structures 21 , a plurality of second trench structures 25 , a plurality of emitter regions 29 , a plurality of contact holes 30 , a plurality of contact regions 31 , and a plurality of floating regions 32 as an IGBT structure Tr.

[0109] The semiconductor device 1A includes a p-type boundary well region 40 formed in the surface portion of the first main surface 3 in the boundary region 8. In this embodiment, the boundary well region 40 has a higher p-type impurity concentration than the base region 20. Of course, the boundary well region 40 may also have a lower p-type impurity concentration than the base region 20.

[0110] The boundary well region 40 is formed in a strip shape extending in the first direction X along the boundary region 8 when viewed from above. That is, the boundary well region 40 is formed in a layer shape extending along the first main surface 3 in the region sandwiched by the first trench isolation structure 15A and the second trench isolation structure 15B, and is exposed from the first main surface 3. The boundary well region 40 is formed in the region sandwiched by the plurality of first trench structures 21 on the first active region 6A side and the plurality of first trench structures 21 on the second active region 6B side.

[0111] The boundary well region 40 includes a first boundary well region 40A formed in the pad region 10 and a second boundary well region 40B formed in the scribe line region 11. The first boundary well region 40A has a relatively large region width in the second direction Y. The first boundary well region 40A is formed in a polygonal shape (a quadrilateral shape in this embodiment) when viewed from above. The first boundary well region 40A is preferably formed in the entire region of the pad region 10.

[0112] The second boundary well region 40B has a smaller area width than the area width of the first boundary well region 40A in the second direction Y, and is led out in a strip shape from the first boundary well region 40A toward the scribe line region 11. In this manner, the second boundary well region 40B is located on a straight line that crosses the center of the first main surface 3 in the first direction X. The second boundary well region 40B extends in a strip shape in a region located on one side (the third side surface 5C side) and a region on the other side (the fourth side surface 5D side) in the first direction X with respect to the straight line that crosses the center of the first main surface 3 in the second direction Y.

[0113] The boundary well region 40 is preferably formed deeper than the base region 20. The boundary well region 40 is particularly preferably formed deeper than the plurality of trench isolation structures 15 (plurality of first trench structures 21). In this embodiment, the boundary well region 40 has a width greater than that of the boundary region 8 in the second direction Y, and is led out from the boundary region 8 into the plurality of active regions 6.

[0114] The boundary well region 40 is connected to the adjacent trench isolation structures 15 in the second direction Y. The boundary well region 40 has a portion covering the bottom walls of the trench isolation structures 15. The boundary well region 40 has a portion crossing the trench isolation structures 15 and covering the bottom walls of the first trench structures 21.

[0115] The boundary well region 40 covers the sidewalls of the trench isolation structure 15 and the sidewalls of the plurality of trench structures in the plurality of active regions 6, and is connected to each base region 20 in the surface portion of the first main surface 3. The depth of the boundary well region 40 may also be greater than 1 μm and less than 20 μm. The depth of the boundary well region 40 is preferably greater than 5 μm and less than 10 μm.

[0116] The semiconductor device 1A includes a p-type peripheral well region 41 formed in the surface portion of the first main surface 3 in the peripheral region 9. In this embodiment, the peripheral well region 41 has a p-type impurity concentration higher than that of the base region 20. Of course, the peripheral well region 41 may also have a p-type impurity concentration lower than that of the base region 20. The p-type impurity concentration of the peripheral well region 41 is preferably substantially equal to the p-type impurity concentration of the boundary well region 40.

[0117] The peripheral well region 41 is formed in a layer extending along the first main surface 3 and exposed from the first main surface 3. The peripheral well region 41 is formed inwardly at intervals from the periphery (the first to fourth side surfaces 5A to 5D) of the first main surface 3. The peripheral well region 41 is formed in a band shape extending along the plurality of active regions 6 when viewed from above. In this embodiment, the peripheral well region 41 is formed in a ring shape (a four-sided ring shape in this embodiment) that surrounds the plurality of active regions 6 when viewed from above.

[0118] The peripheral well region 41 is preferably formed deeper than the base region 20 . The peripheral well region 41 is particularly preferably formed deeper than the plurality of trench isolation structures 15 (plurality of first trench structures 21 ). The peripheral well region 41 preferably has a depth substantially equal to that of the boundary well region 40 .

[0119] The peripheral well region 41 is connected to the plurality of trench isolation structures 15. The peripheral well region 41 has a portion covering the bottom walls of the plurality of trench isolation structures 15. The peripheral well region 41 is led out from the peripheral region 9 into the plurality of active regions 6. The peripheral well region 41 has a portion crossing the plurality of trench isolation structures 15 and covering the bottom walls of the plurality of first trench structures 21.

[0120] The peripheral well region 41 covers the sidewalls of the trench isolation structure 15 and the sidewalls of the plurality of first trench structures 21 in each active region 6, and is connected to the plurality of base regions 20 in the surface portion of the first main surface 3. The peripheral well region 41 is connected to the boundary well region 40 in the connection portion between the boundary region 8 and the peripheral region 9. That is, the peripheral well region 41 and the boundary well region 40 divide the plurality of active regions 6 together.

[0121] Reference Fig.10 The semiconductor device 1A includes at least one (a plurality of in this embodiment) p-type field region 42, and the at least one p-type field region 42 is formed in the surface portion of the first main surface 3 in the peripheral region 9. The number of field regions 42 is arbitrary, and may be more than 1 and less than 20 (typically more than 3 and less than 10).

[0122] The plurality of field regions 42 may also have a higher p-type impurity concentration than the base region 20. The plurality of field regions 42 may also have a higher p-type impurity concentration than the peripheral well region 41. The plurality of field regions 42 may also have a lower p-type impurity concentration than the peripheral well region 41. The plurality of field regions 42 may also have a p-type impurity concentration substantially equal to that of the peripheral well region 41. The plurality of field regions 42 are formed in an electrically floating state.

[0123] A plurality of field regions 42 are formed in the region between the periphery of the chip 2 and the peripheral well region 41 at intervals from the periphery of the chip 2 and the peripheral well region 41. The plurality of field regions 42 are formed into a band shape extending along the peripheral well region 41 when viewed from above. In this embodiment, the plurality of field regions 42 are formed into a ring shape (a quadrilateral ring shape) surrounding the peripheral well region 41 when viewed from above.

[0124] The plurality of field regions 42 are preferably formed deeper than the base region 20. The plurality of field regions 42 may be formed at a depth substantially equal to that of the peripheral well region 41. The plurality of field regions 42 may be formed shallower than the peripheral well region 41. The plurality of field regions 42 may be formed at a constant depth.

[0125] The intervals between the plurality of field regions 42 may gradually increase toward the periphery of the chip 2. The plurality of field regions 42 each have a width smaller than that of the peripheral well region 41. The outermost field region 42 of the plurality of field regions 42 may be formed wider than the other field regions 42.

[0126] Semiconductor device 1A includes n-type channel stop regions 43 formed on the surface of first main surface 3 at intervals from a plurality of field regions 42 toward the periphery of chip 2 in peripheral region 9. Channel stop regions 43 have a higher n-type impurity concentration than drift region 12.

[0127] The channel blocking region 43 is formed in a strip shape extending along the periphery of the chip 2 in a plan view. In this embodiment, the channel blocking region 43 is formed in a ring shape (quadrilateral ring shape) surrounding the plurality of field regions 42 in a plan view. The channel blocking region 43 may also be exposed from the first to fourth side surfaces 5A to 5D. The channel blocking region 43 is formed in an electrically floating state.

[0128] The semiconductor device 1A includes a main surface insulating film 45 that selectively covers the first main surface 3. The main surface insulating film 45 selectively covers the first main surface 3 in the active region 6, the boundary region 8, and the peripheral region 9. The main surface insulating film 45 may include at least one of a silicon oxide film, a silicon nitride film, and an aluminum oxide film.

[0129] The main surface insulating film 45 preferably has a single-layer structure composed of a single insulating film. The main surface insulating film 45 particularly preferably includes a silicon oxide film composed of the oxide of the chip 2. In this embodiment, the main surface insulating film 45 is composed of the same insulating film as the first insulating film 23 (separation insulating film 17). The main surface insulating film 45 covers the first main surface 3 in a manner that exposes the trench isolation structure 15, the first trench structure 21, and the second trench structure 25.

[0130] Specifically, the main surface insulating film 45 is connected to the separation insulating film 17, the first insulating film 23, and the second insulating film 27, and exposes the separation buried electrode 18, the first buried electrode 24, and the second buried electrode 28. The main surface insulating film 45 selectively covers the boundary well region 40, the peripheral well region 41, the field region 42, and the channel stop region 43 in the boundary region 8 and the peripheral region 9.

[0131] The main surface insulating film 45 is formed at intervals inward from the periphery of the first main surface 3 to define a removal portion 46 that exposes the periphery of the first main surface 3. The removal portion 46 exposes the channel blocking region 43 in the periphery of the first main surface 3. The removal portion 46 is formed in a band shape extending along the periphery (the first to fourth side surfaces 5A to 5D) of the first main surface 3. In this embodiment, the removal portion 46 is formed in a ring shape extending along the periphery of the first main surface 3.

[0132] Reference Figure 3 as well as Figure 6 The semiconductor device 1A includes a plurality of emitter electrode films 47 arranged on the first main surface 3 so as to cover the plurality of second trench structures 25 in the active region 6. Specifically, the plurality of emitter electrode films 47 are arranged on the main surface insulating film 45. The plurality of emitter electrode films 47 may also include conductive polysilicon.

[0133] The plurality of emitter electrode films 47 respectively cover both ends of the plurality of second trench structures 25 in the second direction Y. In this embodiment, the plurality of emitter electrode films 47 are formed in a belt shape extending in the second direction Y in a region between the corresponding second trench structures 25 and the trench isolation structure 15. The plurality of emitter electrode films 47 are formed with intervals from the trench isolation structure 15 toward the second trench structure 25. The plurality of emitter electrode films 47 are opposed to the base region 20 via the main surface insulating film 45.

[0134] The plurality of emitter electrode films 47 are formed integrally with the second buried electrodes 28 of the plurality of second trench structures 25. That is, the plurality of emitter electrode films 47 are each composed of a portion of the second buried electrode 28 that is led out in a film-like manner onto the first main surface 3 (main surface insulating film 45). Of course, the plurality of emitter electrode films 47 may also be formed separately from the second buried electrode 28.

[0135] Fig.11 It is an enlarged plan view showing the pad region 10 . Fig.12 Yes means Fig.11 An enlarged top view of the gate resistor structure 50 is shown. Fig.13 Yes means Fig.12 An enlarged top view of the inner portion of the gate resistor structure 50 is shown. Fig.14 Yes means Fig.12 An enlarged top view of one end portion of the gate resistor structure 50 is shown. Fig.15 Yes means Fig.12 An enlarged top view of the other end of the gate resistor structure 50 is shown.

[0136] Fig.16 is along Fig.13 A cross-sectional view taken along line XVI-XVI is shown. Fig.17 is along Fig.13 A cross-sectional view taken along line XVII-XVII is shown. Fig.18 is along Fig.13 A cross-sectional view taken along line XVIII-XVIII is shown. Fig.19 is along Fig.13 A cross-sectional view taken along line XIX-XIX is shown. Fig. 20 is along Fig.14 A cross-sectional view taken along line XX-XX is shown.

[0137] Fig.21 is along Fig.15 A cross-sectional view taken along line XXI-XXI is shown. Fig. 22 is along Fig.12 A cross-sectional view along line XXII-XXII is shown. Fig.23 It is a plan view showing the layout of the resistor film 60 , the gate electrode film 64 , and the gate wiring film 65 . Fig.241 is a circuit diagram showing the gate resistance structure 50 , the gate terminal electrode 90 , and the gate wiring electrode 93 .

[0138] Reference Figure 11 to Figure 24 The semiconductor device 1A includes a gate resistor structure 50 formed in the pad region 10. The gate resistor structure 50 constitutes a gate resistor RG with respect to the gate of the IGBT (the first trench structure 21 of the IGBT structure Tr). For example, the gate resistor RG (gate resistor structure 50) is effective in suppressing oscillation (noise) caused by parasitic inductance at the time of turn-off.

[0139] The gate resistor structure 50 includes a plurality of trench resistor structures 51 formed on the first main surface 3 in the pad region 10. A gate potential is applied to the plurality of trench resistor structures 51, and the plurality of trench resistor structures 51 do not contribute to control of the channel.

[0140] In this embodiment, the plurality of gate resistor structures 50 constitute a first trench group 52 and a second trench group 53. The first trench group 52 includes a plurality of first trench resistor structures 51A constituting a part of the plurality of trench resistor structures 51, and is provided on one side (the first side surface 5A side) in the second direction Y. The number of the first trench resistor structures 51A is arbitrary and is adjusted based on the resistance value to be achieved.

[0141] For example, the first trench group 52 may include more than 2 and less than 100 first trench resistor structures 51A. The number of first trench resistor structures 51A is preferably less than 50. The number of first trench resistor structures 51A may also be less than 25. The number of first trench resistor structures 51A is preferably more than 5. Of course, the gate resistor structure 50 may also include a single first trench resistor structure 51A instead of the first trench group 52.

[0142] In this embodiment, the first groove group 52 is provided in a region on one side (first side surface 5A) in the second direction Y relative to a straight line crossing the center of the first main surface 3 in the first direction X. The first groove group 52 is preferably arranged in the pad region 10 to be closer to the active region 6 side (the scribe line region 11 side) than the peripheral region 9 .

[0143] In this embodiment, the first trench group 52 is arranged at intervals from the center of the pad region 10 toward the active region 6 side (the scribe line region 11 side). These structures are effective in suppressing the electric field concentration on the plurality of first trench resistor structures 51A.

[0144] The plurality of first trench resistor structures 51A are formed on the first main surface 3 at intervals from the plurality of trench isolation structures 15 (plurality of first trench structures 21). The plurality of first trench resistor structures 51A are arranged at intervals in the first direction X in a plan view and are each formed in a strip shape extending in the second direction Y.

[0145] That is, the plurality of first trench resistor structures 51A are arranged in a stripe shape extending in the second direction Y. The plurality of first trench resistor structures 51A have one end on one side of the second direction Y (on the first side surface 5A side) and the other end on the other side of the second direction Y (on the second side surface 5B side).

[0146] The plurality of first trench resistor structures 51A are formed to be located in the boundary well region 40 (first boundary well region 40A) at intervals from the bottom of the boundary well region 40 (first boundary well region 40A) toward the first main surface 3, and are opposed to the drift region 12 via a portion of the boundary well region 40. That is, the plurality of first trench resistor structures 51A do not penetrate the boundary well region 40 (first boundary well region 40A).

[0147] The interval between the plurality of first trench resistor structures 51A is preferably smaller than the width of the scribe line region 11. The interval between the plurality of first trench resistor structures 51A is preferably substantially equal to the interval between the first trench structure 21 and the second trench structure 25. The interval between the plurality of first trench resistor structures 51A may also be smaller than the interval between the first trench structure 21 and the second trench structure 25. The interval between the plurality of first trench resistor structures 51A may also be larger than the interval between the first trench structure 21 and the second trench structure 25.

[0148] The width of the first trench resistor structure 51A is preferably smaller than the width of the scribe line region 11. The width of the first trench resistor structure 51A is a width in a direction perpendicular to the direction in which the first trench resistor structure 51A extends.

[0149] The width of the first trench resistor structure 51A may be 0.1 μm or more and 2.5 μm or less. The width of the first trench resistor structure 51A is preferably 0.3 μm or more and 1 μm or less. The width of the first trench resistor structure 51A is particularly preferably 0.4 μm or more and 0.7 μm or less. The width of the first trench resistor structure 51A is preferably substantially equal to the width of the first trench structure 21.

[0150] The first trench resistor structure 51A may have a depth of 1 μm to 20 μm. The depth of the first trench resistor structure 51A is preferably 4 μm to 10 μm. The depth of the first trench resistor structure 51A is preferably substantially equal to the depth of the first trench structure 21 .

[0151] The second trench group 53 includes a plurality of second trench resistor structures 51B constituting a part of the plurality of trench resistor structures 51, and is disposed at intervals from the first trench group 52 to the other side (the second side surface 5B side) in the second direction Y. The number of the second trench resistor structures 51B is arbitrary and is adjusted based on the resistance value to be achieved. For example, in the case of achieving a resistance value substantially equal to the resistance value on the first trench group 52 side, the second trench group 53 may include the same number of second trench resistor structures 51B as the number of first trench resistor structures 51A.

[0152] For example, in order to realize a resistance value different from the resistance value on the first trench group 52 side, the second trench group 53 may include a number of second trench resistance structures 51B different from the number of first trench resistance structures 51A.

[0153] For example, when the resistance value on the second trench group 53 side is greater than the resistance value on the first trench group 52 side, the number of second trench resistance structures 51B may be less than the number of first trench resistance structures 51A. For example, when the resistance value on the second trench group 53 side is less than the resistance value on the first trench group 52 side, the number of second trench resistance structures 51B may be greater than the number of first trench resistance structures 51A.

[0154] For example, the second trench group 53 may include more than 2 and less than 100 second trench resistor structures 51B. The number of second trench resistor structures 51B is preferably less than 50. The number of second trench resistor structures 51B may also be less than 25. The number of second trench resistor structures 51B is preferably more than 5. Of course, the semiconductor device 1A may also include a single second trench resistor structure 51B instead of the second trench group 53.

[0155] In this embodiment, the second groove group 53 is provided in a region on the other side (second side surface 5B) in the second direction Y relative to a straight line crossing the center of the first main surface 3 in the first direction X. The second groove group 53 faces the first groove group 52 in the second direction Y.

[0156] The second trench group 53 is preferably arranged in the pad region 10 to be closer to the active region 6 side (the scribe line region 11 side) than the peripheral region 9. In this embodiment, the second trench group 53 is arranged with intervals from the central portion of the pad region 10 to the active region 6 side (the scribe line region 11 side). These structures are effective in suppressing the electric field concentration with respect to the plurality of second trench resistor structures 52B.

[0157] The plurality of second trench resistor structures 51B are formed on the first main surface 3 at intervals from the plurality of trench isolation structures 15 (plurality of first trench structures 21). The plurality of second trench resistor structures 51B are arranged at intervals in the first direction X in a plan view and are each formed in a strip shape extending in the second direction Y.

[0158] That is, the plurality of second trench resistor structures 51B are arranged in a stripe shape extending in the second direction Y. The plurality of second trench resistor structures 51B are respectively opposed to the plurality of first trench resistor structures 51A in a one-to-one correspondence in the second direction Y. That is, the plurality of second trench resistor structures 51B are respectively arranged in the same straight line as the plurality of first trench resistor structures 51A. The plurality of second trench resistor structures 51B have one end on one side of the second direction Y (on the first side surface 5A side) and the other end on the other side of the second direction Y (on the second side surface 5B side).

[0159] The plurality of second trench resistor structures 51B are formed at intervals from the bottom of the boundary well region 40 (first boundary well region 40A) toward the first main surface 3 so as to be located in the boundary well region 40 (first boundary well region 40A), and are opposed to the drift region 12 via a portion of the boundary well region 40. That is, the plurality of second trench resistor structures 51B do not penetrate the boundary well region 40 (first boundary well region 40A).

[0160] The interval between the plurality of second trench resistor structures 51B is preferably smaller than the width of the scribe line region 11. The interval between the plurality of second trench resistor structures 51B is preferably substantially equal to the interval between the adjacent first trench structures 21 and the second trench structures 25. The interval between the plurality of second trench resistor structures 51B may also be smaller than the interval between the first trench structures 21 and the second trench structures 25. The interval between the plurality of second trench resistor structures 51B may also be larger than the interval between the first trench structures 21 and the second trench structures 25.

[0161] The intervals between the plurality of second trench resistor structures 51B may be smaller than the intervals between the plurality of first trench resistor structures 51A. The intervals between the plurality of second trench resistor structures 51B may be larger than the intervals between the plurality of first trench resistor structures 51A. The intervals between the plurality of second trench resistor structures 51B are preferably substantially equal to the intervals between the plurality of first trench resistor structures 51A.

[0162] The width of the second trench resistor structure 51B is preferably smaller than the width of the scribe line region 11. The width of the second trench resistor structure 51B is a width in a direction orthogonal to the direction in which the second trench resistor structure 51B extends.

[0163] The width of the second trench resistor structure 51B may be 0.1 μm or more and 2.5 μm or less. The width of the second trench resistor structure 51B is preferably 0.3 μm or more and 1 μm or less. The width of the second trench resistor structure 51B is particularly preferably 0.4 μm or more and 0.7 μm or less. The width of the second trench resistor structure 51B is preferably substantially equal to the width of the first trench resistor structure 51A.

[0164] In this manner, the second trench resistor structure 51B has a length substantially equal to that of the first trench resistor structure 51A in the second direction Y. Of course, the second trench resistor structure 51B may be longer than the first trench resistor structure 51A in the second direction Y. In addition, the second trench resistor structure 51B may be shorter than the first trench resistor structure 51A in the second direction Y. The length of the first trench resistor structure 51A and the length of the second trench resistor structure 51B are adjusted according to the resistance value to be achieved.

[0165] The second trench resistor structure 51B may have a depth of 1 μm to 20 μm. The depth of the second trench resistor structure 51B is preferably 4 μm to 10 μm. The depth of the second trench resistor structure 51B is preferably substantially equal to the depth of the first trench resistor structure 51A (first trench structure 21).

[0166] The following describes the structure of one trench resistor structure 51 (a first trench resistor structure 51A and a second trench resistor structure 51B). The trench resistor structure 51 includes a resistor trench 54, a resistor insulating film 55, and a resistor embedded electrode 56. The resistor trench 54 is formed on the first main surface 3 and defines the wall surface of the trench resistor structure 51.

[0167] The resistor insulating film 55 covers the wall surface of the resistor groove 54 in a film shape. The resistor insulating film 55 is connected to the main surface insulating film 45 in the first main surface 3. The resistor insulating film 55 may also include at least one of a silicon oxide film, a silicon nitride film, and an aluminum oxide film. The resistor insulating film 55 preferably has a single-layer structure composed of a single insulating film. The resistor insulating film 55 particularly preferably includes a silicon oxide film composed of an oxide of the chip 2.

[0168] The resistor embedded electrode 56 is embedded in the resistor trench 54 via the resistor insulating film 55. The resistor embedded electrode 56 may include conductive polysilicon. A gate potential is applied to the resistor embedded electrode 56.

[0169] In this embodiment, the gate resistor structure 50 includes a space region 57 that is divided into a region between the first trench group 52 and the second trench group 53 in the pad region 10. The space region 57 is formed by a flat portion of the first main surface 3 in a region between the other ends of the plurality of first trench resistor structures 51A and one ends of the plurality of second trench resistor structures 51B.

[0170] In this embodiment, the space region 57 is divided into a quadrilateral shape in a plan view. The space region 57 exposes the boundary well region 40 from the first main surface 3. In this embodiment, the space region 57 is formed on a straight line crossing the center of the first main surface 3 in the first direction X in a plan view, and is opposite to the scribe line region 11 in the first direction X.

[0171] The space region 57 has a space width along the second direction Y. The space width is greater than the width of the first trench resistor structure 51A (the second trench resistor structure 51B) in the first direction X. The space width is greater than the interval between two adjacent first trench resistor structures 51A (the second trench resistor structure 51B) in the first direction X. The space width is preferably greater than the width of the first trench group 52 (the second trench group 53) in the first direction X. The space width may also be smaller than the width of the first trench group 52 (the second trench group 53) in the first direction X.

[0172] The space width is preferably smaller than the length of the first groove group 52 (second groove group 53) in the second direction Y. The space width may also be substantially equal to the width of the cutting street region 11 in the second direction Y. The space width may also be larger than the width of the cutting street region 11 in the second direction Y. The space width may also be smaller than the width of the cutting street region 11 in the second direction Y.

[0173] The gate resistor structure 50 includes a resistor film 60 disposed on the first main surface 3 so as to cover the plurality of trench resistor structures 51 in the pad region 10. Specifically, the resistor film 60 is disposed on the main surface insulating film 45. The resistor film 60 includes at least one of a conductive polysilicon film and an alloy film.

[0174] The alloy film may include alloy crystals composed of metal elements and non-metal elements. The alloy film may include at least one of a CrSi film, a CrSiN film, a CrSiO film, a TaN film, and a TiN film. In this embodiment, the resistor film 60 includes conductive polysilicon.

[0175] The thickness of the resistor film 60 is appropriately adjusted according to the resistance value to be achieved. The thickness of the resistor film 60 is preferably less than the depth of the first trench resistor structure 51A (second trench resistor structure 51B). The thickness of the resistor film 60 is particularly preferably less than the depth of the first trench resistor structure 51A (second trench resistor structure 51B).

[0176] The thickness of the resistor film 60 is preferably 0.5 times or more of the width of the first trench resistor structure 51A (the second trench resistor structure 51B). The thickness of the resistor film 60 may also be 0.05 μm or more and 2.5 μm or less. The thickness of the resistor film 60 is preferably 0.5 μm or more and 1.5 μm or less. When the resistor film 60 is composed of an alloy film, the thickness of the resistor film 60 may also be 0.1 nm or more and 100 nm or less.

[0177] The resistor film 60 is formed into a strip extending in the second direction Y, and has a first end 60A on one side of the second direction Y (the first side 5A side) and a second end 60B on the other side of the second direction Y (the second side 5B side). The resistor film 60 has a width in the first direction X that is greater than the width of the first groove group 52 (the second groove group 53) in the first direction X. The width of the resistor film 60 may also be less than the space width. Of course, the width of the resistor film 60 may also be greater than the space width. The resistor film 60 preferably has a uniform width in the first direction X.

[0178] The resistor film 60 has a portion located on one side (on the first side surface 5A side) and a portion located on the other side (on the second side surface 5B side) in the second direction Y relative to a straight line that crosses the center of the first main surface 3 in the first direction X. The resistor film 60 is opposite to the first active region 6A, the second active region 6B, and the scribe line region 11 in the first direction X. That is, the resistor film 60 is opposite to the plurality of trench isolation structures 15, the plurality of first trench structures 21, and the plurality of second trench structures 25 in the first direction X.

[0179] The resistor film 60 includes a first covering portion 61 covering the space region 57, a second covering portion 62 covering the first trench group 52, and a third covering portion 63 covering the second trench group 53. The first covering portion 61 is a portion covering the first main surface 3 in a region outside the first trench group 52 (a plurality of first trench resistor structures 51A) and the second trench group 53 (a plurality of second trench resistor structures 51B). The first covering portion 61 is located in the middle portion between the first end portion 60A and the second end portion 60B, and is opposed to the boundary well region 40 via the main surface insulating film 45 in the thickness direction.

[0180] The second covering portion 62 forms the first end portion 60A of the resistor film 60, covering all the first trench resistor structures 51A. The second covering portion 62 forms the first end portion 60A on the outer side (the peripheral side of the pad region 10) than one end portion of the plurality of first trench resistor structures 51A. That is, the first end portion 60A is opposite to the first covering portion 61 across the first trench group 52 when viewed from above. The second covering portion 62 is connected to the resistor embedded electrodes 56 of the plurality of first trench resistor structures 51A, and is opposite to the boundary well region 40 across the main surface insulating film 45 in the thickness direction.

[0181] The third covering portion 63 forms the second end portion 60B of the resistor film 60, covering all the second trench resistor structures 51B. The third covering portion 63 forms the second end portion 60B on the outside (the peripheral side of the pad region 10) of the other end portion of the plurality of second trench resistor structures 51B. That is, the second end portion 60B is opposite to the first covering portion 61 across the second trench group 53 when viewed from above. The third covering portion 63 is connected to the resistor embedded electrodes 56 of the plurality of second trench resistor structures 51B, and is opposite to the boundary well region 40 across the main surface insulating film 45 in the thickness direction.

[0182] The resistor film 60 is formed integrally with the resistor embedded electrodes 56 of the plurality of first trench resistor structures 51A in the second covering portion 62, and is formed integrally with the resistor embedded electrodes 56 of the plurality of second trench resistor structures 51B in the third covering portion 63. That is, the resistor film 60 is composed of a portion of the resistor embedded electrode 56 that is led out in a film shape onto the first main surface 3 (main surface insulating film 45). Of course, the resistor film 60 may also be formed separately from the resistor embedded electrode 56.

[0183] The semiconductor device 1A includes a gate electrode film 64, which is arranged on the first main surface 3 in a manner adjacent to the resistor film 60. Specifically, the gate electrode film 64 is arranged on the main surface insulating film 45. The gate electrode film 64 includes at least one of a conductive polysilicon film and an alloy film. The alloy film may also include alloy crystals composed of metal elements and non-metal elements.

[0184] The alloy film may also include at least one of a CrSi film, a CrSiN film, a CrSiO film, a TaN film, and a TiN film. The gate electrode film 64 is preferably formed of the same resistance material as the resistance film 60. In this embodiment, the gate electrode film 64 includes conductive polysilicon. The gate electrode film 64 preferably has a thickness substantially equal to that of the resistance film 60.

[0185] The gate electrode film 64 is disposed on the main surface insulating film 45 at a distance from the resistor film 60 toward the inner side (the third side surface 5C side) of the pad region 10, and is physically separated from the resistor film 60. The gate electrode film 64 is formed at a distance from the plurality of trench isolation structures 15 toward the inner side of the pad region 10 in a plan view.

[0186] The gate electrode film 64 is opposite to the boundary well region 40 (first boundary well region 40A) via the main surface insulating film 45. The gate electrode film 64 is formed in a polygonal shape (a quadrilateral shape in this embodiment) when viewed from above. In this embodiment, the gate electrode film 64 is formed in a rectangular shape extending in the second direction Y along the resistor film 60.

[0187] Reference Fig.11 , Fig.12 as well as Fig.24 The semiconductor device 1A includes a gate wiring film 65, which is arranged on the first main surface 3 adjacent to the resistor film 60 in a manner opposite to the gate electrode film 64 with the resistor film 60 interposed therebetween. Specifically, the gate wiring film 65 is arranged on the main surface insulating film 45. The gate wiring film 65 includes at least one of a conductive polysilicon film and an alloy film. The alloy film may also include alloy crystals composed of metal elements and non-metal elements.

[0188] The alloy film may also include at least one of a CrSi film, a CrSiN film, a CrSiO film, a TaN film, and a TiN film. The gate wiring film 65 is preferably formed of the same resistance material as the resistance film 60. In this embodiment, the gate wiring film 65 includes conductive polysilicon. The gate wiring film 65 preferably has a thickness substantially equal to that of the resistance film 60.

[0189] The gate wiring film 65 is disposed on the main surface insulating film 45 at a distance from the gate electrode film 64 and is physically separated from the gate electrode film 64. The gate wiring film 65 has a first connection portion connected to the first end 60A of the resistor film 60 and a second connection portion connected to the second end 60B of the resistor film 60.

[0190] That is, the gate wiring film 65 is electrically connected to the plurality of trench resistor structures 51 via the resistor film 60. Specifically, the gate wiring film 65 is electrically connected to the plurality of first trench resistor structures 51A between the first covering portion 61 and the second covering portion 62 of the resistor film 60, and is electrically connected to the plurality of second trench resistor structures 51B between the first covering portion 61 and the third covering portion 63 of the resistor film 60.

[0191] In this embodiment, the gate wiring film 65 includes a first lower wiring portion 66, a second lower wiring portion 67, and a third lower wiring portion 68. The first lower wiring portion 66 is routed to the pad region 10. Specifically, the first lower wiring portion 66 surrounds the resistor film 60 and the gate electrode film 64 in the pad region 10 from multiple directions (three directions in this embodiment).

[0192] The first lower wiring portion 66 includes a first lower line portion 69 and a plurality of second lower line portions 70A and 70B. The first lower line portion 69 is arranged on the side of the scribe line region 11 with respect to the resistor film 60 in the pad region 10. The first lower line portion 69 is arranged adjacent to the resistor film 60 on the first main surface 3 so as to face the gate electrode film 64 via the resistor film 60 when viewed from above. The first lower line portion 69 faces the boundary well region 40 (first boundary well region 40A) via the main surface insulating film 45 in the thickness direction.

[0193] The first lower line portion 69 is formed in a strip shape extending along the resistor film 60 in the second direction Y. The first lower line portion 69 has a length in the second direction Y that is greater than the length of the resistor film 60 and the length of the gate electrode film 64. The first lower line portion 69 has one end on one side in the second direction Y (on the first side surface 5A side) and the other end on the other side in the second direction Y (on the second side surface 5B side).

[0194] The plurality of second lower line portions 70A and 70B include a second lower line portion 70A on one side and a second lower line portion 70B on the other side. The second lower line portion 70A is disposed in a region on one side (on the first side 5A side) of the second direction Y relative to the resistor film 60 and the gate electrode film 64 in the pad region 10. The second lower line portion 70B is disposed in a region on the other side (on the second side 5B side) of the second direction Y relative to the resistor film 60 and the gate electrode film 64 in the pad region 10.

[0195] The second lower line portion 70A is formed in a strip shape extending in the first direction X, and has one end connected to one end of the first lower line portion 69, and the other end located on the peripheral side (third side 5C side) of the chip 2. The second lower line portion 70A is also connected to the first end 60A of the resistor film 60, and is formed with a gap from the gate electrode film 64. That is, the second lower line portion 70A constitutes a first connection portion with respect to the first end 60A. The second lower line portion 70A is opposed to the boundary well region 40 (first boundary well region 40A) via the main surface insulating film 45 in the thickness direction.

[0196] The second lower line portion 70B is formed in a strip shape extending in the first direction X, and has one end connected to the other end of the first lower line portion 69, and the other end located on the peripheral side (the third side surface 5C side) of the chip 2. The second lower line portion 70B on the other side is also connected to the second end 60B of the resistor film 60, and is formed with a gap from the gate electrode film 64.

[0197] That is, the second lower line portion 70B constitutes a second connection portion with respect to the first end portion 60A. The second lower line portion 70B on the other side is opposed to the second lower line portion 70A on one side via the gate electrode film 64. The second lower line portion 70B on the other side is opposed to the boundary well region 40 (first boundary well region 40A) via the main surface insulating film 45 in the thickness direction.

[0198] The second lower wiring portion 67 is led to the scribe line area 11. Specifically, the second lower wiring portion 67 is led out from the first lower wiring portion 66 to the scribe line area 11. More specifically, the second lower wiring portion 67 is led out from the inner portion (the central portion in this embodiment) of the first lower wiring portion 69 to the scribe line area 11, and is formed in a strip shape extending in the first direction X.

[0199] In this embodiment, the second lower wiring portion 67 crosses the center of the chip 2. The second lower wiring portion 67 extends in a strip shape in a region located on one side (the third side surface 5C side) and the other side (the fourth side surface 5D side) of the first direction X relative to a straight line crossing the center of the first main surface 3 in the second direction Y. The second lower wiring portion 67 has one end connected to the first lower line portion 69 (first lower wiring portion 66) on one side of the first direction X, and the other end on the other side of the first direction X.

[0200] The second lower wiring portion 67 is opposed to the boundary well region 40 (second boundary well region 40B) via the main surface insulating film 45 in the thickness direction. The second lower wiring portion 67 has a width greater than that of the scribe line region 11 in the second direction Y, and is led out from the scribe line region 11 to the plurality of active regions 6. The second lower wiring portion 67 covers the plurality of trench isolation structures 15 in the plurality of active regions 6.

[0201] The second lower wiring portion 67 covers the ends of the first trench structures 21 in the active regions 6. Thus, the second lower wiring portion 67 is electrically connected to the separated buried electrodes 18 and the first buried electrodes 24, and transmits gate potential to the separated buried electrodes 18 and the first buried electrodes 24.

[0202] In this embodiment, the second lower wiring portion 67 is formed integrally with the plurality of separated buried electrodes 18 and the plurality of first buried electrodes 24. That is, the second lower wiring portion 67 is formed by a portion of the plurality of separated buried electrodes 18 and a portion of the plurality of first buried electrodes 24 being led out in a film-like manner onto the first main surface 3 (main surface insulating film 45). Of course, the second lower wiring portion 67 may also be formed separately from the plurality of separated buried electrodes 18 and the plurality of first buried electrodes 24.

[0203] The third lower wiring portion 68 is led to the outer peripheral region 9. Specifically, the third lower wiring portion 68 is led out from the first lower wiring portion 66 to the outer peripheral region 9. More specifically, the third lower wiring portion 68 is led out from the other end portions of the plurality of second lower line portions 70A and 70B to one side (the first side surface 5A side) and the other side (the second side surface 5B side) of the outer peripheral region 9, and is formed in a belt shape extending along the outer peripheral region 9.

[0204] The third lower wiring portion 68 sandwiches the plurality of active regions 6 together with the second lower wiring portion 67. Specifically, the third lower wiring portion 68 extends along the periphery (first side surfaces 5A to 5D) of the chip 2 so as to surround the plurality of active regions 6 in a plan view, and is connected to the other end of the second lower wiring portion 67. Thus, the third lower wiring portion 68 surrounds the plurality of active regions 6 together with the second lower wiring portion 67.

[0205] The third lower wiring portion 68 faces the inner portion of the peripheral well region 41 via the main surface insulating film 45. Specifically, the third lower wiring portion 68 faces the inner portion of the peripheral well region 41 with a gap inward from the inner and outer edges of the peripheral well region 41 in a plan view.

[0206] Reference Figure 3 The third lower wiring portion 68 has at least one (in this embodiment, a plurality of) lead portions 68a extending from the peripheral region 9 to the adjacent active region 6 in the portion extending along the first side surface 5A. The plurality of lead portions 68a cover the first trench isolation structure 15A at intervals in the first direction X on the first active region 6A side, and cover the second trench isolation structure 15B at intervals in the first direction X on the second active region 6B side.

[0207] That is, the plurality of lead portions 68a cover the ends of the plurality of first trench structures 21. Thus, the third lower wiring portion 68 is electrically connected to the plurality of separated buried electrodes 18 and the plurality of first buried electrodes 24 in the first active region 6A, and transmits gate potential to the plurality of separated buried electrodes 18 and the plurality of first buried electrodes 24.

[0208] Of course, a single lead portion 68a extending in a stripe along the first trench isolation structure 15A may be formed on the first active region 6A side. Also, a single lead portion 68a extending in a stripe along the second trench isolation structure 15B may be formed on the second active region 6B side.

[0209] In this embodiment, the third lower wiring portion 68 is formed integrally with the plurality of separated buried electrodes 18 and the plurality of first buried electrodes 24. That is, the third lower wiring portion 68 is formed by a portion of the plurality of separated buried electrodes 18 and a portion of the plurality of first buried electrodes 24 being led out in a film-like manner onto the first main surface 3 (main surface insulating film 45). Of course, the third lower wiring portion 68 may also be formed separately from the plurality of separated buried electrodes 18 and the plurality of first buried electrodes 24.

[0210] Reference Figure 11 to Figure 15 The semiconductor device 1A includes a first slit 71 that defines a region between the resistor film 60 and the gate electrode film 64. The first slit 71 is formed in a strip shape extending in the second direction Y in a plan view and defines the first to third covering portions 61 to 63 of the resistor film 60.

[0211] The first slit 71 exposes the main surface insulating film 45. The first slit 71 is formed outside the plurality of trench resistor structures 51 in a plan view and faces the boundary well region 40 (first boundary well region 40A) in the thickness direction. That is, the first slit 71 does not face the trench resistor structure 51 in the thickness direction.

[0212] The first slit 71 has a first length in the second direction Y. The first slit 71 is formed to be narrower than the gate electrode film 64 in the first direction X. The first slit 71 is preferably formed to be narrower than the resistor film 60 in the first direction X. The first slit 71 is preferably formed to be narrower than the first trench group 52 in the first direction X. The first slit 71 is preferably formed to be wider than the trench resistor structure 51 in the first direction X.

[0213] The width of the first slit 71 may be 0.1 μm to 10 μm. The width of the first slit 71 may be 0.1 μm to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 2.5 μm, 2.5 μm to 5 μm, 5 μm to 7.5 μm, or 7.5 μm to 10 μm. The width of the first slit 71 is preferably 3 μm to 7 μm.

[0214] Reference Figure 11 to Figure 15 The semiconductor device 1A includes a second slit 72 that defines a region between the resistor film 60 and the gate wiring film 65. Specifically, the second slit 72 defines a region between the resistor film 60 and the first lower line portion 69. The second slit 72 faces the first slit 71 across the resistor film 60.

[0215] The second slit 72 is formed in a strip shape extending in the second direction Y in a plan view, and divides the first to third covering portions 61 to 63 of the resistor film 60. That is, the second slit 72 extends parallel to the first slit 71, and divides the resistor film 60 together with the first slit 71. The second slit 72 exposes the main surface insulating film 45.

[0216] The second slit 72 is formed outside the plurality of trench resistor structures 51 in a plan view, and is opposed to the boundary well region 40 (first boundary well region 40A) in the thickness direction. That is, the second slit 72 is not opposed to the trench resistor structure 51 in the thickness direction. The second slit 72 is opposed to the first slit 71 via the plurality of first trench resistor structures 51A and the plurality of second trench resistor structures 51B in a plan view.

[0217] The second slit 72 has a second length in the second direction Y. The second length may also be different from the first length of the first slit 71. From the perspective of properly connecting the resistor film 60 and the gate wiring film 65, the second length is preferably less than the first length. In this embodiment, the second length is less than the first length. Of course, the second length may also be substantially equal to the first length. In addition, the second length may also be greater than the first length.

[0218] The second slit 72 is formed to be narrower than the gate electrode film 64 in the first direction X. The second slit 72 is preferably formed to be narrower than the first lower line portion 69 in the first direction X. The second slit 72 is particularly preferably formed to be narrower than the resistor film 60 in the first direction X. The second slit 72 is preferably formed to be narrower than the first trench group 52 in the first direction X. The second slit 72 is preferably formed to be wider than the trench resistor structure 51.

[0219] The width of the second slit 72 may be 0.1 μm to 10 μm, 0.5 μm to 1 μm, 1 μm to 2.5 μm, 2.5 μm to 5 μm, 5 μm to 7.5 μm, or 7.5 μm to 10 μm.

[0220] The width of the second slit 72 is preferably 3 μm or more and 7 μm or less. The width of the second slit 72 may be greater than the width of the first slit 71. The width of the second slit 72 may be smaller than the width of the first slit 71. The width of the second slit 72 may be substantially equal to the width of the first slit 71.

[0221] Reference Figure 11 to Figure 15 The semiconductor device 1A includes a plurality of third slits 73 that define a region between the gate electrode film 64 and the gate wiring film 65. Specifically, the plurality of third slits 73 define regions between the gate electrode film 64 and the plurality of second lower line portions 70A and 70B.

[0222] The plurality of third slits 73 are formed in a strip shape extending in the first direction X in a plan view, and expose the main surface insulating film 45. The plurality of third slits 73 are connected to the first slit 71, and are opposed to each other in the second direction Y via the gate electrode film 64. That is, the plurality of third slits 73 and the first slit 71 divide the gate electrode film 64. In addition, the plurality of third slits 73 and the first slit 71 physically and electrically cut off the gate electrode film 64 from the gate wiring film 65.

[0223] The third slit 73 is formed to be narrower than the gate electrode film 64. The third slit 73 is preferably formed to be narrower than the second lower line portions 70A and 70B. The third slit 73 is particularly preferably formed to be narrower than the resistor film 60. The third slit 73 is preferably formed to be narrower than the first trench group 52 (second trench group 53). The third slit 73 is preferably formed to be wider than the trench resistor structure 51.

[0224] The width of the third slit 73 may be 0.1 μm to 10 μm. The width of the third slit 73 may be 0.1 μm to 0.5 μm, 0.5 μm to 1 μm, 1 μm to 2.5 μm, 2.5 μm to 5 μm, 5 μm to 7.5 μm, or 7.5 μm to 10 μm.

[0225] The width of the third slit 73 is preferably 3 μm or more and 7 μm or less. The width of the third slit 73 may be greater than the width of the first slit 71. The width of the third slit 73 may be smaller than the width of the first slit 71. The width of the third slit 73 may be substantially equal to the width of the first slit 71.

[0226] The semiconductor device 1A includes an interlayer insulating film 74, which covers the main surface insulating film 45. The interlayer insulating film 74 is thicker than the main surface insulating film 45. The interlayer insulating film 74 may have a single-layer structure composed of a single insulating film, or a stacked structure including a plurality of insulating films. The interlayer insulating film 74 may also include at least one of a silicon oxide film, a silicon nitride film, and an aluminum oxide film.

[0227] The interlayer insulating film 74 may also have a stacked structure including a plurality of silicon oxide films. In this case, the interlayer insulating film 74 may also include at least one of an NSG (Non-doped Silicate Glass) film, a PSG (Phosphor Silicate Glass) film, and a BPSG (Boron Phosphor Silicate Glass) film, which are examples of silicon oxide films. The stacking order of the NSG film, the PSG film, and the BPSG film is arbitrary.

[0228] The interlayer insulating film 74 covers the main surface insulating film 45 in the active region 6 , the boundary region 8 , and the peripheral region 9 . The interlayer insulating film 74 covers the plurality of trench isolation structures 15 , the plurality of first trench structures 21 , and the plurality of second trench structures 25 in the active region 6 .

[0229] The interlayer insulating film 74 covers the plurality of trench resistor structures 51 (resistor embedded electrodes 56), the resistor film 60, the gate electrode film 64, and the gate wiring film 65 in the pad region 10. The interlayer insulating film 74 covers the boundary well region 40 (first boundary well region 40A) via the main surface insulating film 45 in the pad region 10. The interlayer insulating film 74 selectively covers the peripheral well region 41, the field region 42, and the channel stop region 43 via the main surface insulating film 45 in the peripheral region 9.

[0230] The interlayer insulating film 74 enters the first slit 71 from above the resistor film 60 and the gate electrode film 64, and has a portion covering the main surface insulating film 45 in the first slit 71. That is, the interlayer insulating film 74 is opposite to the boundary well region 40 (first boundary well region 40A) in the thickness direction of the first slit 71 via the main surface insulating film 45. The interlayer insulating film 74 electrically insulates the resistor film 60 and the gate electrode film 64 in the first slit 71.

[0231] The interlayer insulating film 74 enters the second slit 72 from above the resistor film 60 and the gate wiring film 65 (the first lower wiring portion 69), and has a portion covering the main surface insulating film 45 in the second slit 72. That is, the interlayer insulating film 74 is opposed to the boundary well region 40 (the first boundary well region 40A) in the thickness direction of the second slit 72 via the main surface insulating film 45. The interlayer insulating film 74 electrically insulates the resistor film 60 and the gate wiring film 65 (the first lower wiring portion 69) in the second slit 72.

[0232] The interlayer insulating film 74 enters the plurality of third slits 73 from above the gate electrode film 64 and the gate wiring film 65 (the second lower line portions 70A and 70B), and has a portion covering the main surface insulating film 45 in the plurality of third slits 73. That is, the interlayer insulating film 74 is opposed to the boundary well region 40 (the first boundary well region 40A) in the plurality of third slits 73 via the main surface insulating film 45 in the thickness direction.

[0233] The interlayer insulating film 74 electrically insulates the gate electrode film 64 and the gate wiring film 65 in the plurality of third slits 73. The interlayer insulating film 74 is formed at intervals inward from the periphery of the first main surface 3, and defines a removal portion 46 that exposes the periphery of the first main surface 3 together with the main surface insulating film 45.

[0234] The interlayer insulating film 74 has an insulating main surface 75 extending along the first main surface 3 (main surface insulating film 45). The insulating main surface 75 has a first groove portion 76, a second groove portion 77, and a plurality of third groove portions 78 in the pad region 10 (see Figure 16 to Figure 22 ). The first groove portion 76 is formed in a portion covering the first slit 71. The first groove portion 76 is recessed toward the first slit 71 and is formed in a strip shape extending in the second direction Y along the first slit 71 in a plan view.

[0235] The second groove portion 77 is formed in a portion covering the second slit 72. The second groove portion 77 is recessed toward the second slit 72, and is formed in a strip shape extending along the second slit 72 in the second direction Y in a plan view. The plurality of third groove portions 78 are respectively formed in portions covering the plurality of third slits 73. The plurality of third groove portions 78 are respectively recessed toward the corresponding third slit 73, and are respectively formed in a strip shape extending along the corresponding third slit 73 in the first direction X in a plan view.

[0236] Reference Figure 11 to Figure 22 The semiconductor device 1A includes at least one (in this embodiment, multiple) first resistor connection electrode 81, which is buried in the interlayer insulating film 74 in a manner electrically connected to the resistor film 60. The first resistor connection electrode 81 can also be called a "first resistor hole electrode". The first resistor connection electrode 81 can also include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film. In this embodiment, the first resistor connection electrode 81 has a stacked structure including a Ti film and a W film.

[0237] In this embodiment, the plurality of first resistor connection electrodes 81 are connected to the first covering portion 61 of the resistor film 60. That is, the plurality of first resistor connection electrodes 81 are connected to the portion of the resistor film 60 covering the region outside the plurality of trench resistor structures 51. Specifically, the plurality of first resistor connection electrodes 81 are connected to the portion of the resistor film 60 covering the space region 57 between the first trench group 52 (the plurality of first trench resistor structures 51A) and the second trench group 53 (the plurality of second trench resistor structures 51B).

[0238] The plurality of first resistor connection electrodes 81 are formed in a region spaced apart from the plurality of trench resistor structures 51 along the second direction Y when viewed from above, and are not opposed to the plurality of trench resistor structures 51 in the first direction X. In this embodiment, the plurality of first resistor connection electrodes 81 are respectively formed in a strip shape extending in the first direction X when viewed from above, and are arranged spaced apart in the second direction Y. That is, the plurality of first resistor connection electrodes 81 are arranged in a strip shape extending in the first direction X when viewed from above.

[0239] The plurality of first resistor connection electrodes 81 extend in a direction that intersects (orthogonally in this embodiment) the extension direction of the resistor film 60 (the plurality of groove resistor structures 51). That is, the plurality of first resistor connection electrodes 81 intersect (orthogonally) the current direction of the resistor film 60. Thus, the current can be appropriately extended from the plurality of first resistor connection electrodes 81 relative to the resistor film 60. That is, the current narrowing caused by the layout of the plurality of first resistor connection electrodes 81 is suppressed, and the change (increase) of the undesired resistance value caused by the current narrowing is suppressed.

[0240] The plurality of first resistor connection electrodes 81 are opposed to only the flat portion of the first main surface 3 via the resistor film 60, and are not opposed to the trench resistor structure 51 via the resistor film 60. The plurality of first resistor connection electrodes 81 are opposed to the boundary well region 40 (first boundary well region 40A) via the resistor film 60 and the main surface insulating film 45. The plurality of first resistor connection electrodes 81 are formed in a region sandwiched by the first slit 71 and the second slit 72 with a gap therebetween when viewed from above.

[0241] That is, the plurality of first resistor connection electrodes 81 are formed to have a width narrower than the resistor film 60 in the first direction X. The plurality of first resistor connection electrodes 81 are opposed to one or more first trench resistor structures 51A on one side (first side surface 5A side) in the second direction Y when viewed from above, and are opposed to one or more second trench resistor structures 51B on the other side (second side surface 5B side) in the second direction Y.

[0242] The plurality of first resistor connection electrodes 81 only need to be opposed to at least two of the plurality of first trench resistor structures 51A in the second direction Y, and need not be opposed to all of the first trench resistor structures 51A. In this embodiment, the plurality of first resistor connection electrodes 81 are opposed to a portion of the plurality of first trench resistor structures 51A in the second direction Y. Of course, the plurality of first resistor connection electrodes 81 may also be opposed to all of the first trench resistor structures 51A in the second direction Y.

[0243] Similarly, the plurality of first resistor connection electrodes 81 only need to be opposed to at least two of the plurality of second trench resistor structures 51B in the second direction Y, and need not be opposed to all of the first trench resistor structures 51A. In this embodiment, the plurality of first resistor connection electrodes 81 are opposed to a portion of the plurality of second trench resistor structures 51B in the second direction Y. Of course, the plurality of first resistor connection electrodes 81 may also be opposed to all of the second trench resistor structures 51B in the second direction Y.

[0244] The plurality of first resistor connection electrodes 81 have a first connection area S1 relative to the resistor film 60. The first connection area S1 is defined by the total plane area of ​​the plurality of first resistor connection electrodes 81. In the case where a single first resistor connection electrode 81 is formed, the first connection area S1 is defined by the plane area of ​​the single first resistor connection electrode 81. The first connection area S1 is adjusted according to the first current I1 flowing through the first resistor connection electrode 81 (refer to Fig.12 ).

[0245] Reference Figure 11 to Figure 22The semiconductor device 1A includes at least one (in this embodiment, multiple) second resistor connection electrode 82, which is buried in the interlayer insulating film 74 in a different position from the first resistor connection electrode 81 so as to be electrically connected to the resistor film 60. The second resistor connection electrode 82 may also be referred to as a "second resistor hole electrode".

[0246] The second resistive connecting electrode 82 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film. In this embodiment, the second resistive connecting electrode 82 has a stacked structure including a Ti film and a W film.

[0247] In this embodiment, the second resistor connection electrodes 82 are connected to the second covering portion 62 of the resistor film 60. That is, the second resistor connection electrodes 82 are connected to the portion of the resistor film 60 covering the first trench group 52 (the first trench resistor structures 51A).

[0248] The plurality of second resistor connection electrodes 82 form a first gate resistor R1 between the plurality of first resistor connection electrodes 81. The first gate resistor R1 is formed by the portion of the resistor film 60 and the plurality of first trench resistor structures 51A located between the plurality of first resistor connection electrodes 81 and the plurality of second resistor connection electrodes 82. The resistance value of the first gate resistor R1 is adjusted according to the distance between the plurality of first resistor connection electrodes 81 and the plurality of second resistor connection electrodes 82.

[0249] The plurality of second resistor connection electrodes 82 are formed in a region opposite to the plurality of first trench resistor structures 51A in the first direction X when viewed from above. In this embodiment, the plurality of second resistor connection electrodes 82 extend in a direction different from the first resistor connection electrodes 81 when viewed from above. Specifically, the plurality of second resistor connection electrodes 82 are respectively formed in a strip shape extending in the second direction Y when viewed from above, and are arranged at intervals in the first direction X. That is, the plurality of second resistor connection electrodes 82 are arranged in a strip shape extending in the second direction Y when viewed from above.

[0250] The second resistor connecting electrodes 82 are respectively arranged between the plurality of first trench resistor structures 51A adjacent to each other with a gap therebetween in a plan view.

[0251] In addition, in this embodiment, the plurality of second resistor connection electrodes 82 are opposed to only the flat portion of the first main surface 3 via the resistor film 60, and are not opposed to the trench resistor structure 51 via the resistor film 60. The plurality of second resistor connection electrodes 82 are opposed to the boundary well region 40 (first boundary well region 40A) via the resistor film 60 and the main surface insulating film 45.

[0252] The plurality of second resistor connection electrodes 82 may be arranged in a part of the region between the plurality of first trench resistor structures 51A, and need not be arranged in the entire region between the plurality of first trench resistor structures 51A. The plurality of second resistor connection electrodes 82 may be arranged in at least one region located on the active region 6 side in the region between the plurality of first trench resistor structures 51A, and need not be arranged in at least one region located on the gate electrode film 64 side.

[0253] At least one of the plurality of second resistance connection electrodes 82 is preferably opposed to the plurality of first resistance connection electrodes 81 in the second direction Y when viewed from above. In this case, at least one of the plurality of second resistance connection electrodes 82 located on the gate electrode film 64 side is preferably opposed to the plurality of first resistance connection electrodes 81 in the second direction Y.

[0254] At least one of the plurality of second resistive connecting electrodes 82 located on the active region 6 side may not be opposite to the plurality of first resistive connecting electrodes 81 in the second direction Y. Of course, all the second resistive connecting electrodes 82 may be arranged to be opposite to the plurality of first resistive connecting electrodes 81 in the second direction Y.

[0255] The second resistor connection electrodes 82 have a length smaller than that of the first trench resistor structures 51A in the second direction Y. The second resistor connection electrodes 82 are preferably arranged in a region on the other end side of the first trench resistor structures 51A relative to the middle portion in the longitudinal direction of the first trench resistor structures 51A.

[0256] The length of the second resistor connection electrodes 82 is preferably 1 / 100 to 1 / 2 of the length of the first trench resistor structures 51A. The length of the second resistor connection electrodes 82 may be 1 / 20 to 1 / 4 of the length of the first trench resistor structures 51A.

[0257] The plurality of second resistance connection electrodes 82 have a second connection area S2 with respect to the resistance film 60. The second connection area S2 is defined by the total plane area of ​​the plurality of second resistance connection electrodes 82. When a single second resistance connection electrode 82 is formed, the second connection area S2 is defined by the plane area of ​​the single second resistance connection electrode 82.

[0258] The second connection area S2 may be substantially equal to the first connection area S1. The second connection area S2 may be larger than the first connection area S1. The second connection area S2 may be smaller than the first connection area S1. The second connection area S2 is adjusted according to the current ratio I2 / I1 (shunt ratio) of the second current I2 flowing through the second resistance connection electrode 82 to the first current I1 flowing through the first resistance connection electrode 81 (refer to Fig.12).

[0259] In this case, the value of the area ratio S2 / S1 of the second connection area S2 relative to the first connection area S1 is preferably set to be greater than the value of the current ratio I2 / I1. For example, when the current ratio I2 / I1 is 1, the area ratio S2 / S1 is preferably set to be greater than 1. For example, when the current ratio I2 / I1 is 1 / 2, the area ratio S2 / S1 is preferably set to be greater than 1 / 2.

[0260] When the current ratio I2 / I1 is 1 / 4, the area ratio S2 / S1 is preferably set to 1 / 4 or more. In this embodiment, the current ratio I2 / I1 is approximately 1 / 2, and the second connection area S2 is 1 / 2 times or more of the first connection area S1. The second connection area S2 is preferably less than 2 times the first connection area S1.

[0261] Reference Figure 11 to Figure 22 The semiconductor device 1A includes at least one (in this embodiment, multiple) third resistor connection electrode 83, which is buried in the interlayer insulating film 74 in a position different from the first resistor connection electrode 81 and the second resistor connection electrode 82 in a manner electrically connected to the resistor film 60. The third resistor connection electrode 83 can also be called a "third resistor hole electrode".

[0262] The third resistive connecting electrode 83 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film. In this embodiment, the third resistive connecting electrode 83 has a stacked structure including a Ti film and a W film.

[0263] In this embodiment, the third resistor connection electrodes 83 are connected to the third covering portion 63 of the resistor film 60. That is, the third resistor connection electrodes 83 are connected to the portion of the resistor film 60 covering the second trench group 53 (second trench resistor structures 51B).

[0264] The third resistor connecting electrodes 83 form a second gate resistor R2 between the first resistor connecting electrodes 81 and the third resistor connecting electrodes 83. The second gate resistor R2 is formed by the resistor film 60 and a portion of the second trench resistor structure 51B located between the first resistor connecting electrodes 81 and the third resistor connecting electrodes 83.

[0265] The resistance value of the second gate resistor R2 is adjusted according to the distance between the plurality of first resistor connection electrodes 81 and the plurality of third resistor connection electrodes 83. In this manner, the resistance value of the second gate resistor R2 is substantially equal to the resistance value of the first gate resistor R1. In addition, the distance between the plurality of first resistor connection electrodes 81 and the plurality of third resistor connection electrodes 83 is substantially equal to the distance between the plurality of first resistor connection electrodes 81 and the plurality of second resistor connection electrodes 82.

[0266] Of course, the resistance value of the second gate resistor R2 may be different from the resistance value of the first gate resistor R1. In this case, the distance between the first resistor connecting electrodes 81 and the third resistor connecting electrodes 83 may be different from the distance between the first resistor connecting electrodes 81 and the second resistor connecting electrodes 82.

[0267] For example, the resistance value of the second gate resistor R2 may be smaller than the resistance value of the first gate resistor R1. In this case, the distance between the first resistor connecting electrodes 81 and the third resistor connecting electrodes 83 may be smaller than the distance between the first resistor connecting electrodes 81 and the second resistor connecting electrodes 82.

[0268] For example, the resistance value of the second gate resistor R2 may be greater than the resistance value of the first gate resistor R1. In this case, the distance between the first resistor connecting electrodes 81 and the third resistor connecting electrodes 83 may be set greater than the distance between the first resistor connecting electrodes 81 and the second resistor connecting electrodes 82.

[0269] The plurality of third resistor connection electrodes 83 are formed in a region opposite to the plurality of second trench resistor structures 51B in the first direction X when viewed from above. In this embodiment, the plurality of third resistor connection electrodes 83 extend in a direction different from the first resistor connection electrodes 81 when viewed from above. Specifically, the plurality of third resistor connection electrodes 83 are respectively formed in a strip shape extending in the second direction Y when viewed from above, and are arranged at intervals in the first direction X. That is, the plurality of third resistor connection electrodes 83 are arranged in a strip shape extending in the second direction Y when viewed from above.

[0270] The third resistor connection electrodes 83 are respectively arranged between the second trench resistor structures 51B adjacent to each other with a gap therebetween in a plan view.

[0271] In addition, in this embodiment, the plurality of third resistor connection electrodes 83 are opposed to only the flat portion of the first main surface 3 via the resistor film 60, and are not opposed to the trench resistor structure 51 via the resistor film 60. The plurality of third resistor connection electrodes 83 are opposed to the boundary well region 40 (first boundary well region 40A) via the resistor film 60 and the main surface insulating film 45.

[0272] The plurality of third resistor connection electrodes 83 may be arranged in a part of the region between the plurality of second trench resistor structures 51B, and need not be arranged in the entire region between the plurality of second trench resistor structures 51B. The plurality of third resistor connection electrodes 83 may be arranged in at least one region located on the active region 6 side in the region between the plurality of second trench resistor structures 51B, and need not be arranged in at least one region located on the gate electrode film 64 side.

[0273] At least one of the plurality of third resistance connection electrodes 83 is preferably opposed to the plurality of first resistance connection electrodes 81 in the second direction Y when viewed from above. In this case, at least one of the plurality of third resistance connection electrodes 83 located on the gate electrode film 64 side is preferably opposed to the plurality of first resistance connection electrodes 81 in the second direction Y.

[0274] At least one of the plurality of third resistive connecting electrodes 83 located on the active region 6 side may not be opposite to the plurality of first resistive connecting electrodes 81 in the second direction Y. Of course, all the third resistive connecting electrodes 83 may be arranged to be opposite to the plurality of first resistive connecting electrodes 81 in the second direction Y.

[0275] At least one of the plurality of third resistor connection electrodes 83 is preferably opposed to the plurality of second resistor connection electrodes 82 in the second direction Y when viewed from above. In this embodiment, the number of the plurality of third resistor connection electrodes 83 is set to be equal to the number of the plurality of second resistor connection electrodes 82, and all the third resistor connection electrodes 83 are opposed to all the second resistor connection electrodes 82 in a one-to-one correspondence in the second direction Y. Of course, the number of the third resistor connection electrodes 83 can be more or less than the number of the second resistor connection electrodes 82.

[0276] The third resistor connection electrodes 83 have a length smaller than that of the second trench resistor structures 51B in the second direction Y. The third resistor connection electrodes 83 are preferably arranged in a region on the other end side of the second trench resistor structures 51B relative to the middle portion in the longitudinal direction of the second trench resistor structures 51B.

[0277] The length of the plurality of third resistor connection electrodes 83 is preferably greater than 1 / 100 and less than 1 / 2 of the length of the plurality of second groove resistor structures 51B. The length of the plurality of third resistor connection electrodes 83 may also be greater than 1 / 20 and less than 1 / 4 of the length of the plurality of second groove resistor structures 51B. The length of the third resistor connection electrode 83 may also be substantially equal to the length of the second resistor connection electrode 82. The length of the third resistor connection electrode 83 may also be greater than the length of the second resistor connection electrode 82. The length of the third resistor connection electrode 83 may also be less than the length of the second resistor connection electrode 82.

[0278] The plurality of third resistor connection electrodes 83 have a third connection area S3 relative to the resistor film 60. The third connection area S3 is defined by the total plane area of ​​the plurality of third resistor connection electrodes 83. In the case where a single third resistor connection electrode 83 is formed, the third connection area S3 is defined by the plane area of ​​the single third resistor connection electrode 83. The third connection area S3 is adjusted according to the current ratio I3 / I1 (shunt ratio) of the third current I3 flowing through the third resistor connection electrode 83 to the first current I1 flowing through the first resistor connection electrode 81 (refer to Fig.12 ).

[0279] In this case, the value of the current ratio I3 / I1 of the third connection area S3 relative to the first connection area S1 is preferably set to be greater than the value of the current ratio I3 / I1. For example, when the current ratio I3 / I1 is 1, the current ratio I3 / I1 is preferably set to be greater than 1. For example, when the current ratio I3 / I1 is 1 / 2, the current ratio I3 / I1 is preferably set to be greater than 1 / 2.

[0280] When the current ratio I3 / I1 is 1 / 4, the current ratio I3 / I1 is preferably set to be greater than 1 / 4. In this manner, the third current I3 is substantially equal to the second current I2, and the current ratio I3 / I1 is substantially 1 / 2, so the third connection area S3 is set to be greater than 1 / 2 times the first connection area S1. The third connection area S3 is preferably set to be less than 2 times the first connection area S1. Of course, the third current I3 may be greater than or less than the second current I2.

[0281] Reference Figures 3 to 10 The semiconductor device 1A includes a plurality of gate connection electrodes 84, which are buried in the interlayer insulating film 74 in the inactive region 7 in a manner electrically connected to the gate wiring film 65. The gate connection electrode 84 may also be referred to as a "gate hole electrode". The plurality of gate connection electrodes 84 may also include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film. In this embodiment, the plurality of gate connection electrodes 84 have a stacked structure including a Ti film and a W film.

[0282] The plurality of gate connection electrodes 84 include at least one (in this embodiment, a plurality of) first gate connection electrodes 84A and at least one (in this embodiment, a plurality of) second gate connection electrodes 84B. The plurality of first gate connection electrodes 84A are embedded in the portion of the interlayer insulating film 74 covering the second lower wiring portion 67 in the dicing street region 11 and are electrically connected to the second lower wiring portion 67 (see Figure 7 to Figure 9 ). In this embodiment, a plurality of first gate connection electrodes 84A are formed at intervals in the second direction Y and are formed in a strip shape extending in the first direction X.

[0283] The plurality of second gate connection electrodes 84B are embedded in the portion of the interlayer insulating film 74 covering the third lower wiring portion 68 in the peripheral region 9 and are electrically connected to the third lower wiring portion 68 (see Figure 3 to Figure 6 ). In this embodiment, the plurality of second gate connection electrodes 84B are formed at intervals from the inner edge side to the outer edge side of the third lower wiring portion 68 and are formed in a belt shape extending along the third lower wiring portion 68 .

[0284] Reference Figure 3 as well as Figure 4 The semiconductor device 1A includes a plurality of first emitter connection electrodes 85 which penetrate the main surface insulating film 45 and are buried in the interlayer insulating film 74 in the active region 6 in a manner electrically connected to the plurality of emitter regions 29. The first emitter connection electrodes 85 may also be referred to as "first emitter hole electrodes".

[0285] The plurality of first emitter connection electrodes 85 may also include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film. In this embodiment, the plurality of first emitter connection electrodes 85 have a stacked structure including a Ti film and a W film.

[0286] The plurality of first emitter connection electrodes 85 are respectively embedded in the plurality of contact holes 30, and are respectively formed into a strip shape extending in the second direction Y along the plurality of first trench structures 21 in a plan view. That is, in this embodiment, the plurality of first emitter connection electrodes 85 extend in the same direction as the extending direction of the plurality of second resistance connection electrodes 82 and the extending direction of the plurality of third resistance connection electrodes 83. The plurality of first emitter connection electrodes 85 are respectively electrically connected to the emitter region 29 and the contact region 31 in the corresponding contact holes 30.

[0287] Reference Figure 3 as well as Figure 5The semiconductor device 1A includes a plurality of second emitter connection electrodes 86 which penetrate the main surface insulating film 45 and are buried in the interlayer insulating film 74 in the active region 6 in a manner electrically connected to the plurality of emitter electrode films 47. The second emitter connection electrodes 86 may also be referred to as "second emitter hole electrodes".

[0288] The plurality of second emitter connection electrodes 86 may also include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film. In this embodiment, the plurality of second emitter connection electrodes 86 have a stacked structure including a Ti film and a W film. The plurality of second emitter connection electrodes 86 are electrically connected to the second embedded electrode 28 via the plurality of emitter electrode films 47.

[0289] Reference Figure 3 to Figure 6 The semiconductor device 1A includes at least one (in this embodiment, multiple) first well connection electrode 87, which penetrates the main surface insulating film 45 and is buried in the interlayer insulating film 74 in a manner electrically connected to the inner edge of the peripheral well region 41. The first well connection electrode 87 can also be called a "first well hole electrode".

[0290] The plurality of first well connection electrodes 87 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film. In this embodiment, the plurality of first well connection electrodes 87 have a stacked structure including a Ti film and a W film.

[0291] In this embodiment, a plurality of first well connection electrodes 87 are arranged at intervals from the inner edge side to the outer edge side of the peripheral well region 41. The plurality of first well connection electrodes 87 are arranged on the inner edge side of the peripheral well region 41 relative to the middle portion in the width direction of the peripheral well region 41, and are electrically connected to the inner edge side region of the peripheral well region 41.

[0292] Specifically, the plurality of first well connection electrodes 87 are arranged in a region between the inner edge of the peripheral well region 41 and the third lower wiring portion 68 of the gate wiring film 65. The plurality of first well connection electrodes 87 extend along the inner edge of the peripheral well region 41 in a strip shape.

[0293] The plurality of first well connection electrodes 87 each have a plurality of segment portions 87a in a portion extending along the first direction X (see Figure 3 ). The plurality of segment portions 87a are spaced apart from the plurality of lead portions 68a of the gate wiring film 65 (third lower wiring portion 68) and are arranged in the region between the plurality of lead portions 68a. When a single lead portion 68a extending in a strip shape along the trench isolation structure 15 is formed, the plurality of segment portions 87a are omitted.

[0294] Reference Figure 3 to Figure 6 The semiconductor device 1A includes at least one (or more in this embodiment) second well connection electrode 88, which penetrates the main surface insulating film 45 and is buried in the interlayer insulating film 74 in a manner electrically connected to the outer edge of the peripheral well region 41. The second well connection electrode 88 may also be referred to as a "second well hole electrode".

[0295] The plurality of second well connection electrodes 88 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film. In this embodiment, the plurality of second well connection electrodes 88 have a stacked structure including a Ti film and a W film.

[0296] The plurality of second well connection electrodes 88 are arranged at intervals from the inner edge side to the outer edge side of the peripheral well region 41. The plurality of second well connection electrodes 88 are arranged on the outer edge side of the peripheral well region 41 relative to the middle portion in the width direction of the peripheral well region 41, and are electrically connected to the region on the outer edge side of the peripheral well region 41. Specifically, the plurality of second well connection electrodes 88 are arranged in the region between the outer edge of the peripheral well region 41 and the third lower wiring portion 68 of the gate wiring film 65. The plurality of second well connection electrodes 88 extend in a strip shape along the outer edge of the peripheral well region 41.

[0297] Reference Fig.10 The semiconductor device 1A includes a plurality of field connection electrodes 89, which penetrate the main surface insulating film 45 and are buried in the interlayer insulating film 74 in a manner electrically connected to the corresponding field regions 42. In this manner, a plurality of field connection electrodes 89 are connected to one field region 42. Of course, a single field connection electrode 89 may also be connected to one field region 42. The field connection electrode 89 may also be referred to as a "field hole electrode".

[0298] The plurality of field connection electrodes 89 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film. In this embodiment, the plurality of field connection electrodes 89 have a stacked structure including a Ti film and a W film.

[0299] The plurality of field connection electrodes 89 are formed in strip shapes extending along the corresponding field regions 42. In this embodiment, the plurality of field connection electrodes 89 are formed in ring shapes (quadrilateral ring shapes) extending along the corresponding field regions 42. In this embodiment, the plurality of field connection electrodes 89 are formed in an electrically floating state.

[0300] Reference Figure 1 as well as Figure 11 to Figure 22The semiconductor device 1A includes a gate terminal electrode 90, which is arranged on the first main surface 3 in a manner electrically connected to the gate resistance structure 50 in the pad region 10 (inactive region 7). Specifically, the gate terminal electrode 90 is arranged on the interlayer insulating film 74. The gate terminal electrode 90 may also be referred to as a "gate pad" or a "gate pad electrode".

[0301] The gate terminal electrode 90 is preferably made of a conductive material different from that of the resistor film 60. The gate terminal electrode 90 is preferably made of a conductive material different from that of the gate electrode film 64. The gate terminal electrode 90 has a lower resistance value than the trench resistor structure 51 and the resistor film 60, and is electrically connected to the trench resistor structure 51 via the resistor film 60. The gate terminal electrode 90 has a lower resistance value than that of the gate electrode film 64.

[0302] In this embodiment, the gate terminal electrode 90 is composed of a metal film. The gate terminal electrode 90 may also be referred to as a "gate metal terminal". The gate terminal electrode 90 may also include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film.

[0303] The gate terminal electrode 90 may also include at least one of a pure Cu film (Cu film with a purity of 99% or more), a pure Al film (Al film with a purity of 99% or more), an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this embodiment, the gate terminal electrode 90 has a stacked structure including a Ti film and an Al alloy film (in this embodiment, an AlCu alloy film) stacked in sequence from the chip 2 side.

[0304] The gate terminal electrode 90 preferably has a thickness greater than the thickness of the resistance film 60 (the thickness of the gate electrode film 64). The thickness of the gate terminal electrode 90 may be greater than or equal to 1 μm and less than or equal to 10 μm.

[0305] The gate terminal electrode 90 preferably has a planar area of ​​1% or more and 30% or less of the planar area of ​​the first main surface 3. The planar area of ​​the gate terminal electrode 90 is particularly preferably 25% or less of the planar area of ​​the first main surface 3. The planar area of ​​the gate terminal electrode 90 may be 10% or less of the planar area of ​​the first main surface 3.

[0306] The gate terminal electrode 90 is arranged on the interlayer insulating film 74 in the pad region 10 in a manner covering the resistor film 60 and the gate electrode film 64. The gate terminal electrode 90 covers the plurality of first resistor connection electrodes 81 in the portion covering the resistor film 60, and is electrically connected to the plurality of first resistor connection electrodes 81. That is, the gate terminal electrode 90 is electrically connected to the resistor film 60 (first covering portion 61) via the plurality of first resistor connection electrodes 81.

[0307] Reference Figure 11 to Figure 22 (in particular Figure 11 to Figure 13 ), the gate terminal electrode 90 includes a first electrode portion 91 and a second electrode portion 92. The first electrode portion 91 has a relatively wide electrode width in the second direction Y. The first electrode portion 91 is a portion forming the terminal body of the gate terminal electrode 90, and is located in a region outside the first resistor connection electrode 81 when viewed from above. The first electrode portion 91 may also be referred to as a "terminal body portion".

[0308] For example, a bonding wire is connected to the first electrode portion 91. Therefore, the first electrode portion 91 is formed to be wider than the bonding portion of the bonding wire. The first electrode portion 91 is formed in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the chip 2 (the periphery of the pad region 10) when viewed from above. The first electrode portion 91 is arranged in a region facing the gate electrode film 64 via the interlayer insulating film 74.

[0309] The first electrode portion 91 preferably covers 50% or more of the gate electrode film 64 in a plan view. The first electrode portion 91 particularly preferably covers 90% or more of the gate electrode film 64 in a plan view. In this embodiment, the first electrode portion 91 has an electrode width wider than the gate electrode film 64 and covers the entire gate electrode film 64.

[0310] The flatness of the first electrode portion 91 is improved by the gate electrode film 64. The first electrode portion 91 may be electrically insulated from the gate electrode film 64 by the interlayer insulating film 74. The first electrode portion 91 may be electrically connected to the gate electrode film 64 via one or more gate connection electrodes 84 embedded in the interlayer insulating film 74.

[0311] The first electrode portion 91 covers the first slit 71 via the interlayer insulating film 74, and fills the first groove portion 76 of the interlayer insulating film 74 (insulating main surface 75). When the gate terminal electrode 90 (first electrode portion 91) is formed so that the first groove portion 76 is partially exposed, electrode residues generated during the formation process of the gate terminal electrode 90 may remain in the first groove portion 76.

[0312] If electrode residues are present, the gate terminal electrode 90 (first electrode portion 91 ) may be electrically connected to other electrodes via the electrode residues. Therefore, the gate terminal electrode 90 (first electrode portion 91 ) preferably covers the entire region of the first slit 71 via the interlayer insulating film 74 .

[0313] That is, the gate terminal electrode 90 (first electrode portion 91) preferably fills the entire area of ​​the first recessed portion 76 of the interlayer insulating film 74 (insulating main surface 75). According to this structure, a layout is provided that avoids the problem of electrode residue in the first recessed portion 76. The present disclosure does not exclude a method including the gate terminal electrode 90 (first electrode portion 91) that partially exposes the first recessed portion 76.

[0314] The first electrode portion 91 is drawn from above the gate electrode film 64 across the first slit 71 to above the resistor film 60 in a plan view. In this embodiment, the first electrode portion 91 covers the edge of the resistor film 60 via the interlayer insulating film 74. Specifically, the first electrode portion 91 covers the edge of the resistor film 60 with a gap toward the gate electrode film 64 relative to a straight line that crosses the center of the resistor film 60 in the second direction Y.

[0315] The first electrode portion 91 may also cover one or more trench resistor structures 51 through the resistor film 60 in the portion covering the resistor film 60. The first electrode portion 91 may also cover one or more first trench resistor structures 51A through the resistor film 60. The first electrode portion 91 may also cover one or more second trench resistor structures 51B through the resistor film 60. In this embodiment, the first electrode portion 91 covers one first trench resistor structure 51A and one second trench resistor structure 51B through the resistor film 60.

[0316] The first electrode portion 91 covers the plurality of third slits 73 via the interlayer insulating film 74, and fills the plurality of third recessed portions 78 of the interlayer insulating film 74 (insulating main surface 75). In the case where the gate terminal electrode 90 (first electrode portion 91) is formed so that the plurality of third recessed portions 78 are partially exposed, electrode residues generated during the formation step of the gate terminal electrode 90 may remain in the plurality of third recessed portions 78.

[0317] If electrode residues are present, the gate terminal electrode 90 (first electrode portion 91 ) may be electrically connected to other electrodes via the electrode residues. Therefore, the gate terminal electrode 90 (first electrode portion 91 ) preferably covers the entire region of the plurality of third recessed grooves 78 via the interlayer insulating film 74 .

[0318] That is, the gate terminal electrode 90 (first electrode portion 91) preferably covers the entire area of ​​the third recessed portion 78 of the interlayer insulating film 74 (insulating main surface 75). According to this structure, a layout is provided that avoids the problem of electrode residues in the plurality of third recessed portions 78. The present disclosure does not exclude a method including the gate terminal electrode 90 (first electrode portion 91) that partially exposes the plurality of third recessed portions 78.

[0319] The first electrode portion 91 is drawn from above the gate electrode film 64 to above the second lower line portions 70A and 70B across the third slits 73 in a plan view. In this embodiment, the first electrode portion 91 covers the edges of the second lower line portions 70A and 70B via the interlayer insulating film 74 .

[0320] The second electrode portion 92 has an electrode width smaller than that of the first electrode portion 91 in the second direction Y, and is composed of a lead portion extending from the first electrode portion 91 toward the plurality of first resistor connection electrodes 81 in the second direction Y. The second electrode portion 92 may also be referred to as a "terminal lead portion". For example, a bonding wire is not connected to the second electrode portion 92. Therefore, the second electrode portion 92 is formed to be narrower in width than the bonding portion of the bonding wire.

[0321] The protruding direction of the second electrode portion 92 is the same as the extending direction of the plurality of first resistance connecting electrodes 81. In this embodiment, the second electrode portion 92 is drawn out from the center of the first electrode portion 91 and covers all the first resistance connecting electrodes 81.

[0322] The second electrode portion 92 is formed with a gap from the first slit 71 to the second slit 72 side in a plan view, and does not intersect the first slit 71. Furthermore, the second electrode portion 92 is formed with a gap from the second slit 72 to the first slit 71 side in a plan view, and does not intersect the second slit 72. That is, the second electrode portion 92 has a width smaller than the width of the resistive film 60 in the first direction X, and is disposed only in a region directly above the resistive film 60.

[0323] The second electrode portion 92 is opposed to the space region 57 via the main surface insulating film 45, the resistor film 60, and the interlayer insulating film 74. That is, the second electrode portion 92 is opposed to the flat portion of the first main surface 3 in the thickness direction. In addition, the second electrode portion 92 is opposed to the boundary well region 40 (first boundary well region 40A) in the thickness direction.

[0324] The second electrode portion 92 has a width in the first direction X that is greater than the width of the trench resistor structure 51 in the first direction X. The second electrode portion 92 has a width in the second direction Y that is smaller than the length of the trench resistor structure 51 in the second direction Y. The second electrode portion 92 preferably has a width in the second direction Y that is smaller than the space width of the space region 57.

[0325] In this embodiment, the second electrode portion 92 is formed from the other end portion (first trench group 52) of the plurality of first trench resistor structures 51A to the space region 57 side with a gap. In addition, in this embodiment, the second electrode portion 92 is formed from one end portion (second trench group 53) of the plurality of second trench resistor structures 51B to the space region 57 side with a gap. That is, the second electrode portion 92 is opposed to only the space region 57 in the thickness direction, and is not opposed to the plurality of trench resistor structures 51 in the thickness direction.

[0326] Of course, the second electrode portion 92 may also be opposite to the other end portion (first groove group 52) of the plurality of first groove resistor structures 51A in the thickness direction. In addition, the second electrode portion 92 may also be opposite to one end portion (second groove group 53) of the plurality of second groove resistor structures 51B in the thickness direction. In view of the flatness of the second electrode portion 92, the second electrode portion 92 is preferably formed in a region outside the plurality of groove resistor structures 51 with a gap therebetween when viewed from above.

[0327] Reference Figures 11 to 23 The semiconductor device 1A includes a gate wiring electrode 93, which is arranged on the first main surface 3 in the pad region 10 (inactive region 7) in a manner electrically connected to the gate resistance structure 50. Specifically, the gate wiring electrode 93 is arranged on the interlayer insulating film 74. The gate wiring electrode 93 may also be referred to as a "gate finger" or a "gate finger electrode".

[0328] The gate wiring electrode 93 is preferably made of a conductive material different from the resistor film 60. The gate wiring electrode 93 is preferably made of a conductive material different from the gate wiring film 65. The gate wiring electrode 93 has a lower resistance value than the trench resistor structure 51 and the resistor film 60, and is electrically connected to the gate terminal electrode 90 via the trench resistor structure 51 and the resistor film 60. The gate wiring electrode 93 has a lower resistance value than the gate wiring film 65.

[0329] In this embodiment, the gate wiring electrode 93 is composed of a metal film. The gate wiring electrode 93 may also be referred to as a "gate metal wiring". The gate wiring electrode 93 may also include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film.

[0330] The gate wiring electrode 93 may also include at least one of a pure Cu film, a pure Al film, an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this embodiment, the gate wiring film 65 has a stacked structure including a Ti film and an Al alloy film (in this embodiment, an AlCu alloy film) stacked in sequence from the chip 2 side. That is, the gate wiring film 65 has the same electrode structure as the gate terminal electrode 90.

[0331] The gate wiring electrode 93 is preferably thicker than the thickness of the resistor film 60 (the thickness of the gate wiring film 65 ). The thickness of the gate wiring electrode 93 may be 1 μm to 10 μm. The thickness of the gate wiring electrode 93 is preferably substantially equal to the thickness of the gate terminal electrode 90 .

[0332] The gate wiring electrode 93 is routed in the region between the active region 6 and the inactive region 7, is electrically connected to the first trench structure 21 (trench isolation structure 15) in the active region 6, and is electrically connected to the resistor film 60 in the inactive region 7. Specifically, the gate wiring electrode 93 is electrically connected to the first end 60A and the second end 60B of the resistor film 60 via the gate wiring film 65.

[0333] That is, the gate wiring electrode 93 forms a parallel resistance circuit PR (also referred to as PR) including a first gate resistor R1 and a second gate resistor R2 between the gate wiring electrode 93 and the gate terminal electrode 90. Fig.24 ). The parallel resistance circuit PR constitutes a gate resistor RG sandwiched between the gate terminal electrode 90 and the gate wiring electrode 93. The parallel resistance circuit PR also exists between the gate electrode film 64 and the gate wiring film 65. The resistance value of the gate resistor RG (parallel resistance circuit PR) is calculated by the combined resistance of the first gate resistor R1 and the second gate resistor R2 (= (R1+R2) / R1·R2).

[0334] In this embodiment, the gate wiring electrode 93 includes a first upper wiring portion 94, a second upper wiring portion 95, and a third upper wiring portion 96. The first upper wiring portion 94 is arranged in the pad region 10 so as to surround the gate terminal electrode 90 from multiple directions (three directions in this embodiment), and is arranged on the first lower wiring portion 66 of the gate wiring film 65 via the interlayer insulating film 74.

[0335] The first upper wiring portion 94 includes a first upper line portion 97 and a plurality of second upper line portions 98A and 98B. The first upper line portion 97 is disposed in the pad region 10 in a region covering the first lower line portion 69 of the gate wiring film 65 via the interlayer insulating film 74 and is formed in a strip shape extending in the second direction Y.

[0336] The first upper wiring portion 97 has one end on one side (the first side surface 5A side) in the second direction Y and the other end on the other side (the second side surface 5B side) in the second direction Y. The first upper wiring portion 97 covers the second slit 72 via the interlayer insulating film 74 and backfills the second groove portion 77 of the interlayer insulating film 74 (insulating main surface 75).

[0337] In the case where a gate terminal electrode 90 (first electrode portion 91 and / or second electrode portion 92) intersecting the second groove portion 77 and a gate wiring electrode 93 (first upper line portion 97) partially exposing the second groove portion 77 are formed, electrode residues generated during the formation process of the gate terminal electrode 90 may remain in multiple second groove portions 77.

[0338] When there is electrode residue, the gate wiring electrode 93 (first upper wiring portion 97) may be electrically connected to the gate terminal electrode 90 via the electrode residue. In this case, the gate wiring electrode 93 (first upper wiring portion 97) and the gate terminal electrode 90 (first electrode portion 91) together form a short circuit that does not pass through the gate resistance structure 50. Therefore, the gate wiring electrode 93 (first upper wiring portion 97) preferably covers the entire area of ​​the second slit 72 via the interlayer insulating film 74.

[0339] That is, the gate wiring electrode 93 (first upper wiring portion 97) preferably fills the entire area of ​​the second recessed portion 77 of the interlayer insulating film 74 (insulating main surface 75). According to this structure, a layout is provided that avoids the problem of electrode residue in the second recessed portion 77. The present disclosure does not exclude a method including making the gate terminal electrode 90 (first electrode portion 91 and / or second electrode portion 92) intersecting the second recessed portion 77 and the gate wiring electrode 93 (first upper wiring portion 97) partially exposed in the second recessed portion 77.

[0340] The first upper wiring portion 97 is drawn from above the gate wiring film 65 (first lower wiring portion 69) across the second slit 72 to the top of the resistor film 60 in a plan view. The first upper wiring portion 97 covers the edge of the resistor film 60 via the interlayer insulating film 74. The first upper wiring portion 97 may further cross a straight line that crosses the center of the resistor film 60 in the second direction Y, and cover a portion of the region of the resistor film 60 that is located on the gate electrode film 64 side relative to the straight line.

[0341] The first upper line portion 97 is formed at a distance from the first electrode portion 91 and the second electrode portion 92 of the gate terminal electrode 90 in the first direction X. In this embodiment, the first upper line portion 97 has a recessed portion 97 a recessed in the first direction X along the second electrode portion 92 at a portion along the second electrode portion 92 of the gate terminal electrode 90 .

[0342] The first upper line portion 97 includes a first connection region 101 and a second connection region 102. The first connection region 101 is formed in a region on one side (on the first side surface 5A side) in the second direction Y relative to the recess 97a, and is opposed to the second electrode portion 92 in the second direction Y. The first connection region 101 covers the second covering portion 62 of the resistor film 60 via the interlayer insulating film 74. That is, the first connection region 101 covers the first trench group 52 (a plurality of first trench resistor structures 51A) via the interlayer insulating film 74 and the second covering portion 62 of the resistor film 60.

[0343] The first connection region 101 further covers the plurality of first resistor connection electrodes 81 and is electrically connected to the plurality of first resistor connection electrodes 81. Thus, the first connection region 101 is electrically connected to the second covering portion 62 of the resistor film 60 and the first trench group 52 (plurality of first trench resistor structures 51A) via the plurality of first resistor connection electrodes 81.

[0344] The first connection region 101 only needs to cover one or more first trench resistor structures 51A adjacent to one or more first resistor connection electrodes 81, and does not need to cover all first trench resistor structures 51A. Of course, the first connection region 101 may also cover all first trench resistor structures 51A.

[0345] The second connection region 102 is formed in a region on the other side (on the second side surface 5B side) in the second direction Y relative to the recessed portion 97a, and is opposed to the second electrode portion 92 in the second direction Y. The second connection region 102 covers the third covering portion 63 of the resistor film 60 via the interlayer insulating film 74. That is, the second connection region 102 covers the second trench group 53 (a plurality of second trench resistor structures 51B) via the interlayer insulating film 74 and the third covering portion 63 of the resistor film 60.

[0346] The second connection region 102 further covers the plurality of second resistor connection electrodes 82 and is electrically connected to the plurality of second resistor connection electrodes 82. Thus, the second connection region 102 is electrically connected to the third covering portion 63 of the resistor film 60 and the second trench group 53 (plurality of second trench resistor structures 51B) via the plurality of second resistor connection electrodes 82.

[0347] The second connection region 102 only needs to cover one or more second trench resistor structures 51B adjacent to one or more second resistor connection electrodes 82, and does not need to cover all second trench resistor structures 51B. Of course, the second connection region 102 may also cover all second trench resistor structures 51B.

[0348] The opposing area of ​​the gate wiring electrode 93 (first upper line portion 97) with respect to the resistor film 60 is preferably larger than the opposing area of ​​the gate terminal electrode 90 (first electrode portion 91 and second electrode portion 92) with respect to the resistor film 60. Of course, the opposing area of ​​the gate wiring electrode 93 may be smaller than the opposing area of ​​the gate terminal electrode 90.

[0349] When a gate terminal electrode 90 (first electrode portion 91 ) partially exposing the first recessed portion 76 and a first upper line portion 97 intersecting the first recessed portion 76 are formed, electrode residues generated during the formation step of the gate terminal electrode 90 may remain in the plurality of first recessed portions 76 .

[0350] When the electrode residue exists, the gate wiring electrode 93 (first upper line portion 97) may be electrically connected to the gate terminal electrode 90 (first electrode portion 91) via the electrode residue. In this case, the gate wiring electrode 93 (first upper line portion 97) and the gate terminal electrode 90 (first electrode portion 91) together form a short circuit that does not pass through the gate resistor structure 50.

[0351] Therefore, the first upper line portion 97 is preferably formed with a gap from the first groove portion 76 (first slit 71) to the second groove portion 77 (second slit 72) side in a plan view, and does not intersect the first groove portion 76 (first slit 71). In this embodiment, the gate terminal electrode 90 (first electrode portion 91) covers the entire area of ​​the first groove portion 76.

[0352] That is, the first upper line portion 97 is opposed to the first electrode portion 91 and the second electrode portion 92 of the gate terminal electrode 90 in the region above the resistor film 60 in the first direction X. According to this structure, a layout is provided that avoids the problem of electrode residues in the first recessed portion 76. The present disclosure does not exclude a method including the gate terminal electrode 90 (first electrode portion 91) that partially exposes the first recessed portion 76 and the first upper line portion 97 that intersects the first recessed portion 76.

[0353] The first current I1 given to the gate terminal electrode 90 (the second electrode portion 92) is transmitted to the first covering portion 61 of the resistor film 60 via the plurality of first resistor connection electrodes 81. The first current I1 transmitted to the first covering portion 61 is split into a second current I2 on the side of the second covering portion 62 (the first groove group 52) of the resistor film 60 and a third current I3 on ​​the side of the third covering portion 63 (the second groove group 53) of the resistor film 60.

[0354] The second current I2 is transmitted to the first connection area 101 of the first upper line portion 97 via the plurality of second resistance connection electrodes 82, and the third current I3 is transmitted to the second connection area 102 of the first upper line portion 97 via the plurality of third resistance connection electrodes 83. In this way, the gate wiring electrode 93 (first upper line portion 97) and the gate terminal electrode 90 (second electrode portion 92) form a parallel resistance circuit PR including the first gate resistor R1 and the second gate resistor R2 (also refer to Fig.24 ).

[0355] The plurality of second upper line portions 98A and 98B include a second upper line portion 98A on one side and a second upper line portion 98B on the other side. The second upper line portion 98A is disposed in a region on one side (on the first side 5A side) in the second direction Y relative to the gate terminal electrode 90 in the pad region 10. The second upper line portion 98B is disposed in a region on the other side (on the second side 5B side) in the second direction Y relative to the gate terminal electrode 90 in the pad region 10.

[0356] The second upper wiring portion 98A is formed in a strip shape extending in the first direction X, and has one end connected to one end of the first upper wiring portion 97, and the other end located on the peripheral side (the third side surface 5C side) of the chip 2. The second upper wiring portion 98A covers the second lower wiring portion 70A of the gate wiring film 65 via the interlayer insulating film 74. The second upper wiring portion 98A is formed to be spaced from the first electrode portion 91 of the gate terminal electrode 90 toward one side in the second direction Y.

[0357] The second upper wiring portion 98B is formed in a strip shape extending in the first direction X, and has one end connected to the other end of the first upper wiring portion 97, and the other end located on the peripheral side (the third side surface 5C side) of the chip 2. The second upper wiring portion 98B covers the second lower wiring portion 70B of the gate wiring film 65 via the interlayer insulating film 74. The second upper wiring portion 98B is formed to be spaced from the first electrode portion 91 of the gate terminal electrode 90 toward the other side in the second direction Y, and is opposed to the second upper wiring portion 98A via the first electrode portion 91.

[0358] When the gate terminal electrode 90 (first electrode portion 91) partially exposes the first recessed portion 76 and the second upper wiring portions 98A and 98B intersecting the first recessed portion 76 are formed, electrode residues generated during the step of forming the gate terminal electrode 90 may remain in the first recessed portion 76. When the electrode residues are present, the gate wiring electrode 93 (second upper wiring portions 98A and 98B) may be electrically connected to the gate terminal electrode 90 (first electrode portion 91) via the electrode residues.

[0359] In this case, the gate wiring electrode 93 (second upper line portions 98A, 98B) and the gate terminal electrode 90 (first electrode portion 91) together form a short circuit that does not pass through the gate resistance structure 50. Therefore, the second upper line portions 98A, 98B are preferably arranged at a distance from the first groove portion 76 and do not have a portion covering the first groove portion 76 (a portion intersecting the first groove portion 76).

[0360] This structure provides a layout that avoids the problem of electrode residue in the first recess 76. The present disclosure does not exclude a configuration including the gate terminal electrode 90 (first electrode portion 91) partially exposing the first recess 76 and the second upper line portions 98A and 98B intersecting the first recess 76.

[0361] In addition, when the gate terminal electrode 90 (first electrode portion 91) partially exposes the plurality of third recessed portions 78 and the second upper wiring portions 98A and 98B intersecting the plurality of third recessed portions 78 are formed, electrode residues generated during the step of forming the gate terminal electrode 90 may remain in the plurality of third recessed portions 78. In these cases, the gate wiring electrode 93 (second upper wiring portions 98A and 98B) together with the gate terminal electrode 90 (first electrode portion 91) form a short circuit that does not pass through the gate resistor structure 50.

[0362] Therefore, the second upper line portions 98A and 98B are preferably arranged at intervals from the plurality of third grooves 78 and do not have a portion covering the plurality of third grooves 78 (a portion intersecting the plurality of third grooves 78). According to this structure, a layout is provided that avoids the problem of electrode residues in the plurality of third grooves 78. In this embodiment, the gate terminal electrode 90 (first electrode portion 91) covers the entire region of the plurality of third grooves 78.

[0363] That is, the second upper line portions 98A and 98B are opposed to the first electrode portion 91 of the gate terminal electrode 90 in the second direction Y in the region above the second lower line portions 70A and 70B. The present disclosure does not exclude a mode including the gate terminal electrode 90 (first electrode portion 91) that partially exposes the plurality of third groove portions 78 and the second upper line portions 98A and 98B that intersect the plurality of third groove portions 78.

[0364] The second upper line portions 98A and 98B preferably cover the inner portions of the second lower line portions 70A and 70B with a gap from the periphery of the second lower line portions 70A and 70B in a plan view. That is, the second upper line portions 98A and 98B preferably face only the second lower line portions 70A and 70B via the interlayer insulating film 74, and do not face the main surface insulating film 45 via the interlayer insulating film 74.

[0365] The second upper wiring portion 95 is led out from the first upper wiring portion 94 toward the scribe line region 11, and covers the second lower wiring portion 67 of the gate wiring film 65 via the interlayer insulating film 74. Specifically, the second upper wiring portion 95 is led out from the inner portion (central portion in this embodiment) of the first upper wiring portion 97, and is formed into a strip extending in the first direction X.

[0366] In this embodiment, the second upper wiring portion 95 crosses the center of the chip 2. The second upper wiring portion 95 extends in a strip shape in a region located on one side (the third side surface 5C side) and another side (the fourth side surface 5D side) of the first direction X with respect to a straight line crossing the center of the first main surface 3 in the second direction Y. The second upper wiring portion 95 has one end connected to the first upper wiring portion 94 on one side of the first direction X, and the other end on the other side of the first direction X. In this embodiment, the other end of the second upper wiring portion 95 is constituted by an open end.

[0367] The second upper wiring portion 95 covers the plurality of first gate connection electrodes 84A and is electrically connected to the second lower wiring portion 67 via the plurality of first gate connection electrodes 84A. The second upper wiring portion 95 has a width smaller than the width of the scribe line region 11 in the second direction Y, and is formed with a gap from the plurality of active regions 6 toward the inside of the scribe line region 11. That is, the second upper wiring portion 95 is formed with a gap from the plurality of trench isolation structures 15 (plurality of first trench structures 21) in a plan view.

[0368] The third upper wiring portion 96 is led out from the first upper wiring portion 94 to the peripheral region 9, and covers the third lower wiring portion 68 of the gate wiring film 65 via the interlayer insulating film 74. Specifically, the third upper wiring portion 96 is led out from the other end portions of the plurality of second upper wiring portions 98A and 98B to one side (the first side surface 5A side) and the other side (the second side surface 5B side) of the peripheral region 9, and is formed into a belt shape extending along the peripheral region 9.

[0369] The third upper wiring portion 96 sandwiches the plurality of active regions 6 together with the second upper wiring portion 95. Specifically, the third upper wiring portion 96 extends along the periphery (first side surface 5A to 5D) of the chip 2 in a manner that surrounds the plurality of active regions 6 when viewed from above. Thus, the third upper wiring portion 96 surrounds the plurality of active regions 6 together with the second upper wiring portion 95. In this manner, the third upper wiring portion 96 is formed with a gap from the second upper wiring portion 95. The third upper wiring portion 96 may also be connected to the second upper wiring portion 95.

[0370] The third upper wiring portion 96 covers the plurality of second gate connection electrodes 84B and is electrically connected to the third lower wiring portion 68 via the plurality of second gate connection electrodes 84B. The third upper wiring portion 96 preferably has a width smaller than that of the third lower wiring portion 68 in a plan view. The third upper wiring portion 96 preferably covers the inner portion of the third lower wiring portion 68 with a gap from the periphery of the third lower wiring portion 68 in a plan view.

[0371] Reference Figure 1 as well as Figure 11 to Figure 22 The semiconductor device 1A includes an emitter terminal electrode 103 disposed on the first main surface 3 at a distance from the gate terminal electrode 90 and the gate wiring electrode 93 in the active region 6 . Specifically, the emitter terminal electrode 103 is disposed on the interlayer insulating film 74 .

[0372] The emitter terminal electrode 103 may also be referred to as an “emitter pad” or an “emitter pad electrode.” The emitter terminal electrode 103 is preferably made of a conductive material different from that of the resistor film 60 . The emitter terminal electrode 103 is preferably made of a conductive material different from that of the emitter electrode film 47 .

[0373] The emitter terminal electrode 103 has a lower resistance value than the trench resistor structure 51 and the resistor film 60. In this embodiment, the emitter terminal electrode 103 is composed of a metal film. The emitter terminal electrode 103 may also be referred to as an "emitter metal terminal". The emitter terminal electrode 103 may also include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film.

[0374] The emitter terminal electrode 103 may also include at least one of a pure Cu film, a pure Al film, an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this embodiment, the emitter terminal electrode 103 has a stacked structure including a Ti film and an Al alloy film (in this embodiment, an AlCu alloy film) stacked in sequence from the chip 2 side. That is, the emitter terminal electrode 103 has the same electrode structure as the gate terminal electrode 90.

[0375] The emitter terminal electrode 103 preferably has a thickness greater than the thickness of the resistor film 60 (the thickness of the gate electrode film 64 ). The thickness of the emitter terminal electrode 103 may be 1 μm or more and 10 μm or less. The thickness of the emitter terminal electrode 103 is preferably substantially equal to the thickness of the gate terminal electrode 90 .

[0376] The emitter terminal electrode 103 has a larger plane area than the gate terminal electrode 90. The plane area of ​​the emitter terminal electrode 103 is preferably 50% or more and 90% or less of the plane area of ​​the first main surface 3. The plane area of ​​the emitter terminal electrode 103 is particularly preferably 70% or more of the plane area of ​​the first main surface 3.

[0377] In this embodiment, the emitter terminal electrode 103 includes a first emitter terminal electrode 103A and a second emitter terminal electrode 103B. The first emitter terminal electrode 103A is arranged in a region between the second upper wiring portion 95 and the third upper wiring portion 96 on a portion of the interlayer insulating film 74 covering the first active region 6A. The first emitter terminal electrode 103A is led out from the first active region 6A to the peripheral region 9 in a plan view.

[0378] The first emitter terminal electrode 103A covers the plurality of first emitter connection electrodes 85 and the plurality of second emitter connection electrodes 86 in the first active region 6A, and covers the plurality of first well connection electrodes 87 in the outer peripheral region 9 .

[0379] The first emitter terminal electrode 103A is electrically connected to the second trench structures 25, the emitter regions 29 and the contact regions 31 via the first emitter connection electrodes 85 and the second emitter connection electrodes 86. The first emitter terminal electrode 103A is electrically connected to the inner edge of the peripheral well region 41 via the first well connection electrodes 87.

[0380] The second emitter terminal electrode 103B is disposed on a portion of the interlayer insulating film 74 covering the second active region 6B in a region between the second upper wiring portion 95 and the third upper wiring portion 96. The second emitter terminal electrode 103B is extended from the second active region 6B to the outer peripheral region 9 in a plan view.

[0381] The second emitter terminal electrode 103B covers the plurality of first emitter connection electrodes 85 and the plurality of second emitter connection electrodes 86 in the second active region 6B, and covers the plurality of first well connection electrodes 87 in the outer peripheral region 9 .

[0382] The second emitter terminal electrode 103B is electrically connected to the second trench structures 25, the emitter regions 29 and the contact regions 31 via the first emitter connection electrodes 85 and the second emitter connection electrodes 86. The second emitter terminal electrode 103B is electrically connected to the inner edge of the peripheral well region 41 via the first well connection electrodes 87.

[0383] The semiconductor device 1A includes an emitter wiring electrode 104, which is led out from the emitter terminal electrode 103 to the region outside the gate wiring electrode 93 on the interlayer insulating film 74. The emitter wiring electrode 104 may also be called an "emitter finger" or an "emitter finger electrode". The emitter wiring electrode 104 is preferably made of a conductive material different from that of the resistor film 60. The emitter wiring electrode 104 is preferably made of a conductive material different from that of the emitter electrode film 47.

[0384] The emitter wiring electrode 104 has a lower resistance value than the trench resistor structure 51 and the resistor film 60. In this embodiment, the emitter wiring electrode 104 is composed of a metal film. The emitter wiring electrode 104 may also be referred to as "emitter metal wiring". The emitter wiring electrode 104 may also include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film.

[0385] The emitter wiring electrode 104 may also include at least one of a pure Cu film, a pure Al film, an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this embodiment, the emitter wiring electrode 104 has a stacked structure including a Ti film and an Al alloy film (in this embodiment, an AlCu alloy film) stacked in sequence from the chip 2 side. That is, the emitter wiring electrode 104 has the same electrode structure as the emitter terminal electrode 103.

[0386] The emitter wiring electrode 104 preferably has a thickness greater than the thickness of the resistor film 60 (the thickness of the gate electrode film 64). The thickness of the emitter wiring electrode 104 may be 1 μm or more and 10 μm or less. The thickness of the emitter wiring electrode 104 is preferably substantially equal to the thickness of the gate terminal electrode 90 (emitter terminal electrode 103).

[0387] The emitter wiring electrode 104 is connected to both the first emitter terminal electrode 103A and the second emitter terminal electrode 103B, and is led out from the first emitter terminal electrode 103A and the second emitter terminal electrode 103B to the outside of the gate wiring electrode 93 (third upper wiring portion 96 ).

[0388] The emitter wiring electrode 104 is formed in a strip shape extending along the periphery of the chip 2 in a manner that surrounds the gate terminal electrode 90, the gate wiring electrode 93, the first emitter terminal electrode 103A, and the second emitter terminal electrode 103B. In this manner, the emitter wiring electrode 104 is formed in a ring shape (specifically, a four-sided ring shape) extending along the periphery (the first to fourth side surfaces 5A to 5D) of the chip 2, and surrounds the gate terminal electrode 90, the gate wiring electrode 93, the first emitter terminal electrode 103A, and the second emitter terminal electrode 103B.

[0389] The emitter wiring electrode 104 is led to the portion of the interlayer insulating film 74 covering the outer edge of the peripheral well region 41. The emitter wiring electrode 104 covers the plurality of second well connection electrodes 88 and is electrically connected to the outer edge of the peripheral well region 41 via the plurality of second well connection electrodes 88.

[0390] The semiconductor device 1A includes a plurality of field electrodes 105 disposed on the interlayer insulating film 74 in the peripheral region 9. The plurality of field electrodes 105 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film.

[0391] The plurality of field electrodes 105 may also include at least one of a pure Cu film, a pure Al film, an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this embodiment, the plurality of field electrodes 105 have a stacked structure including a Ti film and an Al alloy film (in this embodiment, an AlCu alloy film) stacked in sequence from the chip 2 side.

[0392] The plurality of field electrodes 105 cover the corresponding field regions 42 in a one-to-one correspondence. Each field electrode 105 also covers the corresponding plurality of field connection electrodes 89. Each field electrode 105 is electrically connected to the corresponding field region 42 via the corresponding plurality of field connection electrodes 89. The plurality of field electrodes 105 are formed in an electrically floating state.

[0393] The plurality of field electrodes 105 are formed in a strip shape extending along the corresponding field region 42. In this embodiment, the plurality of field electrodes 105 are formed in a ring shape (quadrilateral ring shape) extending along the corresponding field region 42. The outermost field electrode 105 includes a field extraction portion 105a that is extracted toward the peripheral side of the chip 2, and may be formed to be wider than the other field electrodes 105.

[0394] The semiconductor device 1A includes a channel stopper electrode 106 disposed on the interlayer insulating film 74 in the peripheral region 9. The channel stopper electrode 106 may include at least one of a Ti film, a TiN film, a W film, an Al film, a Cu film, an Al alloy film, a Cu alloy film, and a conductive polysilicon film.

[0395] The channel blocking electrode 106 may also include at least one of a pure Cu film, a pure Al film, an AlCu alloy film, an AlSi alloy film, and an AlSiCu alloy film. In this embodiment, the channel blocking electrode 106 has a stacked structure including a Ti film and an Al alloy film (in this embodiment, an AlCu alloy film) stacked in sequence from the chip 2 side.

[0396] The channel stopper electrode 106 is formed in a belt shape extending along the periphery of the first main surface 3. In this embodiment, the channel stopper electrode 106 is formed in a ring shape (quadrilateral ring shape) extending along the periphery of the first main surface 3.

[0397] The channel stopper electrode 106 enters the removed portion 46 of the interlayer insulating film 74 from above the interlayer insulating film 74 and is electrically connected to the channel stopper region 43. The channel stopper electrode 106 is formed in an electrically floating state. The channel stopper electrode 106 may be formed with a gap inward from the periphery of the chip 2 so that the periphery of the first main surface 3 (channel stopper region 43) is exposed.

[0398] The semiconductor device 1A includes a collector electrode 107, which covers the second main surface 4. The collector electrode 107 is electrically connected to the collector region 14 exposed from the second main surface 4. The collector electrode 107 forms an ohmic contact with the collector region 14. The collector electrode 107 may cover the entire area of ​​the second main surface 4 in a manner connected to the periphery (the first to fourth side surfaces 5A to 5D) of the chip 2.

[0399] As described above, the semiconductor device 1A includes the chip 2, the trench resistor structure 51, the resistor film 60, the gate terminal electrode 90, and the gate wiring electrode 93. The chip 2 has the first main surface 3. The trench resistor structure 51 is formed on the first main surface 3. The resistor film 60 is electrically connected to the trench resistor structure 51 on the first main surface 3.

[0400] The gate terminal electrode 90 has a lower resistance value than the resistor film 60 and is electrically connected to the trench resistor structure 51 on the first main surface 3 via the resistor film 60. The gate wiring electrode 93 has a lower resistance value than the resistor film 60 and is electrically connected to the gate terminal electrode 90 on the first main surface 3 via the trench resistor structure 51 and the resistor film 60.

[0401] According to this structure, the gate resistor RG including the trench resistor structure 51 and the resistor film 60 can be sandwiched between the gate terminal electrode 90 and the gate wiring electrode 93. In particular, according to this structure, the trench resistor structure 51 is assembled in the chip 2 in the region between the gate terminal electrode 90 and the gate wiring electrode 93, so that the increase in the exclusive area of ​​the gate resistor RG with respect to the first main surface 3 can be suppressed. Therefore, in the structure including the gate resistor RG, it is possible to provide a semiconductor device 1A having a novel layout that contributes to miniaturization.

[0402] The semiconductor device 1A preferably includes a gate electrode film 64 and a gate wiring film 65. The gate electrode film 64 is disposed on the first main surface 3 adjacent to the resistor film 60. The gate wiring film 65 is disposed on the first main surface 3 adjacent to the resistor film 60 so as to face the gate electrode film 64 with the resistor film 60 interposed therebetween.

[0403] In such a structure, the gate terminal electrode 90 preferably covers the gate electrode film 64. In addition, the gate wiring electrode 93 preferably covers the gate wiring film 65. According to this structure, in a structure including the resistance film 60, the gate electrode film 64, and the gate wiring film 65 on the first main surface 3, a semiconductor device 1A having a novel layout that contributes to miniaturization can be provided.

[0404] The resistor film 60 preferably has a first end 60A on one side and a second end 60B on the other side. In this case, the gate wiring film 65 preferably has a first connection portion connected to the first end 60A of the resistor film 60 and a second connection portion connected to the second end 60B of the resistor film 60. In this case, the gate wiring electrode 93 is preferably electrically connected to the resistor film 60 via the gate wiring film 65.

[0405] According to this structure, the gate wiring electrode 93 can be electrically connected to the resistor film 60 via the gate wiring film 65, so it is not necessary to directly connect the gate wiring electrode 93 to the resistor film 60. This can relax the design rules of the gate wiring electrode 93 and improve the degree of freedom in designing the gate wiring electrode 93.

[0406] The semiconductor device 1A preferably includes: a first slit 71 that divides between the resistor film 60 and the gate electrode film 64; and a second slit 72 that divides between the resistor film 60 and the gate wiring film 65. According to this structure, the resistor film 60 can be appropriately separated (divided) from the gate electrode film 64 and the gate wiring film 65 by the first slit 71 and the second slit 72. As a result, the accuracy of the resistance value of the resistor film 60 can be improved.

[0407] The gate terminal electrode 90 preferably crosses the first slit 71 in a plan view and covers the resistor film 60 and the gate electrode film 64. The gate wiring film 65 preferably crosses the second slit 72 in a plan view and covers the resistor film 60 and the gate electrode film 64. The first slit 71 is preferably formed to be narrower than the resistor film 60. The second slit 72 is preferably formed to be narrower than the resistor film 60.

[0408] The trench resistor structure 51 preferably extends in a strip shape in the second direction Y (one direction) when viewed from above. In this case, the resistor film 60 preferably extends in a strip shape in the second direction Y (one direction) when viewed from above. In addition, the first slit 71 preferably extends in a strip shape in the second direction Y (one direction) when viewed from above.

[0409] In addition, the second slit 72 preferably extends in a strip shape in a plan view in the second direction Y. The first slit 71 has a first length in the second direction Y, and the second slit 72 may have a second length smaller than the first length in the second direction Y.

[0410] The semiconductor device 1A preferably includes a third slit 73 that is divided between the gate electrode film 64 and the gate wiring film 65. According to this structure, the gate wiring film 65 can be appropriately separated (divided) from the gate electrode film 64 by the third slit 73. As a result, it is possible to prevent the gate wiring film 65 from forming a short circuit together with the gate electrode film 64 that does not pass through the resistor film 60. The gate terminal electrode 90 preferably crosses the third slit 73 and covers the gate electrode film 64 and the gate wiring film 65 when viewed from above.

[0411] The plurality of trench resistor structures 51 are preferably formed at intervals on the first main surface 3. In this case, the resistor film 60 preferably covers the plurality of trench resistor structures 51. According to this configuration, the plurality of trench resistor structures 51 can be used to adjust the resistance value of the gate resistor RG.

[0412] The resistor film 60 preferably includes a first covering portion 61 covering the first main surface 3 outside the trench resistor structure 51 and a second covering portion 62 covering the trench resistor structure 51. In this case, the gate terminal electrode 90 is preferably electrically connected to the resistor film 60 at a portion covering the first covering portion 61.

[0413] The gate wiring electrode 93 is preferably electrically connected to the resistor film 60 in the portion covering the second covering portion 62. With this configuration, a portion of the resistor film 60 and a portion of the trench resistor structure 51 can be appropriately interposed between the gate terminal electrode 90 and the gate wiring electrode 93.

[0414] The semiconductor device 1A preferably includes an interlayer insulating film 74, a first resistive connecting electrode 81, and a second resistive connecting electrode 82. The interlayer insulating film 74 covers the resistive film 60. The first resistive connecting electrode 81 is buried in the interlayer insulating film 74 in a manner electrically connected to the resistive film 60. The second resistive connecting electrode 82 is buried in the interlayer insulating film 74 in a manner electrically connected to the resistive film 60 at a position different from that of the first resistive connecting electrode 81.

[0415] In such a structure, the gate terminal electrode 90 is preferably arranged on the interlayer insulating film 74 so as to be electrically connected to the resistor film 60 via the first resistor connecting electrode 81. In addition, the gate wiring electrode 93 is preferably arranged on the interlayer insulating film 74 so as to be electrically connected to the resistor film 60 via the second resistor connecting electrode 82.

[0416] According to this structure, the gate resistor RG can be formed in the region between the first resistor connecting electrode 81 and the second resistor connecting electrode 82. The resistance value of the gate resistor RG can be adjusted by the distance between the first resistor connecting electrode 81 and the second resistor connecting electrode 82.

[0417] The second resistance connection electrode 82 may extend in a direction different from the first resistance connection electrode 81. For example, the first resistance connection electrode 81 may extend in a first direction X (one direction) when viewed from above, and the second resistance connection electrode 82 may extend in a second direction Y (crossing direction) that crosses the first direction X (one direction) when viewed from above.

[0418] The plurality of first resistance connection electrodes 81 are preferably embedded in the interlayer insulating film 74. The plurality of second resistance connection electrodes 82 are preferably embedded in the interlayer insulating film 74. The second connection area S2 of the second resistance connection electrode 82 to the resistance film 60 may be smaller than the first connection area S1 of the first resistance connection electrode 81 to the resistance film 60.

[0419] The gate terminal electrode 90 preferably includes: a first electrode portion 91 located outside the first resistance connection electrode 81 in a plan view; and a second electrode portion 92 protruding from the first electrode portion 91 toward the first resistance connection electrode 81 with a width narrower than the first electrode portion 91. In this case, the first electrode portion 91 is preferably formed as a terminal main body portion of the gate terminal electrode 90. In addition, the second electrode portion 92 is preferably formed as a terminal lead portion led out from the terminal main body portion.

[0420] According to these structures, the first electrode portion 91 can ensure the region to which the gate potential is applied, and the second electrode portion 92 can ensure the region electrically connected to the resistor film 60. For example, when a conductive bonding material such as a bonding wire is bonded to the gate terminal electrode 90, the conductive bonding material can be bonded to the first electrode portion 91. Thus, it is possible to suppress the stress caused by the conductive bonding material in the resistor film 60 and the trench resistor structure 51. Therefore, it is possible to suppress the degradation of the electrical characteristics of the gate resistor RG.

[0421] The semiconductor device 1A preferably includes a p-type boundary well region 40 formed on the surface portion of the first main surface 3. According to this structure, the breakdown voltage can be improved by the boundary well region 40. In this case, the trench resistor structure 51 is preferably formed with a gap from the bottom of the boundary well region 40 toward the first main surface 3. According to this structure, the electric field concentration with respect to the bottom wall of the trench resistor structure 51 can be suppressed by the boundary well region 40. Therefore, the breakdown voltage can be appropriately improved.

[0422] The semiconductor device 1A preferably includes an active region 6 provided on the first main surface 3, an inactive region 7 provided outside the active region 6 on the first main surface 3, and a first trench structure 21 (trench gate structure) formed in the active region 6. In this case, the trench resistor structure 51 is preferably formed in the inactive region 7. In addition, the resistor film 60 preferably covers the trench resistor structure 51 in the inactive region 7.

[0423] In addition, the gate terminal electrode 90 is preferably electrically connected to the resistance film 60 in the inactive region 7. In addition, the gate wiring electrode 93 is preferably electrically connected to the first trench structure 21 in the active region 6, and electrically connected to the resistance film 60 in the inactive region 7. According to these structures, since the gate resistor RG is formed in the inactive region 7, the reduction of the active region 6 can be suppressed.

[0424] Fig.25 1 is a plan view showing the layout of the first main surface 3 of the semiconductor device 1B according to the second embodiment. Fig.26 is along Fig.25 The semiconductor device 1B is a device that achieves the same effects as those of the semiconductor device 1A. The semiconductor device 1A of the first embodiment includes a second trench structure 25 and a floating region 32 .

[0425] In contrast, the semiconductor device 1B does not include the second trench structure 25 and the floating region 32. Fig.25 as well as Fig.26 The semiconductor device 1B includes a plurality of first trench structures 21 which are arranged at intervals in the first direction X so as to be adjacent to each other in the plurality of active regions 6 and are formed in a strip shape extending in the second direction Y.

[0426] The emitter regions 29 are formed in regions between adjacent first trench structures 21 in the surface portion of the first main surface 3. The contact holes 30 are formed in regions between adjacent first trench structures 21 in a plan view.

[0427] In the first direction X, the intervals between the plurality of trench resistor structures 51 may be substantially equal to the intervals between the plurality of first trench structures 21. Of course, the intervals between the plurality of trench resistor structures 51 may be larger than the intervals between the plurality of first trench structures 21. In addition, the intervals between the plurality of trench resistor structures 51 may be smaller than the intervals between the plurality of first trench structures 21.

[0428] Fig. 27 1 is a plan view showing the layout of the first main surface 3 of the semiconductor device 1C according to the third embodiment. Fig.28 Yes means Fig. 27 1 is a cross-sectional view of the structure of the semiconductor device 1C on the boundary region 8 side. Fig.29 Yes means Fig. 27 1 is a cross-sectional view of the structure of the semiconductor device 1C on the peripheral region 9 side. The semiconductor device 1C is a device that achieves the same effects as those of the semiconductor device 1A.

[0429] Reference Figure 27 to Figure 29The semiconductor device 1C is an RC-IGBT semiconductor device having an RC-IGBT (Reverse Conducting-IGBT) which integrally includes an IGBT (Insulated Gate Bipolar Transistor) and a diode. The diode is a freewheeling diode for the IGBT.

[0430] Specifically, in addition to the structure of the semiconductor device 1A described above, the semiconductor device 1C further includes an n-type cathode region 110 formed on the surface portion of the second main surface 4. The cathode region 110 has an n-type impurity concentration higher than the p-type impurity concentration of the collector region 14, and is composed of a region in which the conductivity type of a portion of the collector region 14 is replaced from p-type to n-type.

[0431] The cathode region 110 penetrates the collector region 14 and is connected to the buffer region 13. When the buffer region 13 is not formed, the cathode region 110 is connected to the drift region 12. The cathode region 110 preferably has a higher n-type impurity concentration than the drift region 12 and the buffer region 13.

[0432] In this embodiment, cathode region 110 includes boundary cathode region 111 formed on the surface of second main surface 4 in boundary region 8 and peripheral cathode region 112 formed on the surface of second main surface 4 in peripheral region 9 .

[0433] The cathode region 110 only needs to include at least one of the boundary cathode region 111 and the peripheral cathode region 112, but does not necessarily need to include both. The cathode region 110 may only include the boundary cathode region 111, or the cathode region 110 may only include the peripheral cathode region 112.

[0434] The boundary cathode region 111 is formed on the surface of the second main surface 4 so as to face the boundary well region 40 in the thickness direction of the chip 2 in the boundary region 8. The boundary cathode region 111 is formed in a region sandwiched between the first trench isolation structure 15A and the second trench isolation structure 15B in a plan view.

[0435] That is, the boundary cathode region 111 is formed in a region sandwiched by the plurality of first trench structures 21 on the first active region 6A side and the plurality of first trench structures 21 on the second active region 6B side in a plan view. The boundary cathode region 111 is preferably formed with a gap from the base region 20 in the direction along the second main surface 4 so as not to be opposed to the base region 20 of each active region 6 in the thickness direction.

[0436] The boundary cathode region 111 is particularly preferably formed at a distance from the plurality of first groove structures 21 in the direction along the second main surface 4 in a manner that does not oppose the plurality of first groove structures 21 in the thickness direction of the chip 2. In this manner, the boundary cathode region 111 is formed at a distance from the plurality of groove separation structures 15 in the direction along the second main surface 4.

[0437] That is, the boundary cathode region 111 has a width smaller than that of the boundary region 8 in the second direction Y. In addition, the boundary cathode region 111 is formed in the surface portion of the second main surface 4 in such a manner that a portion of the collector region 14 remains in the boundary region 8. That is, the semiconductor device 1C includes the collector region 14 formed in the scribe line region 11.

[0438] The boundary cathode region 111 is formed in either or both of the pad region 10 and the scribe line region 11. That is, the boundary cathode region 111 may be formed in the scribe line region 11 instead of the pad region 10. In addition, the boundary cathode region 111 may be formed in the pad region 10 instead of the scribe line region 11. In this embodiment, the boundary cathode region 111 is formed in both the pad region 10 and the scribe line region 11.

[0439] When the boundary cathode region 111 is formed in the pad region 10, the boundary cathode region 111 is formed in a polygonal shape (quadrilateral shape) along the periphery of the pad region 10 in the pad region 10. The boundary cathode region 111 is opposed to the first boundary well region 40A of the boundary well region 40 in the thickness direction of the chip 2 in the pad region 10.

[0440] In this case, the boundary cathode region 111 may be opposite to one or both of the first trench group 52 (plural first trench resistor structures 51A) and the second trench group 53 (plural second trench resistor structures 51B) via the first boundary well region 40A. The boundary cathode region 111 may be opposite to a part or all of the plurality of first trench resistor structures 51A. The boundary cathode region 111 may be opposite to a part or all of the plurality of second trench resistor structures 51B.

[0441] When the boundary cathode region 111 is formed in the scribe line region 11 , the boundary cathode region 111 is formed in a strip shape extending in the second direction Y. The boundary cathode region 111 is opposed to the second boundary well region 40B of the boundary well region 40 in the thickness direction of the chip 2 in the scribe line region 11 .

[0442] The peripheral cathode region 112 is formed on the surface of the second main surface 4 so as to face the peripheral well region 41 in the thickness direction of the chip 2 in the peripheral region 9. In this embodiment, the peripheral cathode region 112 is formed in a ring shape (a quadrilateral ring shape in this embodiment) surrounding the plurality of active regions 6 in a plan view.

[0443] The peripheral cathode region 112 is preferably formed with a gap from the base region 20 of each active region 6 toward the peripheral side of the chip 2 in a manner that it does not oppose the base region 20 of each active region 6 at least in the thickness direction. The peripheral cathode region 112 is preferably formed with a gap from the plurality of first groove structures 21 toward the peripheral side of the chip 2 in a manner that it does not oppose the plurality of first groove structures 21 in the thickness direction.

[0444] The peripheral cathode region 112 is preferably formed with a gap from the plurality of trench separation structures 15 toward the peripheral side of the chip 2 in a manner that the plurality of trench separation structures 15 are not opposed in the thickness direction. That is, the peripheral cathode region 112 is preferably formed only in the peripheral region 9, and not in the plurality of active regions 6. The peripheral cathode region 112 may also be connected to the boundary cathode region 111 in the connection portion between the boundary region 8 and the peripheral region 9.

[0445] The collector electrode 107 is electrically connected to the collector region 14 and the cathode region 110. In this way, the semiconductor device 1C includes an IGBT structure Tr formed in each active region 6, a boundary diode D1 formed in the boundary region 8, and an outer diode D2 formed in the peripheral region 9. Each IGBT structure Tr includes a first trench structure 21 as a gate, an emitter region 29 as an emitter, and a collector region 14 as a collector.

[0446] The boundary diode D1 includes a boundary well region 40 as an anode and a boundary cathode region 111 as a cathode. The anode of the boundary diode D1 is electrically connected to the emitter of each IGBT structure Tr, and the cathode of the boundary diode D1 is electrically connected to the collector of each IGBT structure Tr. Thus, the boundary diode D1 functions as a first return diode of each IGBT structure Tr.

[0447] The outer diode D2 includes an outer well region 41 as an anode and an outer cathode region 112 as a cathode. The anode of the outer diode D2 is electrically connected to the emitter of each IGBT structure Tr, and the cathode of the outer diode D2 is electrically connected to the collector of each IGBT structure Tr. Thus, the outer diode D2 is connected in parallel with the boundary diode D1 in the forward direction. In addition, the outer diode D2 functions as a second return diode of each IGBT structure Tr.

[0448] The following are modified examples that can be applied to the above-mentioned embodiments. The following modified examples can also be applied to each embodiment alone. In addition, the following modified examples can also be applied to each embodiment based on appropriate combination. Fig.30 FIG. 8 is an enlarged plan view showing a first resistor connection electrode 81 of a modified example. Fig.30 In FIG. 8 , a plurality of first resistance connecting electrodes 81 are shown, but at least one first resistance connecting electrode 81 may be formed.

[0449] Reference Fig.30 The plurality of first resistor connection electrodes 81 may be arranged at intervals in the first direction X when viewed from above, or may be formed in stripes extending in the second direction Y. That is, the plurality of first resistor connection electrodes 81 may be arranged in stripes extending in the second direction Y when viewed from above. The plurality of first resistor connection electrodes 81 may be disposed in a one-to-one correspondence with the plurality of first trench resistor structures 51A in the second direction Y, or may be disposed in a one-to-one correspondence with the region between the plurality of first trench resistor structures 51A in the second direction Y.

[0450] In the same manner as described above, the second electrode portion 92 is led out from the first electrode portion 91 along the first direction X. In this manner, the protruding direction of the second electrode portion 92 is a direction that intersects with the extending direction of the plurality of first resistance connection electrodes 81. In this manner, the second electrode portion 92 intersects (specifically, is orthogonal to) the plurality of first resistance connection electrodes 81, and is led out from the first electrode portion 91 along the first direction X in a manner that covers the plurality of first resistance connection electrodes 81.

[0451] Fig.31 1 is a cross-sectional view showing a second resistor connecting electrode 82 according to a first modification. Fig.32 1 is an enlarged plan view showing a second resistor connecting electrode 82 according to a second modification. Fig.33 FIG. 8 is an enlarged plan view showing the second resistor connection electrode 82 of the third modification example. Figure 31 to Figure 33 In the figure, a plurality of second resistance connecting electrodes 82 are shown, but it is sufficient if at least one second resistance connecting electrode 82 is formed.

[0452] Reference Fig.31 The plurality of second resistor connection electrodes 82 may be embedded in the interlayer insulating film 74 so as to face the plurality of first trench resistor structures 51A via the resistor film 60. Fig.32 The plurality of second resistor connection electrodes 82 may be formed in stripes extending in the first direction X so as to intersect with the plurality of first trench resistor structures 51A in a plan view, and may be arranged at intervals in the second direction Y. In other words, the plurality of second resistor connection electrodes 82 may be arranged in stripes extending in the first direction X in a plan view.

[0453] The plurality of second resistor connection electrodes 82 only need to intersect at least one of the plurality of first trench resistor structures 51A, and do not need to intersect all of the first trench resistor structures 51A. In this embodiment, the plurality of second resistor connection electrodes 82 intersect a portion of the plurality of first trench resistor structures 51A. Of course, the plurality of second resistor connection electrodes 82 may also be opposite to all of the first trench resistor structures 51A in the second direction Y.

[0454] Reference Fig.33 The plurality of second resistor connection electrodes 82 may also be connected to the first groove group 52 in the resistor film 60 and the region between the first end portion 60A of the resistor film 60 in a plan view. In this embodiment, the plurality of second resistor connection electrodes 82 are arranged in stripes extending in the first direction X.

[0455] The plurality of second resistor connection electrodes 82 may also be opposite to at least one of the plurality of first trench resistor structures 51A in the second direction Y. The plurality of second resistor connection electrodes 82 are preferably opposite to at least two of the plurality of first trench resistor structures 51A in the second direction Y. Of course, the plurality of second resistor connection electrodes 82 may also be opposite to all of the first trench resistor structures 51A in the second direction Y.

[0456] Of course, the plurality of second resistor connection electrodes 82 may also be arranged in a stripe shape extending in the second direction Y. In this case, the plurality of second resistor connection electrodes 82 may also be disposed in a one-to-one correspondence relationship with the plurality of first trench resistor structures 51A in the second direction Y, or may be disposed in a one-to-one correspondence relationship with the region between the plurality of first trench resistor structures 51A in the second direction Y.

[0457] Fig.34 2 is a cross-sectional view showing a third resistance connecting electrode 83 according to a first modification. Fig.35 It is an enlarged plan view showing the third resistance connecting electrode 83 according to the second modification example. Fig.36 FIG. 8 is an enlarged plan view showing a third resistor connection electrode 83 according to a third modification example. Figure 34 to Figure 36 In the figure, a plurality of third resistance connecting electrodes 83 are shown, but it is sufficient if at least one third resistance connecting electrode 83 is formed.

[0458] Reference Fig.34 The plurality of third resistor connection electrodes 83 may be embedded in the interlayer insulating film 74 so as to face the plurality of second trench resistor structures 51B via the resistor film 60. Fig.35The plurality of third resistor connection electrodes 83 may also be formed in stripes extending in the first direction X so as to intersect with the plurality of second trench resistor structures 51B in a plan view, and may be arranged at intervals in the second direction Y. That is, the plurality of third resistor connection electrodes 83 may also be arranged in stripes extending in the first direction X in a plan view.

[0459] The plurality of third resistor connection electrodes 83 only need to intersect at least one of the plurality of second trench resistor structures 51B, and do not need to intersect all of the second trench resistor structures 51B. In this embodiment, the plurality of third resistor connection electrodes 83 intersect a portion of the plurality of second trench resistor structures 51B. Of course, the plurality of third resistor connection electrodes 83 may also be opposite to all of the second trench resistor structures 51B in the second direction Y.

[0460] Reference Fig.36 The plurality of third resistor connection electrodes 83 may also be connected to the second groove group 53 in the resistor film 60 and the region between the second end portion 60B of the resistor film 60 in a plan view. In this embodiment, the plurality of third resistor connection electrodes 83 are arranged in stripes extending in the first direction X.

[0461] The plurality of third resistor connection electrodes 83 may also be opposite to at least one of the plurality of second trench resistor structures 51B in the second direction Y. The plurality of third resistor connection electrodes 83 are preferably opposite to at least two of the plurality of second trench resistor structures 51B in the second direction Y. Of course, the plurality of third resistor connection electrodes 83 may also be opposite to all of the second trench resistor structures 51B in the second direction Y.

[0462] Of course, the plurality of third resistor connection electrodes 83 may also be arranged in a stripe shape extending in the second direction Y. In this case, the plurality of third resistor connection electrodes 83 may also be disposed in a one-to-one correspondence relationship with the plurality of second trench resistor structures 51B in the second direction Y, or may be disposed in a one-to-one correspondence relationship with the region between the plurality of second trench resistor structures 51B in the second direction Y.

[0463] Any of the third resistive connecting electrodes 83 of the first to third modified examples may be applied to the above-mentioned embodiments simultaneously with any of the second resistive connecting electrodes 82 of the first to third modified examples.

[0464] From the viewpoint of layout symmetry, the third resistance connection electrode 83 of the first modification is preferably used simultaneously with the second resistance connection electrode 82 of the first modification. In addition, the third resistance connection electrode 83 of the second modification is preferably used simultaneously with the second resistance connection electrode 82 of the second modification. In addition, the third resistance connection electrode 83 of the third modification is preferably used simultaneously with the second resistance connection electrode 82 of the third modification.

[0465] Fig.37 It is an enlarged plan view showing a gate resistance structure 50 according to a first modification. Fig.38 Yes means Fig.37 1 is an enlarged top view of the inner part of the gate resistor structure 50 shown in FIG. In each of the above-mentioned embodiments, the gate resistor structure 50 includes a first trench group 52 (a plurality of first trench resistor structures 51A) and a second trench group 53 (a plurality of second trench resistor structures 51B). In contrast, the gate resistor structure 50 of the modified example includes a single trench group 121 integrated with the first trench group 52 and the second trench group 53, and does not have a space area 57.

[0466] A single trench group 121 includes a plurality of trench resistor structures 51. The plurality of trench resistor structures 51 are arranged at intervals in the first direction X, and are each formed in a strip shape extending in the second direction Y. That is, the plurality of trench resistor structures 51 are arranged in a strip shape extending in the second direction Y. The plurality of trench resistor structures 51 have one end on one side of the second direction Y (on the first side surface 5A side), and the other end on the other side of the second direction Y (on the second side surface 5B side).

[0467] One end of the plurality of trench resistor structures 51 is opposite to the first active region 6A, and the other end of the plurality of trench resistor structures 51 is opposite to the second active region 6B. The region on one side (on the first side surface 5A side) of the middle portion of the single trench group 121 in the second direction Y can also be regarded as the first trench group 52, and the region on the other side (on the second side surface 5B side) of the middle portion of the single trench group 121 in the second direction Y can also be regarded as the second trench group 53.

[0468] In this embodiment, the resistor film 60 covers a single trench group 121 (multiple trench resistor structures 51 ) collectively. The resistor film 60 has a first end 60A on one end side of the plurality of trench resistor structures 51 and a second end 60B on the other end side of the plurality of trench resistor structures 51 .

[0469] In this embodiment, the plurality of first resistor connection electrodes 81 are connected to the inner portion (middle portion) of the resistor film 60 in a plan view. In this embodiment, the plurality of first resistor connection electrodes 81 are respectively formed in a strip shape extending in the first direction X, and are arranged at intervals in the second direction Y. That is, the plurality of first resistor connection electrodes 81 are arranged in a strip shape extending in the first direction X.

[0470] The plurality of first resistor connection electrodes 81 intersect with the plurality of trench resistor structures 51. The plurality of first resistor connection electrodes 81 only need to intersect with at least one of the plurality of trench resistor structures 51, and do not need to intersect with all of the trench resistor structures 51. In this embodiment, the plurality of first resistor connection electrodes 81 intersect with a portion of the plurality of trench resistor structures 51. Of course, the plurality of first resistor connection electrodes 81 may also be opposite to all of the trench resistor structures 51 in the second direction Y.

[0471] The plurality of second resistor connection electrodes 82 are connected to the resistor film 60 in a region on the first end 60A side of the resistor film 60 (a region on one end side of the plurality of trench resistor structures 51) relative to the plurality of first resistor connection electrodes 81 when viewed from above. The plurality of second resistor connection electrodes 82 are formed in the same layout as in the first embodiment. Of course, any of the second resistor connection electrodes 82 of the first to third modified examples may also be applied.

[0472] The plurality of third resistor connection electrodes 83 are connected to the resistor film 60 in a region on the second end 60B side of the resistor film 60 (a region on the other end side of the plurality of trench resistor structures 51) relative to the plurality of first resistor connection electrodes 81 when viewed from above. The plurality of third resistor connection electrodes 83 are formed in the same layout as in the first embodiment. Of course, any of the third resistor connection electrodes 83 of the first to third modified examples may also be applied.

[0473] Fig.39 1 is an enlarged top view showing the inner part of the gate resistor structure 50 of the second modification. In the gate resistor structure 50 of the first modification, the plurality of first resistor connection electrodes 81 intersect with the plurality of trench resistor structures 51. In contrast, the gate resistor structure 50 of the second modification includes the plurality of first resistor connection electrodes 81 that do not intersect with the plurality of trench resistor structures 51.

[0474] Reference Fig.39 , the plurality of first resistor connection electrodes 81 are formed in a region opposite to the plurality of trench resistor structures 51 in the first direction X in a plan view. In this embodiment, the plurality of first resistor connection electrodes 81 are respectively formed in a strip shape extending in the second direction Y in a plan view, and are arranged at intervals in the first direction X. That is, the plurality of first resistor connection electrodes 81 are arranged in a strip shape extending in the second direction Y in a plan view.

[0475] The first resistor connection electrodes 81 are disposed in a region between adjacent trench resistor structures 51 spaced apart from the trench resistor structures 51 in a plan view.

[0476] In this embodiment, the plurality of first resistor connection electrodes 81 are opposed to only the flat portion of the first main surface 3 via the resistor film 60, and are not opposed to the trench resistor structure 51 via the resistor film 60. The plurality of first resistor connection electrodes 81 are opposed to the boundary well region 40 via the resistor film 60 and the main surface insulating film 45.

[0477] The plurality of first resistor connection electrodes 81 may be arranged in a part of the region between the plurality of trench resistor structures 51, and need not be arranged in the entire region between the plurality of trench resistor structures 51. For example, the plurality of first resistor connection electrodes 81 may be arranged in at least one region located on the gate electrode film 64 side of the region between the plurality of first trench resistor structures 51A, and may not be arranged in at least one region located on the active region 6 side of the region between the plurality of first trench resistor structures 51A.

[0478] Fig.40 It is an enlarged plan view showing a gate resistor structure 50 according to a third modification. Fig.41 is a circuit diagram showing the gate terminal electrode 90, the gate wiring electrode 93, and the gate resistance structure 50. Fig.40 as well as Fig.41 In this manner, the gate resistor structure 50 includes the first trench group 52 but does not have the second trench group 53 .

[0479] In this embodiment, the space region 57 is provided on the other side (the second side surface 5B side) of the first groove group 52 in the second direction Y. That is, in this embodiment, the first covering portion 61 of the resistor film 60 is provided on the region on the second end portion 60B side of the resistor film 60, and the second covering portion 62 of the resistor film 60 is provided on the region on the first end portion 60A side of the resistor film 60.

[0480] The plurality of first resistor connection electrodes 81 are formed in the same layout as in the first embodiment. Of course, the first resistor connection electrodes 81 of the modified embodiment may also be applied. The plurality of second resistor connection electrodes 82 are formed in the same layout as in the first embodiment. Of course, any of the second resistor connection electrodes 82 of the first to third modified embodiments may also be applied. In this embodiment, the plurality of third resistor connection electrodes 83 may not be formed.

[0481] The second current I2 flowing through the second resistance connection electrode 82 is substantially equal to the first current I1 flowing through the first resistance connection electrode 81. That is, the current ratio I2 / I1 (shunt ratio) is substantially 1. In this case, the area ratio S2 / S1 of the second connection area S2 of the plurality of second resistance connection electrodes 82 relative to the first connection area S1 of the plurality of first resistance connection electrodes 81 may also be greater than 1. The area ratio S2 / S1 is preferably less than 2.

[0482] In this embodiment, the gate wiring electrode 93 includes a first connection region 101 in the first upper line portion 97, and does not have a second connection region 102. As in the above-mentioned embodiments, the first connection region 101 is electrically connected to the plurality of first resistance connection electrodes 81. Thus, the first connection region 101 is electrically connected to the second covering portion 62 of the resistance film 60 and the first trench group 52 (plurality of first trench resistance structures 51A) via the plurality of first resistance connection electrodes 81.

[0483] Thus, the first upper wiring portion 97 (gate wiring electrode 93) forms a series resistance circuit SC including the first gate resistor R1 between the first upper wiring portion 97 (gate wiring electrode 93) and the second electrode portion 92 (gate terminal electrode 90) (also refer to Fig.41 ).

[0484] In this embodiment, the gate resistor structure 50 includes the first trench group 52 but does not include the second trench group 53. However, a gate resistor structure 50 may include the second trench group 53 but does not include the first trench group 52. The specific structure in this case is obtained by replacing the structure on the first trench group 52 side with the structure on the second trench group 53 side in the above description and drawings.

[0485] In this embodiment, the gate resistor structure 50 having the space region 57 is shown. However, a gate resistor structure 50 not having the space region 57 may be used as in the first to second modified examples (see Figure 37 to Figure 39 ).

[0486] Fig.42 1 is a plan view showing a gate wiring electrode 93 according to a modified example and an emitter terminal electrode 103 according to a modified example. Fig.42 , a gate wiring electrode 93 without the second upper wiring portion 95 may be used. In this case, a single emitter terminal electrode 103 may be arranged on the interlayer insulating film 74. In this case, a plurality of active regions 6 may be provided on the first main surface 3, or a single active region 6 may be provided on the first main surface 3.

[0487] When multiple active regions 6 are provided on the first main surface 3, a single emitter terminal electrode 103 crosses the boundary region 8 in a plan view and covers the multiple active regions 6. When a single active region 6 is provided on the first main surface 3, a single emitter terminal electrode 103 covers the single active region 6 in a plan view.

[0488] In the case of a single active region 6, the scribe line region 11 is omitted. The single active region 6 is divided by a single trench isolation structure 15. The planar shape of the single active region 6 is different from the planar shape of the first active region 6A (second active region 6B), but the internal structure of the single active region 6 is the same as the internal structure of the first active region 6A (second active region 6B). The description of the internal structure of the single active region 6 can also be applied to the description of the internal structure of the first active region 6A (second active region 6B).

[0489] Fig.43 It is an enlarged plan view showing a gate connection electrode 84 according to a modification. Fig.44 is along Fig.43 The cross-sectional view along the line XLIV-XLIV is shown. Fig.43 as well as Fig.44 In this embodiment, the plurality of gate connection electrodes 84 include at least one (a plurality in this embodiment) third gate connection electrode 84C in addition to the first gate connection electrode 84A and the second gate connection electrode 84B.

[0490] The plurality of third gate connection electrodes 84C include at least one (in this embodiment, a plurality) third gate connection electrode 84CA on the second lower line portion 70A side and at least one (in this embodiment, a plurality) third gate connection electrode 84CB on the second lower line portion 70B side.

[0491] The plurality of third gate connection electrodes 84CA on one side are embedded in the portion of the interlayer insulating film 74 covering the second lower line portion 70A in the pad region 10 and are electrically connected to the second lower line portion 70A. In this embodiment, the plurality of third gate connection electrodes 84CA are formed at intervals in the second direction Y and are formed in a strip shape extending in the first direction X.

[0492] Each of the plurality of third gate connection electrodes 84CA includes a gate opposing portion 131A that is opposed to the gate electrode film 64 via the third slit 73 in the second direction Y. In this embodiment, each of the plurality of third gate connection electrodes 84CA includes a resistor opposing portion 132A that is led out from the gate opposing portion 131A to the first lower line portion 69 side (resistor film 60 side) in a manner that is opposed to the resistor film 60 in the second direction Y.

[0493] That is, the resistor opposing portion 132A is opposed to the first slit 71 in the second direction Y. In this embodiment, the resistor opposing portion 132A is formed to have a width wider than the width of the resistor film 60 in the first direction X, and has a portion located above the first lower line portion 69. That is, the resistor opposing portion 132A is opposed to the second slit 72 in the second direction Y. Thus, the resistor opposing portion 132A is opposed to the entire width of the resistor film 60 in the first direction X in the second direction Y.

[0494] Of course, the resistor opposing portion 132A may be formed offset from the first lower line portion 69 toward the second lower line portion 70A side without covering the first lower line portion 69, and opposed to a part or all of the resistor film 60 in the second direction Y. In this case, the resistor opposing portion 132A may be opposed to the second slit 72 in the second direction Y, or may not be opposed to the second slit 72 in the second direction Y.

[0495] Of course, the plurality of third gate connection electrodes 84CA may not include the resistor opposing portion 132A but only include the gate opposing portion 131A. In this case, the gate opposing portion 131A may or may not be opposed to the first slit 71 in the second direction Y.

[0496] The third gate connection electrodes 84CB on the other side are embedded in the interlayer insulating film 74 covering the second lower line portion 70B in the pad region 10 and are electrically connected to the second lower line portion 70B. In this embodiment, the third gate connection electrodes 84CB are formed at intervals in the second direction Y and are formed in a strip shape extending in the first direction X.

[0497] Each of the third gate connection electrodes 84CB has a gate opposing portion 131B that opposes the gate electrode film 64 via the third slit 73 in the second direction Y. That is, the gate opposing portion 131B opposes the gate opposing portion 131A in the second direction Y via the gate electrode film 64 .

[0498] In this embodiment, each of the plurality of third gate connection electrodes 84CB includes a resistor opposing portion 132B, which is led out from the gate opposing portion 131B to the first lower line portion 69 side (resistance film 60 side) in a manner opposing the resistance film 60 in the second direction Y. That is, the resistor opposing portion 132B is opposed to the first slit 71 in the second direction Y. In addition, the resistor opposing portion 132B is opposed to the resistor opposing portion 132A in the second direction Y via the resistance film 60 and the first slit 71.

[0499] In this embodiment, the resistor opposing portion 132B is formed to have a width wider than the width of the resistor film 60 in the first direction X and has a portion located above the first lower line portion 69. That is, the resistor opposing portion 132B is opposed to the second slit 72 in the second direction Y. Thus, the resistor opposing portion 132B is opposed to the entire width of the resistor film 60 in the first direction X in the second direction Y.

[0500] Of course, the resistor opposing portion 132B may be formed offset from the first lower line portion 69 toward the second lower line portion 70B side in a manner not to cover the first lower line portion 69, and may be opposed to a part or the entirety of the resistor film 60 in the second direction Y. In this case, the resistor opposing portion 132B may be opposed to the second slit 72 in the second direction Y, or may not be opposed to the second slit 72 in the second direction Y.

[0501] Of course, the plurality of third gate connection electrodes 84CB may not include the resistor opposing portion 132B but only include the gate opposing portion 131B. In this case, the gate opposing portion 131B may or may not be opposed to the first slit 71 in the second direction Y.

[0502] The second upper line portion 98A covers a plurality of third gate connection electrodes 84CA and is electrically connected to the second lower line portion 70A via the third gate connection electrodes 84CA. The second upper line portion 98B covers a plurality of third gate connection electrodes 84CB and is electrically connected to the second lower line portion 70B via the third gate connection electrodes 84CB.

[0503] The above-mentioned embodiments and modifications can also be implemented in other embodiments. For example, in the above-mentioned embodiments, an example is shown in which the chip 2 is composed of a silicon single crystal substrate. However, the chip 2 can also be composed of a SiC (silicon carbide) single crystal substrate.

[0504] In each of the above-mentioned embodiments, the n-type semiconductor region may be replaced by a p-type semiconductor region, and the p-type semiconductor region may be replaced by an n-type semiconductor region. The specific structure in this case is obtained by replacing "n-type" with "p-type" and replacing "p-type" with "n-type" in the above-mentioned description and drawings.

[0505] In the above-mentioned embodiment, a p-type collector region 14 is shown. However, an n-type drain region may be used instead of the p-type collector region 14. In this case, the buffer region 13 is omitted. The n-type drain region may also be formed by an n-type semiconductor substrate, and the n-type drift region 12 may also be formed by an n-type epitaxial layer. The n-type impurity concentration of the drift region 12 is preferably smaller than the n-type impurity concentration of the drain region.

[0506] In this case, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) structure is formed instead of the IGBT. The specific structure in this case is obtained by replacing the "emitter" with the "source" and the "collector" with the "drain" in the above description.

[0507] In each of the above-mentioned embodiments, the first direction X and the second direction Y are defined by the extension direction of the first to fourth side surfaces 5A to 5D. However, the first direction X and the second direction Y may be any direction as long as they maintain a mutually intersecting (specifically, orthogonal) relationship. For example, the first direction X may be the extension direction of the third side surface 5C (fourth side surface 5D), and the second direction Y may be the extension direction of the first side surface 5A (second side surface 5B). In addition, the first direction X may be a direction intersecting the first to fourth side surfaces 5A to 5D, and the second direction Y may be a direction intersecting the first to fourth side surfaces 5A to 5D.

[0508] The following are examples of features extracted from the specification and the accompanying drawings. In the following, numbers, etc. indicate corresponding components in the above-mentioned methods, etc., but are not intended to limit the scope of each clause to the method. The "semiconductor device" in the following items can also be replaced by a "semiconductor switching device", "IGBT semiconductor device", "RC-IGBT semiconductor device" or "MISFET semiconductor device".

[0509] [A1] A semiconductor device 1A, 1B, or 1C, comprising:

[0510] A chip 2 having a main surface 3: a trench resistor structure 51, 51A, 51B formed on the main surface 3; a resistor film 60 electrically connected to the trench resistor structure 51, 51A, 51B on the main surface 3; a gate terminal electrode 90 having a lower resistance value than the resistor film 60, and electrically connected to the trench resistor structure 51, 51A, 51B on the main surface 3 via the resistor film 60; and a gate wiring electrode 93 having a lower resistance value than the resistor film 60, and electrically connected to the gate terminal electrode 90 on the main surface 3 via the resistor film 60 and the trench resistor structure 51, 51A, 51B.

[0511] [A2] The semiconductor device 1A, 1B, or 1C according to A1, further comprising:

[0512] A gate electrode film 64 is arranged on the main surface 3 adjacent to the resistor film 60; and a gate wiring film 65 is arranged on the main surface 3 adjacent to the resistor film 60 in a manner opposite to the gate electrode film 64 with the resistor film 60 interposed therebetween, the gate terminal electrode 90 covers the gate electrode film 64, and the gate wiring electrode 93 covers the gate wiring film 65.

[0513] [A3] The semiconductor devices 1A, 1B, and 1C according to A2,

[0514] The resistor film 60 has a first end 60A on one side and a second end 60B on the other side, and the gate wiring film 65 has a first connection portion 70A connected to the first end 60A of the resistor film 60 and a second connection portion 70B connected to the second end 60B of the resistor film 60 .

[0515] [A4] The semiconductor device 1A, 1B, or 1C according to A2 or A3, further comprising:

[0516] The first slit 71 defines between the resistor film 60 and the gate electrode film 64 , and the second slit 72 defines between the resistor film 60 and the gate wiring film 65 .

[0517] [A5] The semiconductor devices 1A, 1B, and 1C according to A4,

[0518] The gate terminal electrode 90 crosses the first slit 71 and covers the resistor film 60 and the gate electrode film 64 in a plan view.

[0519] [A6] The semiconductor device 1A, 1B, or 1C according to A4 or A5,

[0520] The gate wiring film 65 crosses the second slit 72 and covers the resistor film 60 and the gate electrode film 64 in a plan view.

[0521] [A7] A semiconductor device 1A, 1B, or 1C according to any one of A4 to A6,

[0522] The first slit 71 is formed to have a narrower width than the resistance film 60 , and the second slit 72 is formed to have a narrower width than the resistance film 60 .

[0523] [A8] The semiconductor device 1A, 1B, or 1C according to any one of A4 to A7,

[0524] The above-mentioned groove resistor structures 51, 51A, and 51B extend in a band shape in one direction Y when viewed from above, the above-mentioned resistor film 60 extends in a band shape in the above-mentioned direction Y when viewed from above, the above-mentioned first slit 71 extends in a band shape in the above-mentioned direction Y when viewed from above, and the above-mentioned second slit 72 extends in a band shape in the above-mentioned direction Y when viewed from above.

[0525] [A9] The semiconductor devices 1A, 1B, and 1C according to A8,

[0526] The first slit 71 has a first length in the one direction Y, and the second slit 72 has a second length in the one direction Y that is smaller than the first length.

[0527] [A10] A semiconductor device 1A, 1B, or 1C according to any one of A3 to A9,

[0528] The third slit 73 is further included, and the third slit 73 is defined between the gate electrode film 64 and the gate wiring film 65 .

[0529] [A11] The semiconductor devices 1A, 1B, and 1C according to A10,

[0530] The gate terminal electrode 90 crosses the third slit 73 and covers the gate electrode film 64 and the gate wiring film 65 in a plan view.

[0531] [A12] A semiconductor device 1A, 1B, or 1C according to any one of A1 to A11,

[0532] The plurality of trench resistor structures 51 , 51A, and 51B are formed at intervals on the main surface 3 , and the resistor film 60 covers the plurality of trench resistor structures 51 , 51A, and 51B.

[0533] [A13] The semiconductor device 1A, 1B, or 1C according to any one of A1 to A12,

[0534] The above-mentioned resistor film 60 has a first covering portion 61 covering the above-mentioned main surface 3 outside the above-mentioned groove resistor structure 51, 51A, 51B, and a second covering portion 62, 63 covering the above-mentioned groove resistor structure 51, 51A, 51B, the above-mentioned gate terminal electrode 90 is electrically connected to the above-mentioned resistor film 60 in the portion covering the above-mentioned first covering portion 61, and the above-mentioned gate wiring electrode 93 is electrically connected to the above-mentioned resistor film 60 in the portion covering the above-mentioned second covering portion 62, 63.

[0535] [A14] A semiconductor device 1A, 1B, or 1C according to any one of A1 to A13,

[0536] It also includes: an interlayer insulating film 74, which covers the above-mentioned resistor film 60; a first connecting electrode 81, which is buried in the above-mentioned interlayer insulating film 74 in a manner electrically connected to the above-mentioned resistor film 60; and second connecting electrodes 82, 83, which are buried in the above-mentioned interlayer insulating film 74 in a manner electrically connected to the above-mentioned resistor film 60 at a position different from the above-mentioned first connecting electrode 81. The above-mentioned gate terminal electrode 90 is arranged on the above-mentioned interlayer insulating film 74 in a manner electrically connected to the above-mentioned resistor film 60 via the above-mentioned first connecting electrode 81, and the above-mentioned gate wiring electrode 93 is arranged on the above-mentioned interlayer insulating film 74 in a manner electrically connected to the above-mentioned resistor film 60 via the above-mentioned second connecting electrodes 82, 83.

[0537] [A15] The semiconductor devices 1A, 1B, and 1C according to A14,

[0538] The second connection electrodes 82 and 83 extend in a direction different from that of the first connection electrode 81 .

[0539] [A16] The semiconductor device 1A, 1B, or 1C according to A14 or A15,

[0540] The plurality of first connection electrodes 81 are buried in the interlayer insulating film 74 , and the plurality of second connection electrodes 82 and 83 are buried in the interlayer insulating film 74 .

[0541] [A17] A semiconductor device 1A, 1B, or 1C according to any one of A14 to A16,

[0542] A connection area of ​​the second connection electrodes 82 and 83 to the resistance film 60 is different from a connection area of ​​the first connection electrode 81 to the resistance film 60 .

[0543] [A18] A semiconductor device 1A, 1B, or 1C according to any one of A14 to A17,

[0544] The gate terminal electrode 90 includes a first electrode portion 91 located outside the first connection electrode 81 in a plan view, and a second electrode portion 92 protruding from the first electrode portion 91 toward the first connection electrode 81 with a width narrower than that of the first electrode portion 91 .

[0545] [A19] A semiconductor device 1A, 1B, or 1C according to any one of A1 to A18,

[0546] A p-type well region 40 is formed on the surface of the main surface 3 , and the trench resistor structures 51 , 51A, and 51B are formed with a gap from the bottom of the well region 40 toward the main surface 3 so as to be located in the well region 40 .

[0547] [A20] A semiconductor device 1A, 1B, or 1C according to any one of A1 to A19,

[0548] It also includes: active areas 6, 6A, 6B, which are arranged on the above-mentioned main surface 3; inactive areas 7, which are arranged outside the active areas 6, 6A, 6B in the above-mentioned main surface 3; and groove structures 15, 21, which are formed in the above-mentioned active areas 6, 6A, 6B, the above-mentioned groove resistance structures 51, 51A, 51B are formed in the above-mentioned inactive area 7, the above-mentioned resistance film 60 covers the above-mentioned groove resistance structures 51, 51A, 51B in the above-mentioned inactive area 7, the above-mentioned gate terminal electrode 90 is electrically connected to the above-mentioned resistance film 60 in the above-mentioned inactive area 7, and the above-mentioned gate wiring electrode 93 is electrically connected to the above-mentioned groove structures 15, 21 in the above-mentioned active areas 6, 6A, 6B, and is electrically connected to the above-mentioned resistance film 60 in the above-mentioned inactive area 7.

[0549] [B1] A semiconductor device 1A, 1B, or 1C, comprising:

[0550] A chip 2, which has a main surface 3; a trench resistor structure 51, 51A, 51B, which is formed on the above-mentioned main surface 3; a gate terminal electrode 90, which has a lower resistance value than the above-mentioned trench resistor structure 51, 51A, 51B, and is electrically connected to the above-mentioned trench resistor structure 51, 51A, 51B on the above-mentioned main surface 3; and a gate wiring electrode 93, which has a lower resistance value than the above-mentioned trench resistor structure 51, 51A, 51B, and is electrically connected to the above-mentioned gate terminal electrode 90 via the above-mentioned trench resistor structure 51, 51A, 51B on the above-mentioned main surface 3.

[0551] [C1] A semiconductor device 1A, 1B, or 1C, comprising:

[0552] A chip 2, which has a main surface 3; a resistor film 60, which is formed on the above-mentioned main surface 3; a gate terminal electrode 90, which has a lower resistance value than the above-mentioned resistor film 60 and is electrically connected to the above-mentioned resistor film 60 on the above-mentioned main surface 3; and a gate wiring electrode 93, which has a lower resistance value than the above-mentioned resistor film 60 and is electrically connected to the above-mentioned gate terminal electrode 90 via the above-mentioned resistor film 60 on the above-mentioned main surface 3.

[0553] Although specific embodiments have been described in detail above, these are only specific examples to clarify the technical contents. Various technical ideas extracted from this specification are not limited by the order of description in the specification, the order of embodiment examples, etc., and can be appropriately combined between them.

[0554] Explanation of symbols

[0555] 1A—semiconductor device, 1B—semiconductor device, 1C—semiconductor device, 2—chip, 3—first main surface, 6—active region, 6A—first active region, 6B—second active region, 7—inactive region, 15—trench isolation structure, 15A—first trench isolation structure, 15B—second trench isolation structure, 21—first trench structure, 40—boundary well region, 51—trench resistor structure, 51A—first trench resistor structure, 51B—second trench resistor structure, 60—resistance film, 60A—first end portion of the resistance film, 60B—second end portion of the resistance film, 61—first covering portion of the resistance film , 62—the second covering portion of the resistor film, 63—the second covering portion of the resistor film, 64—the gate electrode film, 65—the gate wiring film, 70A—the second lower line portion (the first connecting portion) on one side, 70B—the second lower line portion (the second connecting portion) on the other side, 71—the first slit, 72—the second slit, 73—the third slit, 74—the interlayer insulating film, 81—the first resistor connecting electrode, 82—the second resistor connecting electrode, 83—the third resistor connecting electrode, 90—the gate terminal electrode, 91—the first electrode portion, 92—the second electrode portion, 93—the gate wiring electrode, X—the first direction, Y—the second direction.

Claims

1. A semiconductor device, characterized in that: include: A chip having a main surface; A trench resistor structure formed on the main surface; a resistor film electrically connected to the trench resistor structure on the main surface; a gate terminal electrode having a lower resistance value than the resistance film and electrically connected to the trench resistance structure via the resistance film on the main surface; as well as A gate wiring electrode has a lower resistance value than the resistance film and is electrically connected to the gate terminal electrode via the resistance film and the trench resistance structure on the main surface.

2. The semiconductor device according to claim 1, wherein: Also includes: a gate electrode film disposed on the main surface adjacent to the resistor film; as well as a gate wiring film disposed on the main surface adjacent to the resistive film so as to face the gate electrode film with the resistive film interposed therebetween, The gate terminal electrode covers the gate electrode film. The gate wiring electrode covers the gate wiring film.

3. The semiconductor device according to claim 2, wherein: The resistive film has a first end on one side and a second end on the other side. The gate wiring film includes a first connection portion connected to the first end portion of the resistance film and a second connection portion connected to the second end portion of the resistance film.

4. The semiconductor device according to claim 2 or 3, characterized in that Also includes: A first slit defined between the resistor film and the gate electrode film; and The second slit is defined between the resistance film and the gate wiring film.

5. The semiconductor device according to claim 4, wherein: The gate terminal electrode crosses the first slit and covers the resistor film and the gate electrode film in a plan view.

6. The semiconductor device according to claim 4 or 5, characterized in that: The gate wiring film crosses the second slit and covers the resistor film and the gate electrode film in a plan view.

7. The semiconductor device according to any one of claims 4 to 6, characterized in that The first slit is formed to have a width narrower than that of the resistive film. The second slit is formed to have a narrower width than the resistive film.

8. The semiconductor device according to any one of claims 4 to 7, wherein: The trench resistor structure extends in a strip shape in one direction when viewed from above. The resistive film extends in a strip shape in the one direction when viewed from above. The first slit extends in a strip shape in the one direction when viewed from above. The second slit extends in a strip shape in the one direction in a plan view.

9. The semiconductor device according to claim 8, wherein: The first slit has a first length in the one direction. The second slit has a second length in the one direction that is smaller than the first length.

10. The semiconductor device according to any one of claims 3 to 9, wherein: The invention further includes a third slit defining a portion between the gate electrode film and the gate wiring film.

11. The semiconductor device according to claim 10, wherein: The gate terminal electrode crosses the third slit and covers the gate electrode film and the gate wiring film in a plan view.

12. The semiconductor device according to any one of claims 1 to 11, characterized in that A plurality of the trench resistor structures are formed on the main surface at intervals. The resistor film covers the plurality of trench resistor structures.

13. The semiconductor device according to any one of claims 1 to 12, wherein: The resistor film includes a first covering portion covering the main surface outside the trench resistor structure, and a second covering portion covering the trench resistor structure. The gate terminal electrode is electrically connected to the resistance film in a portion covering the first covering portion. The gate wiring electrode is electrically connected to the resistance film in a portion covering the second covering portion.

14. The semiconductor device according to any one of claims 1 to 13, wherein: Also includes: an interlayer insulating film covering the resistor film; a first connection electrode embedded in the interlayer insulating film so as to be electrically connected to the resistance film; and a second connection electrode embedded in the interlayer insulating film at a position different from that of the first connection electrode so as to be electrically connected to the resistance film; The gate terminal electrode is arranged on the interlayer insulating film so as to be electrically connected to the resistance film via the first connection electrode. The gate wiring electrode is arranged on the interlayer insulating film so as to be electrically connected to the resistance film via the second connection electrode.

15. The semiconductor device according to claim 14, wherein: The second connection electrode extends in a direction different from that of the first connection electrode.

16. The semiconductor device according to claim 14 or 15, characterized in that: The plurality of first connection electrodes are embedded in the interlayer insulating film. The plurality of second connection electrodes are embedded in the interlayer insulating film.

17. The semiconductor device according to any one of claims 14 to 16, characterized in that A connection area of ​​the second connection electrode with respect to the resistance film is different from a connection area of ​​the first connection electrode with respect to the resistance film.

18. The semiconductor device according to any one of claims 14 to 17, wherein: The gate terminal electrode has: A first electrode portion, which is located outside the first connecting electrode when viewed from above; and The second electrode portion protrudes from the first electrode portion toward the first connecting electrode with a width narrower than that of the first electrode portion.

19. The semiconductor device according to any one of claims 1 to 18, wherein: further comprising a p-type well region formed in a surface portion of the main surface, The trench resistor structure is formed with a gap from a bottom of the well region toward the main surface so as to be located in the well region.

20. The semiconductor device according to any one of claims 1 to 19, wherein: Also includes: an active region disposed on the main surface; an inactive region disposed outside the active region in the main surface; and A trench structure is formed in the active region. The trench resistor structure is formed in the inactive region. The resistor film covers the trench resistor structure in the inactive region. The gate terminal electrode is electrically connected to the resistance film in the inactive region. The gate wiring electrode is electrically connected to the trench structure in the active region, and is electrically connected to the resistance film in the inactive region.

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