Semiconductor devices with embedded quantum dots and related methods

Abstract

A semiconductor device may include at least one semiconductor layer including a superlattice therein. The superlattice may include a plurality of stacked sets of layers, where each set of layers includes a stacked base semiconductor monolayer defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a lattice of an adjacent base semiconductor portion. The semiconductor device may also include quantum dots spaced apart over the superlattice in the at least one semiconductor layer, and the quantum dots include a different semiconductor material than the semiconductor layer.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor devices and, more particularly, to semiconductor quantum devices and related methods. Background Art

[0002] Various structures and techniques have been proposed to enhance the performance of semiconductor devices, such as by increasing the mobility of charge carriers. For example, U.S. Patent Application No. 2003 / 0057416 to Currie et al. discloses a strained material layer having silicon, silicon germanium, and relaxed silicon, and also includes an impurity-free region without which performance degradation may occur. The biaxial strain produced in the upper silicon layer changes the charge carrier mobility, thereby achieving a higher speed and / or lower power device. Published U.S. Patent Application No. 2003 / 0034529 to Fitzgerald et al. discloses a CMOS inverter also based on similar strained silicon technology.

[0003] Takagi's U.S. Patent No. 6,472,685 B2 discloses a semiconductor device including silicon and carbon layers sandwiched between silicon layers, so that the conduction band and the valence band of the second silicon layer are subjected to tensile strain. Electrons have a smaller effective mass and are induced by an electric field applied to a gate electrode, such electrons are confined in the second silicon layer, and therefore, an n-channel MOSFET is identified to have a higher mobility.

[0004] Ishibashi et al., US Pat. No. 4,937,204 discloses a superlattice in which multiple layers less than 8 monolayers and including fractional or binary or binary compound semiconductor layers are alternately epitaxially grown. The direction of main current flow is perpendicular to the layers of the superlattice.

[0005] U.S. Patent No. 5,357,119 to Wang et al. discloses a Si-Ge short period superlattice with higher mobility, which is achieved by reducing alloy scattering in the superlattice. Along these lines, U.S. Patent No. 5,683,934 to Candelaria discloses an enhanced mobility MOSFET including a channel layer comprising an alloy of silicon and a second material, the second material being alternately present in the silicon lattice in a percentage such that the channel layer is under tensile stress.

[0006] Tsu's U.S. Patent No. 5,216,262 discloses a quantum well structure comprising two barrier regions and an epitaxially grown thin semiconductor layer sandwiched between the barriers. Each barrier region consists of alternating SiO2 / Si layers with a thickness typically in the range of 2 to 6 monolayers. Much thicker silicon portions are sandwiched between the barriers.

[0007] On September 6, 2000, a paper entitled "Phenomena in silicon nanostructure devices" also belonging to Tsu and published online in Applied Physics and Materials Science & Processing, pp. 391-402, disclosed a semiconductor atomic superlattice (SAS) of silicon and oxygen. It is disclosed that the Si / O superlattice can be used in silicon quantum and light-emitting devices. In particular, a green electroluminescent diode structure was constructed and tested. The current flow in the diode structure is vertical, that is, perpendicular to the layers of the SAS. The disclosed SAS can include semiconductor layers separated by adsorbed substances such as oxygen atoms and CO molecules. The silicon growth beyond the adsorbed oxygen monolayer is described as epitaxial growth with a relatively low defect density. One SAS structure includes a 1.1nm thick silicon portion of about 8 silicon atomic layers, and another structure has silicon twice that thickness. Luo et al. further discussed Tsu's light-emitting SAS structure in a paper entitled "Chemical Design of Direct-Gap Light-Emitting Silicon" published in Physical Review Letters, Vol. 89, No. 7 (August 12, 2002).

[0008] Wang et al., U.S. Patent No. 7,105,895 discloses a barrier building block having thin silicon and oxygen, carbon, nitrogen, phosphorus, antimony, arsenic or hydrogen to reduce the vertical current flowing through the lattice by more than four orders of magnitude. The insulating layer / barrier layer allows low-defect epitaxial silicon to be deposited next to the insulating layer.

[0009] Published British patent application 2,347,520 to Mears et al. discloses that the principles of aperiodic photonic bandgap (APBG) structures can be adapted for electronic bandgap engineering. In particular, the application discloses that material parameters, such as the location of band minima, effective mass, etc., can be adjusted to produce new aperiodic materials with desired band structure properties. It is disclosed that other parameters, such as electrical conductivity, thermal conductivity, and dielectric constant or magnetic permeability, can also be engineered into the material.

[0010] In addition, U.S. Pat. No. 6,376,337 to Wang et al. discloses a method for producing an insulating layer or barrier layer of a semiconductor device, the method comprising depositing a layer of silicon and at least one additional element on a silicon substrate, whereby the deposited layer is substantially free of defects, so that substantially defect-free epitaxial silicon can be deposited on the deposited layer. Alternatively, a monolayer is adsorbed on the silicon substrate, the monolayer having one or more elements, preferably including oxygen. Multiple insulating layers sandwiched between the epitaxial silicon form a barrier composite.

[0011] Despite these approaches, further enhancements can be expected to be achieved using advanced semiconductor materials and processing techniques to increase the performance of semiconductor devices. Summary of the invention

[0012] A semiconductor device may include at least one semiconductor layer including a superlattice. The superlattice may include a plurality of stacked layer groups, wherein each layer group includes a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a lattice of an adjacent base semiconductor portion. The semiconductor device may also include a plurality of quantum dots spaced above the superlattice in the at least one semiconductor layer and including a semiconductor material different from the semiconductor layer.

[0013] In example embodiments, the at least one semiconductor layer may include a semiconductor substrate and an epitaxial semiconductor layer on the substrate, the superlattice may be within the epitaxial semiconductor layer, and the quantum dots may be within the epitaxial semiconductor layer and above the superlattice. In some embodiments, the semiconductor substrate and the epitaxial semiconductor layer may include silicon, and the epitaxial semiconductor layer may have a higher percentage of silicon 28 than the semiconductor substrate. 28 For example, the quantum dots may include germanium, gallium arsenide, etc.

[0014] In an example implementation, the semiconductor device may further include a source region and a drain region spaced apart in the epitaxial semiconductor layer defining a channel region therebetween, and a gate on the epitaxial semiconductor layer above the channel region. For example, the gate may include at least one accumulation gate, at least one plug gate, and / or at least one barrier gate. Also for example, the at least one non-semiconductor may include oxygen.

[0015] A method of manufacturing a semiconductor device may include forming at least one semiconductor layer including a superlattice. The superlattice may include a plurality of stacked layer groups, wherein each layer group includes a plurality of stacked base semiconductor monolayers defining a base semiconductor portion and at least one non-semiconductor monolayer constrained within a lattice of an adjacent base semiconductor portion. The method may also include forming a plurality of quantum dots spaced apart above the superlattice in the at least one semiconductor layer and including a semiconductor material different from the semiconductor layer.

[0016] In example embodiments, forming the at least one semiconductor layer may include forming an epitaxial semiconductor layer including a superlattice on a substrate, and the quantum dots may be within the epitaxial semiconductor layer and above the superlattice. In some embodiments, the semiconductor substrate and the epitaxial semiconductor layer may include silicon, and the epitaxial semiconductor layer may have a higher percentage of silicon 28 than the semiconductor substrate. 28 For example, the quantum dots may include germanium, gallium arsenide, etc.

[0017] In an example implementation, the method may further include forming a source region and a drain region spaced apart in the epitaxial semiconductor layer defining a channel region therebetween, and forming a gate on the epitaxial semiconductor layer above the channel region. For example, the gate may include at least one accumulation gate, at least one plug gate, and / or at least one barrier gate. Also for example, the at least one non-semiconductor may include oxygen. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 is a greatly enlarged schematic cross-sectional view of a superlattice for a semiconductor device according to example embodiments.

[0019] Figure 2 yes Figure 1 A perspective schematic atomic diagram of a portion of the superlattice shown in FIG.

[0020] Figure 3 is a greatly enlarged schematic cross-sectional view of another embodiment of a superlattice according to an example embodiment.

[0021] Figure 4A For bulk silicon as in the prior art and for Figure 1-2 The band structure diagram of the 4 / 1Si / O superlattice calculated from the γ point (G) is shown in FIG.

[0022] Figure 4B For bulk silicon as in the prior art and for Figure 1-2 The band structure diagram of the 4 / 1Si / O superlattice calculated from the Z point is shown in FIG.

[0023] Figure 4C For bulk silicon as in the prior art and for Figure 3 The band structure diagram of the 5 / 1 / 3 / 1 Si / O superlattice shown in FIG. 1 is calculated from both the γ point and the Z point.

[0024] Figure 5 is a cross-sectional view of a semiconductor device including embedded quantum dots in an epitaxial layer having a superlattice according to example embodiments.

[0025] Figure 6 yes Figure 5A partial view of a semiconductor device showing electron volt (eV) levels associated with different portions thereof.

[0026] Figure 7A to Figure 7F is a series of cross-sectional views illustrating an example method for fabricating embedded quantum dots in an epitaxial layer having a superlattice therein in an example embodiment.

[0027] Figure 8A to Figure 8F is a series of cross-sectional views illustrating another example method for fabricating embedded quantum dots in an epitaxial layer having a superlattice therein in an example embodiment. DETAILED DESCRIPTION

[0028] Example embodiments will now be described more fully hereinafter with reference to the accompanying drawings in which example embodiments are shown. However, embodiments may be implemented in many different forms and should not be construed as being limited to the specific examples described herein. Instead, these embodiments are provided so that this disclosure will be thorough and complete. The same reference numerals always refer to the same elements, and in different embodiments, primes are used to indicate similar elements.

[0029] In general, the present disclosure relates to semiconductor devices having an enhanced semiconductor superlattice therein to provide performance enhancing characteristics. In the present disclosure, the enhanced semiconductor superlattice may also be referred to as an "MST" layer or "MST technology."

[0030] More particularly, the MST technique involves advanced semiconductor materials, such as superlattices 25, described further below. Applicants theorize, but do not wish to be bound by this, that certain superlattices as described herein reduce the effective mass of charge carriers, and that this thereby results in higher charge carrier mobility. Effective mass is variously defined in the literature. As a measure of improvement in effective mass, Applicants use the "conductivity reciprocal effective mass tensor" for electrons and holes, respectively. and

[0031] For electrons, it is defined as:

[0032]

[0033] And for holes, it is defined as:

[0034]

[0035] where f is the Fermi-Dirac distribution, E Fis the Fermi energy, T is the temperature, E(k,n) is the energy of an electron in the state corresponding to wave vector k and the nth energy band, the indices i and j refer to the Cartesian coordinates x, y and z, the integration is performed over the Brillouin zone (BZ) and the summation is performed over energy bands above and below the Fermi energy for electrons and holes, respectively.

[0036] Applicants define the conductivity reciprocal effective mass tensor such that for larger values ​​of corresponding components of the conductivity reciprocal effective mass tensor, the tensor component of the conductivity of the material is larger. Again, Applicants theoretically believe, but do not wish to be bound by this, that the superlattice described herein sets the value of the conductivity reciprocal effective mass tensor so as to enhance the conductive properties of the material, such as typically with respect to the preferred direction of charge carrier transport. The reciprocal of the appropriate tensor element is called the conductivity effective mass. In other words, for the purpose of characterizing semiconductor material structures, the conductivity effective mass of electrons / holes, as described above and calculated in the direction of expected carrier transport, is used to distinguish improved materials.

[0037] Applicants have identified improved materials or structures for semiconductor devices. More specifically, Applicants have identified materials or structures having band structures for which the appropriate conductivity effective masses for electrons and / or holes are substantially lower than the corresponding values ​​for silicon. In addition to the enhanced mobility characteristics of these structures, they may also be formed or used in such a manner that they provide piezoelectric, pyroelectric, and / or ferroelectric properties that are beneficial for use in a variety of different types of devices, as further described below.

[0038] Reference now Figure 1 and Figure 2 The material or structure is in the form of a superlattice 25 whose structure is controlled at the atomic or molecular level and can be formed using known atomic or molecular layer deposition techniques. The superlattice 25 includes a plurality of layer groups 45a-45n arranged in a stacked relationship, perhaps with specific reference to Figure 1 This can be best understood by way of a schematic cross-sectional view of the FIG.

[0039] Each layer group 45a-45n of the superlattice 25 illustratively includes a plurality of stacked base semiconductor single layers 46 defining corresponding base semiconductor portions 46a-46n and an energy band modification layer 50 thereon. For clarity of illustration, the energy band modification layer 50 is shown in FIG. Figure 1 It is represented by dots and strokes.

[0040] The energy band modifying layer 50 illustratively comprises a non-semiconductor monolayer constrained within the crystal lattice of an adjacent base semiconductor portion. Figure 2As shown in , "confined within the crystal lattice of adjacent base semiconductor portions" means that at least some of the semiconductor atoms from the opposing base semiconductor portions 46a-46n are chemically bonded together by the non-semiconductor monolayer 50 therebetween. Generally, such formation is made possible by controlling the amount of non-semiconductor material deposited on the semiconductor portions 46a-46n by atomic layer deposition techniques so that not all available semiconductor bonding sites are filled with bonds to non-semiconductor atoms (i.e., less than full or 100% coverage), as further described below. Thus, when an additional monolayer 46 of semiconductor material is deposited on or over the non-semiconductor monolayer 50, the newly deposited semiconductor atoms will fill the remaining empty bonding sites of the semiconductor atoms below the non-semiconductor monolayer.

[0041] In other embodiments, more than one such non-semiconductor monolayer is possible. It should be noted that references herein to non-semiconductor or semiconductor monolayers mean that the material used for the monolayer would be a non-semiconductor or semiconductor if formed in bulk. That is, as will be appreciated by those skilled in the art, a single monolayer of a material such as silicon may not necessarily exhibit the same properties as would be exhibited if formed in bulk or in a relatively thick layer.

[0042] Applicants have theorized, but do not wish to be bound by it, that the band modifying layer 50 and adjacent base semiconductor portions 46a-46n cause the superlattice 25 to have a suitable conductive effective mass for charge carriers in a direction parallel to the layers that is lower than the conductive effective mass that would otherwise exist. Considered from another perspective, the parallel direction is orthogonal to the stacking direction. The band modifying layer 50 can also provide the superlattice 25 with a common band structure while also advantageously acting as an insulator between layers or regions vertically above and below the superlattice.

[0043] In addition, such a superlattice structure can also advantageously act as a barrier to diffusion of dopants and / or materials between layers vertically above and below the superlattice 25. Therefore, it will be appreciated by those skilled in the art that these properties can advantageously allow the superlattice 25 to provide an interface for the high-K dielectric, which not only reduces diffusion of high-K materials into the channel region, but can also advantageously reduce undesirable scattering effects and improve device mobility.

[0044] It is also theorized that semiconductor devices including superlattice 25 may enjoy higher charge carrier mobility based on lower conductivity effective mass than would otherwise be present. In some embodiments, and as a result of the band engineering achieved by the present invention, superlattice 25 may also have a substantially direct band gap that may be particularly advantageous, for example, for optoelectronic devices.

[0045] The superlattice 25 further illustratively includes a capping layer 52 on the upper layer group 45n. The capping layer 52 may include a plurality of base semiconductor monolayers 46. The capping layer 52 may have 2 to 100 base semiconductor monolayers, more preferably 10 to 50 monolayers.

[0046] Each base semiconductor portion 46a-46n may include a base semiconductor selected from a group IV semiconductor, a group III-V semiconductor, and a group II-VI semiconductor. Of course, those skilled in the art will appreciate that the term group IV semiconductor also includes group IV-IV semiconductors. More specifically, for example, the base semiconductor may include at least one of silicon and germanium.

[0047] For example, each band modification layer 50 may include a non-semiconductor selected from oxygen, nitrogen, fluorine, carbon and carbon-oxygen. The non-semiconductor is also expected to be thermally stable during the deposition process of the next layer, so as to facilitate manufacturing. In other embodiments, those skilled in the art will appreciate that the non-semiconductor can be other inorganic or organic elements or compounds compatible with a given semiconductor process. More specifically, for example, the base semiconductor can include at least one of silicon and germanium.

[0048] It should be noted that the term monolayer is meant to include a single atomic layer as well as a single molecular layer. It should also be noted that the band-modifying layer 50 provided by a single monolayer is also meant to include a monolayer in which not all possible sites are occupied (i.e., there is less than full or 100% coverage). For example, with particular reference to Figure 2 Atomic diagram of a semiconductor material, showing a 4 / 1 repeating structure for silicon as the base semiconductor material and oxygen as the band modifier. In the example shown in the diagram, only half of the possible sites for oxygen are occupied.

[0049] In other embodiments and / or when different materials are used, one skilled in the art will appreciate that this one-half occupancy is not necessarily the case. One skilled in the art of atomic deposition will also appreciate that, in fact, even in this schematic diagram, the individual atoms of oxygen in a given monolayer are not precisely arranged along a flat plane. For example, a preferred occupancy range is about one-eighth to one-half of the possible oxygen sites being filled, although other numbers may be used in certain embodiments.

[0050] Silicon and oxygen are currently widely used in conventional semiconductor processes, so manufacturers will be able to easily use these materials described herein. Atomic deposition or monolayer deposition is also now widely used. Thus, those skilled in the art will appreciate that semiconductor devices incorporating superlattices 25 according to the present invention can be easily adopted and implemented.

[0051] Theoretically, but the applicant does not wish to be bound by this, for a superlattice, such as a Si / O superlattice, the number of silicon monolayers should desirably be 7 or less so that the energy bands of the superlattice are common or relatively uniform as a whole to achieve the desired advantages. For Si / O, Figure 1 and Figure 2 The 4 / 1 repeating structure shown in has been modeled to indicate the enhanced mobility of electrons and holes in the X direction. For example, the conductivity effective mass of the electrons (isotropic for bulk silicon) is calculated to be 0.26, and for the 4 / 1 SiO superlattice it is 0.12 in the X direction, resulting in a ratio of 0.46. Similarly, the calculations for holes yield a value of 0.36 for bulk silicon and 0.16 for the 4 / 1 Si / O superlattice, resulting in a ratio of 0.44.

[0052] While this directionally preferred feature may be desirable in certain semiconductor devices, other devices may benefit from a more uniform increase in mobility in any direction parallel to the layer group. Those skilled in the art will appreciate that it may also be beneficial to have increased mobility for both electrons and holes or just one of these types of charge carriers.

[0053] The lower conductivity effective mass of the 4 / 1 Si / O embodiment of the superlattice 25 may be less than two-thirds of the conductivity effective mass that would otherwise occur, and this applies to both electrons and holes. Of course, those skilled in the art will appreciate that the superlattice 25 may also include at least one type of conductivity dopant therein.

[0054] In fact, now refer to Figure 3 , another embodiment of a superlattice 25' according to the present invention having different properties is now described. In this embodiment, a repeating pattern of 3 / 1 / 5 / 1 is shown. More particularly, the lowest base semiconductor portion 46a' has 3 monolayers, while the second lowest base semiconductor portion 46b' has 5 monolayers. This pattern is repeated throughout the superlattice 25'. The band modifying layers 50' can each include a single monolayer. For such a superlattice 25' comprising Si / O, the enhancement of charge carrier mobility is independent of the orientation in the plane of the layers. Figure 3 Those other elements not specifically mentioned in the Figure 1 those elements discussed, and need not be discussed further here.

[0055] In some device embodiments, all base semiconductor portions of the superlattice may be the same number of monolayers thick. In other embodiments, at least some of the base semiconductor portions may be different numbers of monolayers thick. In still other embodiments, all base semiconductor portions may be different numbers of monolayers thick.

[0056] exist Figure 4A to Figure 4C In the paper, the band structure calculated using density functional theory (DFT) is presented. It is well known in the art that DFT underestimates the absolute value of the band gap. Therefore, all bands above the band gap can be shifted by appropriate "scissors". However, the shape of the known bands is much more reliable. The vertical energy axis should be interpreted from this perspective.

[0057] Figure 4A The plots for bulk silicon (shown by the solid line) and for Figure 1 The 4 / 1 Si / O superlattice 25 (indicated by the dashed lines) shown in the figure both have band structures calculated from the γ point (G). The directions relate to the unit cell of the 4 / 1 Si / O structure and not to the conventional unit cell of Si, although the (001) direction in the figure does correspond to the (001) direction of the conventional unit cell of Si, and thus shows the expected location of the Si conduction band minimum. The (100) and (010) directions in the figure correspond to the (110) and (-110) directions of the conventional Si unit cell. Those skilled in the art will appreciate that the bands of Si in the figure are folded to represent them on the appropriate reciprocal lattice directions of the 4 / 1 Si / O structure.

[0058] It can be seen that compared to bulk silicon (Si), the conduction band minimum of the 4 / 1Si / O structure is located at the γ point, while the valence band minimum appears at the edge of the Brillouin zone in the (001) direction, which we call the Z point. It can also be noted that the curvature of the conduction band minimum of the 4 / 1Si / O structure is larger than that of the conduction band minimum of Si due to the band splitting caused by the perturbation introduced by the additional oxygen layer.

[0059] Figure 4B The calculated band structures from point Z are shown both for bulk silicon (solid line) and for the 4 / 1 Si / O superlattice 25 (dashed line). The figure illustrates the enhanced curvature of the valence band in the (100) direction.

[0060] Figure 4C The solid line for bulk silicon and the Figure 3 Figure 2 shows the calculated band structures for both the 5 / 1 / 3 / 1 Si / O structure (dashed lines) and the Z-point for the superlattice 25'. Due to the symmetry of the 5 / 1 / 3 / 1 Si / O structure, the calculated band structures in the (100) and (010) directions are identical. Therefore, the conductivity effective mass and mobility are expected to be isotropic in the plane parallel to the layers, i.e., perpendicular to the (001) stacking direction. Note that in the 5 / 1 / 3 / 1 Si / O case, both the conduction band minimum and the valence band maximum are located at or near the Z-point.

[0061] Although increased curvature is an indication of reduced effective mass, appropriate comparison and distinction can be made through conductivity reciprocal effective mass tensor calculations. This leads applicants to further theorize that the 5 / 1 / 3 / 1 superlattice 25' should be substantially direct bandgap. As will be appreciated by those skilled in the art, the appropriate matrix elements for optical transitions is another indicator of the distinction between direct and indirect bandgap behavior.

[0062] Now see also Figure 5-6 , the above-described superlattice structures can be advantageously used in the preparation of semiconductor wafers and devices including embedded quantum dots. As background, several properties have been identified that are important for quantum device applications. One property is scalability, that is, the ability to be a scalable physical system with well-defined quantum bits. Another property is initialization, in that the system should be initialized to a simple reference state, such as |000…>. Yet another property is decoherence, in that the system should have a gate operation time that is much smaller than the decoherence time (e.g., 10 4 ~10 5 times the “clock time”, then error correction is feasible). The fourth property is universality, in that the system should have a universal set of quantum gates (CNOT). The last property is measurement, in that the system should have high-fidelity measurement capabilities specific to the qubit. These properties can be achieved with silicon spin-based qubits. However, in many cases this may require relatively pure 28 Si substrate.

[0063] More specifically, with respect to semiconductor quantum devices, 28 Si offers certain advantages, but also presents challenges. Advantages include higher thermal conductivity, which allows for better heat dissipation, and higher decoherence times, which makes quantum bits possible. However, 28 Si can also be subject to silicon interdiffusion and is relatively expensive to grow.

[0064] Figure 5 The metal oxide semiconductor (MOS) device 30 illustrated in the figure is a spin qubit device that exemplarily includes a silicon substrate 31, which can be a natural or typical silicon material (e.g., non 28 Si enriched). Growing enriched on substrate 31 28 Epitaxial layer 32 of Si, although non-Si may be used in other embodiments. 28 Si-enriched epitaxial or other semiconductor materials (e.g., Ge). In the example shown in the diagram, the epitaxial layer 33 also includes a superlattice 25 therein. That is, the MST film formation module can be performed during the epitaxial layer growth so that the superlattice 25 is grown on the relatively thin epitaxial-enriched 28The Si seed layer is formed on the superlattice, and the cap layer defines the upper portion of the epitaxial layer 32. As described above, the enriched 28 The crystal lattice of the Si material penetrates the superlattice layer 25, so the epitaxial layer 32 is considered herein as a single layer with an embedded MST film, although it can also be considered as two separate epitaxially enriched 28 Si layer with MST film in between. In some embodiments, additional MST films may be incorporated into epitaxial layer 32 or grown on top of epitaxial layer 32 if desired.

[0065] Semiconductor device 30 also illustratively includes a plurality of quantum dots 33 spaced apart in epitaxial layer 32 over superlattice 25. Quantum dots 33 include a semiconductor material different from that of epitaxial layer 32. More specifically, for example, quantum dots 33 may include a semiconductor such as germanium (Ge) or gallium arsenide (GaAs), although other suitable materials may be used in different embodiments.

[0066] The substrate 31 and the epitaxial layer 32 having the superlattice 25 and the quantum dots 33 can be collectively regarded as 28 Si quantum substrates offer numerous advantages for quantum applications. First, they are comparable to conventional silicon substrates that require relatively thick layers to prevent unwanted isotope intermixing. 28 This allows the use of relatively small amounts or thinner Si 28 Si. Attributed to 28 The higher cost of Si deposition is important because 28 Si quantum substrates require less 28 Si gas. In addition, 28 The incorporation of MST films into Si quantum substrates advantageously helps eliminate point defects, provides better thermal stability, and helps maintain higher 28 Si purity. In particular, the dopant blocking properties of the superlattice 25 discussed above help block contaminants (e.g., boron) from migrating to the quantum dots 33. 28 Example devices on Si quantum substrates include silicon spin qubits (e.g. Figure 5 ), as well as quantum sensors, single electron transistors (SETs), resonant tunneling diodes (RTDs), and trench FET (TFET) devices.

[0067] The semiconductor device 30 also exemplarily includes a source region 34 and a drain region 35 separated in the epitaxial semiconductor layer 32, defining a channel region where the quantum dot 33 is located. Corresponding source contacts 36 / drain contacts 37 are formed on the source region 34 and the drain region 35. In addition, a gate structure is above the channel region on the epitaxial layer 32, as shown in the figure, and the gate structure exemplarily includes an accumulation gate electrode 38, a barrier gate electrode 39 and a plug gate electrode 40, and a gate dielectric layer 41. Figure 6 In the example illustrated in FIG, the quantum dot is Ge, and the corresponding eV values ​​of Si and Ge are shown on the right side of the example implementation.

[0068] Reference now Figures 7A to 7F Describes the method for preparing the 28 The first exemplary method of Si quantum substrate. After forming epitaxial layer 32 on substrate 31 ( Fig. 7A ), forming a pattern of small (eg, less than 10 nanometers) holes or pits 60 in the epitaxial (crystalline) layer 32 ( Figure 7B ). Then, if Figure 7C and Fig.7D As shown, holes 60 may be filled with quantum dot material (eg, Ge) 61, and the surface of epitaxial layer 32 may be cleaned (eg, using CMP) to remove excess Ge and define quantum dots 33 ( Fig. 7E ). Epitaxial growth of additional silicon (e.g. enrichment 28 Si) to embed the quantum dots 33 into the epitaxial layer 32 ( Figure 7F ). At this stage, 28 Si quantum substrates can be used to prepare various quantum devices, such as those described further above.

[0069] Reference now Figure 8A to Figure 8F In the described alternative embodiment, in forming the epitaxial layer 32' ( Fig. 8A ) After that, an oxide mask 62' is formed on the epitaxial layer, and the oxide mask 62' is used to define the hole 60' at the desired position ( Figure 8C ), and depositing quantum dot material 61' ( Fig.8D ). Then the oxide mask 62' is removed ( Fig. 8E ), and epitaxially grow additional silicon on the structure to produce embedded quantum dots 33'( Figure 8F ).

[0070] For example, the epitaxial layers 32, 32' may have a relative humidity greater than 93% and more particularly greater than 99%. 28 Si isotope concentration. In U.S. Application Nos. US2022 / 0344155 and 2022 / 0352322, both of which are incorporated herein by reference in their entirety and are both by Hytha et al., information regarding 28 More details for Si and MST films.

[0071] In general, the above method advantageously provides a method for growing very small, uniformly distributed quantum dots 33, 33' that are essentially single electron (hole) quantum dots due to their size and Coulomb blockade. In some implementations, this can be combined with gate control, as discussed further above. In addition, it should be noted that28 Si is only one option for epitaxial layers 32, 32', although 28 Si is helpful for qubit applications, but not necessary for other applications, such as single electron transistors (SETs). 28 Si. Furthermore, it should be noted that in some embodiments, the MST film need not be present in the epitaxial layers 32, 32'.

[0072] Also as described above, in different embodiments, other materials other than silicon may be used with germanium / GaAs quantum dots. As example alternative substrate / epitaxial layer materials, wide bandgap semiconductors such as SiC or GaN may be used. Other example materials that may be used for quantum dots include Si, SiC, GaN, InP, etc.

[0073] Many modifications and other embodiments of the present invention will come to mind to one skilled in the art having benefit of the teachings presented in the foregoing description and the associated drawings. It should therefore be understood that the present invention is not limited to the particular embodiments disclosed but is intended to encompass various modifications and embodiments.

Claims

1. A semiconductor device, comprising: at least one semiconductor layer, the at least one semiconductor layer including a superlattice therein, the superlattice comprising a plurality of stacked layer groups, each layer group comprising a plurality of stacked base semiconductor monolayers and at least one non-semiconductor monolayer, the plurality of stacked base semiconductor monolayers defining a base semiconductor portion, the at least one non-semiconductor monolayer being constrained within a lattice of an adjacent base semiconductor portion; and A plurality of quantum dots are spaced apart above the superlattice in the at least one semiconductor layer and comprise a different semiconductor material than the semiconductor layer.

2. A semiconductor device according to claim 1, wherein the at least one semiconductor layer includes a semiconductor substrate and an epitaxial semiconductor layer on the substrate; wherein the superlattice is within the epitaxial semiconductor layer; and wherein the quantum dots are above the superlattice within the epitaxial semiconductor layer.

3. The semiconductor device of claim 2 , wherein the semiconductor substrate and the epitaxial semiconductor layer comprise silicon; and wherein the epitaxial semiconductor layer has a higher percentage of silicon 28 ( 28 Si).

4. The semiconductor device of claim 1, wherein the plurality of quantum dots comprises germanium.

5. The semiconductor device of claim 1, wherein the plurality of quantum dots comprises gallium arsenide.

6. The semiconductor device of claim 2, further comprising spaced-apart source and drain regions in the epitaxial semiconductor layer defining a channel region therebetween, and a gate on the epitaxial semiconductor layer over the channel region.

7. The semiconductor device according to claim 6, wherein the gate comprises at least one accumulation gate.

8. The semiconductor device according to claim 6, wherein the gate comprises at least one plug gate.

9. The semiconductor device according to claim 6, wherein the gate comprises at least one barrier gate.

10. The semiconductor device according to claim 1, wherein the at least one non-semiconductor comprises oxygen.

11. A method for manufacturing a semiconductor device, comprising: forming at least one semiconductor layer, the at least one semiconductor layer including a superlattice therein, the superlattice comprising a plurality of stacked layer groups, each layer group comprising a plurality of stacked base semiconductor monolayers and at least one non-semiconductor monolayer, the plurality of stacked base semiconductor monolayers defining a base semiconductor portion, the at least one non-semiconductor monolayer being confined within a lattice of an adjacent base semiconductor portion; and A plurality of quantum dots are formed, the plurality of quantum dots being spaced apart above the superlattice in the at least one semiconductor layer and comprising a different semiconductor material than the semiconductor layer.

12. The method of claim 11, wherein forming the at least one semiconductor layer comprises forming a semiconductor substrate and an epitaxial semiconductor layer on the substrate, wherein the superlattice is within the epitaxial semiconductor layer; and wherein the quantum dots are above the superlattice within the epitaxial semiconductor layer.

13. The method of claim 12, wherein the semiconductor substrate and the epitaxial semiconductor layer comprise silicon; and wherein the epitaxial semiconductor layer has a higher percentage of silicon 28 than the semiconductor substrate. 28 Si).

14. The method of claim 11, wherein the plurality of quantum dots comprises germanium.

15. The method of claim 11, wherein the plurality of quantum dots comprises gallium arsenide.

16. The method of claim 12, further comprising forming spaced-apart source and drain regions defining a channel region therebetween in the epitaxial semiconductor layer, and forming a gate over the channel region on the epitaxial semiconductor layer.

17. The method of claim 16, wherein the gate comprises at least one accumulation gate.

18. The method of claim 16, wherein the gate comprises at least one plug gate.

19. The method of claim 16, wherein the gate comprises at least one barrier gate.

20. The method of claim 11, wherein the at least one non-semiconductor comprises oxygen.

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